blob: f7f28f2f864179546332482087ad64a7782a8c16 [file] [log] [blame]
Ben Skeggs6ee73862009-12-11 19:24:15 +10001/*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#include <linux/console.h>
26
27#include "drmP.h"
28#include "drm.h"
29#include "drm_crtc_helper.h"
30#include "nouveau_drv.h"
31#include "nouveau_hw.h"
32#include "nouveau_fb.h"
33#include "nouveau_fbcon.h"
34#include "nv50_display.h"
35
36#include "drm_pciids.h"
37
Ben Skeggs054b93e2009-12-15 22:02:47 +100038MODULE_PARM_DESC(ctxfw, "Use external firmware blob for grctx init (NV40)");
39int nouveau_ctxfw = 0;
40module_param_named(ctxfw, nouveau_ctxfw, int, 0400);
41
Ben Skeggs6ee73862009-12-11 19:24:15 +100042MODULE_PARM_DESC(noagp, "Disable AGP");
43int nouveau_noagp;
44module_param_named(noagp, nouveau_noagp, int, 0400);
45
46MODULE_PARM_DESC(modeset, "Enable kernel modesetting");
47static int nouveau_modeset = -1; /* kms */
48module_param_named(modeset, nouveau_modeset, int, 0400);
49
50MODULE_PARM_DESC(vbios, "Override default VBIOS location");
51char *nouveau_vbios;
52module_param_named(vbios, nouveau_vbios, charp, 0400);
53
54MODULE_PARM_DESC(vram_pushbuf, "Force DMA push buffers to be in VRAM");
55int nouveau_vram_pushbuf;
56module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);
57
58MODULE_PARM_DESC(vram_notify, "Force DMA notifiers to be in VRAM");
Ben Skeggsf927b892010-01-27 14:29:05 +100059int nouveau_vram_notify = 1;
Ben Skeggs6ee73862009-12-11 19:24:15 +100060module_param_named(vram_notify, nouveau_vram_notify, int, 0400);
61
62MODULE_PARM_DESC(duallink, "Allow dual-link TMDS (>=GeForce 8)");
63int nouveau_duallink = 1;
64module_param_named(duallink, nouveau_duallink, int, 0400);
65
66MODULE_PARM_DESC(uscript_lvds, "LVDS output script table ID (>=GeForce 8)");
67int nouveau_uscript_lvds = -1;
68module_param_named(uscript_lvds, nouveau_uscript_lvds, int, 0400);
69
70MODULE_PARM_DESC(uscript_tmds, "TMDS output script table ID (>=GeForce 8)");
71int nouveau_uscript_tmds = -1;
72module_param_named(uscript_tmds, nouveau_uscript_tmds, int, 0400);
73
Ben Skeggsa1470892010-01-18 11:42:37 +100074MODULE_PARM_DESC(ignorelid, "Ignore ACPI lid status");
75int nouveau_ignorelid = 0;
76module_param_named(ignorelid, nouveau_ignorelid, int, 0400);
77
Marcin Kościelnicki81e2d422010-02-25 00:54:04 +000078MODULE_PARM_DESC(noaccel, "Disable all acceleration");
Marcin Kościelnickia32ed692010-01-26 14:00:42 +000079int nouveau_noaccel = 0;
80module_param_named(noaccel, nouveau_noaccel, int, 0400);
81
Marcin Kościelnicki81e2d422010-02-25 00:54:04 +000082MODULE_PARM_DESC(nofbaccel, "Disable fbcon acceleration");
Marcin Kościelnickia32ed692010-01-26 14:00:42 +000083int nouveau_nofbaccel = 0;
84module_param_named(nofbaccel, nouveau_nofbaccel, int, 0400);
85
Ben Skeggsda647d52010-03-04 12:00:39 +100086MODULE_PARM_DESC(override_conntype, "Ignore DCB connector type");
87int nouveau_override_conntype = 0;
88module_param_named(override_conntype, nouveau_override_conntype, int, 0400);
89
Ben Skeggs6ee73862009-12-11 19:24:15 +100090MODULE_PARM_DESC(tv_norm, "Default TV norm.\n"
91 "\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n"
92 "\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n"
93 "\t\tDefault: PAL\n"
94 "\t\t*NOTE* Ignored for cards with external TV encoders.");
95char *nouveau_tv_norm;
96module_param_named(tv_norm, nouveau_tv_norm, charp, 0400);
97
98MODULE_PARM_DESC(reg_debug, "Register access debug bitmask:\n"
99 "\t\t0x1 mc, 0x2 video, 0x4 fb, 0x8 extdev,\n"
100 "\t\t0x10 crtc, 0x20 ramdac, 0x40 vgacrtc, 0x80 rmvio,\n"
101 "\t\t0x100 vgaattr, 0x200 EVO (G80+). ");
102int nouveau_reg_debug;
103module_param_named(reg_debug, nouveau_reg_debug, int, 0600);
104
105int nouveau_fbpercrtc;
106#if 0
107module_param_named(fbpercrtc, nouveau_fbpercrtc, int, 0400);
108#endif
109
110static struct pci_device_id pciidlist[] = {
111 {
112 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
113 .class = PCI_BASE_CLASS_DISPLAY << 16,
114 .class_mask = 0xff << 16,
115 },
116 {
117 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
118 .class = PCI_BASE_CLASS_DISPLAY << 16,
119 .class_mask = 0xff << 16,
120 },
121 {}
122};
123
124MODULE_DEVICE_TABLE(pci, pciidlist);
125
126static struct drm_driver driver;
127
128static int __devinit
129nouveau_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
130{
131 return drm_get_dev(pdev, ent, &driver);
132}
133
134static void
135nouveau_pci_remove(struct pci_dev *pdev)
136{
137 struct drm_device *dev = pci_get_drvdata(pdev);
138
139 drm_put_dev(dev);
140}
141
142static int
143nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state)
144{
145 struct drm_device *dev = pci_get_drvdata(pdev);
146 struct drm_nouveau_private *dev_priv = dev->dev_private;
147 struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
148 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
149 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
150 struct nouveau_channel *chan;
151 struct drm_crtc *crtc;
152 uint32_t fbdev_flags;
153 int ret, i;
154
155 if (!drm_core_check_feature(dev, DRIVER_MODESET))
156 return -ENODEV;
157
158 if (pm_state.event == PM_EVENT_PRETHAW)
159 return 0;
160
161 fbdev_flags = dev_priv->fbdev_info->flags;
162 dev_priv->fbdev_info->flags |= FBINFO_HWACCEL_DISABLED;
163
164 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
165 struct nouveau_framebuffer *nouveau_fb;
166
167 nouveau_fb = nouveau_framebuffer(crtc->fb);
168 if (!nouveau_fb || !nouveau_fb->nvbo)
169 continue;
170
171 nouveau_bo_unpin(nouveau_fb->nvbo);
172 }
173
174 NV_INFO(dev, "Evicting buffers...\n");
175 ttm_bo_evict_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
176
177 NV_INFO(dev, "Idling channels...\n");
178 for (i = 0; i < pfifo->channels; i++) {
179 struct nouveau_fence *fence = NULL;
180
181 chan = dev_priv->fifos[i];
182 if (!chan || (dev_priv->card_type >= NV_50 &&
183 chan == dev_priv->fifos[0]))
184 continue;
185
186 ret = nouveau_fence_new(chan, &fence, true);
187 if (ret == 0) {
188 ret = nouveau_fence_wait(fence, NULL, false, false);
189 nouveau_fence_unref((void *)&fence);
190 }
191
192 if (ret) {
193 NV_ERROR(dev, "Failed to idle channel %d for suspend\n",
194 chan->id);
195 }
196 }
197
198 pgraph->fifo_access(dev, false);
199 nouveau_wait_for_idle(dev);
200 pfifo->reassign(dev, false);
201 pfifo->disable(dev);
202 pfifo->unload_context(dev);
203 pgraph->unload_context(dev);
204
205 NV_INFO(dev, "Suspending GPU objects...\n");
206 ret = nouveau_gpuobj_suspend(dev);
207 if (ret) {
208 NV_ERROR(dev, "... failed: %d\n", ret);
209 goto out_abort;
210 }
211
212 ret = pinstmem->suspend(dev);
213 if (ret) {
214 NV_ERROR(dev, "... failed: %d\n", ret);
215 nouveau_gpuobj_suspend_cleanup(dev);
216 goto out_abort;
217 }
218
219 NV_INFO(dev, "And we're gone!\n");
220 pci_save_state(pdev);
221 if (pm_state.event == PM_EVENT_SUSPEND) {
222 pci_disable_device(pdev);
223 pci_set_power_state(pdev, PCI_D3hot);
224 }
225
226 acquire_console_sem();
227 fb_set_suspend(dev_priv->fbdev_info, 1);
228 release_console_sem();
229 dev_priv->fbdev_info->flags = fbdev_flags;
230 return 0;
231
232out_abort:
233 NV_INFO(dev, "Re-enabling acceleration..\n");
234 pfifo->enable(dev);
235 pfifo->reassign(dev, true);
236 pgraph->fifo_access(dev, true);
237 return ret;
238}
239
240static int
241nouveau_pci_resume(struct pci_dev *pdev)
242{
243 struct drm_device *dev = pci_get_drvdata(pdev);
244 struct drm_nouveau_private *dev_priv = dev->dev_private;
245 struct nouveau_engine *engine = &dev_priv->engine;
246 struct drm_crtc *crtc;
247 uint32_t fbdev_flags;
248 int ret, i;
249
250 if (!drm_core_check_feature(dev, DRIVER_MODESET))
251 return -ENODEV;
252
253 fbdev_flags = dev_priv->fbdev_info->flags;
254 dev_priv->fbdev_info->flags |= FBINFO_HWACCEL_DISABLED;
255
256 NV_INFO(dev, "We're back, enabling device...\n");
257 pci_set_power_state(pdev, PCI_D0);
258 pci_restore_state(pdev);
259 if (pci_enable_device(pdev))
260 return -1;
261 pci_set_master(dev->pdev);
262
263 NV_INFO(dev, "POSTing device...\n");
264 ret = nouveau_run_vbios_init(dev);
265 if (ret)
266 return ret;
267
268 if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
269 ret = nouveau_mem_init_agp(dev);
270 if (ret) {
271 NV_ERROR(dev, "error reinitialising AGP: %d\n", ret);
272 return ret;
273 }
274 }
275
276 NV_INFO(dev, "Reinitialising engines...\n");
277 engine->instmem.resume(dev);
278 engine->mc.init(dev);
279 engine->timer.init(dev);
280 engine->fb.init(dev);
281 engine->graph.init(dev);
282 engine->fifo.init(dev);
283
284 NV_INFO(dev, "Restoring GPU objects...\n");
285 nouveau_gpuobj_resume(dev);
286
287 nouveau_irq_postinstall(dev);
288
289 /* Re-write SKIPS, they'll have been lost over the suspend */
290 if (nouveau_vram_pushbuf) {
291 struct nouveau_channel *chan;
292 int j;
293
294 for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
295 chan = dev_priv->fifos[i];
Ben Skeggs3c8868d2009-12-16 14:51:13 +1000296 if (!chan || !chan->pushbuf_bo)
Ben Skeggs6ee73862009-12-11 19:24:15 +1000297 continue;
298
299 for (j = 0; j < NOUVEAU_DMA_SKIPS; j++)
300 nouveau_bo_wr32(chan->pushbuf_bo, i, 0);
301 }
302 }
303
304 NV_INFO(dev, "Restoring mode...\n");
305 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
306 struct nouveau_framebuffer *nouveau_fb;
307
308 nouveau_fb = nouveau_framebuffer(crtc->fb);
309 if (!nouveau_fb || !nouveau_fb->nvbo)
310 continue;
311
312 nouveau_bo_pin(nouveau_fb->nvbo, TTM_PL_FLAG_VRAM);
313 }
314
315 if (dev_priv->card_type < NV_50) {
316 nv04_display_restore(dev);
317 NVLockVgaCrtcs(dev, false);
318 } else
319 nv50_display_init(dev);
320
321 /* Force CLUT to get re-loaded during modeset */
322 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
323 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
324
325 nv_crtc->lut.depth = 0;
326 }
327
328 acquire_console_sem();
329 fb_set_suspend(dev_priv->fbdev_info, 0);
330 release_console_sem();
331
332 nouveau_fbcon_zfill(dev);
333
334 drm_helper_resume_force_mode(dev);
335 dev_priv->fbdev_info->flags = fbdev_flags;
336 return 0;
337}
338
339static struct drm_driver driver = {
340 .driver_features =
341 DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG |
342 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
343 .load = nouveau_load,
344 .firstopen = nouveau_firstopen,
345 .lastclose = nouveau_lastclose,
346 .unload = nouveau_unload,
347 .preclose = nouveau_preclose,
348#if defined(CONFIG_DRM_NOUVEAU_DEBUG)
349 .debugfs_init = nouveau_debugfs_init,
350 .debugfs_cleanup = nouveau_debugfs_takedown,
351#endif
352 .irq_preinstall = nouveau_irq_preinstall,
353 .irq_postinstall = nouveau_irq_postinstall,
354 .irq_uninstall = nouveau_irq_uninstall,
355 .irq_handler = nouveau_irq_handler,
356 .reclaim_buffers = drm_core_reclaim_buffers,
357 .get_map_ofs = drm_core_get_map_ofs,
358 .get_reg_ofs = drm_core_get_reg_ofs,
359 .ioctls = nouveau_ioctls,
360 .fops = {
361 .owner = THIS_MODULE,
362 .open = drm_open,
363 .release = drm_release,
Arnd Bergmanned8b6702009-12-16 22:17:09 +0000364 .unlocked_ioctl = drm_ioctl,
Ben Skeggs6ee73862009-12-11 19:24:15 +1000365 .mmap = nouveau_ttm_mmap,
366 .poll = drm_poll,
367 .fasync = drm_fasync,
368#if defined(CONFIG_COMPAT)
369 .compat_ioctl = nouveau_compat_ioctl,
370#endif
371 },
372 .pci_driver = {
373 .name = DRIVER_NAME,
374 .id_table = pciidlist,
375 .probe = nouveau_pci_probe,
376 .remove = nouveau_pci_remove,
377 .suspend = nouveau_pci_suspend,
378 .resume = nouveau_pci_resume
379 },
380
381 .gem_init_object = nouveau_gem_object_new,
382 .gem_free_object = nouveau_gem_object_del,
383
384 .name = DRIVER_NAME,
385 .desc = DRIVER_DESC,
386#ifdef GIT_REVISION
387 .date = GIT_REVISION,
388#else
389 .date = DRIVER_DATE,
390#endif
391 .major = DRIVER_MAJOR,
392 .minor = DRIVER_MINOR,
393 .patchlevel = DRIVER_PATCHLEVEL,
394};
395
396static int __init nouveau_init(void)
397{
398 driver.num_ioctls = nouveau_max_ioctl;
399
400 if (nouveau_modeset == -1) {
401#ifdef CONFIG_VGA_CONSOLE
402 if (vgacon_text_force())
403 nouveau_modeset = 0;
404 else
405#endif
406 nouveau_modeset = 1;
407 }
408
409 if (nouveau_modeset == 1)
410 driver.driver_features |= DRIVER_MODESET;
411
412 return drm_init(&driver);
413}
414
415static void __exit nouveau_exit(void)
416{
417 drm_exit(&driver);
418}
419
420module_init(nouveau_init);
421module_exit(nouveau_exit);
422
423MODULE_AUTHOR(DRIVER_AUTHOR);
424MODULE_DESCRIPTION(DRIVER_DESC);
425MODULE_LICENSE("GPL and additional rights");