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Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001/*
2 * linux/drivers/video/omap2/dss/dsi.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#define DSS_SUBSYS_NAME "DSI"
21
22#include <linux/kernel.h>
23#include <linux/io.h>
24#include <linux/clk.h>
25#include <linux/device.h>
26#include <linux/err.h>
27#include <linux/interrupt.h>
28#include <linux/delay.h>
29#include <linux/mutex.h>
30#include <linux/seq_file.h>
31#include <linux/platform_device.h>
32#include <linux/regulator/consumer.h>
33#include <linux/kthread.h>
34#include <linux/wait.h>
35
36#include <plat/display.h>
37#include <plat/clock.h>
38
39#include "dss.h"
40
41/*#define VERBOSE_IRQ*/
42#define DSI_CATCH_MISSING_TE
43
44#define DSI_BASE 0x4804FC00
45
46struct dsi_reg { u16 idx; };
47
48#define DSI_REG(idx) ((const struct dsi_reg) { idx })
49
50#define DSI_SZ_REGS SZ_1K
51/* DSI Protocol Engine */
52
53#define DSI_REVISION DSI_REG(0x0000)
54#define DSI_SYSCONFIG DSI_REG(0x0010)
55#define DSI_SYSSTATUS DSI_REG(0x0014)
56#define DSI_IRQSTATUS DSI_REG(0x0018)
57#define DSI_IRQENABLE DSI_REG(0x001C)
58#define DSI_CTRL DSI_REG(0x0040)
59#define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048)
60#define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C)
61#define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050)
62#define DSI_CLK_CTRL DSI_REG(0x0054)
63#define DSI_TIMING1 DSI_REG(0x0058)
64#define DSI_TIMING2 DSI_REG(0x005C)
65#define DSI_VM_TIMING1 DSI_REG(0x0060)
66#define DSI_VM_TIMING2 DSI_REG(0x0064)
67#define DSI_VM_TIMING3 DSI_REG(0x0068)
68#define DSI_CLK_TIMING DSI_REG(0x006C)
69#define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070)
70#define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074)
71#define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078)
72#define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C)
73#define DSI_VM_TIMING4 DSI_REG(0x0080)
74#define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084)
75#define DSI_VM_TIMING5 DSI_REG(0x0088)
76#define DSI_VM_TIMING6 DSI_REG(0x008C)
77#define DSI_VM_TIMING7 DSI_REG(0x0090)
78#define DSI_STOPCLK_TIMING DSI_REG(0x0094)
79#define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20))
80#define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20))
81#define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20))
82#define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20))
83#define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20))
84#define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20))
85#define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20))
86
87/* DSIPHY_SCP */
88
89#define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000)
90#define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004)
91#define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008)
92#define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014)
93
94/* DSI_PLL_CTRL_SCP */
95
96#define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000)
97#define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004)
98#define DSI_PLL_GO DSI_REG(0x300 + 0x0008)
99#define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C)
100#define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010)
101
102#define REG_GET(idx, start, end) \
103 FLD_GET(dsi_read_reg(idx), start, end)
104
105#define REG_FLD_MOD(idx, val, start, end) \
106 dsi_write_reg(idx, FLD_MOD(dsi_read_reg(idx), val, start, end))
107
108/* Global interrupts */
109#define DSI_IRQ_VC0 (1 << 0)
110#define DSI_IRQ_VC1 (1 << 1)
111#define DSI_IRQ_VC2 (1 << 2)
112#define DSI_IRQ_VC3 (1 << 3)
113#define DSI_IRQ_WAKEUP (1 << 4)
114#define DSI_IRQ_RESYNC (1 << 5)
115#define DSI_IRQ_PLL_LOCK (1 << 7)
116#define DSI_IRQ_PLL_UNLOCK (1 << 8)
117#define DSI_IRQ_PLL_RECALL (1 << 9)
118#define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
119#define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
120#define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
121#define DSI_IRQ_TE_TRIGGER (1 << 16)
122#define DSI_IRQ_ACK_TRIGGER (1 << 17)
123#define DSI_IRQ_SYNC_LOST (1 << 18)
124#define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
125#define DSI_IRQ_TA_TIMEOUT (1 << 20)
126#define DSI_IRQ_ERROR_MASK \
127 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
128 DSI_IRQ_TA_TIMEOUT)
129#define DSI_IRQ_CHANNEL_MASK 0xf
130
131/* Virtual channel interrupts */
132#define DSI_VC_IRQ_CS (1 << 0)
133#define DSI_VC_IRQ_ECC_CORR (1 << 1)
134#define DSI_VC_IRQ_PACKET_SENT (1 << 2)
135#define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
136#define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
137#define DSI_VC_IRQ_BTA (1 << 5)
138#define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
139#define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
140#define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
141#define DSI_VC_IRQ_ERROR_MASK \
142 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
143 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
144 DSI_VC_IRQ_FIFO_TX_UDF)
145
146/* ComplexIO interrupts */
147#define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
148#define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
149#define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
150#define DSI_CIO_IRQ_ERRESC1 (1 << 5)
151#define DSI_CIO_IRQ_ERRESC2 (1 << 6)
152#define DSI_CIO_IRQ_ERRESC3 (1 << 7)
153#define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
154#define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
155#define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
156#define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
157#define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
158#define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
159#define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
160#define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
161#define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
162#define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
163#define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
164#define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
165#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
166#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
167
168#define DSI_DT_DCS_SHORT_WRITE_0 0x05
169#define DSI_DT_DCS_SHORT_WRITE_1 0x15
170#define DSI_DT_DCS_READ 0x06
171#define DSI_DT_SET_MAX_RET_PKG_SIZE 0x37
172#define DSI_DT_NULL_PACKET 0x09
173#define DSI_DT_DCS_LONG_WRITE 0x39
174
175#define DSI_DT_RX_ACK_WITH_ERR 0x02
176#define DSI_DT_RX_DCS_LONG_READ 0x1c
177#define DSI_DT_RX_SHORT_READ_1 0x21
178#define DSI_DT_RX_SHORT_READ_2 0x22
179
180#define FINT_MAX 2100000
181#define FINT_MIN 750000
182#define REGN_MAX (1 << 7)
183#define REGM_MAX ((1 << 11) - 1)
184#define REGM3_MAX (1 << 4)
185#define REGM4_MAX (1 << 4)
186#define LP_DIV_MAX ((1 << 13) - 1)
187
188enum fifo_size {
189 DSI_FIFO_SIZE_0 = 0,
190 DSI_FIFO_SIZE_32 = 1,
191 DSI_FIFO_SIZE_64 = 2,
192 DSI_FIFO_SIZE_96 = 3,
193 DSI_FIFO_SIZE_128 = 4,
194};
195
196enum dsi_vc_mode {
197 DSI_VC_MODE_L4 = 0,
198 DSI_VC_MODE_VP,
199};
200
201struct dsi_update_region {
202 bool dirty;
203 u16 x, y, w, h;
204 struct omap_dss_device *device;
205};
206
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +0200207struct dsi_irq_stats {
208 unsigned long last_reset;
209 unsigned irq_count;
210 unsigned dsi_irqs[32];
211 unsigned vc_irqs[4][32];
212 unsigned cio_irqs[32];
213};
214
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200215static struct
216{
217 void __iomem *base;
218
219 struct dsi_clock_info current_cinfo;
220
221 struct regulator *vdds_dsi_reg;
222
223 struct {
224 enum dsi_vc_mode mode;
225 struct omap_dss_device *dssdev;
226 enum fifo_size fifo_size;
227 int dest_per; /* destination peripheral 0-3 */
228 } vc[4];
229
230 struct mutex lock;
231 struct mutex bus_lock;
232
233 unsigned pll_locked;
234
235 struct completion bta_completion;
236
237 struct task_struct *thread;
238 wait_queue_head_t waitqueue;
239
240 spinlock_t update_lock;
241 bool framedone_received;
242 struct dsi_update_region update_region;
243 struct dsi_update_region active_update_region;
244 struct completion update_completion;
245
246 enum omap_dss_update_mode user_update_mode;
247 enum omap_dss_update_mode update_mode;
248 bool te_enabled;
249 bool use_ext_te;
250
251#ifdef DSI_CATCH_MISSING_TE
252 struct timer_list te_timer;
253#endif
254
255 unsigned long cache_req_pck;
256 unsigned long cache_clk_freq;
257 struct dsi_clock_info cache_cinfo;
258
259 u32 errors;
260 spinlock_t errors_lock;
261#ifdef DEBUG
262 ktime_t perf_setup_time;
263 ktime_t perf_start_time;
264 ktime_t perf_start_time_auto;
265 int perf_measure_frames;
266#endif
267 int debug_read;
268 int debug_write;
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +0200269
270#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
271 spinlock_t irq_stats_lock;
272 struct dsi_irq_stats irq_stats;
273#endif
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200274} dsi;
275
276#ifdef DEBUG
277static unsigned int dsi_perf;
278module_param_named(dsi_perf, dsi_perf, bool, 0644);
279#endif
280
281static inline void dsi_write_reg(const struct dsi_reg idx, u32 val)
282{
283 __raw_writel(val, dsi.base + idx.idx);
284}
285
286static inline u32 dsi_read_reg(const struct dsi_reg idx)
287{
288 return __raw_readl(dsi.base + idx.idx);
289}
290
291
292void dsi_save_context(void)
293{
294}
295
296void dsi_restore_context(void)
297{
298}
299
300void dsi_bus_lock(void)
301{
302 mutex_lock(&dsi.bus_lock);
303}
304EXPORT_SYMBOL(dsi_bus_lock);
305
306void dsi_bus_unlock(void)
307{
308 mutex_unlock(&dsi.bus_lock);
309}
310EXPORT_SYMBOL(dsi_bus_unlock);
311
Tomi Valkeinen4f765022010-01-18 16:27:52 +0200312static bool dsi_bus_is_locked(void)
313{
314 return mutex_is_locked(&dsi.bus_lock);
315}
316
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200317static inline int wait_for_bit_change(const struct dsi_reg idx, int bitnum,
318 int value)
319{
320 int t = 100000;
321
322 while (REG_GET(idx, bitnum, bitnum) != value) {
323 if (--t == 0)
324 return !value;
325 }
326
327 return value;
328}
329
330#ifdef DEBUG
331static void dsi_perf_mark_setup(void)
332{
333 dsi.perf_setup_time = ktime_get();
334}
335
336static void dsi_perf_mark_start(void)
337{
338 dsi.perf_start_time = ktime_get();
339}
340
341static void dsi_perf_mark_start_auto(void)
342{
343 dsi.perf_measure_frames = 0;
344 dsi.perf_start_time_auto = ktime_get();
345}
346
347static void dsi_perf_show(const char *name)
348{
349 ktime_t t, setup_time, trans_time;
350 u32 total_bytes;
351 u32 setup_us, trans_us, total_us;
352
353 if (!dsi_perf)
354 return;
355
356 if (dsi.update_mode == OMAP_DSS_UPDATE_DISABLED)
357 return;
358
359 t = ktime_get();
360
361 setup_time = ktime_sub(dsi.perf_start_time, dsi.perf_setup_time);
362 setup_us = (u32)ktime_to_us(setup_time);
363 if (setup_us == 0)
364 setup_us = 1;
365
366 trans_time = ktime_sub(t, dsi.perf_start_time);
367 trans_us = (u32)ktime_to_us(trans_time);
368 if (trans_us == 0)
369 trans_us = 1;
370
371 total_us = setup_us + trans_us;
372
373 total_bytes = dsi.active_update_region.w *
374 dsi.active_update_region.h *
375 dsi.active_update_region.device->ctrl.pixel_size / 8;
376
377 if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO) {
378 static u32 s_total_trans_us, s_total_setup_us;
379 static u32 s_min_trans_us = 0xffffffff, s_min_setup_us;
380 static u32 s_max_trans_us, s_max_setup_us;
381 const int numframes = 100;
382 ktime_t total_time_auto;
383 u32 total_time_auto_us;
384
385 dsi.perf_measure_frames++;
386
387 if (setup_us < s_min_setup_us)
388 s_min_setup_us = setup_us;
389
390 if (setup_us > s_max_setup_us)
391 s_max_setup_us = setup_us;
392
393 s_total_setup_us += setup_us;
394
395 if (trans_us < s_min_trans_us)
396 s_min_trans_us = trans_us;
397
398 if (trans_us > s_max_trans_us)
399 s_max_trans_us = trans_us;
400
401 s_total_trans_us += trans_us;
402
403 if (dsi.perf_measure_frames < numframes)
404 return;
405
406 total_time_auto = ktime_sub(t, dsi.perf_start_time_auto);
407 total_time_auto_us = (u32)ktime_to_us(total_time_auto);
408
409 printk(KERN_INFO "DSI(%s): %u fps, setup %u/%u/%u, "
410 "trans %u/%u/%u\n",
411 name,
412 1000 * 1000 * numframes / total_time_auto_us,
413 s_min_setup_us,
414 s_max_setup_us,
415 s_total_setup_us / numframes,
416 s_min_trans_us,
417 s_max_trans_us,
418 s_total_trans_us / numframes);
419
420 s_total_setup_us = 0;
421 s_min_setup_us = 0xffffffff;
422 s_max_setup_us = 0;
423 s_total_trans_us = 0;
424 s_min_trans_us = 0xffffffff;
425 s_max_trans_us = 0;
426 dsi_perf_mark_start_auto();
427 } else {
428 printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
429 "%u bytes, %u kbytes/sec\n",
430 name,
431 setup_us,
432 trans_us,
433 total_us,
434 1000*1000 / total_us,
435 total_bytes,
436 total_bytes * 1000 / total_us);
437 }
438}
439#else
440#define dsi_perf_mark_setup()
441#define dsi_perf_mark_start()
442#define dsi_perf_mark_start_auto()
443#define dsi_perf_show(x)
444#endif
445
446static void print_irq_status(u32 status)
447{
448#ifndef VERBOSE_IRQ
449 if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0)
450 return;
451#endif
452 printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status);
453
454#define PIS(x) \
455 if (status & DSI_IRQ_##x) \
456 printk(#x " ");
457#ifdef VERBOSE_IRQ
458 PIS(VC0);
459 PIS(VC1);
460 PIS(VC2);
461 PIS(VC3);
462#endif
463 PIS(WAKEUP);
464 PIS(RESYNC);
465 PIS(PLL_LOCK);
466 PIS(PLL_UNLOCK);
467 PIS(PLL_RECALL);
468 PIS(COMPLEXIO_ERR);
469 PIS(HS_TX_TIMEOUT);
470 PIS(LP_RX_TIMEOUT);
471 PIS(TE_TRIGGER);
472 PIS(ACK_TRIGGER);
473 PIS(SYNC_LOST);
474 PIS(LDO_POWER_GOOD);
475 PIS(TA_TIMEOUT);
476#undef PIS
477
478 printk("\n");
479}
480
481static void print_irq_status_vc(int channel, u32 status)
482{
483#ifndef VERBOSE_IRQ
484 if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
485 return;
486#endif
487 printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status);
488
489#define PIS(x) \
490 if (status & DSI_VC_IRQ_##x) \
491 printk(#x " ");
492 PIS(CS);
493 PIS(ECC_CORR);
494#ifdef VERBOSE_IRQ
495 PIS(PACKET_SENT);
496#endif
497 PIS(FIFO_TX_OVF);
498 PIS(FIFO_RX_OVF);
499 PIS(BTA);
500 PIS(ECC_NO_CORR);
501 PIS(FIFO_TX_UDF);
502 PIS(PP_BUSY_CHANGE);
503#undef PIS
504 printk("\n");
505}
506
507static void print_irq_status_cio(u32 status)
508{
509 printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status);
510
511#define PIS(x) \
512 if (status & DSI_CIO_IRQ_##x) \
513 printk(#x " ");
514 PIS(ERRSYNCESC1);
515 PIS(ERRSYNCESC2);
516 PIS(ERRSYNCESC3);
517 PIS(ERRESC1);
518 PIS(ERRESC2);
519 PIS(ERRESC3);
520 PIS(ERRCONTROL1);
521 PIS(ERRCONTROL2);
522 PIS(ERRCONTROL3);
523 PIS(STATEULPS1);
524 PIS(STATEULPS2);
525 PIS(STATEULPS3);
526 PIS(ERRCONTENTIONLP0_1);
527 PIS(ERRCONTENTIONLP1_1);
528 PIS(ERRCONTENTIONLP0_2);
529 PIS(ERRCONTENTIONLP1_2);
530 PIS(ERRCONTENTIONLP0_3);
531 PIS(ERRCONTENTIONLP1_3);
532 PIS(ULPSACTIVENOT_ALL0);
533 PIS(ULPSACTIVENOT_ALL1);
534#undef PIS
535
536 printk("\n");
537}
538
539static int debug_irq;
540
541/* called from dss */
542void dsi_irq_handler(void)
543{
544 u32 irqstatus, vcstatus, ciostatus;
545 int i;
546
547 irqstatus = dsi_read_reg(DSI_IRQSTATUS);
548
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +0200549#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
550 spin_lock(&dsi.irq_stats_lock);
551 dsi.irq_stats.irq_count++;
552 dss_collect_irq_stats(irqstatus, dsi.irq_stats.dsi_irqs);
553#endif
554
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200555 if (irqstatus & DSI_IRQ_ERROR_MASK) {
556 DSSERR("DSI error, irqstatus %x\n", irqstatus);
557 print_irq_status(irqstatus);
558 spin_lock(&dsi.errors_lock);
559 dsi.errors |= irqstatus & DSI_IRQ_ERROR_MASK;
560 spin_unlock(&dsi.errors_lock);
561 } else if (debug_irq) {
562 print_irq_status(irqstatus);
563 }
564
565#ifdef DSI_CATCH_MISSING_TE
566 if (irqstatus & DSI_IRQ_TE_TRIGGER)
567 del_timer(&dsi.te_timer);
568#endif
569
570 for (i = 0; i < 4; ++i) {
571 if ((irqstatus & (1<<i)) == 0)
572 continue;
573
574 vcstatus = dsi_read_reg(DSI_VC_IRQSTATUS(i));
575
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +0200576#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
577 dss_collect_irq_stats(vcstatus, dsi.irq_stats.vc_irqs[i]);
578#endif
579
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200580 if (vcstatus & DSI_VC_IRQ_BTA)
581 complete(&dsi.bta_completion);
582
583 if (vcstatus & DSI_VC_IRQ_ERROR_MASK) {
584 DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
585 i, vcstatus);
586 print_irq_status_vc(i, vcstatus);
587 } else if (debug_irq) {
588 print_irq_status_vc(i, vcstatus);
589 }
590
591 dsi_write_reg(DSI_VC_IRQSTATUS(i), vcstatus);
592 /* flush posted write */
593 dsi_read_reg(DSI_VC_IRQSTATUS(i));
594 }
595
596 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
597 ciostatus = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
598
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +0200599#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
600 dss_collect_irq_stats(ciostatus, dsi.irq_stats.cio_irqs);
601#endif
602
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200603 dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
604 /* flush posted write */
605 dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
606
607 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
608 print_irq_status_cio(ciostatus);
609 }
610
611 dsi_write_reg(DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
612 /* flush posted write */
613 dsi_read_reg(DSI_IRQSTATUS);
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +0200614
615#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
616 spin_unlock(&dsi.irq_stats_lock);
617#endif
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200618}
619
620
621static void _dsi_initialize_irq(void)
622{
623 u32 l;
624 int i;
625
626 /* disable all interrupts */
627 dsi_write_reg(DSI_IRQENABLE, 0);
628 for (i = 0; i < 4; ++i)
629 dsi_write_reg(DSI_VC_IRQENABLE(i), 0);
630 dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE, 0);
631
632 /* clear interrupt status */
633 l = dsi_read_reg(DSI_IRQSTATUS);
634 dsi_write_reg(DSI_IRQSTATUS, l & ~DSI_IRQ_CHANNEL_MASK);
635
636 for (i = 0; i < 4; ++i) {
637 l = dsi_read_reg(DSI_VC_IRQSTATUS(i));
638 dsi_write_reg(DSI_VC_IRQSTATUS(i), l);
639 }
640
641 l = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
642 dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, l);
643
644 /* enable error irqs */
645 l = DSI_IRQ_ERROR_MASK;
646#ifdef DSI_CATCH_MISSING_TE
647 l |= DSI_IRQ_TE_TRIGGER;
648#endif
649 dsi_write_reg(DSI_IRQENABLE, l);
650
651 l = DSI_VC_IRQ_ERROR_MASK;
652 for (i = 0; i < 4; ++i)
653 dsi_write_reg(DSI_VC_IRQENABLE(i), l);
654
655 /* XXX zonda responds incorrectly, causing control error:
656 Exit from LP-ESC mode to LP11 uses wrong transition states on the
657 data lines LP0 and LN0. */
658 dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE,
659 -1 & (~DSI_CIO_IRQ_ERRCONTROL2));
660}
661
662static u32 dsi_get_errors(void)
663{
664 unsigned long flags;
665 u32 e;
666 spin_lock_irqsave(&dsi.errors_lock, flags);
667 e = dsi.errors;
668 dsi.errors = 0;
669 spin_unlock_irqrestore(&dsi.errors_lock, flags);
670 return e;
671}
672
673static void dsi_vc_enable_bta_irq(int channel)
674{
675 u32 l;
676
677 dsi_write_reg(DSI_VC_IRQSTATUS(channel), DSI_VC_IRQ_BTA);
678
679 l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
680 l |= DSI_VC_IRQ_BTA;
681 dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
682}
683
684static void dsi_vc_disable_bta_irq(int channel)
685{
686 u32 l;
687
688 l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
689 l &= ~DSI_VC_IRQ_BTA;
690 dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
691}
692
693/* DSI func clock. this could also be DSI2_PLL_FCLK */
694static inline void enable_clocks(bool enable)
695{
696 if (enable)
697 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
698 else
699 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
700}
701
702/* source clock for DSI PLL. this could also be PCLKFREE */
703static inline void dsi_enable_pll_clock(bool enable)
704{
705 if (enable)
706 dss_clk_enable(DSS_CLK_FCK2);
707 else
708 dss_clk_disable(DSS_CLK_FCK2);
709
710 if (enable && dsi.pll_locked) {
711 if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1)
712 DSSERR("cannot lock PLL when enabling clocks\n");
713 }
714}
715
716#ifdef DEBUG
717static void _dsi_print_reset_status(void)
718{
719 u32 l;
720
721 if (!dss_debug)
722 return;
723
724 /* A dummy read using the SCP interface to any DSIPHY register is
725 * required after DSIPHY reset to complete the reset of the DSI complex
726 * I/O. */
727 l = dsi_read_reg(DSI_DSIPHY_CFG5);
728
729 printk(KERN_DEBUG "DSI resets: ");
730
731 l = dsi_read_reg(DSI_PLL_STATUS);
732 printk("PLL (%d) ", FLD_GET(l, 0, 0));
733
734 l = dsi_read_reg(DSI_COMPLEXIO_CFG1);
735 printk("CIO (%d) ", FLD_GET(l, 29, 29));
736
737 l = dsi_read_reg(DSI_DSIPHY_CFG5);
738 printk("PHY (%x, %d, %d, %d)\n",
739 FLD_GET(l, 28, 26),
740 FLD_GET(l, 29, 29),
741 FLD_GET(l, 30, 30),
742 FLD_GET(l, 31, 31));
743}
744#else
745#define _dsi_print_reset_status()
746#endif
747
748static inline int dsi_if_enable(bool enable)
749{
750 DSSDBG("dsi_if_enable(%d)\n", enable);
751
752 enable = enable ? 1 : 0;
753 REG_FLD_MOD(DSI_CTRL, enable, 0, 0); /* IF_EN */
754
755 if (wait_for_bit_change(DSI_CTRL, 0, enable) != enable) {
756 DSSERR("Failed to set dsi_if_enable to %d\n", enable);
757 return -EIO;
758 }
759
760 return 0;
761}
762
763unsigned long dsi_get_dsi1_pll_rate(void)
764{
765 return dsi.current_cinfo.dsi1_pll_fclk;
766}
767
768static unsigned long dsi_get_dsi2_pll_rate(void)
769{
770 return dsi.current_cinfo.dsi2_pll_fclk;
771}
772
773static unsigned long dsi_get_txbyteclkhs(void)
774{
775 return dsi.current_cinfo.clkin4ddr / 16;
776}
777
778static unsigned long dsi_fclk_rate(void)
779{
780 unsigned long r;
781
782 if (dss_get_dsi_clk_source() == 0) {
783 /* DSI FCLK source is DSS1_ALWON_FCK, which is dss1_fck */
784 r = dss_clk_get_rate(DSS_CLK_FCK1);
785 } else {
786 /* DSI FCLK source is DSI2_PLL_FCLK */
787 r = dsi_get_dsi2_pll_rate();
788 }
789
790 return r;
791}
792
793static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev)
794{
795 unsigned long dsi_fclk;
796 unsigned lp_clk_div;
797 unsigned long lp_clk;
798
799 lp_clk_div = dssdev->phy.dsi.div.lp_clk_div;
800
801 if (lp_clk_div == 0 || lp_clk_div > LP_DIV_MAX)
802 return -EINVAL;
803
804 dsi_fclk = dsi_fclk_rate();
805
806 lp_clk = dsi_fclk / 2 / lp_clk_div;
807
808 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
809 dsi.current_cinfo.lp_clk = lp_clk;
810 dsi.current_cinfo.lp_clk_div = lp_clk_div;
811
812 REG_FLD_MOD(DSI_CLK_CTRL, lp_clk_div, 12, 0); /* LP_CLK_DIVISOR */
813
814 REG_FLD_MOD(DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0,
815 21, 21); /* LP_RX_SYNCHRO_ENABLE */
816
817 return 0;
818}
819
820
821enum dsi_pll_power_state {
822 DSI_PLL_POWER_OFF = 0x0,
823 DSI_PLL_POWER_ON_HSCLK = 0x1,
824 DSI_PLL_POWER_ON_ALL = 0x2,
825 DSI_PLL_POWER_ON_DIV = 0x3,
826};
827
828static int dsi_pll_power(enum dsi_pll_power_state state)
829{
830 int t = 0;
831
832 REG_FLD_MOD(DSI_CLK_CTRL, state, 31, 30); /* PLL_PWR_CMD */
833
834 /* PLL_PWR_STATUS */
835 while (FLD_GET(dsi_read_reg(DSI_CLK_CTRL), 29, 28) != state) {
Tomi Valkeinen24be78b2010-01-07 14:19:48 +0200836 if (++t > 1000) {
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200837 DSSERR("Failed to set DSI PLL power mode to %d\n",
838 state);
839 return -ENODEV;
840 }
Tomi Valkeinen24be78b2010-01-07 14:19:48 +0200841 udelay(1);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200842 }
843
844 return 0;
845}
846
847/* calculate clock rates using dividers in cinfo */
848static int dsi_calc_clock_rates(struct dsi_clock_info *cinfo)
849{
850 if (cinfo->regn == 0 || cinfo->regn > REGN_MAX)
851 return -EINVAL;
852
853 if (cinfo->regm == 0 || cinfo->regm > REGM_MAX)
854 return -EINVAL;
855
856 if (cinfo->regm3 > REGM3_MAX)
857 return -EINVAL;
858
859 if (cinfo->regm4 > REGM4_MAX)
860 return -EINVAL;
861
862 if (cinfo->use_dss2_fck) {
863 cinfo->clkin = dss_clk_get_rate(DSS_CLK_FCK2);
864 /* XXX it is unclear if highfreq should be used
865 * with DSS2_FCK source also */
866 cinfo->highfreq = 0;
867 } else {
868 cinfo->clkin = dispc_pclk_rate();
869
870 if (cinfo->clkin < 32000000)
871 cinfo->highfreq = 0;
872 else
873 cinfo->highfreq = 1;
874 }
875
876 cinfo->fint = cinfo->clkin / (cinfo->regn * (cinfo->highfreq ? 2 : 1));
877
878 if (cinfo->fint > FINT_MAX || cinfo->fint < FINT_MIN)
879 return -EINVAL;
880
881 cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint;
882
883 if (cinfo->clkin4ddr > 1800 * 1000 * 1000)
884 return -EINVAL;
885
886 if (cinfo->regm3 > 0)
887 cinfo->dsi1_pll_fclk = cinfo->clkin4ddr / cinfo->regm3;
888 else
889 cinfo->dsi1_pll_fclk = 0;
890
891 if (cinfo->regm4 > 0)
892 cinfo->dsi2_pll_fclk = cinfo->clkin4ddr / cinfo->regm4;
893 else
894 cinfo->dsi2_pll_fclk = 0;
895
896 return 0;
897}
898
899int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck,
900 struct dsi_clock_info *dsi_cinfo,
901 struct dispc_clock_info *dispc_cinfo)
902{
903 struct dsi_clock_info cur, best;
904 struct dispc_clock_info best_dispc;
905 int min_fck_per_pck;
906 int match = 0;
907 unsigned long dss_clk_fck2;
908
909 dss_clk_fck2 = dss_clk_get_rate(DSS_CLK_FCK2);
910
911 if (req_pck == dsi.cache_req_pck &&
912 dsi.cache_cinfo.clkin == dss_clk_fck2) {
913 DSSDBG("DSI clock info found from cache\n");
914 *dsi_cinfo = dsi.cache_cinfo;
915 dispc_find_clk_divs(is_tft, req_pck, dsi_cinfo->dsi1_pll_fclk,
916 dispc_cinfo);
917 return 0;
918 }
919
920 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
921
922 if (min_fck_per_pck &&
923 req_pck * min_fck_per_pck > DISPC_MAX_FCK) {
924 DSSERR("Requested pixel clock not possible with the current "
925 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
926 "the constraint off.\n");
927 min_fck_per_pck = 0;
928 }
929
930 DSSDBG("dsi_pll_calc\n");
931
932retry:
933 memset(&best, 0, sizeof(best));
934 memset(&best_dispc, 0, sizeof(best_dispc));
935
936 memset(&cur, 0, sizeof(cur));
937 cur.clkin = dss_clk_fck2;
938 cur.use_dss2_fck = 1;
939 cur.highfreq = 0;
940
941 /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
942 /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
943 /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
944 for (cur.regn = 1; cur.regn < REGN_MAX; ++cur.regn) {
945 if (cur.highfreq == 0)
946 cur.fint = cur.clkin / cur.regn;
947 else
948 cur.fint = cur.clkin / (2 * cur.regn);
949
950 if (cur.fint > FINT_MAX || cur.fint < FINT_MIN)
951 continue;
952
953 /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
954 for (cur.regm = 1; cur.regm < REGM_MAX; ++cur.regm) {
955 unsigned long a, b;
956
957 a = 2 * cur.regm * (cur.clkin/1000);
958 b = cur.regn * (cur.highfreq + 1);
959 cur.clkin4ddr = a / b * 1000;
960
961 if (cur.clkin4ddr > 1800 * 1000 * 1000)
962 break;
963
964 /* DSI1_PLL_FCLK(MHz) = DSIPHY(MHz) / regm3 < 173MHz */
965 for (cur.regm3 = 1; cur.regm3 < REGM3_MAX;
966 ++cur.regm3) {
967 struct dispc_clock_info cur_dispc;
968 cur.dsi1_pll_fclk = cur.clkin4ddr / cur.regm3;
969
970 /* this will narrow down the search a bit,
971 * but still give pixclocks below what was
972 * requested */
973 if (cur.dsi1_pll_fclk < req_pck)
974 break;
975
976 if (cur.dsi1_pll_fclk > DISPC_MAX_FCK)
977 continue;
978
979 if (min_fck_per_pck &&
980 cur.dsi1_pll_fclk <
981 req_pck * min_fck_per_pck)
982 continue;
983
984 match = 1;
985
986 dispc_find_clk_divs(is_tft, req_pck,
987 cur.dsi1_pll_fclk,
988 &cur_dispc);
989
990 if (abs(cur_dispc.pck - req_pck) <
991 abs(best_dispc.pck - req_pck)) {
992 best = cur;
993 best_dispc = cur_dispc;
994
995 if (cur_dispc.pck == req_pck)
996 goto found;
997 }
998 }
999 }
1000 }
1001found:
1002 if (!match) {
1003 if (min_fck_per_pck) {
1004 DSSERR("Could not find suitable clock settings.\n"
1005 "Turning FCK/PCK constraint off and"
1006 "trying again.\n");
1007 min_fck_per_pck = 0;
1008 goto retry;
1009 }
1010
1011 DSSERR("Could not find suitable clock settings.\n");
1012
1013 return -EINVAL;
1014 }
1015
1016 /* DSI2_PLL_FCLK (regm4) is not used */
1017 best.regm4 = 0;
1018 best.dsi2_pll_fclk = 0;
1019
1020 if (dsi_cinfo)
1021 *dsi_cinfo = best;
1022 if (dispc_cinfo)
1023 *dispc_cinfo = best_dispc;
1024
1025 dsi.cache_req_pck = req_pck;
1026 dsi.cache_clk_freq = 0;
1027 dsi.cache_cinfo = best;
1028
1029 return 0;
1030}
1031
1032int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo)
1033{
1034 int r = 0;
1035 u32 l;
1036 int f;
1037
1038 DSSDBGF();
1039
1040 dsi.current_cinfo.fint = cinfo->fint;
1041 dsi.current_cinfo.clkin4ddr = cinfo->clkin4ddr;
1042 dsi.current_cinfo.dsi1_pll_fclk = cinfo->dsi1_pll_fclk;
1043 dsi.current_cinfo.dsi2_pll_fclk = cinfo->dsi2_pll_fclk;
1044
1045 dsi.current_cinfo.regn = cinfo->regn;
1046 dsi.current_cinfo.regm = cinfo->regm;
1047 dsi.current_cinfo.regm3 = cinfo->regm3;
1048 dsi.current_cinfo.regm4 = cinfo->regm4;
1049
1050 DSSDBG("DSI Fint %ld\n", cinfo->fint);
1051
1052 DSSDBG("clkin (%s) rate %ld, highfreq %d\n",
1053 cinfo->use_dss2_fck ? "dss2_fck" : "pclkfree",
1054 cinfo->clkin,
1055 cinfo->highfreq);
1056
1057 /* DSIPHY == CLKIN4DDR */
1058 DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu / %d = %lu\n",
1059 cinfo->regm,
1060 cinfo->regn,
1061 cinfo->clkin,
1062 cinfo->highfreq + 1,
1063 cinfo->clkin4ddr);
1064
1065 DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
1066 cinfo->clkin4ddr / 1000 / 1000 / 2);
1067
1068 DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);
1069
1070 DSSDBG("regm3 = %d, dsi1_pll_fclk = %lu\n",
1071 cinfo->regm3, cinfo->dsi1_pll_fclk);
1072 DSSDBG("regm4 = %d, dsi2_pll_fclk = %lu\n",
1073 cinfo->regm4, cinfo->dsi2_pll_fclk);
1074
1075 REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */
1076
1077 l = dsi_read_reg(DSI_PLL_CONFIGURATION1);
1078 l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */
1079 l = FLD_MOD(l, cinfo->regn - 1, 7, 1); /* DSI_PLL_REGN */
1080 l = FLD_MOD(l, cinfo->regm, 18, 8); /* DSI_PLL_REGM */
1081 l = FLD_MOD(l, cinfo->regm3 > 0 ? cinfo->regm3 - 1 : 0,
1082 22, 19); /* DSI_CLOCK_DIV */
1083 l = FLD_MOD(l, cinfo->regm4 > 0 ? cinfo->regm4 - 1 : 0,
1084 26, 23); /* DSIPROTO_CLOCK_DIV */
1085 dsi_write_reg(DSI_PLL_CONFIGURATION1, l);
1086
1087 BUG_ON(cinfo->fint < 750000 || cinfo->fint > 2100000);
1088 if (cinfo->fint < 1000000)
1089 f = 0x3;
1090 else if (cinfo->fint < 1250000)
1091 f = 0x4;
1092 else if (cinfo->fint < 1500000)
1093 f = 0x5;
1094 else if (cinfo->fint < 1750000)
1095 f = 0x6;
1096 else
1097 f = 0x7;
1098
1099 l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
1100 l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */
1101 l = FLD_MOD(l, cinfo->use_dss2_fck ? 0 : 1,
1102 11, 11); /* DSI_PLL_CLKSEL */
1103 l = FLD_MOD(l, cinfo->highfreq,
1104 12, 12); /* DSI_PLL_HIGHFREQ */
1105 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1106 l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */
1107 l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */
1108 dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
1109
1110 REG_FLD_MOD(DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */
1111
1112 if (wait_for_bit_change(DSI_PLL_GO, 0, 0) != 0) {
1113 DSSERR("dsi pll go bit not going down.\n");
1114 r = -EIO;
1115 goto err;
1116 }
1117
1118 if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1) {
1119 DSSERR("cannot lock PLL\n");
1120 r = -EIO;
1121 goto err;
1122 }
1123
1124 dsi.pll_locked = 1;
1125
1126 l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
1127 l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */
1128 l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */
1129 l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */
1130 l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */
1131 l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */
1132 l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */
1133 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1134 l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */
1135 l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */
1136 l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */
1137 l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */
1138 l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */
1139 l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */
1140 l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */
1141 dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
1142
1143 DSSDBG("PLL config done\n");
1144err:
1145 return r;
1146}
1147
1148int dsi_pll_init(struct omap_dss_device *dssdev, bool enable_hsclk,
1149 bool enable_hsdiv)
1150{
1151 int r = 0;
1152 enum dsi_pll_power_state pwstate;
1153
1154 DSSDBG("PLL init\n");
1155
1156 enable_clocks(1);
1157 dsi_enable_pll_clock(1);
1158
1159 r = regulator_enable(dsi.vdds_dsi_reg);
1160 if (r)
1161 goto err0;
1162
1163 /* XXX PLL does not come out of reset without this... */
1164 dispc_pck_free_enable(1);
1165
1166 if (wait_for_bit_change(DSI_PLL_STATUS, 0, 1) != 1) {
1167 DSSERR("PLL not coming out of reset.\n");
1168 r = -ENODEV;
1169 goto err1;
1170 }
1171
1172 /* XXX ... but if left on, we get problems when planes do not
1173 * fill the whole display. No idea about this */
1174 dispc_pck_free_enable(0);
1175
1176 if (enable_hsclk && enable_hsdiv)
1177 pwstate = DSI_PLL_POWER_ON_ALL;
1178 else if (enable_hsclk)
1179 pwstate = DSI_PLL_POWER_ON_HSCLK;
1180 else if (enable_hsdiv)
1181 pwstate = DSI_PLL_POWER_ON_DIV;
1182 else
1183 pwstate = DSI_PLL_POWER_OFF;
1184
1185 r = dsi_pll_power(pwstate);
1186
1187 if (r)
1188 goto err1;
1189
1190 DSSDBG("PLL init done\n");
1191
1192 return 0;
1193err1:
1194 regulator_disable(dsi.vdds_dsi_reg);
1195err0:
1196 enable_clocks(0);
1197 dsi_enable_pll_clock(0);
1198 return r;
1199}
1200
1201void dsi_pll_uninit(void)
1202{
1203 enable_clocks(0);
1204 dsi_enable_pll_clock(0);
1205
1206 dsi.pll_locked = 0;
1207 dsi_pll_power(DSI_PLL_POWER_OFF);
1208 regulator_disable(dsi.vdds_dsi_reg);
1209 DSSDBG("PLL uninit done\n");
1210}
1211
1212void dsi_dump_clocks(struct seq_file *s)
1213{
1214 int clksel;
1215 struct dsi_clock_info *cinfo = &dsi.current_cinfo;
1216
1217 enable_clocks(1);
1218
1219 clksel = REG_GET(DSI_PLL_CONFIGURATION2, 11, 11);
1220
1221 seq_printf(s, "- DSI PLL -\n");
1222
1223 seq_printf(s, "dsi pll source = %s\n",
1224 clksel == 0 ?
1225 "dss2_alwon_fclk" : "pclkfree");
1226
1227 seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);
1228
1229 seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n",
1230 cinfo->clkin4ddr, cinfo->regm);
1231
1232 seq_printf(s, "dsi1_pll_fck\t%-16luregm3 %u\t(%s)\n",
1233 cinfo->dsi1_pll_fclk,
1234 cinfo->regm3,
1235 dss_get_dispc_clk_source() == 0 ? "off" : "on");
1236
1237 seq_printf(s, "dsi2_pll_fck\t%-16luregm4 %u\t(%s)\n",
1238 cinfo->dsi2_pll_fclk,
1239 cinfo->regm4,
1240 dss_get_dsi_clk_source() == 0 ? "off" : "on");
1241
1242 seq_printf(s, "- DSI -\n");
1243
1244 seq_printf(s, "dsi fclk source = %s\n",
1245 dss_get_dsi_clk_source() == 0 ?
1246 "dss1_alwon_fclk" : "dsi2_pll_fclk");
1247
1248 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate());
1249
1250 seq_printf(s, "DDR_CLK\t\t%lu\n",
1251 cinfo->clkin4ddr / 4);
1252
1253 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs());
1254
1255 seq_printf(s, "LP_CLK\t\t%lu\n", cinfo->lp_clk);
1256
1257 seq_printf(s, "VP_CLK\t\t%lu\n"
1258 "VP_PCLK\t\t%lu\n",
1259 dispc_lclk_rate(),
1260 dispc_pclk_rate());
1261
1262 enable_clocks(0);
1263}
1264
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +02001265#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1266void dsi_dump_irqs(struct seq_file *s)
1267{
1268 unsigned long flags;
1269 struct dsi_irq_stats stats;
1270
1271 spin_lock_irqsave(&dsi.irq_stats_lock, flags);
1272
1273 stats = dsi.irq_stats;
1274 memset(&dsi.irq_stats, 0, sizeof(dsi.irq_stats));
1275 dsi.irq_stats.last_reset = jiffies;
1276
1277 spin_unlock_irqrestore(&dsi.irq_stats_lock, flags);
1278
1279 seq_printf(s, "period %u ms\n",
1280 jiffies_to_msecs(jiffies - stats.last_reset));
1281
1282 seq_printf(s, "irqs %d\n", stats.irq_count);
1283#define PIS(x) \
1284 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1285
1286 seq_printf(s, "-- DSI interrupts --\n");
1287 PIS(VC0);
1288 PIS(VC1);
1289 PIS(VC2);
1290 PIS(VC3);
1291 PIS(WAKEUP);
1292 PIS(RESYNC);
1293 PIS(PLL_LOCK);
1294 PIS(PLL_UNLOCK);
1295 PIS(PLL_RECALL);
1296 PIS(COMPLEXIO_ERR);
1297 PIS(HS_TX_TIMEOUT);
1298 PIS(LP_RX_TIMEOUT);
1299 PIS(TE_TRIGGER);
1300 PIS(ACK_TRIGGER);
1301 PIS(SYNC_LOST);
1302 PIS(LDO_POWER_GOOD);
1303 PIS(TA_TIMEOUT);
1304#undef PIS
1305
1306#define PIS(x) \
1307 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1308 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1309 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1310 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1311 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1312
1313 seq_printf(s, "-- VC interrupts --\n");
1314 PIS(CS);
1315 PIS(ECC_CORR);
1316 PIS(PACKET_SENT);
1317 PIS(FIFO_TX_OVF);
1318 PIS(FIFO_RX_OVF);
1319 PIS(BTA);
1320 PIS(ECC_NO_CORR);
1321 PIS(FIFO_TX_UDF);
1322 PIS(PP_BUSY_CHANGE);
1323#undef PIS
1324
1325#define PIS(x) \
1326 seq_printf(s, "%-20s %10d\n", #x, \
1327 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1328
1329 seq_printf(s, "-- CIO interrupts --\n");
1330 PIS(ERRSYNCESC1);
1331 PIS(ERRSYNCESC2);
1332 PIS(ERRSYNCESC3);
1333 PIS(ERRESC1);
1334 PIS(ERRESC2);
1335 PIS(ERRESC3);
1336 PIS(ERRCONTROL1);
1337 PIS(ERRCONTROL2);
1338 PIS(ERRCONTROL3);
1339 PIS(STATEULPS1);
1340 PIS(STATEULPS2);
1341 PIS(STATEULPS3);
1342 PIS(ERRCONTENTIONLP0_1);
1343 PIS(ERRCONTENTIONLP1_1);
1344 PIS(ERRCONTENTIONLP0_2);
1345 PIS(ERRCONTENTIONLP1_2);
1346 PIS(ERRCONTENTIONLP0_3);
1347 PIS(ERRCONTENTIONLP1_3);
1348 PIS(ULPSACTIVENOT_ALL0);
1349 PIS(ULPSACTIVENOT_ALL1);
1350#undef PIS
1351}
1352#endif
1353
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001354void dsi_dump_regs(struct seq_file *s)
1355{
1356#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(r))
1357
1358 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
1359
1360 DUMPREG(DSI_REVISION);
1361 DUMPREG(DSI_SYSCONFIG);
1362 DUMPREG(DSI_SYSSTATUS);
1363 DUMPREG(DSI_IRQSTATUS);
1364 DUMPREG(DSI_IRQENABLE);
1365 DUMPREG(DSI_CTRL);
1366 DUMPREG(DSI_COMPLEXIO_CFG1);
1367 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1368 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1369 DUMPREG(DSI_CLK_CTRL);
1370 DUMPREG(DSI_TIMING1);
1371 DUMPREG(DSI_TIMING2);
1372 DUMPREG(DSI_VM_TIMING1);
1373 DUMPREG(DSI_VM_TIMING2);
1374 DUMPREG(DSI_VM_TIMING3);
1375 DUMPREG(DSI_CLK_TIMING);
1376 DUMPREG(DSI_TX_FIFO_VC_SIZE);
1377 DUMPREG(DSI_RX_FIFO_VC_SIZE);
1378 DUMPREG(DSI_COMPLEXIO_CFG2);
1379 DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1380 DUMPREG(DSI_VM_TIMING4);
1381 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1382 DUMPREG(DSI_VM_TIMING5);
1383 DUMPREG(DSI_VM_TIMING6);
1384 DUMPREG(DSI_VM_TIMING7);
1385 DUMPREG(DSI_STOPCLK_TIMING);
1386
1387 DUMPREG(DSI_VC_CTRL(0));
1388 DUMPREG(DSI_VC_TE(0));
1389 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1390 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1391 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1392 DUMPREG(DSI_VC_IRQSTATUS(0));
1393 DUMPREG(DSI_VC_IRQENABLE(0));
1394
1395 DUMPREG(DSI_VC_CTRL(1));
1396 DUMPREG(DSI_VC_TE(1));
1397 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1398 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1399 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1400 DUMPREG(DSI_VC_IRQSTATUS(1));
1401 DUMPREG(DSI_VC_IRQENABLE(1));
1402
1403 DUMPREG(DSI_VC_CTRL(2));
1404 DUMPREG(DSI_VC_TE(2));
1405 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1406 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1407 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1408 DUMPREG(DSI_VC_IRQSTATUS(2));
1409 DUMPREG(DSI_VC_IRQENABLE(2));
1410
1411 DUMPREG(DSI_VC_CTRL(3));
1412 DUMPREG(DSI_VC_TE(3));
1413 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1414 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1415 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1416 DUMPREG(DSI_VC_IRQSTATUS(3));
1417 DUMPREG(DSI_VC_IRQENABLE(3));
1418
1419 DUMPREG(DSI_DSIPHY_CFG0);
1420 DUMPREG(DSI_DSIPHY_CFG1);
1421 DUMPREG(DSI_DSIPHY_CFG2);
1422 DUMPREG(DSI_DSIPHY_CFG5);
1423
1424 DUMPREG(DSI_PLL_CONTROL);
1425 DUMPREG(DSI_PLL_STATUS);
1426 DUMPREG(DSI_PLL_GO);
1427 DUMPREG(DSI_PLL_CONFIGURATION1);
1428 DUMPREG(DSI_PLL_CONFIGURATION2);
1429
1430 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
1431#undef DUMPREG
1432}
1433
1434enum dsi_complexio_power_state {
1435 DSI_COMPLEXIO_POWER_OFF = 0x0,
1436 DSI_COMPLEXIO_POWER_ON = 0x1,
1437 DSI_COMPLEXIO_POWER_ULPS = 0x2,
1438};
1439
1440static int dsi_complexio_power(enum dsi_complexio_power_state state)
1441{
1442 int t = 0;
1443
1444 /* PWR_CMD */
1445 REG_FLD_MOD(DSI_COMPLEXIO_CFG1, state, 28, 27);
1446
1447 /* PWR_STATUS */
1448 while (FLD_GET(dsi_read_reg(DSI_COMPLEXIO_CFG1), 26, 25) != state) {
Tomi Valkeinen24be78b2010-01-07 14:19:48 +02001449 if (++t > 1000) {
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001450 DSSERR("failed to set complexio power state to "
1451 "%d\n", state);
1452 return -ENODEV;
1453 }
Tomi Valkeinen24be78b2010-01-07 14:19:48 +02001454 udelay(1);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001455 }
1456
1457 return 0;
1458}
1459
1460static void dsi_complexio_config(struct omap_dss_device *dssdev)
1461{
1462 u32 r;
1463
1464 int clk_lane = dssdev->phy.dsi.clk_lane;
1465 int data1_lane = dssdev->phy.dsi.data1_lane;
1466 int data2_lane = dssdev->phy.dsi.data2_lane;
1467 int clk_pol = dssdev->phy.dsi.clk_pol;
1468 int data1_pol = dssdev->phy.dsi.data1_pol;
1469 int data2_pol = dssdev->phy.dsi.data2_pol;
1470
1471 r = dsi_read_reg(DSI_COMPLEXIO_CFG1);
1472 r = FLD_MOD(r, clk_lane, 2, 0);
1473 r = FLD_MOD(r, clk_pol, 3, 3);
1474 r = FLD_MOD(r, data1_lane, 6, 4);
1475 r = FLD_MOD(r, data1_pol, 7, 7);
1476 r = FLD_MOD(r, data2_lane, 10, 8);
1477 r = FLD_MOD(r, data2_pol, 11, 11);
1478 dsi_write_reg(DSI_COMPLEXIO_CFG1, r);
1479
1480 /* The configuration of the DSI complex I/O (number of data lanes,
1481 position, differential order) should not be changed while
1482 DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. In order for
1483 the hardware to take into account a new configuration of the complex
1484 I/O (done in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to
1485 follow this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1,
1486 then reset the DSS.DSI_CTRL[0] IF_EN to 0, then set
1487 DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE to 1 and finally set again the
1488 DSS.DSI_CTRL[0] IF_EN bit to 1. If the sequence is not followed, the
1489 DSI complex I/O configuration is unknown. */
1490
1491 /*
1492 REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
1493 REG_FLD_MOD(DSI_CTRL, 0, 0, 0);
1494 REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20);
1495 REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
1496 */
1497}
1498
1499static inline unsigned ns2ddr(unsigned ns)
1500{
1501 /* convert time in ns to ddr ticks, rounding up */
1502 unsigned long ddr_clk = dsi.current_cinfo.clkin4ddr / 4;
1503 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
1504}
1505
1506static inline unsigned ddr2ns(unsigned ddr)
1507{
1508 unsigned long ddr_clk = dsi.current_cinfo.clkin4ddr / 4;
1509 return ddr * 1000 * 1000 / (ddr_clk / 1000);
1510}
1511
1512static void dsi_complexio_timings(void)
1513{
1514 u32 r;
1515 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
1516 u32 tlpx_half, tclk_trail, tclk_zero;
1517 u32 tclk_prepare;
1518
1519 /* calculate timings */
1520
1521 /* 1 * DDR_CLK = 2 * UI */
1522
1523 /* min 40ns + 4*UI max 85ns + 6*UI */
1524 ths_prepare = ns2ddr(70) + 2;
1525
1526 /* min 145ns + 10*UI */
1527 ths_prepare_ths_zero = ns2ddr(175) + 2;
1528
1529 /* min max(8*UI, 60ns+4*UI) */
1530 ths_trail = ns2ddr(60) + 5;
1531
1532 /* min 100ns */
1533 ths_exit = ns2ddr(145);
1534
1535 /* tlpx min 50n */
1536 tlpx_half = ns2ddr(25);
1537
1538 /* min 60ns */
1539 tclk_trail = ns2ddr(60) + 2;
1540
1541 /* min 38ns, max 95ns */
1542 tclk_prepare = ns2ddr(65);
1543
1544 /* min tclk-prepare + tclk-zero = 300ns */
1545 tclk_zero = ns2ddr(260);
1546
1547 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
1548 ths_prepare, ddr2ns(ths_prepare),
1549 ths_prepare_ths_zero, ddr2ns(ths_prepare_ths_zero));
1550 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
1551 ths_trail, ddr2ns(ths_trail),
1552 ths_exit, ddr2ns(ths_exit));
1553
1554 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
1555 "tclk_zero %u (%uns)\n",
1556 tlpx_half, ddr2ns(tlpx_half),
1557 tclk_trail, ddr2ns(tclk_trail),
1558 tclk_zero, ddr2ns(tclk_zero));
1559 DSSDBG("tclk_prepare %u (%uns)\n",
1560 tclk_prepare, ddr2ns(tclk_prepare));
1561
1562 /* program timings */
1563
1564 r = dsi_read_reg(DSI_DSIPHY_CFG0);
1565 r = FLD_MOD(r, ths_prepare, 31, 24);
1566 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
1567 r = FLD_MOD(r, ths_trail, 15, 8);
1568 r = FLD_MOD(r, ths_exit, 7, 0);
1569 dsi_write_reg(DSI_DSIPHY_CFG0, r);
1570
1571 r = dsi_read_reg(DSI_DSIPHY_CFG1);
1572 r = FLD_MOD(r, tlpx_half, 22, 16);
1573 r = FLD_MOD(r, tclk_trail, 15, 8);
1574 r = FLD_MOD(r, tclk_zero, 7, 0);
1575 dsi_write_reg(DSI_DSIPHY_CFG1, r);
1576
1577 r = dsi_read_reg(DSI_DSIPHY_CFG2);
1578 r = FLD_MOD(r, tclk_prepare, 7, 0);
1579 dsi_write_reg(DSI_DSIPHY_CFG2, r);
1580}
1581
1582
1583static int dsi_complexio_init(struct omap_dss_device *dssdev)
1584{
1585 int r = 0;
1586
1587 DSSDBG("dsi_complexio_init\n");
1588
1589 /* CIO_CLK_ICG, enable L3 clk to CIO */
1590 REG_FLD_MOD(DSI_CLK_CTRL, 1, 14, 14);
1591
1592 /* A dummy read using the SCP interface to any DSIPHY register is
1593 * required after DSIPHY reset to complete the reset of the DSI complex
1594 * I/O. */
1595 dsi_read_reg(DSI_DSIPHY_CFG5);
1596
1597 if (wait_for_bit_change(DSI_DSIPHY_CFG5, 30, 1) != 1) {
1598 DSSERR("ComplexIO PHY not coming out of reset.\n");
1599 r = -ENODEV;
1600 goto err;
1601 }
1602
1603 dsi_complexio_config(dssdev);
1604
1605 r = dsi_complexio_power(DSI_COMPLEXIO_POWER_ON);
1606
1607 if (r)
1608 goto err;
1609
1610 if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
1611 DSSERR("ComplexIO not coming out of reset.\n");
1612 r = -ENODEV;
1613 goto err;
1614 }
1615
1616 if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 21, 1) != 1) {
1617 DSSERR("ComplexIO LDO power down.\n");
1618 r = -ENODEV;
1619 goto err;
1620 }
1621
1622 dsi_complexio_timings();
1623
1624 /*
1625 The configuration of the DSI complex I/O (number of data lanes,
1626 position, differential order) should not be changed while
1627 DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. For the
1628 hardware to recognize a new configuration of the complex I/O (done
1629 in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to follow
1630 this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1, next
1631 reset the DSS.DSI_CTRL[0] IF_EN to 0, then set DSS.DSI_CLK_CTRL[20]
1632 LP_CLK_ENABLE to 1, and finally, set again the DSS.DSI_CTRL[0] IF_EN
1633 bit to 1. If the sequence is not followed, the DSi complex I/O
1634 configuration is undetermined.
1635 */
1636 dsi_if_enable(1);
1637 dsi_if_enable(0);
1638 REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
1639 dsi_if_enable(1);
1640 dsi_if_enable(0);
1641
1642 DSSDBG("CIO init done\n");
1643err:
1644 return r;
1645}
1646
1647static void dsi_complexio_uninit(void)
1648{
1649 dsi_complexio_power(DSI_COMPLEXIO_POWER_OFF);
1650}
1651
1652static int _dsi_wait_reset(void)
1653{
Tomi Valkeinen24be78b2010-01-07 14:19:48 +02001654 int t = 0;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001655
1656 while (REG_GET(DSI_SYSSTATUS, 0, 0) == 0) {
Tomi Valkeinen24be78b2010-01-07 14:19:48 +02001657 if (++t > 5) {
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001658 DSSERR("soft reset failed\n");
1659 return -ENODEV;
1660 }
1661 udelay(1);
1662 }
1663
1664 return 0;
1665}
1666
1667static int _dsi_reset(void)
1668{
1669 /* Soft reset */
1670 REG_FLD_MOD(DSI_SYSCONFIG, 1, 1, 1);
1671 return _dsi_wait_reset();
1672}
1673
1674static void dsi_reset_tx_fifo(int channel)
1675{
1676 u32 mask;
1677 u32 l;
1678
1679 /* set fifosize of the channel to 0, then return the old size */
1680 l = dsi_read_reg(DSI_TX_FIFO_VC_SIZE);
1681
1682 mask = FLD_MASK((8 * channel) + 7, (8 * channel) + 4);
1683 dsi_write_reg(DSI_TX_FIFO_VC_SIZE, l & ~mask);
1684
1685 dsi_write_reg(DSI_TX_FIFO_VC_SIZE, l);
1686}
1687
1688static void dsi_config_tx_fifo(enum fifo_size size1, enum fifo_size size2,
1689 enum fifo_size size3, enum fifo_size size4)
1690{
1691 u32 r = 0;
1692 int add = 0;
1693 int i;
1694
1695 dsi.vc[0].fifo_size = size1;
1696 dsi.vc[1].fifo_size = size2;
1697 dsi.vc[2].fifo_size = size3;
1698 dsi.vc[3].fifo_size = size4;
1699
1700 for (i = 0; i < 4; i++) {
1701 u8 v;
1702 int size = dsi.vc[i].fifo_size;
1703
1704 if (add + size > 4) {
1705 DSSERR("Illegal FIFO configuration\n");
1706 BUG();
1707 }
1708
1709 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
1710 r |= v << (8 * i);
1711 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
1712 add += size;
1713 }
1714
1715 dsi_write_reg(DSI_TX_FIFO_VC_SIZE, r);
1716}
1717
1718static void dsi_config_rx_fifo(enum fifo_size size1, enum fifo_size size2,
1719 enum fifo_size size3, enum fifo_size size4)
1720{
1721 u32 r = 0;
1722 int add = 0;
1723 int i;
1724
1725 dsi.vc[0].fifo_size = size1;
1726 dsi.vc[1].fifo_size = size2;
1727 dsi.vc[2].fifo_size = size3;
1728 dsi.vc[3].fifo_size = size4;
1729
1730 for (i = 0; i < 4; i++) {
1731 u8 v;
1732 int size = dsi.vc[i].fifo_size;
1733
1734 if (add + size > 4) {
1735 DSSERR("Illegal FIFO configuration\n");
1736 BUG();
1737 }
1738
1739 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
1740 r |= v << (8 * i);
1741 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
1742 add += size;
1743 }
1744
1745 dsi_write_reg(DSI_RX_FIFO_VC_SIZE, r);
1746}
1747
1748static int dsi_force_tx_stop_mode_io(void)
1749{
1750 u32 r;
1751
1752 r = dsi_read_reg(DSI_TIMING1);
1753 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
1754 dsi_write_reg(DSI_TIMING1, r);
1755
1756 if (wait_for_bit_change(DSI_TIMING1, 15, 0) != 0) {
1757 DSSERR("TX_STOP bit not going down\n");
1758 return -EIO;
1759 }
1760
1761 return 0;
1762}
1763
1764static void dsi_vc_print_status(int channel)
1765{
1766 u32 r;
1767
1768 r = dsi_read_reg(DSI_VC_CTRL(channel));
1769 DSSDBG("vc %d: TX_FIFO_NOT_EMPTY %d, BTA_EN %d, VC_BUSY %d, "
1770 "TX_FIFO_FULL %d, RX_FIFO_NOT_EMPTY %d, ",
1771 channel,
1772 FLD_GET(r, 5, 5),
1773 FLD_GET(r, 6, 6),
1774 FLD_GET(r, 15, 15),
1775 FLD_GET(r, 16, 16),
1776 FLD_GET(r, 20, 20));
1777
1778 r = dsi_read_reg(DSI_TX_FIFO_VC_EMPTINESS);
1779 DSSDBG("EMPTINESS %d\n", (r >> (8 * channel)) & 0xff);
1780}
1781
1782static int dsi_vc_enable(int channel, bool enable)
1783{
1784 if (dsi.update_mode != OMAP_DSS_UPDATE_AUTO)
1785 DSSDBG("dsi_vc_enable channel %d, enable %d\n",
1786 channel, enable);
1787
1788 enable = enable ? 1 : 0;
1789
1790 REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 0, 0);
1791
1792 if (wait_for_bit_change(DSI_VC_CTRL(channel), 0, enable) != enable) {
1793 DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
1794 return -EIO;
1795 }
1796
1797 return 0;
1798}
1799
1800static void dsi_vc_initial_config(int channel)
1801{
1802 u32 r;
1803
1804 DSSDBGF("%d", channel);
1805
1806 r = dsi_read_reg(DSI_VC_CTRL(channel));
1807
1808 if (FLD_GET(r, 15, 15)) /* VC_BUSY */
1809 DSSERR("VC(%d) busy when trying to configure it!\n",
1810 channel);
1811
1812 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
1813 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
1814 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
1815 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
1816 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
1817 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
1818 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
1819
1820 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
1821 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
1822
1823 dsi_write_reg(DSI_VC_CTRL(channel), r);
1824
1825 dsi.vc[channel].mode = DSI_VC_MODE_L4;
1826}
1827
1828static void dsi_vc_config_l4(int channel)
1829{
1830 if (dsi.vc[channel].mode == DSI_VC_MODE_L4)
1831 return;
1832
1833 DSSDBGF("%d", channel);
1834
1835 dsi_vc_enable(channel, 0);
1836
1837 if (REG_GET(DSI_VC_CTRL(channel), 15, 15)) /* VC_BUSY */
1838 DSSERR("vc(%d) busy when trying to config for L4\n", channel);
1839
1840 REG_FLD_MOD(DSI_VC_CTRL(channel), 0, 1, 1); /* SOURCE, 0 = L4 */
1841
1842 dsi_vc_enable(channel, 1);
1843
1844 dsi.vc[channel].mode = DSI_VC_MODE_L4;
1845}
1846
1847static void dsi_vc_config_vp(int channel)
1848{
1849 if (dsi.vc[channel].mode == DSI_VC_MODE_VP)
1850 return;
1851
1852 DSSDBGF("%d", channel);
1853
1854 dsi_vc_enable(channel, 0);
1855
1856 if (REG_GET(DSI_VC_CTRL(channel), 15, 15)) /* VC_BUSY */
1857 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
1858
1859 REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 1, 1); /* SOURCE, 1 = video port */
1860
1861 dsi_vc_enable(channel, 1);
1862
1863 dsi.vc[channel].mode = DSI_VC_MODE_VP;
1864}
1865
1866
1867static void dsi_vc_enable_hs(int channel, bool enable)
1868{
1869 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
1870
1871 dsi_vc_enable(channel, 0);
1872 dsi_if_enable(0);
1873
1874 REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 9, 9);
1875
1876 dsi_vc_enable(channel, 1);
1877 dsi_if_enable(1);
1878
1879 dsi_force_tx_stop_mode_io();
1880}
1881
1882static void dsi_vc_flush_long_data(int channel)
1883{
1884 while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
1885 u32 val;
1886 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
1887 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
1888 (val >> 0) & 0xff,
1889 (val >> 8) & 0xff,
1890 (val >> 16) & 0xff,
1891 (val >> 24) & 0xff);
1892 }
1893}
1894
1895static void dsi_show_rx_ack_with_err(u16 err)
1896{
1897 DSSERR("\tACK with ERROR (%#x):\n", err);
1898 if (err & (1 << 0))
1899 DSSERR("\t\tSoT Error\n");
1900 if (err & (1 << 1))
1901 DSSERR("\t\tSoT Sync Error\n");
1902 if (err & (1 << 2))
1903 DSSERR("\t\tEoT Sync Error\n");
1904 if (err & (1 << 3))
1905 DSSERR("\t\tEscape Mode Entry Command Error\n");
1906 if (err & (1 << 4))
1907 DSSERR("\t\tLP Transmit Sync Error\n");
1908 if (err & (1 << 5))
1909 DSSERR("\t\tHS Receive Timeout Error\n");
1910 if (err & (1 << 6))
1911 DSSERR("\t\tFalse Control Error\n");
1912 if (err & (1 << 7))
1913 DSSERR("\t\t(reserved7)\n");
1914 if (err & (1 << 8))
1915 DSSERR("\t\tECC Error, single-bit (corrected)\n");
1916 if (err & (1 << 9))
1917 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
1918 if (err & (1 << 10))
1919 DSSERR("\t\tChecksum Error\n");
1920 if (err & (1 << 11))
1921 DSSERR("\t\tData type not recognized\n");
1922 if (err & (1 << 12))
1923 DSSERR("\t\tInvalid VC ID\n");
1924 if (err & (1 << 13))
1925 DSSERR("\t\tInvalid Transmission Length\n");
1926 if (err & (1 << 14))
1927 DSSERR("\t\t(reserved14)\n");
1928 if (err & (1 << 15))
1929 DSSERR("\t\tDSI Protocol Violation\n");
1930}
1931
1932static u16 dsi_vc_flush_receive_data(int channel)
1933{
1934 /* RX_FIFO_NOT_EMPTY */
1935 while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
1936 u32 val;
1937 u8 dt;
1938 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
1939 DSSDBG("\trawval %#08x\n", val);
1940 dt = FLD_GET(val, 5, 0);
1941 if (dt == DSI_DT_RX_ACK_WITH_ERR) {
1942 u16 err = FLD_GET(val, 23, 8);
1943 dsi_show_rx_ack_with_err(err);
1944 } else if (dt == DSI_DT_RX_SHORT_READ_1) {
1945 DSSDBG("\tDCS short response, 1 byte: %#x\n",
1946 FLD_GET(val, 23, 8));
1947 } else if (dt == DSI_DT_RX_SHORT_READ_2) {
1948 DSSDBG("\tDCS short response, 2 byte: %#x\n",
1949 FLD_GET(val, 23, 8));
1950 } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
1951 DSSDBG("\tDCS long response, len %d\n",
1952 FLD_GET(val, 23, 8));
1953 dsi_vc_flush_long_data(channel);
1954 } else {
1955 DSSERR("\tunknown datatype 0x%02x\n", dt);
1956 }
1957 }
1958 return 0;
1959}
1960
1961static int dsi_vc_send_bta(int channel)
1962{
1963 if (dsi.update_mode != OMAP_DSS_UPDATE_AUTO &&
1964 (dsi.debug_write || dsi.debug_read))
1965 DSSDBG("dsi_vc_send_bta %d\n", channel);
1966
Tomi Valkeinen4f765022010-01-18 16:27:52 +02001967 WARN_ON(!dsi_bus_is_locked());
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001968
1969 if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { /* RX_FIFO_NOT_EMPTY */
1970 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
1971 dsi_vc_flush_receive_data(channel);
1972 }
1973
1974 REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
1975
1976 return 0;
1977}
1978
1979int dsi_vc_send_bta_sync(int channel)
1980{
1981 int r = 0;
1982 u32 err;
1983
1984 INIT_COMPLETION(dsi.bta_completion);
1985
1986 dsi_vc_enable_bta_irq(channel);
1987
1988 r = dsi_vc_send_bta(channel);
1989 if (r)
1990 goto err;
1991
1992 if (wait_for_completion_timeout(&dsi.bta_completion,
1993 msecs_to_jiffies(500)) == 0) {
1994 DSSERR("Failed to receive BTA\n");
1995 r = -EIO;
1996 goto err;
1997 }
1998
1999 err = dsi_get_errors();
2000 if (err) {
2001 DSSERR("Error while sending BTA: %x\n", err);
2002 r = -EIO;
2003 goto err;
2004 }
2005err:
2006 dsi_vc_disable_bta_irq(channel);
2007
2008 return r;
2009}
2010EXPORT_SYMBOL(dsi_vc_send_bta_sync);
2011
2012static inline void dsi_vc_write_long_header(int channel, u8 data_type,
2013 u16 len, u8 ecc)
2014{
2015 u32 val;
2016 u8 data_id;
2017
Tomi Valkeinen4f765022010-01-18 16:27:52 +02002018 WARN_ON(!dsi_bus_is_locked());
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002019
2020 /*data_id = data_type | channel << 6; */
2021 data_id = data_type | dsi.vc[channel].dest_per << 6;
2022
2023 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
2024 FLD_VAL(ecc, 31, 24);
2025
2026 dsi_write_reg(DSI_VC_LONG_PACKET_HEADER(channel), val);
2027}
2028
2029static inline void dsi_vc_write_long_payload(int channel,
2030 u8 b1, u8 b2, u8 b3, u8 b4)
2031{
2032 u32 val;
2033
2034 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0;
2035
2036/* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
2037 b1, b2, b3, b4, val); */
2038
2039 dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
2040}
2041
2042static int dsi_vc_send_long(int channel, u8 data_type, u8 *data, u16 len,
2043 u8 ecc)
2044{
2045 /*u32 val; */
2046 int i;
2047 u8 *p;
2048 int r = 0;
2049 u8 b1, b2, b3, b4;
2050
2051 if (dsi.debug_write)
2052 DSSDBG("dsi_vc_send_long, %d bytes\n", len);
2053
2054 /* len + header */
2055 if (dsi.vc[channel].fifo_size * 32 * 4 < len + 4) {
2056 DSSERR("unable to send long packet: packet too long.\n");
2057 return -EINVAL;
2058 }
2059
2060 dsi_vc_config_l4(channel);
2061
2062 dsi_vc_write_long_header(channel, data_type, len, ecc);
2063
2064 /*dsi_vc_print_status(0); */
2065
2066 p = data;
2067 for (i = 0; i < len >> 2; i++) {
2068 if (dsi.debug_write)
2069 DSSDBG("\tsending full packet %d\n", i);
2070 /*dsi_vc_print_status(0); */
2071
2072 b1 = *p++;
2073 b2 = *p++;
2074 b3 = *p++;
2075 b4 = *p++;
2076
2077 dsi_vc_write_long_payload(channel, b1, b2, b3, b4);
2078 }
2079
2080 i = len % 4;
2081 if (i) {
2082 b1 = 0; b2 = 0; b3 = 0;
2083
2084 if (dsi.debug_write)
2085 DSSDBG("\tsending remainder bytes %d\n", i);
2086
2087 switch (i) {
2088 case 3:
2089 b1 = *p++;
2090 b2 = *p++;
2091 b3 = *p++;
2092 break;
2093 case 2:
2094 b1 = *p++;
2095 b2 = *p++;
2096 break;
2097 case 1:
2098 b1 = *p++;
2099 break;
2100 }
2101
2102 dsi_vc_write_long_payload(channel, b1, b2, b3, 0);
2103 }
2104
2105 return r;
2106}
2107
2108static int dsi_vc_send_short(int channel, u8 data_type, u16 data, u8 ecc)
2109{
2110 u32 r;
2111 u8 data_id;
2112
Tomi Valkeinen4f765022010-01-18 16:27:52 +02002113 WARN_ON(!dsi_bus_is_locked());
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002114
2115 if (dsi.debug_write)
2116 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
2117 channel,
2118 data_type, data & 0xff, (data >> 8) & 0xff);
2119
2120 dsi_vc_config_l4(channel);
2121
2122 if (FLD_GET(dsi_read_reg(DSI_VC_CTRL(channel)), 16, 16)) {
2123 DSSERR("ERROR FIFO FULL, aborting transfer\n");
2124 return -EINVAL;
2125 }
2126
Tomi Valkeinen397bb3c2009-12-03 13:37:31 +02002127 data_id = data_type | dsi.vc[channel].dest_per << 6;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002128
2129 r = (data_id << 0) | (data << 8) | (ecc << 24);
2130
2131 dsi_write_reg(DSI_VC_SHORT_PACKET_HEADER(channel), r);
2132
2133 return 0;
2134}
2135
2136int dsi_vc_send_null(int channel)
2137{
2138 u8 nullpkg[] = {0, 0, 0, 0};
Tomi Valkeinen397bb3c2009-12-03 13:37:31 +02002139 return dsi_vc_send_long(channel, DSI_DT_NULL_PACKET, nullpkg, 4, 0);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002140}
2141EXPORT_SYMBOL(dsi_vc_send_null);
2142
2143int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len)
2144{
2145 int r;
2146
2147 BUG_ON(len == 0);
2148
2149 if (len == 1) {
2150 r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_0,
2151 data[0], 0);
2152 } else if (len == 2) {
2153 r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_1,
2154 data[0] | (data[1] << 8), 0);
2155 } else {
2156 /* 0x39 = DCS Long Write */
2157 r = dsi_vc_send_long(channel, DSI_DT_DCS_LONG_WRITE,
2158 data, len, 0);
2159 }
2160
2161 return r;
2162}
2163EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
2164
2165int dsi_vc_dcs_write(int channel, u8 *data, int len)
2166{
2167 int r;
2168
2169 r = dsi_vc_dcs_write_nosync(channel, data, len);
2170 if (r)
2171 return r;
2172
2173 r = dsi_vc_send_bta_sync(channel);
2174
2175 return r;
2176}
2177EXPORT_SYMBOL(dsi_vc_dcs_write);
2178
Tomi Valkeinen828c48f2009-12-16 14:53:15 +02002179int dsi_vc_dcs_write_0(int channel, u8 dcs_cmd)
2180{
2181 return dsi_vc_dcs_write(channel, &dcs_cmd, 1);
2182}
2183EXPORT_SYMBOL(dsi_vc_dcs_write_0);
2184
2185int dsi_vc_dcs_write_1(int channel, u8 dcs_cmd, u8 param)
2186{
2187 u8 buf[2];
2188 buf[0] = dcs_cmd;
2189 buf[1] = param;
2190 return dsi_vc_dcs_write(channel, buf, 2);
2191}
2192EXPORT_SYMBOL(dsi_vc_dcs_write_1);
2193
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002194int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen)
2195{
2196 u32 val;
2197 u8 dt;
2198 int r;
2199
2200 if (dsi.debug_read)
Tomi Valkeinenff90a342009-12-03 13:38:04 +02002201 DSSDBG("dsi_vc_dcs_read(ch%d, dcs_cmd %x)\n", channel, dcs_cmd);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002202
2203 r = dsi_vc_send_short(channel, DSI_DT_DCS_READ, dcs_cmd, 0);
2204 if (r)
2205 return r;
2206
2207 r = dsi_vc_send_bta_sync(channel);
2208 if (r)
2209 return r;
2210
2211 /* RX_FIFO_NOT_EMPTY */
2212 if (REG_GET(DSI_VC_CTRL(channel), 20, 20) == 0) {
2213 DSSERR("RX fifo empty when trying to read.\n");
2214 return -EIO;
2215 }
2216
2217 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
2218 if (dsi.debug_read)
2219 DSSDBG("\theader: %08x\n", val);
2220 dt = FLD_GET(val, 5, 0);
2221 if (dt == DSI_DT_RX_ACK_WITH_ERR) {
2222 u16 err = FLD_GET(val, 23, 8);
2223 dsi_show_rx_ack_with_err(err);
2224 return -EIO;
2225
2226 } else if (dt == DSI_DT_RX_SHORT_READ_1) {
2227 u8 data = FLD_GET(val, 15, 8);
2228 if (dsi.debug_read)
2229 DSSDBG("\tDCS short response, 1 byte: %02x\n", data);
2230
2231 if (buflen < 1)
2232 return -EIO;
2233
2234 buf[0] = data;
2235
2236 return 1;
2237 } else if (dt == DSI_DT_RX_SHORT_READ_2) {
2238 u16 data = FLD_GET(val, 23, 8);
2239 if (dsi.debug_read)
2240 DSSDBG("\tDCS short response, 2 byte: %04x\n", data);
2241
2242 if (buflen < 2)
2243 return -EIO;
2244
2245 buf[0] = data & 0xff;
2246 buf[1] = (data >> 8) & 0xff;
2247
2248 return 2;
2249 } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
2250 int w;
2251 int len = FLD_GET(val, 23, 8);
2252 if (dsi.debug_read)
2253 DSSDBG("\tDCS long response, len %d\n", len);
2254
2255 if (len > buflen)
2256 return -EIO;
2257
2258 /* two byte checksum ends the packet, not included in len */
2259 for (w = 0; w < len + 2;) {
2260 int b;
2261 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
2262 if (dsi.debug_read)
2263 DSSDBG("\t\t%02x %02x %02x %02x\n",
2264 (val >> 0) & 0xff,
2265 (val >> 8) & 0xff,
2266 (val >> 16) & 0xff,
2267 (val >> 24) & 0xff);
2268
2269 for (b = 0; b < 4; ++b) {
2270 if (w < len)
2271 buf[w] = (val >> (b * 8)) & 0xff;
2272 /* we discard the 2 byte checksum */
2273 ++w;
2274 }
2275 }
2276
2277 return len;
2278
2279 } else {
2280 DSSERR("\tunknown datatype 0x%02x\n", dt);
2281 return -EIO;
2282 }
2283}
2284EXPORT_SYMBOL(dsi_vc_dcs_read);
2285
Tomi Valkeinen828c48f2009-12-16 14:53:15 +02002286int dsi_vc_dcs_read_1(int channel, u8 dcs_cmd, u8 *data)
2287{
2288 int r;
2289
2290 r = dsi_vc_dcs_read(channel, dcs_cmd, data, 1);
2291
2292 if (r < 0)
2293 return r;
2294
2295 if (r != 1)
2296 return -EIO;
2297
2298 return 0;
2299}
2300EXPORT_SYMBOL(dsi_vc_dcs_read_1);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002301
2302int dsi_vc_set_max_rx_packet_size(int channel, u16 len)
2303{
2304 int r;
2305 r = dsi_vc_send_short(channel, DSI_DT_SET_MAX_RET_PKG_SIZE,
2306 len, 0);
2307
2308 if (r)
2309 return r;
2310
2311 r = dsi_vc_send_bta_sync(channel);
2312
2313 return r;
2314}
2315EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
2316
2317static void dsi_set_lp_rx_timeout(unsigned long ns)
2318{
2319 u32 r;
2320 unsigned x4, x16;
2321 unsigned long fck;
2322 unsigned long ticks;
2323
2324 /* ticks in DSI_FCK */
2325
2326 fck = dsi_fclk_rate();
2327 ticks = (fck / 1000 / 1000) * ns / 1000;
2328 x4 = 0;
2329 x16 = 0;
2330
2331 if (ticks > 0x1fff) {
2332 ticks = (fck / 1000 / 1000) * ns / 1000 / 4;
2333 x4 = 1;
2334 x16 = 0;
2335 }
2336
2337 if (ticks > 0x1fff) {
2338 ticks = (fck / 1000 / 1000) * ns / 1000 / 16;
2339 x4 = 0;
2340 x16 = 1;
2341 }
2342
2343 if (ticks > 0x1fff) {
2344 ticks = (fck / 1000 / 1000) * ns / 1000 / (4 * 16);
2345 x4 = 1;
2346 x16 = 1;
2347 }
2348
2349 if (ticks > 0x1fff) {
2350 DSSWARN("LP_TX_TO over limit, setting it to max\n");
2351 ticks = 0x1fff;
2352 x4 = 1;
2353 x16 = 1;
2354 }
2355
2356 r = dsi_read_reg(DSI_TIMING2);
2357 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
2358 r = FLD_MOD(r, x16, 14, 14); /* LP_RX_TO_X16 */
2359 r = FLD_MOD(r, x4, 13, 13); /* LP_RX_TO_X4 */
2360 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
2361 dsi_write_reg(DSI_TIMING2, r);
2362
2363 DSSDBG("LP_RX_TO %lu ns (%#lx ticks%s%s)\n",
2364 (ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
2365 (fck / 1000 / 1000),
2366 ticks, x4 ? " x4" : "", x16 ? " x16" : "");
2367}
2368
2369static void dsi_set_ta_timeout(unsigned long ns)
2370{
2371 u32 r;
2372 unsigned x8, x16;
2373 unsigned long fck;
2374 unsigned long ticks;
2375
2376 /* ticks in DSI_FCK */
2377 fck = dsi_fclk_rate();
2378 ticks = (fck / 1000 / 1000) * ns / 1000;
2379 x8 = 0;
2380 x16 = 0;
2381
2382 if (ticks > 0x1fff) {
2383 ticks = (fck / 1000 / 1000) * ns / 1000 / 8;
2384 x8 = 1;
2385 x16 = 0;
2386 }
2387
2388 if (ticks > 0x1fff) {
2389 ticks = (fck / 1000 / 1000) * ns / 1000 / 16;
2390 x8 = 0;
2391 x16 = 1;
2392 }
2393
2394 if (ticks > 0x1fff) {
2395 ticks = (fck / 1000 / 1000) * ns / 1000 / (8 * 16);
2396 x8 = 1;
2397 x16 = 1;
2398 }
2399
2400 if (ticks > 0x1fff) {
2401 DSSWARN("TA_TO over limit, setting it to max\n");
2402 ticks = 0x1fff;
2403 x8 = 1;
2404 x16 = 1;
2405 }
2406
2407 r = dsi_read_reg(DSI_TIMING1);
2408 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
2409 r = FLD_MOD(r, x16, 30, 30); /* TA_TO_X16 */
2410 r = FLD_MOD(r, x8, 29, 29); /* TA_TO_X8 */
2411 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
2412 dsi_write_reg(DSI_TIMING1, r);
2413
2414 DSSDBG("TA_TO %lu ns (%#lx ticks%s%s)\n",
2415 (ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1) * 1000) /
2416 (fck / 1000 / 1000),
2417 ticks, x8 ? " x8" : "", x16 ? " x16" : "");
2418}
2419
2420static void dsi_set_stop_state_counter(unsigned long ns)
2421{
2422 u32 r;
2423 unsigned x4, x16;
2424 unsigned long fck;
2425 unsigned long ticks;
2426
2427 /* ticks in DSI_FCK */
2428
2429 fck = dsi_fclk_rate();
2430 ticks = (fck / 1000 / 1000) * ns / 1000;
2431 x4 = 0;
2432 x16 = 0;
2433
2434 if (ticks > 0x1fff) {
2435 ticks = (fck / 1000 / 1000) * ns / 1000 / 4;
2436 x4 = 1;
2437 x16 = 0;
2438 }
2439
2440 if (ticks > 0x1fff) {
2441 ticks = (fck / 1000 / 1000) * ns / 1000 / 16;
2442 x4 = 0;
2443 x16 = 1;
2444 }
2445
2446 if (ticks > 0x1fff) {
2447 ticks = (fck / 1000 / 1000) * ns / 1000 / (4 * 16);
2448 x4 = 1;
2449 x16 = 1;
2450 }
2451
2452 if (ticks > 0x1fff) {
2453 DSSWARN("STOP_STATE_COUNTER_IO over limit, "
2454 "setting it to max\n");
2455 ticks = 0x1fff;
2456 x4 = 1;
2457 x16 = 1;
2458 }
2459
2460 r = dsi_read_reg(DSI_TIMING1);
2461 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2462 r = FLD_MOD(r, x16, 14, 14); /* STOP_STATE_X16_IO */
2463 r = FLD_MOD(r, x4, 13, 13); /* STOP_STATE_X4_IO */
2464 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
2465 dsi_write_reg(DSI_TIMING1, r);
2466
2467 DSSDBG("STOP_STATE_COUNTER %lu ns (%#lx ticks%s%s)\n",
2468 (ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
2469 (fck / 1000 / 1000),
2470 ticks, x4 ? " x4" : "", x16 ? " x16" : "");
2471}
2472
2473static void dsi_set_hs_tx_timeout(unsigned long ns)
2474{
2475 u32 r;
2476 unsigned x4, x16;
2477 unsigned long fck;
2478 unsigned long ticks;
2479
2480 /* ticks in TxByteClkHS */
2481
2482 fck = dsi_get_txbyteclkhs();
2483 ticks = (fck / 1000 / 1000) * ns / 1000;
2484 x4 = 0;
2485 x16 = 0;
2486
2487 if (ticks > 0x1fff) {
2488 ticks = (fck / 1000 / 1000) * ns / 1000 / 4;
2489 x4 = 1;
2490 x16 = 0;
2491 }
2492
2493 if (ticks > 0x1fff) {
2494 ticks = (fck / 1000 / 1000) * ns / 1000 / 16;
2495 x4 = 0;
2496 x16 = 1;
2497 }
2498
2499 if (ticks > 0x1fff) {
2500 ticks = (fck / 1000 / 1000) * ns / 1000 / (4 * 16);
2501 x4 = 1;
2502 x16 = 1;
2503 }
2504
2505 if (ticks > 0x1fff) {
2506 DSSWARN("HS_TX_TO over limit, setting it to max\n");
2507 ticks = 0x1fff;
2508 x4 = 1;
2509 x16 = 1;
2510 }
2511
2512 r = dsi_read_reg(DSI_TIMING2);
2513 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
2514 r = FLD_MOD(r, x16, 30, 30); /* HS_TX_TO_X16 */
2515 r = FLD_MOD(r, x4, 29, 29); /* HS_TX_TO_X8 (4 really) */
2516 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
2517 dsi_write_reg(DSI_TIMING2, r);
2518
2519 DSSDBG("HS_TX_TO %lu ns (%#lx ticks%s%s)\n",
2520 (ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
2521 (fck / 1000 / 1000),
2522 ticks, x4 ? " x4" : "", x16 ? " x16" : "");
2523}
2524static int dsi_proto_config(struct omap_dss_device *dssdev)
2525{
2526 u32 r;
2527 int buswidth = 0;
2528
2529 dsi_config_tx_fifo(DSI_FIFO_SIZE_128,
2530 DSI_FIFO_SIZE_0,
2531 DSI_FIFO_SIZE_0,
2532 DSI_FIFO_SIZE_0);
2533
2534 dsi_config_rx_fifo(DSI_FIFO_SIZE_128,
2535 DSI_FIFO_SIZE_0,
2536 DSI_FIFO_SIZE_0,
2537 DSI_FIFO_SIZE_0);
2538
2539 /* XXX what values for the timeouts? */
2540 dsi_set_stop_state_counter(1000);
2541 dsi_set_ta_timeout(6400000);
2542 dsi_set_lp_rx_timeout(48000);
2543 dsi_set_hs_tx_timeout(1000000);
2544
2545 switch (dssdev->ctrl.pixel_size) {
2546 case 16:
2547 buswidth = 0;
2548 break;
2549 case 18:
2550 buswidth = 1;
2551 break;
2552 case 24:
2553 buswidth = 2;
2554 break;
2555 default:
2556 BUG();
2557 }
2558
2559 r = dsi_read_reg(DSI_CTRL);
2560 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
2561 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
2562 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
2563 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/
2564 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
2565 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
2566 r = FLD_MOD(r, 2, 13, 12); /* LINE_BUFFER, 2 lines */
2567 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
2568 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
2569 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
2570 r = FLD_MOD(r, 0, 25, 25); /* DCS_CMD_CODE, 1=start, 0=continue */
2571
2572 dsi_write_reg(DSI_CTRL, r);
2573
2574 dsi_vc_initial_config(0);
2575
2576 /* set all vc targets to peripheral 0 */
2577 dsi.vc[0].dest_per = 0;
2578 dsi.vc[1].dest_per = 0;
2579 dsi.vc[2].dest_per = 0;
2580 dsi.vc[3].dest_per = 0;
2581
2582 return 0;
2583}
2584
2585static void dsi_proto_timings(struct omap_dss_device *dssdev)
2586{
2587 unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
2588 unsigned tclk_pre, tclk_post;
2589 unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
2590 unsigned ths_trail, ths_exit;
2591 unsigned ddr_clk_pre, ddr_clk_post;
2592 unsigned enter_hs_mode_lat, exit_hs_mode_lat;
2593 unsigned ths_eot;
2594 u32 r;
2595
2596 r = dsi_read_reg(DSI_DSIPHY_CFG0);
2597 ths_prepare = FLD_GET(r, 31, 24);
2598 ths_prepare_ths_zero = FLD_GET(r, 23, 16);
2599 ths_zero = ths_prepare_ths_zero - ths_prepare;
2600 ths_trail = FLD_GET(r, 15, 8);
2601 ths_exit = FLD_GET(r, 7, 0);
2602
2603 r = dsi_read_reg(DSI_DSIPHY_CFG1);
2604 tlpx = FLD_GET(r, 22, 16) * 2;
2605 tclk_trail = FLD_GET(r, 15, 8);
2606 tclk_zero = FLD_GET(r, 7, 0);
2607
2608 r = dsi_read_reg(DSI_DSIPHY_CFG2);
2609 tclk_prepare = FLD_GET(r, 7, 0);
2610
2611 /* min 8*UI */
2612 tclk_pre = 20;
2613 /* min 60ns + 52*UI */
2614 tclk_post = ns2ddr(60) + 26;
2615
2616 /* ths_eot is 2 for 2 datalanes and 4 for 1 datalane */
2617 if (dssdev->phy.dsi.data1_lane != 0 &&
2618 dssdev->phy.dsi.data2_lane != 0)
2619 ths_eot = 2;
2620 else
2621 ths_eot = 4;
2622
2623 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
2624 4);
2625 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
2626
2627 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
2628 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
2629
2630 r = dsi_read_reg(DSI_CLK_TIMING);
2631 r = FLD_MOD(r, ddr_clk_pre, 15, 8);
2632 r = FLD_MOD(r, ddr_clk_post, 7, 0);
2633 dsi_write_reg(DSI_CLK_TIMING, r);
2634
2635 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
2636 ddr_clk_pre,
2637 ddr_clk_post);
2638
2639 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
2640 DIV_ROUND_UP(ths_prepare, 4) +
2641 DIV_ROUND_UP(ths_zero + 3, 4);
2642
2643 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
2644
2645 r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
2646 FLD_VAL(exit_hs_mode_lat, 15, 0);
2647 dsi_write_reg(DSI_VM_TIMING7, r);
2648
2649 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
2650 enter_hs_mode_lat, exit_hs_mode_lat);
2651}
2652
2653
2654#define DSI_DECL_VARS \
2655 int __dsi_cb = 0; u32 __dsi_cv = 0;
2656
2657#define DSI_FLUSH(ch) \
2658 if (__dsi_cb > 0) { \
2659 /*DSSDBG("sending long packet %#010x\n", __dsi_cv);*/ \
2660 dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(ch), __dsi_cv); \
2661 __dsi_cb = __dsi_cv = 0; \
2662 }
2663
2664#define DSI_PUSH(ch, data) \
2665 do { \
2666 __dsi_cv |= (data) << (__dsi_cb * 8); \
2667 /*DSSDBG("cv = %#010x, cb = %d\n", __dsi_cv, __dsi_cb);*/ \
2668 if (++__dsi_cb > 3) \
2669 DSI_FLUSH(ch); \
2670 } while (0)
2671
2672static int dsi_update_screen_l4(struct omap_dss_device *dssdev,
2673 int x, int y, int w, int h)
2674{
2675 /* Note: supports only 24bit colors in 32bit container */
2676 int first = 1;
2677 int fifo_stalls = 0;
2678 int max_dsi_packet_size;
2679 int max_data_per_packet;
2680 int max_pixels_per_packet;
2681 int pixels_left;
2682 int bytespp = dssdev->ctrl.pixel_size / 8;
2683 int scr_width;
2684 u32 __iomem *data;
2685 int start_offset;
2686 int horiz_inc;
2687 int current_x;
2688 struct omap_overlay *ovl;
2689
2690 debug_irq = 0;
2691
2692 DSSDBG("dsi_update_screen_l4 (%d,%d %dx%d)\n",
2693 x, y, w, h);
2694
2695 ovl = dssdev->manager->overlays[0];
2696
2697 if (ovl->info.color_mode != OMAP_DSS_COLOR_RGB24U)
2698 return -EINVAL;
2699
2700 if (dssdev->ctrl.pixel_size != 24)
2701 return -EINVAL;
2702
2703 scr_width = ovl->info.screen_width;
2704 data = ovl->info.vaddr;
2705
2706 start_offset = scr_width * y + x;
2707 horiz_inc = scr_width - w;
2708 current_x = x;
2709
2710 /* We need header(4) + DCSCMD(1) + pixels(numpix*bytespp) bytes
2711 * in fifo */
2712
2713 /* When using CPU, max long packet size is TX buffer size */
2714 max_dsi_packet_size = dsi.vc[0].fifo_size * 32 * 4;
2715
2716 /* we seem to get better perf if we divide the tx fifo to half,
2717 and while the other half is being sent, we fill the other half
2718 max_dsi_packet_size /= 2; */
2719
2720 max_data_per_packet = max_dsi_packet_size - 4 - 1;
2721
2722 max_pixels_per_packet = max_data_per_packet / bytespp;
2723
2724 DSSDBG("max_pixels_per_packet %d\n", max_pixels_per_packet);
2725
2726 pixels_left = w * h;
2727
2728 DSSDBG("total pixels %d\n", pixels_left);
2729
2730 data += start_offset;
2731
2732 while (pixels_left > 0) {
2733 /* 0x2c = write_memory_start */
2734 /* 0x3c = write_memory_continue */
2735 u8 dcs_cmd = first ? 0x2c : 0x3c;
2736 int pixels;
2737 DSI_DECL_VARS;
2738 first = 0;
2739
2740#if 1
2741 /* using fifo not empty */
2742 /* TX_FIFO_NOT_EMPTY */
2743 while (FLD_GET(dsi_read_reg(DSI_VC_CTRL(0)), 5, 5)) {
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002744 fifo_stalls++;
2745 if (fifo_stalls > 0xfffff) {
2746 DSSERR("fifo stalls overflow, pixels left %d\n",
2747 pixels_left);
2748 dsi_if_enable(0);
2749 return -EIO;
2750 }
Tomi Valkeinen24be78b2010-01-07 14:19:48 +02002751 udelay(1);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002752 }
2753#elif 1
2754 /* using fifo emptiness */
2755 while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 <
2756 max_dsi_packet_size) {
2757 fifo_stalls++;
2758 if (fifo_stalls > 0xfffff) {
2759 DSSERR("fifo stalls overflow, pixels left %d\n",
2760 pixels_left);
2761 dsi_if_enable(0);
2762 return -EIO;
2763 }
2764 }
2765#else
2766 while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 == 0) {
2767 fifo_stalls++;
2768 if (fifo_stalls > 0xfffff) {
2769 DSSERR("fifo stalls overflow, pixels left %d\n",
2770 pixels_left);
2771 dsi_if_enable(0);
2772 return -EIO;
2773 }
2774 }
2775#endif
2776 pixels = min(max_pixels_per_packet, pixels_left);
2777
2778 pixels_left -= pixels;
2779
2780 dsi_vc_write_long_header(0, DSI_DT_DCS_LONG_WRITE,
2781 1 + pixels * bytespp, 0);
2782
2783 DSI_PUSH(0, dcs_cmd);
2784
2785 while (pixels-- > 0) {
2786 u32 pix = __raw_readl(data++);
2787
2788 DSI_PUSH(0, (pix >> 16) & 0xff);
2789 DSI_PUSH(0, (pix >> 8) & 0xff);
2790 DSI_PUSH(0, (pix >> 0) & 0xff);
2791
2792 current_x++;
2793 if (current_x == x+w) {
2794 current_x = x;
2795 data += horiz_inc;
2796 }
2797 }
2798
2799 DSI_FLUSH(0);
2800 }
2801
2802 return 0;
2803}
2804
2805static void dsi_update_screen_dispc(struct omap_dss_device *dssdev,
2806 u16 x, u16 y, u16 w, u16 h)
2807{
2808 unsigned bytespp;
2809 unsigned bytespl;
2810 unsigned bytespf;
2811 unsigned total_len;
2812 unsigned packet_payload;
2813 unsigned packet_len;
2814 u32 l;
2815 bool use_te_trigger;
2816 const unsigned channel = 0;
2817 /* line buffer is 1024 x 24bits */
2818 /* XXX: for some reason using full buffer size causes considerable TX
2819 * slowdown with update sizes that fill the whole buffer */
2820 const unsigned line_buf_size = 1023 * 3;
2821
2822 use_te_trigger = dsi.te_enabled && !dsi.use_ext_te;
2823
2824 if (dsi.update_mode != OMAP_DSS_UPDATE_AUTO)
2825 DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n",
2826 x, y, w, h);
2827
2828 bytespp = dssdev->ctrl.pixel_size / 8;
2829 bytespl = w * bytespp;
2830 bytespf = bytespl * h;
2831
2832 /* NOTE: packet_payload has to be equal to N * bytespl, where N is
2833 * number of lines in a packet. See errata about VP_CLK_RATIO */
2834
2835 if (bytespf < line_buf_size)
2836 packet_payload = bytespf;
2837 else
2838 packet_payload = (line_buf_size) / bytespl * bytespl;
2839
2840 packet_len = packet_payload + 1; /* 1 byte for DCS cmd */
2841 total_len = (bytespf / packet_payload) * packet_len;
2842
2843 if (bytespf % packet_payload)
2844 total_len += (bytespf % packet_payload) + 1;
2845
2846 if (0)
2847 dsi_vc_print_status(1);
2848
2849 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
2850 dsi_write_reg(DSI_VC_TE(channel), l);
2851
2852 dsi_vc_write_long_header(channel, DSI_DT_DCS_LONG_WRITE, packet_len, 0);
2853
2854 if (use_te_trigger)
2855 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
2856 else
2857 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
2858 dsi_write_reg(DSI_VC_TE(channel), l);
2859
2860 /* We put SIDLEMODE to no-idle for the duration of the transfer,
2861 * because DSS interrupts are not capable of waking up the CPU and the
2862 * framedone interrupt could be delayed for quite a long time. I think
2863 * the same goes for any DSS interrupts, but for some reason I have not
2864 * seen the problem anywhere else than here.
2865 */
2866 dispc_disable_sidle();
2867
2868 dss_start_update(dssdev);
2869
2870 if (use_te_trigger) {
2871 /* disable LP_RX_TO, so that we can receive TE. Time to wait
2872 * for TE is longer than the timer allows */
2873 REG_FLD_MOD(DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
2874
2875 dsi_vc_send_bta(channel);
2876
2877#ifdef DSI_CATCH_MISSING_TE
2878 mod_timer(&dsi.te_timer, jiffies + msecs_to_jiffies(250));
2879#endif
2880 }
2881}
2882
2883#ifdef DSI_CATCH_MISSING_TE
2884static void dsi_te_timeout(unsigned long arg)
2885{
2886 DSSERR("TE not received for 250ms!\n");
2887}
2888#endif
2889
2890static void dsi_framedone_irq_callback(void *data, u32 mask)
2891{
2892 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
2893 * turns itself off. However, DSI still has the pixels in its buffers,
2894 * and is sending the data.
2895 */
2896
2897 /* SIDLEMODE back to smart-idle */
2898 dispc_enable_sidle();
2899
2900 dsi.framedone_received = true;
2901 wake_up(&dsi.waitqueue);
2902}
2903
2904static void dsi_set_update_region(struct omap_dss_device *dssdev,
2905 u16 x, u16 y, u16 w, u16 h)
2906{
2907 spin_lock(&dsi.update_lock);
2908 if (dsi.update_region.dirty) {
2909 dsi.update_region.x = min(x, dsi.update_region.x);
2910 dsi.update_region.y = min(y, dsi.update_region.y);
2911 dsi.update_region.w = max(w, dsi.update_region.w);
2912 dsi.update_region.h = max(h, dsi.update_region.h);
2913 } else {
2914 dsi.update_region.x = x;
2915 dsi.update_region.y = y;
2916 dsi.update_region.w = w;
2917 dsi.update_region.h = h;
2918 }
2919
2920 dsi.update_region.device = dssdev;
2921 dsi.update_region.dirty = true;
2922
2923 spin_unlock(&dsi.update_lock);
2924
2925}
2926
2927static int dsi_set_update_mode(struct omap_dss_device *dssdev,
2928 enum omap_dss_update_mode mode)
2929{
2930 int r = 0;
2931 int i;
2932
Tomi Valkeinen4f765022010-01-18 16:27:52 +02002933 WARN_ON(!dsi_bus_is_locked());
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002934
2935 if (dsi.update_mode != mode) {
2936 dsi.update_mode = mode;
2937
2938 /* Mark the overlays dirty, and do apply(), so that we get the
2939 * overlays configured properly after update mode change. */
2940 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2941 struct omap_overlay *ovl;
2942 ovl = omap_dss_get_overlay(i);
2943 if (ovl->manager == dssdev->manager)
2944 ovl->info_dirty = true;
2945 }
2946
2947 r = dssdev->manager->apply(dssdev->manager);
2948
2949 if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE &&
2950 mode == OMAP_DSS_UPDATE_AUTO) {
2951 u16 w, h;
2952
2953 DSSDBG("starting auto update\n");
2954
2955 dssdev->get_resolution(dssdev, &w, &h);
2956
2957 dsi_set_update_region(dssdev, 0, 0, w, h);
2958
2959 dsi_perf_mark_start_auto();
2960
2961 wake_up(&dsi.waitqueue);
2962 }
2963 }
2964
2965 return r;
2966}
2967
2968static int dsi_set_te(struct omap_dss_device *dssdev, bool enable)
2969{
Tomi Valkeinen7475e442009-12-08 17:30:24 +02002970 int r = 0;
2971
2972 if (dssdev->driver->enable_te) {
2973 r = dssdev->driver->enable_te(dssdev, enable);
2974 /* XXX for some reason, DSI TE breaks if we don't wait here.
2975 * Panel bug? Needs more studying */
2976 msleep(100);
2977 }
2978
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002979 return r;
2980}
2981
2982static void dsi_handle_framedone(void)
2983{
2984 int r;
2985 const int channel = 0;
2986 bool use_te_trigger;
2987
2988 use_te_trigger = dsi.te_enabled && !dsi.use_ext_te;
2989
2990 if (dsi.update_mode != OMAP_DSS_UPDATE_AUTO)
2991 DSSDBG("FRAMEDONE\n");
2992
2993 if (use_te_trigger) {
2994 /* enable LP_RX_TO again after the TE */
2995 REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
2996 }
2997
2998 /* Send BTA after the frame. We need this for the TE to work, as TE
2999 * trigger is only sent for BTAs without preceding packet. Thus we need
3000 * to BTA after the pixel packets so that next BTA will cause TE
3001 * trigger.
3002 *
3003 * This is not needed when TE is not in use, but we do it anyway to
3004 * make sure that the transfer has been completed. It would be more
3005 * optimal, but more complex, to wait only just before starting next
3006 * transfer. */
3007 r = dsi_vc_send_bta_sync(channel);
3008 if (r)
3009 DSSERR("BTA after framedone failed\n");
3010
3011 /* RX_FIFO_NOT_EMPTY */
3012 if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
3013 DSSERR("Received error during frame transfer:\n");
3014 dsi_vc_flush_receive_data(0);
3015 }
3016
3017#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3018 dispc_fake_vsync_irq();
3019#endif
3020}
3021
3022static int dsi_update_thread(void *data)
3023{
3024 unsigned long timeout;
3025 struct omap_dss_device *device;
3026 u16 x, y, w, h;
3027
3028 while (1) {
3029 bool sched;
3030
3031 wait_event_interruptible(dsi.waitqueue,
3032 dsi.update_mode == OMAP_DSS_UPDATE_AUTO ||
3033 (dsi.update_mode == OMAP_DSS_UPDATE_MANUAL &&
3034 dsi.update_region.dirty == true) ||
3035 kthread_should_stop());
3036
3037 if (kthread_should_stop())
3038 break;
3039
3040 dsi_bus_lock();
3041
3042 if (dsi.update_mode == OMAP_DSS_UPDATE_DISABLED ||
3043 kthread_should_stop()) {
3044 dsi_bus_unlock();
3045 break;
3046 }
3047
3048 dsi_perf_mark_setup();
3049
3050 if (dsi.update_region.dirty) {
3051 spin_lock(&dsi.update_lock);
3052 dsi.active_update_region = dsi.update_region;
3053 dsi.update_region.dirty = false;
3054 spin_unlock(&dsi.update_lock);
3055 }
3056
3057 device = dsi.active_update_region.device;
3058 x = dsi.active_update_region.x;
3059 y = dsi.active_update_region.y;
3060 w = dsi.active_update_region.w;
3061 h = dsi.active_update_region.h;
3062
3063 if (device->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
3064
3065 if (dsi.update_mode == OMAP_DSS_UPDATE_MANUAL)
3066 dss_setup_partial_planes(device,
3067 &x, &y, &w, &h);
3068
3069 dispc_set_lcd_size(w, h);
3070 }
3071
3072 if (dsi.active_update_region.dirty) {
3073 dsi.active_update_region.dirty = false;
3074 /* XXX TODO we don't need to send the coords, if they
3075 * are the same that are already programmed to the
3076 * panel. That should speed up manual update a bit */
3077 device->driver->setup_update(device, x, y, w, h);
3078 }
3079
3080 dsi_perf_mark_start();
3081
3082 if (device->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
3083 dsi_vc_config_vp(0);
3084
3085 if (dsi.te_enabled && dsi.use_ext_te)
3086 device->driver->wait_for_te(device);
3087
3088 dsi.framedone_received = false;
3089
3090 dsi_update_screen_dispc(device, x, y, w, h);
3091
3092 /* wait for framedone */
3093 timeout = msecs_to_jiffies(1000);
3094 wait_event_timeout(dsi.waitqueue,
3095 dsi.framedone_received == true,
3096 timeout);
3097
3098 if (!dsi.framedone_received) {
3099 DSSERR("framedone timeout\n");
3100 DSSERR("failed update %d,%d %dx%d\n",
3101 x, y, w, h);
3102
3103 dispc_enable_sidle();
3104 dispc_enable_lcd_out(0);
3105
3106 dsi_reset_tx_fifo(0);
3107 } else {
3108 dsi_handle_framedone();
3109 dsi_perf_show("DISPC");
3110 }
3111 } else {
3112 dsi_update_screen_l4(device, x, y, w, h);
3113 dsi_perf_show("L4");
3114 }
3115
3116 sched = atomic_read(&dsi.bus_lock.count) < 0;
3117
3118 complete_all(&dsi.update_completion);
3119
3120 dsi_bus_unlock();
3121
3122 /* XXX We need to give others chance to get the bus lock. Is
3123 * there a better way for this? */
3124 if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO && sched)
3125 schedule_timeout_interruptible(1);
3126 }
3127
3128 DSSDBG("update thread exiting\n");
3129
3130 return 0;
3131}
3132
3133
3134
3135/* Display funcs */
3136
3137static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
3138{
3139 int r;
3140
3141 r = omap_dispc_register_isr(dsi_framedone_irq_callback, NULL,
3142 DISPC_IRQ_FRAMEDONE);
3143 if (r) {
3144 DSSERR("can't get FRAMEDONE irq\n");
3145 return r;
3146 }
3147
3148 dispc_set_lcd_display_type(OMAP_DSS_LCD_DISPLAY_TFT);
3149
3150 dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_DSI);
3151 dispc_enable_fifohandcheck(1);
3152
3153 dispc_set_tft_data_lines(dssdev->ctrl.pixel_size);
3154
3155 {
3156 struct omap_video_timings timings = {
3157 .hsw = 1,
3158 .hfp = 1,
3159 .hbp = 1,
3160 .vsw = 1,
3161 .vfp = 0,
3162 .vbp = 0,
3163 };
3164
3165 dispc_set_lcd_timings(&timings);
3166 }
3167
3168 return 0;
3169}
3170
3171static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev)
3172{
3173 omap_dispc_unregister_isr(dsi_framedone_irq_callback, NULL,
3174 DISPC_IRQ_FRAMEDONE);
3175}
3176
3177static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev)
3178{
3179 struct dsi_clock_info cinfo;
3180 int r;
3181
3182 /* we always use DSS2_FCK as input clock */
3183 cinfo.use_dss2_fck = true;
3184 cinfo.regn = dssdev->phy.dsi.div.regn;
3185 cinfo.regm = dssdev->phy.dsi.div.regm;
3186 cinfo.regm3 = dssdev->phy.dsi.div.regm3;
3187 cinfo.regm4 = dssdev->phy.dsi.div.regm4;
3188 r = dsi_calc_clock_rates(&cinfo);
3189 if (r)
3190 return r;
3191
3192 r = dsi_pll_set_clock_div(&cinfo);
3193 if (r) {
3194 DSSERR("Failed to set dsi clocks\n");
3195 return r;
3196 }
3197
3198 return 0;
3199}
3200
3201static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev)
3202{
3203 struct dispc_clock_info dispc_cinfo;
3204 int r;
3205 unsigned long long fck;
3206
3207 fck = dsi_get_dsi1_pll_rate();
3208
3209 dispc_cinfo.lck_div = dssdev->phy.dsi.div.lck_div;
3210 dispc_cinfo.pck_div = dssdev->phy.dsi.div.pck_div;
3211
3212 r = dispc_calc_clock_rates(fck, &dispc_cinfo);
3213 if (r) {
3214 DSSERR("Failed to calc dispc clocks\n");
3215 return r;
3216 }
3217
3218 r = dispc_set_clock_div(&dispc_cinfo);
3219 if (r) {
3220 DSSERR("Failed to set dispc clocks\n");
3221 return r;
3222 }
3223
3224 return 0;
3225}
3226
3227static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
3228{
3229 int r;
3230
3231 _dsi_print_reset_status();
3232
3233 r = dsi_pll_init(dssdev, true, true);
3234 if (r)
3235 goto err0;
3236
3237 r = dsi_configure_dsi_clocks(dssdev);
3238 if (r)
3239 goto err1;
3240
Tomi Valkeinen2f18c4d2010-01-08 18:00:36 +02003241 dss_select_dispc_clk_source(DSS_SRC_DSI1_PLL_FCLK);
3242 dss_select_dsi_clk_source(DSS_SRC_DSI2_PLL_FCLK);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003243
3244 DSSDBG("PLL OK\n");
3245
3246 r = dsi_configure_dispc_clocks(dssdev);
3247 if (r)
3248 goto err2;
3249
3250 r = dsi_complexio_init(dssdev);
3251 if (r)
3252 goto err2;
3253
3254 _dsi_print_reset_status();
3255
3256 dsi_proto_timings(dssdev);
3257 dsi_set_lp_clk_divisor(dssdev);
3258
3259 if (1)
3260 _dsi_print_reset_status();
3261
3262 r = dsi_proto_config(dssdev);
3263 if (r)
3264 goto err3;
3265
3266 /* enable interface */
3267 dsi_vc_enable(0, 1);
3268 dsi_if_enable(1);
3269 dsi_force_tx_stop_mode_io();
3270
3271 if (dssdev->driver->enable) {
3272 r = dssdev->driver->enable(dssdev);
3273 if (r)
3274 goto err4;
3275 }
3276
3277 /* enable high-speed after initial config */
3278 dsi_vc_enable_hs(0, 1);
3279
3280 return 0;
3281err4:
3282 dsi_if_enable(0);
3283err3:
3284 dsi_complexio_uninit();
3285err2:
Tomi Valkeinen2f18c4d2010-01-08 18:00:36 +02003286 dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
3287 dss_select_dsi_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003288err1:
3289 dsi_pll_uninit();
3290err0:
3291 return r;
3292}
3293
3294static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev)
3295{
3296 if (dssdev->driver->disable)
3297 dssdev->driver->disable(dssdev);
3298
Tomi Valkeinen2f18c4d2010-01-08 18:00:36 +02003299 dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
3300 dss_select_dsi_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003301 dsi_complexio_uninit();
3302 dsi_pll_uninit();
3303}
3304
3305static int dsi_core_init(void)
3306{
3307 /* Autoidle */
3308 REG_FLD_MOD(DSI_SYSCONFIG, 1, 0, 0);
3309
3310 /* ENWAKEUP */
3311 REG_FLD_MOD(DSI_SYSCONFIG, 1, 2, 2);
3312
3313 /* SIDLEMODE smart-idle */
3314 REG_FLD_MOD(DSI_SYSCONFIG, 2, 4, 3);
3315
3316 _dsi_initialize_irq();
3317
3318 return 0;
3319}
3320
3321static int dsi_display_enable(struct omap_dss_device *dssdev)
3322{
3323 int r = 0;
3324
3325 DSSDBG("dsi_display_enable\n");
3326
3327 mutex_lock(&dsi.lock);
3328 dsi_bus_lock();
3329
3330 r = omap_dss_start_device(dssdev);
3331 if (r) {
3332 DSSERR("failed to start device\n");
3333 goto err0;
3334 }
3335
3336 if (dssdev->state != OMAP_DSS_DISPLAY_DISABLED) {
3337 DSSERR("dssdev already enabled\n");
3338 r = -EINVAL;
3339 goto err1;
3340 }
3341
3342 enable_clocks(1);
3343 dsi_enable_pll_clock(1);
3344
3345 r = _dsi_reset();
3346 if (r)
3347 goto err2;
3348
3349 dsi_core_init();
3350
3351 r = dsi_display_init_dispc(dssdev);
3352 if (r)
3353 goto err2;
3354
3355 r = dsi_display_init_dsi(dssdev);
3356 if (r)
3357 goto err3;
3358
3359 dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
3360
3361 dsi.use_ext_te = dssdev->phy.dsi.ext_te;
3362 r = dsi_set_te(dssdev, dsi.te_enabled);
3363 if (r)
3364 goto err4;
3365
3366 dsi_set_update_mode(dssdev, dsi.user_update_mode);
3367
3368 dsi_bus_unlock();
3369 mutex_unlock(&dsi.lock);
3370
3371 return 0;
3372
3373err4:
3374
3375 dsi_display_uninit_dsi(dssdev);
3376err3:
3377 dsi_display_uninit_dispc(dssdev);
3378err2:
3379 enable_clocks(0);
3380 dsi_enable_pll_clock(0);
3381err1:
3382 omap_dss_stop_device(dssdev);
3383err0:
3384 dsi_bus_unlock();
3385 mutex_unlock(&dsi.lock);
3386 DSSDBG("dsi_display_enable FAILED\n");
3387 return r;
3388}
3389
3390static void dsi_display_disable(struct omap_dss_device *dssdev)
3391{
3392 DSSDBG("dsi_display_disable\n");
3393
3394 mutex_lock(&dsi.lock);
3395 dsi_bus_lock();
3396
3397 if (dssdev->state == OMAP_DSS_DISPLAY_DISABLED ||
3398 dssdev->state == OMAP_DSS_DISPLAY_SUSPENDED)
3399 goto end;
3400
3401 dsi.update_mode = OMAP_DSS_UPDATE_DISABLED;
3402 dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
3403
3404 dsi_display_uninit_dispc(dssdev);
3405
3406 dsi_display_uninit_dsi(dssdev);
3407
3408 enable_clocks(0);
3409 dsi_enable_pll_clock(0);
3410
3411 omap_dss_stop_device(dssdev);
3412end:
3413 dsi_bus_unlock();
3414 mutex_unlock(&dsi.lock);
3415}
3416
3417static int dsi_display_suspend(struct omap_dss_device *dssdev)
3418{
3419 DSSDBG("dsi_display_suspend\n");
3420
3421 mutex_lock(&dsi.lock);
3422 dsi_bus_lock();
3423
3424 if (dssdev->state == OMAP_DSS_DISPLAY_DISABLED ||
3425 dssdev->state == OMAP_DSS_DISPLAY_SUSPENDED)
3426 goto end;
3427
3428 dsi.update_mode = OMAP_DSS_UPDATE_DISABLED;
3429 dssdev->state = OMAP_DSS_DISPLAY_SUSPENDED;
3430
3431 dsi_display_uninit_dispc(dssdev);
3432
3433 dsi_display_uninit_dsi(dssdev);
3434
3435 enable_clocks(0);
3436 dsi_enable_pll_clock(0);
3437end:
3438 dsi_bus_unlock();
3439 mutex_unlock(&dsi.lock);
3440
3441 return 0;
3442}
3443
3444static int dsi_display_resume(struct omap_dss_device *dssdev)
3445{
3446 int r;
3447
3448 DSSDBG("dsi_display_resume\n");
3449
3450 mutex_lock(&dsi.lock);
3451 dsi_bus_lock();
3452
3453 if (dssdev->state != OMAP_DSS_DISPLAY_SUSPENDED) {
3454 DSSERR("dssdev not suspended\n");
3455 r = -EINVAL;
3456 goto err0;
3457 }
3458
3459 enable_clocks(1);
3460 dsi_enable_pll_clock(1);
3461
3462 r = _dsi_reset();
3463 if (r)
3464 goto err1;
3465
3466 dsi_core_init();
3467
3468 r = dsi_display_init_dispc(dssdev);
3469 if (r)
3470 goto err1;
3471
3472 r = dsi_display_init_dsi(dssdev);
3473 if (r)
3474 goto err2;
3475
3476 dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
3477
3478 r = dsi_set_te(dssdev, dsi.te_enabled);
3479 if (r)
3480 goto err2;
3481
3482 dsi_set_update_mode(dssdev, dsi.user_update_mode);
3483
3484 dsi_bus_unlock();
3485 mutex_unlock(&dsi.lock);
3486
3487 return 0;
3488
3489err2:
3490 dsi_display_uninit_dispc(dssdev);
3491err1:
3492 enable_clocks(0);
3493 dsi_enable_pll_clock(0);
3494err0:
3495 dsi_bus_unlock();
3496 mutex_unlock(&dsi.lock);
3497 DSSDBG("dsi_display_resume FAILED\n");
3498 return r;
3499}
3500
3501static int dsi_display_update(struct omap_dss_device *dssdev,
3502 u16 x, u16 y, u16 w, u16 h)
3503{
3504 int r = 0;
3505 u16 dw, dh;
3506
3507 DSSDBG("dsi_display_update(%d,%d %dx%d)\n", x, y, w, h);
3508
3509 mutex_lock(&dsi.lock);
3510
3511 if (dsi.update_mode != OMAP_DSS_UPDATE_MANUAL)
3512 goto end;
3513
3514 if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)
3515 goto end;
3516
3517 dssdev->get_resolution(dssdev, &dw, &dh);
3518
3519 if (x > dw || y > dh)
3520 goto end;
3521
3522 if (x + w > dw)
3523 w = dw - x;
3524
3525 if (y + h > dh)
3526 h = dh - y;
3527
3528 if (w == 0 || h == 0)
3529 goto end;
3530
3531 if (w == 1) {
3532 r = -EINVAL;
3533 goto end;
3534 }
3535
3536 dsi_set_update_region(dssdev, x, y, w, h);
3537
3538 wake_up(&dsi.waitqueue);
3539
3540end:
3541 mutex_unlock(&dsi.lock);
3542
3543 return r;
3544}
3545
3546static int dsi_display_sync(struct omap_dss_device *dssdev)
3547{
3548 bool wait;
3549
3550 DSSDBG("dsi_display_sync()\n");
3551
3552 mutex_lock(&dsi.lock);
3553 dsi_bus_lock();
3554
3555 if (dsi.update_mode == OMAP_DSS_UPDATE_MANUAL &&
3556 dsi.update_region.dirty) {
3557 INIT_COMPLETION(dsi.update_completion);
3558 wait = true;
3559 } else {
3560 wait = false;
3561 }
3562
3563 dsi_bus_unlock();
3564 mutex_unlock(&dsi.lock);
3565
3566 if (wait)
3567 wait_for_completion_interruptible(&dsi.update_completion);
3568
3569 DSSDBG("dsi_display_sync() done\n");
3570 return 0;
3571}
3572
3573static int dsi_display_set_update_mode(struct omap_dss_device *dssdev,
3574 enum omap_dss_update_mode mode)
3575{
3576 int r = 0;
3577
3578 DSSDBGF("%d", mode);
3579
3580 mutex_lock(&dsi.lock);
3581 dsi_bus_lock();
3582
3583 dsi.user_update_mode = mode;
3584 r = dsi_set_update_mode(dssdev, mode);
3585
3586 dsi_bus_unlock();
3587 mutex_unlock(&dsi.lock);
3588
3589 return r;
3590}
3591
3592static enum omap_dss_update_mode dsi_display_get_update_mode(
3593 struct omap_dss_device *dssdev)
3594{
3595 return dsi.update_mode;
3596}
3597
3598
3599static int dsi_display_enable_te(struct omap_dss_device *dssdev, bool enable)
3600{
3601 int r = 0;
3602
3603 DSSDBGF("%d", enable);
3604
3605 if (!dssdev->driver->enable_te)
3606 return -ENOENT;
3607
3608 dsi_bus_lock();
3609
3610 dsi.te_enabled = enable;
3611
3612 if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)
3613 goto end;
3614
3615 r = dsi_set_te(dssdev, enable);
3616end:
3617 dsi_bus_unlock();
3618
3619 return r;
3620}
3621
3622static int dsi_display_get_te(struct omap_dss_device *dssdev)
3623{
3624 return dsi.te_enabled;
3625}
3626
3627static int dsi_display_set_rotate(struct omap_dss_device *dssdev, u8 rotate)
3628{
3629
3630 DSSDBGF("%d", rotate);
3631
3632 if (!dssdev->driver->set_rotate || !dssdev->driver->get_rotate)
3633 return -EINVAL;
3634
3635 dsi_bus_lock();
3636 dssdev->driver->set_rotate(dssdev, rotate);
3637 if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO) {
3638 u16 w, h;
3639 /* the display dimensions may have changed, so set a new
3640 * update region */
3641 dssdev->get_resolution(dssdev, &w, &h);
3642 dsi_set_update_region(dssdev, 0, 0, w, h);
3643 }
3644 dsi_bus_unlock();
3645
3646 return 0;
3647}
3648
3649static u8 dsi_display_get_rotate(struct omap_dss_device *dssdev)
3650{
3651 if (!dssdev->driver->set_rotate || !dssdev->driver->get_rotate)
3652 return 0;
3653
3654 return dssdev->driver->get_rotate(dssdev);
3655}
3656
3657static int dsi_display_set_mirror(struct omap_dss_device *dssdev, bool mirror)
3658{
3659 DSSDBGF("%d", mirror);
3660
3661 if (!dssdev->driver->set_mirror || !dssdev->driver->get_mirror)
3662 return -EINVAL;
3663
3664 dsi_bus_lock();
3665 dssdev->driver->set_mirror(dssdev, mirror);
3666 dsi_bus_unlock();
3667
3668 return 0;
3669}
3670
3671static bool dsi_display_get_mirror(struct omap_dss_device *dssdev)
3672{
3673 if (!dssdev->driver->set_mirror || !dssdev->driver->get_mirror)
3674 return 0;
3675
3676 return dssdev->driver->get_mirror(dssdev);
3677}
3678
3679static int dsi_display_run_test(struct omap_dss_device *dssdev, int test_num)
3680{
3681 int r;
3682
3683 if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)
3684 return -EIO;
3685
3686 DSSDBGF("%d", test_num);
3687
3688 dsi_bus_lock();
3689
3690 /* run test first in low speed mode */
3691 dsi_vc_enable_hs(0, 0);
3692
3693 if (dssdev->driver->run_test) {
3694 r = dssdev->driver->run_test(dssdev, test_num);
3695 if (r)
3696 goto end;
3697 }
3698
3699 /* then in high speed */
3700 dsi_vc_enable_hs(0, 1);
3701
3702 if (dssdev->driver->run_test) {
3703 r = dssdev->driver->run_test(dssdev, test_num);
3704 if (r)
3705 goto end;
3706 }
3707
3708end:
3709 dsi_vc_enable_hs(0, 1);
3710
3711 dsi_bus_unlock();
3712
3713 return r;
3714}
3715
3716static int dsi_display_memory_read(struct omap_dss_device *dssdev,
3717 void *buf, size_t size,
3718 u16 x, u16 y, u16 w, u16 h)
3719{
3720 int r;
3721
3722 DSSDBGF("");
3723
3724 if (!dssdev->driver->memory_read)
3725 return -EINVAL;
3726
3727 if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)
3728 return -EIO;
3729
3730 dsi_bus_lock();
3731
3732 r = dssdev->driver->memory_read(dssdev, buf, size,
3733 x, y, w, h);
3734
3735 /* Memory read usually changes the update area. This will
3736 * force the next update to re-set the update area */
3737 dsi.active_update_region.dirty = true;
3738
3739 dsi_bus_unlock();
3740
3741 return r;
3742}
3743
3744void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
3745 u32 fifo_size, enum omap_burst_size *burst_size,
3746 u32 *fifo_low, u32 *fifo_high)
3747{
3748 unsigned burst_size_bytes;
3749
3750 *burst_size = OMAP_DSS_BURST_16x32;
3751 burst_size_bytes = 16 * 32 / 8;
3752
3753 *fifo_high = fifo_size - burst_size_bytes;
3754 *fifo_low = fifo_size - burst_size_bytes * 8;
3755}
3756
3757int dsi_init_display(struct omap_dss_device *dssdev)
3758{
3759 DSSDBG("DSI init\n");
3760
3761 dssdev->enable = dsi_display_enable;
3762 dssdev->disable = dsi_display_disable;
3763 dssdev->suspend = dsi_display_suspend;
3764 dssdev->resume = dsi_display_resume;
3765 dssdev->update = dsi_display_update;
3766 dssdev->sync = dsi_display_sync;
3767 dssdev->set_update_mode = dsi_display_set_update_mode;
3768 dssdev->get_update_mode = dsi_display_get_update_mode;
3769 dssdev->enable_te = dsi_display_enable_te;
3770 dssdev->get_te = dsi_display_get_te;
3771
3772 dssdev->get_rotate = dsi_display_get_rotate;
3773 dssdev->set_rotate = dsi_display_set_rotate;
3774
3775 dssdev->get_mirror = dsi_display_get_mirror;
3776 dssdev->set_mirror = dsi_display_set_mirror;
3777
3778 dssdev->run_test = dsi_display_run_test;
3779 dssdev->memory_read = dsi_display_memory_read;
3780
3781 /* XXX these should be figured out dynamically */
3782 dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE |
3783 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM;
3784
3785 dsi.vc[0].dssdev = dssdev;
3786 dsi.vc[1].dssdev = dssdev;
3787
3788 return 0;
3789}
3790
3791int dsi_init(struct platform_device *pdev)
3792{
3793 u32 rev;
3794 int r;
3795 struct sched_param param = {
3796 .sched_priority = MAX_USER_RT_PRIO-1
3797 };
3798
3799 spin_lock_init(&dsi.errors_lock);
3800 dsi.errors = 0;
3801
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +02003802#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3803 spin_lock_init(&dsi.irq_stats_lock);
3804 dsi.irq_stats.last_reset = jiffies;
3805#endif
3806
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003807 init_completion(&dsi.bta_completion);
3808 init_completion(&dsi.update_completion);
3809
3810 dsi.thread = kthread_create(dsi_update_thread, NULL, "dsi");
3811 if (IS_ERR(dsi.thread)) {
3812 DSSERR("cannot create kthread\n");
3813 r = PTR_ERR(dsi.thread);
3814 goto err0;
3815 }
3816 sched_setscheduler(dsi.thread, SCHED_FIFO, &param);
3817
3818 init_waitqueue_head(&dsi.waitqueue);
3819 spin_lock_init(&dsi.update_lock);
3820
3821 mutex_init(&dsi.lock);
3822 mutex_init(&dsi.bus_lock);
3823
3824#ifdef DSI_CATCH_MISSING_TE
3825 init_timer(&dsi.te_timer);
3826 dsi.te_timer.function = dsi_te_timeout;
3827 dsi.te_timer.data = 0;
3828#endif
3829
3830 dsi.update_mode = OMAP_DSS_UPDATE_DISABLED;
3831 dsi.user_update_mode = OMAP_DSS_UPDATE_DISABLED;
3832
3833 dsi.base = ioremap(DSI_BASE, DSI_SZ_REGS);
3834 if (!dsi.base) {
3835 DSSERR("can't ioremap DSI\n");
3836 r = -ENOMEM;
3837 goto err1;
3838 }
3839
Tomi Valkeinen8a2cfea2010-02-04 17:03:41 +02003840 dsi.vdds_dsi_reg = dss_get_vdds_dsi();
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003841 if (IS_ERR(dsi.vdds_dsi_reg)) {
3842 iounmap(dsi.base);
3843 DSSERR("can't get VDDS_DSI regulator\n");
3844 r = PTR_ERR(dsi.vdds_dsi_reg);
3845 goto err2;
3846 }
3847
3848 enable_clocks(1);
3849
3850 rev = dsi_read_reg(DSI_REVISION);
3851 printk(KERN_INFO "OMAP DSI rev %d.%d\n",
3852 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3853
3854 enable_clocks(0);
3855
3856 wake_up_process(dsi.thread);
3857
3858 return 0;
3859err2:
3860 iounmap(dsi.base);
3861err1:
3862 kthread_stop(dsi.thread);
3863err0:
3864 return r;
3865}
3866
3867void dsi_exit(void)
3868{
3869 kthread_stop(dsi.thread);
3870
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003871 iounmap(dsi.base);
3872
3873 DSSDBG("omap_dsi_exit\n");
3874}
3875