blob: 5d4292811c146285f45acc0f47ebe0618d210127 [file] [log] [blame]
Jason Uhlenkott535c6a52007-07-19 01:49:48 -07001/*
2 * Intel 3000/3010 Memory Controller kernel module
3 * Copyright (C) 2007 Akamai Technologies, Inc.
4 * Shamelessly copied from:
5 * Intel D82875P Memory Controller kernel module
6 * (C) 2003 Linux Networx (http://lnxi.com)
7 *
8 * This file may be distributed under the terms of the
9 * GNU General Public License.
10 */
11
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/pci.h>
15#include <linux/pci_ids.h>
16#include <linux/slab.h>
Hitoshi Mitake7ed31e02008-02-07 00:15:02 -080017#include <linux/edac.h>
Jason Uhlenkott535c6a52007-07-19 01:49:48 -070018#include "edac_core.h"
19
20#define I3000_REVISION "1.1"
21
22#define EDAC_MOD_STR "i3000_edac"
23
24#define I3000_RANKS 8
25#define I3000_RANKS_PER_CHANNEL 4
26#define I3000_CHANNELS 2
27
28/* Intel 3000 register addresses - device 0 function 0 - DRAM Controller */
29
30#define I3000_MCHBAR 0x44 /* MCH Memory Mapped Register BAR */
31#define I3000_MCHBAR_MASK 0xffffc000
32#define I3000_MMR_WINDOW_SIZE 16384
33
Jason Uhlenkottce783d72008-02-07 00:14:53 -080034#define I3000_EDEAP 0x70 /* Extended DRAM Error Address Pointer (8b)
35 *
36 * 7:1 reserved
37 * 0 bit 32 of address
38 */
39#define I3000_DEAP 0x58 /* DRAM Error Address Pointer (32b)
40 *
41 * 31:7 address
42 * 6:1 reserved
43 * 0 Error channel 0/1
44 */
45#define I3000_DEAP_GRAIN (1 << 7)
Jason Uhlenkott4d2b1652008-02-07 00:14:54 -080046
Jason Uhlenkott870897a2008-02-07 00:15:05 -080047/*
48 * Helper functions to decode the DEAP/EDEAP hardware registers.
49 *
50 * The type promotion here is deliberate; we're deriving an
51 * unsigned long pfn and offset from hardware regs which are u8/u32.
52 */
53
Jason Uhlenkott4d2b1652008-02-07 00:14:54 -080054static inline unsigned long deap_pfn(u8 edeap, u32 deap)
55{
56 deap >>= PAGE_SHIFT;
57 deap |= (edeap & 1) << (32 - PAGE_SHIFT);
58 return deap;
59}
60
61static inline unsigned long deap_offset(u32 deap)
62{
63 return deap & ~(I3000_DEAP_GRAIN - 1) & ~PAGE_MASK;
64}
65
66static inline int deap_channel(u32 deap)
67{
68 return deap & 1;
69}
Jason Uhlenkott535c6a52007-07-19 01:49:48 -070070
Jason Uhlenkottce783d72008-02-07 00:14:53 -080071#define I3000_DERRSYN 0x5c /* DRAM Error Syndrome (8b)
72 *
73 * 7:0 DRAM ECC Syndrome
74 */
Jason Uhlenkott535c6a52007-07-19 01:49:48 -070075
Jason Uhlenkottce783d72008-02-07 00:14:53 -080076#define I3000_ERRSTS 0xc8 /* Error Status Register (16b)
77 *
78 * 15:12 reserved
79 * 11 MCH Thermal Sensor Event
80 * for SMI/SCI/SERR
81 * 10 reserved
82 * 9 LOCK to non-DRAM Memory Flag (LCKF)
83 * 8 Received Refresh Timeout Flag (RRTOF)
84 * 7:2 reserved
85 * 1 Multi-bit DRAM ECC Error Flag (DMERR)
86 * 0 Single-bit DRAM ECC Error Flag (DSERR)
87 */
Jason Uhlenkott535c6a52007-07-19 01:49:48 -070088#define I3000_ERRSTS_BITS 0x0b03 /* bits which indicate errors */
89#define I3000_ERRSTS_UE 0x0002
90#define I3000_ERRSTS_CE 0x0001
91
Jason Uhlenkottce783d72008-02-07 00:14:53 -080092#define I3000_ERRCMD 0xca /* Error Command (16b)
93 *
94 * 15:12 reserved
95 * 11 SERR on MCH Thermal Sensor Event
96 * (TSESERR)
97 * 10 reserved
98 * 9 SERR on LOCK to non-DRAM Memory
99 * (LCKERR)
100 * 8 SERR on DRAM Refresh Timeout
101 * (DRTOERR)
102 * 7:2 reserved
103 * 1 SERR Multi-Bit DRAM ECC Error
104 * (DMERR)
105 * 0 SERR on Single-Bit ECC Error
106 * (DSERR)
107 */
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700108
109/* Intel MMIO register space - device 0 function 0 - MMR space */
110
111#define I3000_DRB_SHIFT 25 /* 32MiB grain */
112
Jason Uhlenkottce783d72008-02-07 00:14:53 -0800113#define I3000_C0DRB 0x100 /* Channel 0 DRAM Rank Boundary (8b x 4)
114 *
115 * 7:0 Channel 0 DRAM Rank Boundary Address
116 */
117#define I3000_C1DRB 0x180 /* Channel 1 DRAM Rank Boundary (8b x 4)
118 *
119 * 7:0 Channel 1 DRAM Rank Boundary Address
120 */
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700121
Jason Uhlenkottce783d72008-02-07 00:14:53 -0800122#define I3000_C0DRA 0x108 /* Channel 0 DRAM Rank Attribute (8b x 2)
123 *
124 * 7 reserved
125 * 6:4 DRAM odd Rank Attribute
126 * 3 reserved
127 * 2:0 DRAM even Rank Attribute
128 *
129 * Each attribute defines the page
130 * size of the corresponding rank:
131 * 000: unpopulated
132 * 001: reserved
133 * 010: 4 KB
134 * 011: 8 KB
135 * 100: 16 KB
136 * Others: reserved
137 */
138#define I3000_C1DRA 0x188 /* Channel 1 DRAM Rank Attribute (8b x 2) */
Jason Uhlenkott4d2b1652008-02-07 00:14:54 -0800139
140static inline unsigned char odd_rank_attrib(unsigned char dra)
141{
142 return (dra & 0x70) >> 4;
143}
144
145static inline unsigned char even_rank_attrib(unsigned char dra)
146{
147 return dra & 0x07;
148}
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700149
Jason Uhlenkottce783d72008-02-07 00:14:53 -0800150#define I3000_C0DRC0 0x120 /* DRAM Controller Mode 0 (32b)
151 *
152 * 31:30 reserved
153 * 29 Initialization Complete (IC)
154 * 28:11 reserved
155 * 10:8 Refresh Mode Select (RMS)
156 * 7 reserved
157 * 6:4 Mode Select (SMS)
158 * 3:2 reserved
159 * 1:0 DRAM Type (DT)
160 */
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700161
Jason Uhlenkottce783d72008-02-07 00:14:53 -0800162#define I3000_C0DRC1 0x124 /* DRAM Controller Mode 1 (32b)
163 *
164 * 31 Enhanced Addressing Enable (ENHADE)
165 * 30:0 reserved
166 */
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700167
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700168enum i3000p_chips {
169 I3000 = 0,
170};
171
172struct i3000_dev_info {
173 const char *ctl_name;
174};
175
176struct i3000_error_info {
177 u16 errsts;
178 u8 derrsyn;
179 u8 edeap;
180 u32 deap;
181 u16 errsts2;
182};
183
184static const struct i3000_dev_info i3000_devs[] = {
185 [I3000] = {
Douglas Thompson052dfb42007-07-19 01:50:13 -0700186 .ctl_name = "i3000"},
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700187};
188
Douglas Thompsonf0440912007-07-19 01:50:19 -0700189static struct pci_dev *mci_pdev;
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700190static int i3000_registered = 1;
Dave Jiang456a2f92007-07-19 01:50:10 -0700191static struct edac_pci_ctl_info *i3000_pci;
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700192
193static void i3000_get_error_info(struct mem_ctl_info *mci,
Dave Jiang36b82892007-07-19 01:50:04 -0700194 struct i3000_error_info *info)
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700195{
196 struct pci_dev *pdev;
197
198 pdev = to_pci_dev(mci->dev);
199
200 /*
201 * This is a mess because there is no atomic way to read all the
202 * registers at once and the registers can transition from CE being
203 * overwritten by UE.
204 */
205 pci_read_config_word(pdev, I3000_ERRSTS, &info->errsts);
206 if (!(info->errsts & I3000_ERRSTS_BITS))
207 return;
208 pci_read_config_byte(pdev, I3000_EDEAP, &info->edeap);
209 pci_read_config_dword(pdev, I3000_DEAP, &info->deap);
210 pci_read_config_byte(pdev, I3000_DERRSYN, &info->derrsyn);
211 pci_read_config_word(pdev, I3000_ERRSTS, &info->errsts2);
212
213 /*
214 * If the error is the same for both reads then the first set
215 * of reads is valid. If there is a change then there is a CE
216 * with no info and the second set of reads is valid and
217 * should be UE info.
218 */
219 if ((info->errsts ^ info->errsts2) & I3000_ERRSTS_BITS) {
Dave Jiang36b82892007-07-19 01:50:04 -0700220 pci_read_config_byte(pdev, I3000_EDEAP, &info->edeap);
221 pci_read_config_dword(pdev, I3000_DEAP, &info->deap);
222 pci_read_config_byte(pdev, I3000_DERRSYN, &info->derrsyn);
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700223 }
224
Jason Uhlenkottce783d72008-02-07 00:14:53 -0800225 /*
226 * Clear any error bits.
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700227 * (Yes, we really clear bits by writing 1 to them.)
228 */
Dave Jiang36b82892007-07-19 01:50:04 -0700229 pci_write_bits16(pdev, I3000_ERRSTS, I3000_ERRSTS_BITS,
230 I3000_ERRSTS_BITS);
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700231}
232
233static int i3000_process_error_info(struct mem_ctl_info *mci,
Douglas Thompson052dfb42007-07-19 01:50:13 -0700234 struct i3000_error_info *info,
235 int handle_errors)
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700236{
Jason Uhlenkott4d2b1652008-02-07 00:14:54 -0800237 int row, multi_chan, channel;
238 unsigned long pfn, offset;
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700239
240 multi_chan = mci->csrows[0].nr_channels - 1;
241
242 if (!(info->errsts & I3000_ERRSTS_BITS))
243 return 0;
244
245 if (!handle_errors)
246 return 1;
247
248 if ((info->errsts ^ info->errsts2) & I3000_ERRSTS_BITS) {
249 edac_mc_handle_ce_no_info(mci, "UE overwrote CE");
250 info->errsts = info->errsts2;
251 }
252
Jason Uhlenkott4d2b1652008-02-07 00:14:54 -0800253 pfn = deap_pfn(info->edeap, info->deap);
254 offset = deap_offset(info->deap);
255 channel = deap_channel(info->deap);
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700256
257 row = edac_mc_find_csrow_by_page(mci, pfn);
258
259 if (info->errsts & I3000_ERRSTS_UE)
260 edac_mc_handle_ue(mci, pfn, offset, row, "i3000 UE");
261 else
262 edac_mc_handle_ce(mci, pfn, offset, info->derrsyn, row,
Douglas Thompson052dfb42007-07-19 01:50:13 -0700263 multi_chan ? channel : 0, "i3000 CE");
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700264
265 return 1;
266}
267
268static void i3000_check(struct mem_ctl_info *mci)
269{
270 struct i3000_error_info info;
271
272 debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
273 i3000_get_error_info(mci, &info);
274 i3000_process_error_info(mci, &info, 1);
275}
276
277static int i3000_is_interleaved(const unsigned char *c0dra,
278 const unsigned char *c1dra,
279 const unsigned char *c0drb,
280 const unsigned char *c1drb)
281{
282 int i;
283
Jason Uhlenkottce783d72008-02-07 00:14:53 -0800284 /*
285 * If the channels aren't populated identically then
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700286 * we're not interleaved.
287 */
288 for (i = 0; i < I3000_RANKS_PER_CHANNEL / 2; i++)
Jason Uhlenkott4d2b1652008-02-07 00:14:54 -0800289 if (odd_rank_attrib(c0dra[i]) != odd_rank_attrib(c1dra[i]) ||
290 even_rank_attrib(c0dra[i]) !=
291 even_rank_attrib(c1dra[i]))
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700292 return 0;
293
Jason Uhlenkottce783d72008-02-07 00:14:53 -0800294 /*
295 * If the rank boundaries for the two channels are different
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700296 * then we're not interleaved.
297 */
298 for (i = 0; i < I3000_RANKS_PER_CHANNEL; i++)
299 if (c0drb[i] != c1drb[i])
300 return 0;
301
302 return 1;
303}
304
305static int i3000_probe1(struct pci_dev *pdev, int dev_idx)
306{
307 int rc;
308 int i;
309 struct mem_ctl_info *mci = NULL;
310 unsigned long last_cumul_size;
311 int interleaved, nr_channels;
312 unsigned char dra[I3000_RANKS / 2], drb[I3000_RANKS];
313 unsigned char *c0dra = dra, *c1dra = &dra[I3000_RANKS_PER_CHANNEL / 2];
314 unsigned char *c0drb = drb, *c1drb = &drb[I3000_RANKS_PER_CHANNEL];
315 unsigned long mchbar;
Al Viro0bd84962007-07-26 17:36:09 +0100316 void __iomem *window;
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700317
318 debugf0("MC: %s()\n", __func__);
319
Dave Jiang36b82892007-07-19 01:50:04 -0700320 pci_read_config_dword(pdev, I3000_MCHBAR, (u32 *) & mchbar);
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700321 mchbar &= I3000_MCHBAR_MASK;
322 window = ioremap_nocache(mchbar, I3000_MMR_WINDOW_SIZE);
323 if (!window) {
Dave Jiang36b82892007-07-19 01:50:04 -0700324 printk(KERN_ERR "i3000: cannot map mmio space at 0x%lx\n",
Douglas Thompson052dfb42007-07-19 01:50:13 -0700325 mchbar);
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700326 return -ENODEV;
327 }
328
Hitoshi Mitake7ed31e02008-02-07 00:15:02 -0800329 switch (edac_op_state) {
330 case EDAC_OPSTATE_POLL:
331 case EDAC_OPSTATE_NMI:
332 break;
333 default:
334 edac_op_state = EDAC_OPSTATE_POLL;
335 break;
336 }
337
Dave Jiang36b82892007-07-19 01:50:04 -0700338 c0dra[0] = readb(window + I3000_C0DRA + 0); /* ranks 0,1 */
339 c0dra[1] = readb(window + I3000_C0DRA + 1); /* ranks 2,3 */
340 c1dra[0] = readb(window + I3000_C1DRA + 0); /* ranks 0,1 */
341 c1dra[1] = readb(window + I3000_C1DRA + 1); /* ranks 2,3 */
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700342
343 for (i = 0; i < I3000_RANKS_PER_CHANNEL; i++) {
344 c0drb[i] = readb(window + I3000_C0DRB + i);
345 c1drb[i] = readb(window + I3000_C1DRB + i);
346 }
347
348 iounmap(window);
349
Jason Uhlenkottce783d72008-02-07 00:14:53 -0800350 /*
351 * Figure out how many channels we have.
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700352 *
353 * If we have what the datasheet calls "asymmetric channels"
354 * (essentially the same as what was called "virtual single
355 * channel mode" in the i82875) then it's a single channel as
356 * far as EDAC is concerned.
357 */
358 interleaved = i3000_is_interleaved(c0dra, c1dra, c0drb, c1drb);
359 nr_channels = interleaved ? 2 : 1;
Doug Thompsonb8f6f972007-07-19 01:50:26 -0700360 mci = edac_mc_alloc(0, I3000_RANKS / nr_channels, nr_channels, 0);
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700361 if (!mci)
362 return -ENOMEM;
363
364 debugf3("MC: %s(): init mci\n", __func__);
365
366 mci->dev = &pdev->dev;
367 mci->mtype_cap = MEM_FLAG_DDR2;
368
369 mci->edac_ctl_cap = EDAC_FLAG_SECDED;
370 mci->edac_cap = EDAC_FLAG_SECDED;
371
372 mci->mod_name = EDAC_MOD_STR;
373 mci->mod_ver = I3000_REVISION;
374 mci->ctl_name = i3000_devs[dev_idx].ctl_name;
375 mci->dev_name = pci_name(pdev);
376 mci->edac_check = i3000_check;
377 mci->ctl_page_to_phys = NULL;
378
379 /*
380 * The dram rank boundary (DRB) reg values are boundary addresses
381 * for each DRAM rank with a granularity of 32MB. DRB regs are
382 * cumulative; the last one will contain the total memory
383 * contained in all ranks.
384 *
385 * If we're in interleaved mode then we're only walking through
386 * the ranks of controller 0, so we double all the values we see.
387 */
388 for (last_cumul_size = i = 0; i < mci->nr_csrows; i++) {
389 u8 value;
390 u32 cumul_size;
391 struct csrow_info *csrow = &mci->csrows[i];
392
393 value = drb[i];
394 cumul_size = value << (I3000_DRB_SHIFT - PAGE_SHIFT);
395 if (interleaved)
396 cumul_size <<= 1;
397 debugf3("MC: %s(): (%d) cumul_size 0x%x\n",
398 __func__, i, cumul_size);
399 if (cumul_size == last_cumul_size) {
400 csrow->mtype = MEM_EMPTY;
401 continue;
402 }
403
404 csrow->first_page = last_cumul_size;
405 csrow->last_page = cumul_size - 1;
406 csrow->nr_pages = cumul_size - last_cumul_size;
407 last_cumul_size = cumul_size;
408 csrow->grain = I3000_DEAP_GRAIN;
409 csrow->mtype = MEM_DDR2;
410 csrow->dtype = DEV_UNKNOWN;
411 csrow->edac_mode = EDAC_UNKNOWN;
412 }
413
Jason Uhlenkottce783d72008-02-07 00:14:53 -0800414 /*
415 * Clear any error bits.
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700416 * (Yes, we really clear bits by writing 1 to them.)
417 */
Dave Jiang36b82892007-07-19 01:50:04 -0700418 pci_write_bits16(pdev, I3000_ERRSTS, I3000_ERRSTS_BITS,
419 I3000_ERRSTS_BITS);
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700420
421 rc = -ENODEV;
Doug Thompsonb8f6f972007-07-19 01:50:26 -0700422 if (edac_mc_add_mc(mci)) {
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700423 debugf3("MC: %s(): failed edac_mc_add_mc()\n", __func__);
424 goto fail;
425 }
426
Dave Jiang456a2f92007-07-19 01:50:10 -0700427 /* allocating generic PCI control info */
428 i3000_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
429 if (!i3000_pci) {
430 printk(KERN_WARNING
431 "%s(): Unable to create PCI control\n",
432 __func__);
433 printk(KERN_WARNING
434 "%s(): PCI error report via EDAC not setup\n",
435 __func__);
436 }
437
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700438 /* get this far and it's successful */
439 debugf3("MC: %s(): success\n", __func__);
440 return 0;
441
Jason Uhlenkottce783d72008-02-07 00:14:53 -0800442fail:
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700443 if (mci)
444 edac_mc_free(mci);
445
446 return rc;
447}
448
449/* returns count (>= 0), or negative on error */
450static int __devinit i3000_init_one(struct pci_dev *pdev,
Douglas Thompson052dfb42007-07-19 01:50:13 -0700451 const struct pci_device_id *ent)
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700452{
453 int rc;
454
455 debugf0("MC: %s()\n", __func__);
456
457 if (pci_enable_device(pdev) < 0)
458 return -EIO;
459
460 rc = i3000_probe1(pdev, ent->driver_data);
Jason Uhlenkottce783d72008-02-07 00:14:53 -0800461 if (!mci_pdev)
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700462 mci_pdev = pci_dev_get(pdev);
463
464 return rc;
465}
466
467static void __devexit i3000_remove_one(struct pci_dev *pdev)
468{
469 struct mem_ctl_info *mci;
470
471 debugf0("%s()\n", __func__);
472
Dave Jiang456a2f92007-07-19 01:50:10 -0700473 if (i3000_pci)
474 edac_pci_release_generic_ctl(i3000_pci);
475
Jason Uhlenkottce783d72008-02-07 00:14:53 -0800476 mci = edac_mc_del_mc(&pdev->dev);
477 if (!mci)
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700478 return;
479
480 edac_mc_free(mci);
481}
482
483static const struct pci_device_id i3000_pci_tbl[] __devinitdata = {
484 {
Dave Jiang36b82892007-07-19 01:50:04 -0700485 PCI_VEND_DEV(INTEL, 3000_HB), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
486 I3000},
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700487 {
Dave Jiang36b82892007-07-19 01:50:04 -0700488 0,
489 } /* 0 terminated list. */
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700490};
491
492MODULE_DEVICE_TABLE(pci, i3000_pci_tbl);
493
494static struct pci_driver i3000_driver = {
495 .name = EDAC_MOD_STR,
496 .probe = i3000_init_one,
497 .remove = __devexit_p(i3000_remove_one),
498 .id_table = i3000_pci_tbl,
499};
500
501static int __init i3000_init(void)
502{
503 int pci_rc;
504
505 debugf3("MC: %s()\n", __func__);
506 pci_rc = pci_register_driver(&i3000_driver);
507 if (pci_rc < 0)
508 goto fail0;
509
Jason Uhlenkottce783d72008-02-07 00:14:53 -0800510 if (!mci_pdev) {
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700511 i3000_registered = 0;
512 mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
Douglas Thompson052dfb42007-07-19 01:50:13 -0700513 PCI_DEVICE_ID_INTEL_3000_HB, NULL);
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700514 if (!mci_pdev) {
515 debugf0("i3000 pci_get_device fail\n");
516 pci_rc = -ENODEV;
517 goto fail1;
518 }
519
520 pci_rc = i3000_init_one(mci_pdev, i3000_pci_tbl);
521 if (pci_rc < 0) {
522 debugf0("i3000 init fail\n");
523 pci_rc = -ENODEV;
524 goto fail1;
525 }
526 }
527
528 return 0;
529
Douglas Thompson052dfb42007-07-19 01:50:13 -0700530fail1:
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700531 pci_unregister_driver(&i3000_driver);
532
Douglas Thompson052dfb42007-07-19 01:50:13 -0700533fail0:
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700534 if (mci_pdev)
535 pci_dev_put(mci_pdev);
536
537 return pci_rc;
538}
539
540static void __exit i3000_exit(void)
541{
542 debugf3("MC: %s()\n", __func__);
543
544 pci_unregister_driver(&i3000_driver);
545 if (!i3000_registered) {
546 i3000_remove_one(mci_pdev);
547 pci_dev_put(mci_pdev);
548 }
549}
550
551module_init(i3000_init);
552module_exit(i3000_exit);
553
554MODULE_LICENSE("GPL");
555MODULE_AUTHOR("Akamai Technologies Arthur Ulfeldt/Jason Uhlenkott");
556MODULE_DESCRIPTION("MC support for Intel 3000 memory hub controllers");
Hitoshi Mitake7ed31e02008-02-07 00:15:02 -0800557
558module_param(edac_op_state, int, 0444);
559MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");