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gerrit-public.fairphone.software / kernel / msm / 8768eff1b9a1a2baec5cd3bb9655ab0325976a27 / . / arch / arm / mach-msm / clock-dss-8960.c
blob: 7374f92d9bc3c642b44abee08f4aa2a1fbc33ed3 [file] [log] [blame]
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <linux/kernel.h>
14#include <linux/io.h>
15#include <linux/errno.h>
16#include <linux/delay.h>
17#include <asm/processor.h>
18#include <mach/msm_iomap.h>
19#include "clock-dss-8960.h"
20
21/* HDMI PLL macros */
22#define HDMI_PHY_PLL_REFCLK_CFG (MSM_HDMI_BASE + 0x00000500)
23#define HDMI_PHY_PLL_CHRG_PUMP_CFG (MSM_HDMI_BASE + 0x00000504)
24#define HDMI_PHY_PLL_LOOP_FLT_CFG0 (MSM_HDMI_BASE + 0x00000508)
25#define HDMI_PHY_PLL_LOOP_FLT_CFG1 (MSM_HDMI_BASE + 0x0000050c)
26#define HDMI_PHY_PLL_IDAC_ADJ_CFG (MSM_HDMI_BASE + 0x00000510)
27#define HDMI_PHY_PLL_I_VI_KVCO_CFG (MSM_HDMI_BASE + 0x00000514)
28#define HDMI_PHY_PLL_PWRDN_B (MSM_HDMI_BASE + 0x00000518)
29#define HDMI_PHY_PLL_SDM_CFG0 (MSM_HDMI_BASE + 0x0000051c)
30#define HDMI_PHY_PLL_SDM_CFG1 (MSM_HDMI_BASE + 0x00000520)
31#define HDMI_PHY_PLL_SDM_CFG2 (MSM_HDMI_BASE + 0x00000524)
32#define HDMI_PHY_PLL_SDM_CFG3 (MSM_HDMI_BASE + 0x00000528)
33#define HDMI_PHY_PLL_SDM_CFG4 (MSM_HDMI_BASE + 0x0000052c)
34#define HDMI_PHY_PLL_SSC_CFG0 (MSM_HDMI_BASE + 0x00000530)
35#define HDMI_PHY_PLL_SSC_CFG1 (MSM_HDMI_BASE + 0x00000534)
36#define HDMI_PHY_PLL_SSC_CFG2 (MSM_HDMI_BASE + 0x00000538)
37#define HDMI_PHY_PLL_SSC_CFG3 (MSM_HDMI_BASE + 0x0000053c)
38#define HDMI_PHY_PLL_LOCKDET_CFG0 (MSM_HDMI_BASE + 0x00000540)
39#define HDMI_PHY_PLL_LOCKDET_CFG1 (MSM_HDMI_BASE + 0x00000544)
40#define HDMI_PHY_PLL_LOCKDET_CFG2 (MSM_HDMI_BASE + 0x00000548)
41#define HDMI_PHY_PLL_VCOCAL_CFG0 (MSM_HDMI_BASE + 0x0000054c)
42#define HDMI_PHY_PLL_VCOCAL_CFG1 (MSM_HDMI_BASE + 0x00000550)
43#define HDMI_PHY_PLL_VCOCAL_CFG2 (MSM_HDMI_BASE + 0x00000554)
44#define HDMI_PHY_PLL_VCOCAL_CFG3 (MSM_HDMI_BASE + 0x00000558)
45#define HDMI_PHY_PLL_VCOCAL_CFG4 (MSM_HDMI_BASE + 0x0000055c)
46#define HDMI_PHY_PLL_VCOCAL_CFG5 (MSM_HDMI_BASE + 0x00000560)
47#define HDMI_PHY_PLL_VCOCAL_CFG6 (MSM_HDMI_BASE + 0x00000564)
48#define HDMI_PHY_PLL_VCOCAL_CFG7 (MSM_HDMI_BASE + 0x00000568)
49#define HDMI_PHY_PLL_DEBUG_SEL (MSM_HDMI_BASE + 0x0000056c)
50#define HDMI_PHY_PLL_MISC0 (MSM_HDMI_BASE + 0x00000570)
51#define HDMI_PHY_PLL_MISC1 (MSM_HDMI_BASE + 0x00000574)
52#define HDMI_PHY_PLL_MISC2 (MSM_HDMI_BASE + 0x00000578)
53#define HDMI_PHY_PLL_MISC3 (MSM_HDMI_BASE + 0x0000057c)
54#define HDMI_PHY_PLL_MISC4 (MSM_HDMI_BASE + 0x00000580)
55#define HDMI_PHY_PLL_MISC5 (MSM_HDMI_BASE + 0x00000584)
56#define HDMI_PHY_PLL_MISC6 (MSM_HDMI_BASE + 0x00000588)
57#define HDMI_PHY_PLL_DEBUG_BUS0 (MSM_HDMI_BASE + 0x0000058c)
58#define HDMI_PHY_PLL_DEBUG_BUS1 (MSM_HDMI_BASE + 0x00000590)
59#define HDMI_PHY_PLL_DEBUG_BUS2 (MSM_HDMI_BASE + 0x00000594)
60#define HDMI_PHY_PLL_STATUS0 (MSM_HDMI_BASE + 0x00000598)
61#define HDMI_PHY_PLL_STATUS1 (MSM_HDMI_BASE + 0x0000059c)
62#define HDMI_PHY_CTRL (MSM_HDMI_BASE + 0x000002D4)
63#define HDMI_PHY_REG_0 (MSM_HDMI_BASE + 0x00000400)
64#define HDMI_PHY_REG_1 (MSM_HDMI_BASE + 0x00000404)
65#define HDMI_PHY_REG_2 (MSM_HDMI_BASE + 0x00000408)
66#define HDMI_PHY_REG_3 (MSM_HDMI_BASE + 0x0000040c)
67#define HDMI_PHY_REG_4 (MSM_HDMI_BASE + 0x00000410)
68#define HDMI_PHY_REG_5 (MSM_HDMI_BASE + 0x00000414)
69#define HDMI_PHY_REG_6 (MSM_HDMI_BASE + 0x00000418)
70#define HDMI_PHY_REG_7 (MSM_HDMI_BASE + 0x0000041c)
71#define HDMI_PHY_REG_8 (MSM_HDMI_BASE + 0x00000420)
72#define HDMI_PHY_REG_9 (MSM_HDMI_BASE + 0x00000424)
73#define HDMI_PHY_REG_10 (MSM_HDMI_BASE + 0x00000428)
74#define HDMI_PHY_REG_11 (MSM_HDMI_BASE + 0x0000042c)
75#define HDMI_PHY_REG_12 (MSM_HDMI_BASE + 0x00000430)
76#define HDMI_PHY_REG_BIST_CFG (MSM_HDMI_BASE + 0x00000434)
77#define HDMI_PHY_DEBUG_BUS_SEL (MSM_HDMI_BASE + 0x00000438)
78#define HDMI_PHY_REG_MISC0 (MSM_HDMI_BASE + 0x0000043c)
79#define HDMI_PHY_REG_13 (MSM_HDMI_BASE + 0x00000440)
80#define HDMI_PHY_REG_14 (MSM_HDMI_BASE + 0x00000444)
81#define HDMI_PHY_REG_15 (MSM_HDMI_BASE + 0x00000448)
82
83#define AHB_EN_REG (MSM_MMSS_CLK_CTL_BASE + 0x0008)
84
85/* HDMI PHY/PLL bit field macros */
86#define SW_RESET BIT(2)
87#define SW_RESET_PLL BIT(0)
88#define PWRDN_B BIT(7)
89
90#define PLL_PWRDN_B BIT(3)
91#define PD_PLL BIT(1)
92
93static unsigned current_rate;
94static unsigned hdmi_pll_on;
95
96int hdmi_pll_enable(void)
97{
98 unsigned int val;
99 u32 ahb_en_reg, ahb_enabled;
100
101 ahb_en_reg = readl_relaxed(AHB_EN_REG);
102 ahb_enabled = ahb_en_reg & BIT(4);
103 if (!ahb_enabled) {
104 writel_relaxed(ahb_en_reg | BIT(4), AHB_EN_REG);
105 mb();
106 }
107
108 val = readl_relaxed(HDMI_PHY_PLL_PWRDN_B);
109 val |= PLL_PWRDN_B;
110 writel_relaxed(val, HDMI_PHY_PLL_PWRDN_B);
111 mb();
112 val &= ~PD_PLL;
113 writel_relaxed(val, HDMI_PHY_PLL_PWRDN_B);
114 mb();
115
116 while (!(readl_relaxed(HDMI_PHY_PLL_STATUS0) & BIT(0)))
117 cpu_relax();
118
119 if (!ahb_enabled)
120 writel_relaxed(ahb_en_reg & ~BIT(4), AHB_EN_REG);
121 hdmi_pll_on = 1;
122 return 0;
123}
124
125void hdmi_pll_disable(void)
126{
127 unsigned int val;
128 u32 ahb_en_reg, ahb_enabled;
129
130 ahb_en_reg = readl_relaxed(AHB_EN_REG);
131 ahb_enabled = ahb_en_reg & BIT(4);
132 if (!ahb_enabled) {
133 writel_relaxed(ahb_en_reg | BIT(4), AHB_EN_REG);
134 mb();
135 }
136
137 val = readl_relaxed(HDMI_PHY_PLL_PWRDN_B);
138 val |= PD_PLL;
139 writel_relaxed(val, HDMI_PHY_PLL_PWRDN_B);
140 mb();
141
142 val = val & (~PLL_PWRDN_B);
143 writel_relaxed(val, HDMI_PHY_PLL_PWRDN_B);
144 mb();
145
146 if (!ahb_enabled)
147 writel_relaxed(ahb_en_reg & ~BIT(4), AHB_EN_REG);
148 hdmi_pll_on = 0;
149}
150
151unsigned hdmi_pll_get_rate(void)
152{
153 return current_rate;
154}
155
156int hdmi_pll_set_rate(unsigned rate)
157{
158 unsigned int set_power_dwn = 0;
159 unsigned int val;
160 u32 ahb_en_reg = readl_relaxed(AHB_EN_REG);
161 u32 ahb_enabled = ahb_en_reg & BIT(4);
162
163 if (!ahb_enabled) {
164 writel_relaxed(ahb_en_reg | BIT(4), AHB_EN_REG);
165 mb();
166 }
167
168 writel_relaxed(0x7f, HDMI_PHY_REG_2);
169 writel_relaxed(0x3f, HDMI_PHY_REG_2);
170 writel_relaxed(0x1f, HDMI_PHY_REG_2);
171
172 val = readl_relaxed(HDMI_PHY_REG_12);
173 val |= PWRDN_B;
174 writel_relaxed(val, HDMI_PHY_REG_12);
175 mb();
176
177 writel_relaxed(0x81, HDMI_PHY_REG_2);
178 if (hdmi_pll_on) {
179 hdmi_pll_disable();
180 set_power_dwn = 1;
181 }
182
183 switch (rate) {
184 case 27030000:
185 /* 480p60/480i60 case */
186 writel_relaxed(0x32, HDMI_PHY_PLL_REFCLK_CFG);
187 writel_relaxed(0x2, HDMI_PHY_PLL_CHRG_PUMP_CFG);
188 writel_relaxed(0x08, HDMI_PHY_PLL_LOOP_FLT_CFG0);
189 writel_relaxed(0x77, HDMI_PHY_PLL_LOOP_FLT_CFG1);
190 writel_relaxed(0x2C, HDMI_PHY_PLL_IDAC_ADJ_CFG);
191 writel_relaxed(0x6, HDMI_PHY_PLL_I_VI_KVCO_CFG);
192 writel_relaxed(0x7b, HDMI_PHY_PLL_SDM_CFG0);
193 writel_relaxed(0x01, HDMI_PHY_PLL_SDM_CFG1);
194 writel_relaxed(0x4C, HDMI_PHY_PLL_SDM_CFG2);
195 writel_relaxed(0xC0, HDMI_PHY_PLL_SDM_CFG3);
196 writel_relaxed(0x00, HDMI_PHY_PLL_SDM_CFG4);
197 writel_relaxed(0x9A, HDMI_PHY_PLL_SSC_CFG0);
198 writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG1);
199 writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG2);
200 writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG3);
201 writel_relaxed(0x10, HDMI_PHY_PLL_LOCKDET_CFG0);
202 writel_relaxed(0x1A, HDMI_PHY_PLL_LOCKDET_CFG1);
203 writel_relaxed(0x0D, HDMI_PHY_PLL_LOCKDET_CFG2);
204 writel_relaxed(0x2A, HDMI_PHY_PLL_VCOCAL_CFG0);
205 writel_relaxed(0x03, HDMI_PHY_PLL_VCOCAL_CFG1);
206 writel_relaxed(0x2B, HDMI_PHY_PLL_VCOCAL_CFG2);
207 writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG3);
208 writel_relaxed(0x86, HDMI_PHY_PLL_VCOCAL_CFG4);
209 writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG5);
210 writel_relaxed(0x33, HDMI_PHY_PLL_VCOCAL_CFG6);
211 writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG7);
212 break;
213
214 case 25200000:
215 /* 640x480p60 */
216 writel_relaxed(0x32, HDMI_PHY_PLL_REFCLK_CFG);
217 writel_relaxed(0x2, HDMI_PHY_PLL_CHRG_PUMP_CFG);
218 writel_relaxed(0x01, HDMI_PHY_PLL_LOOP_FLT_CFG0);
219 writel_relaxed(0x33, HDMI_PHY_PLL_LOOP_FLT_CFG1);
220 writel_relaxed(0x2C, HDMI_PHY_PLL_IDAC_ADJ_CFG);
221 writel_relaxed(0x6, HDMI_PHY_PLL_I_VI_KVCO_CFG);
222 writel_relaxed(0x77, HDMI_PHY_PLL_SDM_CFG0);
223 writel_relaxed(0x4C, HDMI_PHY_PLL_SDM_CFG1);
224 writel_relaxed(0x00, HDMI_PHY_PLL_SDM_CFG2);
225 writel_relaxed(0xC0, HDMI_PHY_PLL_SDM_CFG3);
226 writel_relaxed(0x00, HDMI_PHY_PLL_SDM_CFG4);
227 writel_relaxed(0x9A, HDMI_PHY_PLL_SSC_CFG0);
228 writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG1);
229 writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG2);
230 writel_relaxed(0x20, HDMI_PHY_PLL_SSC_CFG3);
231 writel_relaxed(0x10, HDMI_PHY_PLL_LOCKDET_CFG0);
232 writel_relaxed(0x1A, HDMI_PHY_PLL_LOCKDET_CFG1);
233 writel_relaxed(0x0D, HDMI_PHY_PLL_LOCKDET_CFG2);
234 writel_relaxed(0xF4, HDMI_PHY_PLL_VCOCAL_CFG0);
235 writel_relaxed(0x02, HDMI_PHY_PLL_VCOCAL_CFG1);
236 writel_relaxed(0x2B, HDMI_PHY_PLL_VCOCAL_CFG2);
237 writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG3);
238 writel_relaxed(0x86, HDMI_PHY_PLL_VCOCAL_CFG4);
239 writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG5);
240 writel_relaxed(0x33, HDMI_PHY_PLL_VCOCAL_CFG6);
241 writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG7);
242 break;
243
244 case 27000000:
245 /* 576p50/576i50 case */
246 writel_relaxed(0x32, HDMI_PHY_PLL_REFCLK_CFG);
247 writel_relaxed(0x2, HDMI_PHY_PLL_CHRG_PUMP_CFG);
248 writel_relaxed(0x01, HDMI_PHY_PLL_LOOP_FLT_CFG0);
249 writel_relaxed(0x33, HDMI_PHY_PLL_LOOP_FLT_CFG1);
250 writel_relaxed(0x2C, HDMI_PHY_PLL_IDAC_ADJ_CFG);
251 writel_relaxed(0x6, HDMI_PHY_PLL_I_VI_KVCO_CFG);
252 writel_relaxed(0x7B, HDMI_PHY_PLL_SDM_CFG0);
253 writel_relaxed(0x01, HDMI_PHY_PLL_SDM_CFG1);
254 writel_relaxed(0x4C, HDMI_PHY_PLL_SDM_CFG2);
255 writel_relaxed(0xC0, HDMI_PHY_PLL_SDM_CFG3);
256 writel_relaxed(0x00, HDMI_PHY_PLL_SDM_CFG4);
257 writel_relaxed(0x9A, HDMI_PHY_PLL_SSC_CFG0);
258 writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG1);
259 writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG2);
260 writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG3);
261 writel_relaxed(0x10, HDMI_PHY_PLL_LOCKDET_CFG0);
262 writel_relaxed(0x1A, HDMI_PHY_PLL_LOCKDET_CFG1);
263 writel_relaxed(0x0D, HDMI_PHY_PLL_LOCKDET_CFG2);
264 writel_relaxed(0x2a, HDMI_PHY_PLL_VCOCAL_CFG0);
265 writel_relaxed(0x03, HDMI_PHY_PLL_VCOCAL_CFG1);
266 writel_relaxed(0x2B, HDMI_PHY_PLL_VCOCAL_CFG2);
267 writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG3);
268 writel_relaxed(0x86, HDMI_PHY_PLL_VCOCAL_CFG4);
269 writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG5);
270 writel_relaxed(0x33, HDMI_PHY_PLL_VCOCAL_CFG6);
271 writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG7);
272 break;
273
274 case 74250000:
275 /* 720p60/720p50/1080i60/1080i50
276 * 1080p24/1080p30/1080p25 case
277 */
278 writel_relaxed(0x12, HDMI_PHY_PLL_REFCLK_CFG);
279 writel_relaxed(0x01, HDMI_PHY_PLL_LOOP_FLT_CFG0);
280 writel_relaxed(0x33, HDMI_PHY_PLL_LOOP_FLT_CFG1);
281 writel_relaxed(0x76, HDMI_PHY_PLL_SDM_CFG0);
282 writel_relaxed(0xE6, HDMI_PHY_PLL_VCOCAL_CFG0);
283 writel_relaxed(0x02, HDMI_PHY_PLL_VCOCAL_CFG1);
284 break;
285
286 case 148500000:
287 /* 1080p60/1080p50 case */
288 writel_relaxed(0x2, HDMI_PHY_PLL_REFCLK_CFG);
289 writel_relaxed(0x2, HDMI_PHY_PLL_CHRG_PUMP_CFG);
290 writel_relaxed(0x01, HDMI_PHY_PLL_LOOP_FLT_CFG0);
291 writel_relaxed(0x33, HDMI_PHY_PLL_LOOP_FLT_CFG1);
292 writel_relaxed(0x2C, HDMI_PHY_PLL_IDAC_ADJ_CFG);
293 writel_relaxed(0x6, HDMI_PHY_PLL_I_VI_KVCO_CFG);
294 writel_relaxed(0x76, HDMI_PHY_PLL_SDM_CFG0);
295 writel_relaxed(0x01, HDMI_PHY_PLL_SDM_CFG1);
296 writel_relaxed(0x4C, HDMI_PHY_PLL_SDM_CFG2);
297 writel_relaxed(0xC0, HDMI_PHY_PLL_SDM_CFG3);
298 writel_relaxed(0x00, HDMI_PHY_PLL_SDM_CFG4);
299 writel_relaxed(0x9A, HDMI_PHY_PLL_SSC_CFG0);
300 writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG1);
301 writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG2);
302 writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG3);
303 writel_relaxed(0x10, HDMI_PHY_PLL_LOCKDET_CFG0);
304 writel_relaxed(0x1A, HDMI_PHY_PLL_LOCKDET_CFG1);
305 writel_relaxed(0x0D, HDMI_PHY_PLL_LOCKDET_CFG2);
306 writel_relaxed(0xe6, HDMI_PHY_PLL_VCOCAL_CFG0);
307 writel_relaxed(0x02, HDMI_PHY_PLL_VCOCAL_CFG1);
308 writel_relaxed(0x2B, HDMI_PHY_PLL_VCOCAL_CFG2);
309 writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG3);
310 writel_relaxed(0x86, HDMI_PHY_PLL_VCOCAL_CFG4);
311 writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG5);
312 writel_relaxed(0x33, HDMI_PHY_PLL_VCOCAL_CFG6);
313 writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG7);
314 writel_relaxed(0x0D, HDMI_PHY_PLL_LOCKDET_CFG2);
315 break;
316 }
317
318 mb();
319
320 if (set_power_dwn)
321 hdmi_pll_enable();
322
323 current_rate = rate;
324 if (!ahb_enabled)
325 writel_relaxed(ahb_en_reg & ~BIT(4), AHB_EN_REG);
326
327 return 0;
328}