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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Uwe Zeisbergerf30c2262006-10-03 23:01:26 +02002 * linux/drivers/ide/ppc/pmac.c
Linus Torvalds1da177e2005-04-16 15:20:36 -07003 *
4 * Support for IDE interfaces on PowerMacs.
5 * These IDE interfaces are memory-mapped and have a DBDMA channel
6 * for doing DMA.
7 *
8 * Copyright (C) 1998-2003 Paul Mackerras & Ben. Herrenschmidt
Bartlomiej Zolnierkiewiczc15d5d42007-10-11 23:54:01 +02009 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
Linus Torvalds1da177e2005-04-16 15:20:36 -070010 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
15 *
16 * Some code taken from drivers/ide/ide-dma.c:
17 *
18 * Copyright (c) 1995-1998 Mark Lord
19 *
20 * TODO: - Use pre-calculated (kauai) timing tables all the time and
21 * get rid of the "rounded" tables used previously, so we have the
22 * same table format for all controllers and can then just have one
23 * big table
24 *
25 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070026#include <linux/types.h>
27#include <linux/kernel.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070028#include <linux/init.h>
29#include <linux/delay.h>
30#include <linux/ide.h>
31#include <linux/notifier.h>
32#include <linux/reboot.h>
33#include <linux/pci.h>
34#include <linux/adb.h>
35#include <linux/pmu.h>
36#include <linux/scatterlist.h>
37
38#include <asm/prom.h>
39#include <asm/io.h>
40#include <asm/dbdma.h>
41#include <asm/ide.h>
42#include <asm/pci-bridge.h>
43#include <asm/machdep.h>
44#include <asm/pmac_feature.h>
45#include <asm/sections.h>
46#include <asm/irq.h>
47
48#ifndef CONFIG_PPC64
49#include <asm/mediabay.h>
50#endif
51
Andrew Morton9e5755b2007-03-03 17:48:54 +010052#include "../ide-timing.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070053
54#undef IDE_PMAC_DEBUG
55
56#define DMA_WAIT_TIMEOUT 50
57
58typedef struct pmac_ide_hwif {
59 unsigned long regbase;
60 int irq;
61 int kind;
62 int aapl_bus_id;
63 unsigned cable_80 : 1;
64 unsigned mediabay : 1;
65 unsigned broken_dma : 1;
66 unsigned broken_dma_warn : 1;
67 struct device_node* node;
68 struct macio_dev *mdev;
69 u32 timings[4];
70 volatile u32 __iomem * *kauai_fcr;
71#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
72 /* Those fields are duplicating what is in hwif. We currently
73 * can't use the hwif ones because of some assumptions that are
74 * beeing done by the generic code about the kind of dma controller
75 * and format of the dma table. This will have to be fixed though.
76 */
77 volatile struct dbdma_regs __iomem * dma_regs;
78 struct dbdma_cmd* dma_table_cpu;
79#endif
80
81} pmac_ide_hwif_t;
82
Jon Loeligeraacaf9b2005-09-17 10:36:54 -050083static pmac_ide_hwif_t pmac_ide[MAX_HWIFS];
Linus Torvalds1da177e2005-04-16 15:20:36 -070084static int pmac_ide_count;
85
86enum {
87 controller_ohare, /* OHare based */
88 controller_heathrow, /* Heathrow/Paddington */
89 controller_kl_ata3, /* KeyLargo ATA-3 */
90 controller_kl_ata4, /* KeyLargo ATA-4 */
91 controller_un_ata6, /* UniNorth2 ATA-6 */
92 controller_k2_ata6, /* K2 ATA-6 */
93 controller_sh_ata6, /* Shasta ATA-6 */
94};
95
96static const char* model_name[] = {
97 "OHare ATA", /* OHare based */
98 "Heathrow ATA", /* Heathrow/Paddington */
99 "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
100 "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */
101 "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */
102 "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */
103 "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */
104};
105
106/*
107 * Extra registers, both 32-bit little-endian
108 */
109#define IDE_TIMING_CONFIG 0x200
110#define IDE_INTERRUPT 0x300
111
112/* Kauai (U2) ATA has different register setup */
113#define IDE_KAUAI_PIO_CONFIG 0x200
114#define IDE_KAUAI_ULTRA_CONFIG 0x210
115#define IDE_KAUAI_POLL_CONFIG 0x220
116
117/*
118 * Timing configuration register definitions
119 */
120
121/* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
122#define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
123#define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
124#define IDE_SYSCLK_NS 30 /* 33Mhz cell */
125#define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */
126
127/* 133Mhz cell, found in shasta.
128 * See comments about 100 Mhz Uninorth 2...
129 * Note that PIO_MASK and MDMA_MASK seem to overlap
130 */
131#define TR_133_PIOREG_PIO_MASK 0xff000fff
132#define TR_133_PIOREG_MDMA_MASK 0x00fff800
133#define TR_133_UDMAREG_UDMA_MASK 0x0003ffff
134#define TR_133_UDMAREG_UDMA_EN 0x00000001
135
136/* 100Mhz cell, found in Uninorth 2. I don't have much infos about
137 * this one yet, it appears as a pci device (106b/0033) on uninorth
138 * internal PCI bus and it's clock is controlled like gem or fw. It
139 * appears to be an evolution of keylargo ATA4 with a timing register
140 * extended to 2 32bits registers and a similar DBDMA channel. Other
141 * registers seem to exist but I can't tell much about them.
142 *
143 * So far, I'm using pre-calculated tables for this extracted from
144 * the values used by the MacOS X driver.
145 *
146 * The "PIO" register controls PIO and MDMA timings, the "ULTRA"
147 * register controls the UDMA timings. At least, it seems bit 0
148 * of this one enables UDMA vs. MDMA, and bits 4..7 are the
149 * cycle time in units of 10ns. Bits 8..15 are used by I don't
150 * know their meaning yet
151 */
152#define TR_100_PIOREG_PIO_MASK 0xff000fff
153#define TR_100_PIOREG_MDMA_MASK 0x00fff000
154#define TR_100_UDMAREG_UDMA_MASK 0x0000ffff
155#define TR_100_UDMAREG_UDMA_EN 0x00000001
156
157
158/* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
159 * 40 connector cable and to 4 on 80 connector one.
160 * Clock unit is 15ns (66Mhz)
161 *
162 * 3 Values can be programmed:
163 * - Write data setup, which appears to match the cycle time. They
164 * also call it DIOW setup.
165 * - Ready to pause time (from spec)
166 * - Address setup. That one is weird. I don't see where exactly
167 * it fits in UDMA cycles, I got it's name from an obscure piece
168 * of commented out code in Darwin. They leave it to 0, we do as
169 * well, despite a comment that would lead to think it has a
170 * min value of 45ns.
171 * Apple also add 60ns to the write data setup (or cycle time ?) on
172 * reads.
173 */
174#define TR_66_UDMA_MASK 0xfff00000
175#define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */
176#define TR_66_UDMA_ADDRSETUP_MASK 0xe0000000 /* Address setup */
177#define TR_66_UDMA_ADDRSETUP_SHIFT 29
178#define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */
179#define TR_66_UDMA_RDY2PAUS_SHIFT 25
180#define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */
181#define TR_66_UDMA_WRDATASETUP_SHIFT 21
182#define TR_66_MDMA_MASK 0x000ffc00
183#define TR_66_MDMA_RECOVERY_MASK 0x000f8000
184#define TR_66_MDMA_RECOVERY_SHIFT 15
185#define TR_66_MDMA_ACCESS_MASK 0x00007c00
186#define TR_66_MDMA_ACCESS_SHIFT 10
187#define TR_66_PIO_MASK 0x000003ff
188#define TR_66_PIO_RECOVERY_MASK 0x000003e0
189#define TR_66_PIO_RECOVERY_SHIFT 5
190#define TR_66_PIO_ACCESS_MASK 0x0000001f
191#define TR_66_PIO_ACCESS_SHIFT 0
192
193/* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo
194 * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
195 *
196 * The access time and recovery time can be programmed. Some older
197 * Darwin code base limit OHare to 150ns cycle time. I decided to do
198 * the same here fore safety against broken old hardware ;)
199 * The HalfTick bit, when set, adds half a clock (15ns) to the access
200 * time and removes one from recovery. It's not supported on KeyLargo
201 * implementation afaik. The E bit appears to be set for PIO mode 0 and
202 * is used to reach long timings used in this mode.
203 */
204#define TR_33_MDMA_MASK 0x003ff800
205#define TR_33_MDMA_RECOVERY_MASK 0x001f0000
206#define TR_33_MDMA_RECOVERY_SHIFT 16
207#define TR_33_MDMA_ACCESS_MASK 0x0000f800
208#define TR_33_MDMA_ACCESS_SHIFT 11
209#define TR_33_MDMA_HALFTICK 0x00200000
210#define TR_33_PIO_MASK 0x000007ff
211#define TR_33_PIO_E 0x00000400
212#define TR_33_PIO_RECOVERY_MASK 0x000003e0
213#define TR_33_PIO_RECOVERY_SHIFT 5
214#define TR_33_PIO_ACCESS_MASK 0x0000001f
215#define TR_33_PIO_ACCESS_SHIFT 0
216
217/*
218 * Interrupt register definitions
219 */
220#define IDE_INTR_DMA 0x80000000
221#define IDE_INTR_DEVICE 0x40000000
222
223/*
224 * FCR Register on Kauai. Not sure what bit 0x4 is ...
225 */
226#define KAUAI_FCR_UATA_MAGIC 0x00000004
227#define KAUAI_FCR_UATA_RESET_N 0x00000002
228#define KAUAI_FCR_UATA_ENABLE 0x00000001
229
230#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
231
232/* Rounded Multiword DMA timings
233 *
234 * I gave up finding a generic formula for all controller
235 * types and instead, built tables based on timing values
236 * used by Apple in Darwin's implementation.
237 */
238struct mdma_timings_t {
239 int accessTime;
240 int recoveryTime;
241 int cycleTime;
242};
243
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500244struct mdma_timings_t mdma_timings_33[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700245{
246 { 240, 240, 480 },
247 { 180, 180, 360 },
248 { 135, 135, 270 },
249 { 120, 120, 240 },
250 { 105, 105, 210 },
251 { 90, 90, 180 },
252 { 75, 75, 150 },
253 { 75, 45, 120 },
254 { 0, 0, 0 }
255};
256
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500257struct mdma_timings_t mdma_timings_33k[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700258{
259 { 240, 240, 480 },
260 { 180, 180, 360 },
261 { 150, 150, 300 },
262 { 120, 120, 240 },
263 { 90, 120, 210 },
264 { 90, 90, 180 },
265 { 90, 60, 150 },
266 { 90, 30, 120 },
267 { 0, 0, 0 }
268};
269
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500270struct mdma_timings_t mdma_timings_66[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700271{
272 { 240, 240, 480 },
273 { 180, 180, 360 },
274 { 135, 135, 270 },
275 { 120, 120, 240 },
276 { 105, 105, 210 },
277 { 90, 90, 180 },
278 { 90, 75, 165 },
279 { 75, 45, 120 },
280 { 0, 0, 0 }
281};
282
283/* KeyLargo ATA-4 Ultra DMA timings (rounded) */
284struct {
285 int addrSetup; /* ??? */
286 int rdy2pause;
287 int wrDataSetup;
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500288} kl66_udma_timings[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700289{
290 { 0, 180, 120 }, /* Mode 0 */
291 { 0, 150, 90 }, /* 1 */
292 { 0, 120, 60 }, /* 2 */
293 { 0, 90, 45 }, /* 3 */
294 { 0, 90, 30 } /* 4 */
295};
296
297/* UniNorth 2 ATA/100 timings */
298struct kauai_timing {
299 int cycle_time;
300 u32 timing_reg;
301};
302
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500303static struct kauai_timing kauai_pio_timings[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700304{
305 { 930 , 0x08000fff },
306 { 600 , 0x08000a92 },
307 { 383 , 0x0800060f },
308 { 360 , 0x08000492 },
309 { 330 , 0x0800048f },
310 { 300 , 0x080003cf },
311 { 270 , 0x080003cc },
312 { 240 , 0x0800038b },
313 { 239 , 0x0800030c },
314 { 180 , 0x05000249 },
Bartlomiej Zolnierkiewiczc15d5d42007-10-11 23:54:01 +0200315 { 120 , 0x04000148 },
316 { 0 , 0 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700317};
318
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500319static struct kauai_timing kauai_mdma_timings[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700320{
321 { 1260 , 0x00fff000 },
322 { 480 , 0x00618000 },
323 { 360 , 0x00492000 },
324 { 270 , 0x0038e000 },
325 { 240 , 0x0030c000 },
326 { 210 , 0x002cb000 },
327 { 180 , 0x00249000 },
328 { 150 , 0x00209000 },
329 { 120 , 0x00148000 },
330 { 0 , 0 },
331};
332
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500333static struct kauai_timing kauai_udma_timings[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700334{
335 { 120 , 0x000070c0 },
336 { 90 , 0x00005d80 },
337 { 60 , 0x00004a60 },
338 { 45 , 0x00003a50 },
339 { 30 , 0x00002a30 },
340 { 20 , 0x00002921 },
341 { 0 , 0 },
342};
343
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500344static struct kauai_timing shasta_pio_timings[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700345{
346 { 930 , 0x08000fff },
347 { 600 , 0x0A000c97 },
348 { 383 , 0x07000712 },
349 { 360 , 0x040003cd },
350 { 330 , 0x040003cd },
351 { 300 , 0x040003cd },
352 { 270 , 0x040003cd },
353 { 240 , 0x040003cd },
354 { 239 , 0x040003cd },
355 { 180 , 0x0400028b },
Bartlomiej Zolnierkiewiczc15d5d42007-10-11 23:54:01 +0200356 { 120 , 0x0400010a },
357 { 0 , 0 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700358};
359
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500360static struct kauai_timing shasta_mdma_timings[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700361{
362 { 1260 , 0x00fff000 },
363 { 480 , 0x00820800 },
364 { 360 , 0x00820800 },
365 { 270 , 0x00820800 },
366 { 240 , 0x00820800 },
367 { 210 , 0x00820800 },
368 { 180 , 0x00820800 },
369 { 150 , 0x0028b000 },
370 { 120 , 0x001ca000 },
371 { 0 , 0 },
372};
373
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500374static struct kauai_timing shasta_udma133_timings[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700375{
376 { 120 , 0x00035901, },
377 { 90 , 0x000348b1, },
378 { 60 , 0x00033881, },
379 { 45 , 0x00033861, },
380 { 30 , 0x00033841, },
381 { 20 , 0x00033031, },
382 { 15 , 0x00033021, },
383 { 0 , 0 },
384};
385
386
387static inline u32
388kauai_lookup_timing(struct kauai_timing* table, int cycle_time)
389{
390 int i;
391
392 for (i=0; table[i].cycle_time; i++)
393 if (cycle_time > table[i+1].cycle_time)
394 return table[i].timing_reg;
Bartlomiej Zolnierkiewicz90a87ea2007-10-13 17:47:48 +0200395 BUG();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700396 return 0;
397}
398
399/* allow up to 256 DBDMA commands per xfer */
400#define MAX_DCMDS 256
401
402/*
403 * Wait 1s for disk to answer on IDE bus after a hard reset
404 * of the device (via GPIO/FCR).
405 *
406 * Some devices seem to "pollute" the bus even after dropping
407 * the BSY bit (typically some combo drives slave on the UDMA
408 * bus) after a hard reset. Since we hard reset all drives on
409 * KeyLargo ATA66, we have to keep that delay around. I may end
410 * up not hard resetting anymore on these and keep the delay only
411 * for older interfaces instead (we have to reset when coming
412 * from MacOS...) --BenH.
413 */
414#define IDE_WAKEUP_DELAY (1*HZ)
415
416static void pmac_ide_setup_dma(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif);
417static int pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700418static void pmac_ide_selectproc(ide_drive_t *drive);
419static void pmac_ide_kauai_selectproc(ide_drive_t *drive);
420
421#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
422
423/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700424 * N.B. this can't be an initfunc, because the media-bay task can
425 * call ide_[un]register at any time.
426 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500427void
Linus Torvalds1da177e2005-04-16 15:20:36 -0700428pmac_ide_init_hwif_ports(hw_regs_t *hw,
429 unsigned long data_port, unsigned long ctrl_port,
430 int *irq)
431{
432 int i, ix;
433
434 if (data_port == 0)
435 return;
436
437 for (ix = 0; ix < MAX_HWIFS; ++ix)
438 if (data_port == pmac_ide[ix].regbase)
439 break;
440
441 if (ix >= MAX_HWIFS) {
442 /* Probably a PCI interface... */
443 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; ++i)
444 hw->io_ports[i] = data_port + i - IDE_DATA_OFFSET;
445 hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
446 return;
447 }
448
449 for (i = 0; i < 8; ++i)
450 hw->io_ports[i] = data_port + i * 0x10;
451 hw->io_ports[8] = data_port + 0x160;
452
453 if (irq != NULL)
454 *irq = pmac_ide[ix].irq;
Benjamin Herrenschmidt22192cc2006-05-20 14:59:53 -0700455
456 hw->dev = &pmac_ide[ix].mdev->ofdev.dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700457}
458
459#define PMAC_IDE_REG(x) ((void __iomem *)(IDE_DATA_REG+(x)))
460
461/*
462 * Apply the timings of the proper unit (master/slave) to the shared
463 * timing register when selecting that unit. This version is for
464 * ASICs with a single timing register
465 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500466static void
Linus Torvalds1da177e2005-04-16 15:20:36 -0700467pmac_ide_selectproc(ide_drive_t *drive)
468{
469 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
470
471 if (pmif == NULL)
472 return;
473
474 if (drive->select.b.unit & 0x01)
475 writel(pmif->timings[1], PMAC_IDE_REG(IDE_TIMING_CONFIG));
476 else
477 writel(pmif->timings[0], PMAC_IDE_REG(IDE_TIMING_CONFIG));
478 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
479}
480
481/*
482 * Apply the timings of the proper unit (master/slave) to the shared
483 * timing register when selecting that unit. This version is for
484 * ASICs with a dual timing register (Kauai)
485 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500486static void
Linus Torvalds1da177e2005-04-16 15:20:36 -0700487pmac_ide_kauai_selectproc(ide_drive_t *drive)
488{
489 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
490
491 if (pmif == NULL)
492 return;
493
494 if (drive->select.b.unit & 0x01) {
495 writel(pmif->timings[1], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
496 writel(pmif->timings[3], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
497 } else {
498 writel(pmif->timings[0], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
499 writel(pmif->timings[2], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
500 }
501 (void)readl(PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
502}
503
504/*
505 * Force an update of controller timing values for a given drive
506 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500507static void
Linus Torvalds1da177e2005-04-16 15:20:36 -0700508pmac_ide_do_update_timings(ide_drive_t *drive)
509{
510 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
511
512 if (pmif == NULL)
513 return;
514
515 if (pmif->kind == controller_sh_ata6 ||
516 pmif->kind == controller_un_ata6 ||
517 pmif->kind == controller_k2_ata6)
518 pmac_ide_kauai_selectproc(drive);
519 else
520 pmac_ide_selectproc(drive);
521}
522
523static void
524pmac_outbsync(ide_drive_t *drive, u8 value, unsigned long port)
525{
526 u32 tmp;
527
528 writeb(value, (void __iomem *) port);
529 tmp = readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
530}
531
532/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700533 * Old tuning functions (called on hdparm -p), sets up drive PIO timings
534 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500535static void
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +0200536pmac_ide_set_pio_mode(ide_drive_t *drive, const u8 pio)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700537{
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200538 u32 *timings, t;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700539 unsigned accessTicks, recTicks;
540 unsigned accessTime, recTime;
541 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
Bartlomiej Zolnierkiewicz7dd00082007-07-20 01:11:56 +0200542 unsigned int cycle_time;
543
Linus Torvalds1da177e2005-04-16 15:20:36 -0700544 if (pmif == NULL)
545 return;
546
547 /* which drive is it ? */
548 timings = &pmif->timings[drive->select.b.unit & 0x01];
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200549 t = *timings;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700550
Bartlomiej Zolnierkiewicz7dd00082007-07-20 01:11:56 +0200551 cycle_time = ide_pio_cycle_time(drive, pio);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700552
553 switch (pmif->kind) {
554 case controller_sh_ata6: {
555 /* 133Mhz cell */
Bartlomiej Zolnierkiewicz7dd00082007-07-20 01:11:56 +0200556 u32 tr = kauai_lookup_timing(shasta_pio_timings, cycle_time);
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200557 t = (t & ~TR_133_PIOREG_PIO_MASK) | tr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700558 break;
559 }
560 case controller_un_ata6:
561 case controller_k2_ata6: {
562 /* 100Mhz cell */
Bartlomiej Zolnierkiewicz7dd00082007-07-20 01:11:56 +0200563 u32 tr = kauai_lookup_timing(kauai_pio_timings, cycle_time);
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200564 t = (t & ~TR_100_PIOREG_PIO_MASK) | tr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700565 break;
566 }
567 case controller_kl_ata4:
568 /* 66Mhz cell */
Bartlomiej Zolnierkiewicz7dd00082007-07-20 01:11:56 +0200569 recTime = cycle_time - ide_pio_timings[pio].active_time
Linus Torvalds1da177e2005-04-16 15:20:36 -0700570 - ide_pio_timings[pio].setup_time;
571 recTime = max(recTime, 150U);
572 accessTime = ide_pio_timings[pio].active_time;
573 accessTime = max(accessTime, 150U);
574 accessTicks = SYSCLK_TICKS_66(accessTime);
575 accessTicks = min(accessTicks, 0x1fU);
576 recTicks = SYSCLK_TICKS_66(recTime);
577 recTicks = min(recTicks, 0x1fU);
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200578 t = (t & ~TR_66_PIO_MASK) |
579 (accessTicks << TR_66_PIO_ACCESS_SHIFT) |
580 (recTicks << TR_66_PIO_RECOVERY_SHIFT);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700581 break;
582 default: {
583 /* 33Mhz cell */
584 int ebit = 0;
Bartlomiej Zolnierkiewicz7dd00082007-07-20 01:11:56 +0200585 recTime = cycle_time - ide_pio_timings[pio].active_time
Linus Torvalds1da177e2005-04-16 15:20:36 -0700586 - ide_pio_timings[pio].setup_time;
587 recTime = max(recTime, 150U);
588 accessTime = ide_pio_timings[pio].active_time;
589 accessTime = max(accessTime, 150U);
590 accessTicks = SYSCLK_TICKS(accessTime);
591 accessTicks = min(accessTicks, 0x1fU);
592 accessTicks = max(accessTicks, 4U);
593 recTicks = SYSCLK_TICKS(recTime);
594 recTicks = min(recTicks, 0x1fU);
595 recTicks = max(recTicks, 5U) - 4;
596 if (recTicks > 9) {
597 recTicks--; /* guess, but it's only for PIO0, so... */
598 ebit = 1;
599 }
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200600 t = (t & ~TR_33_PIO_MASK) |
Linus Torvalds1da177e2005-04-16 15:20:36 -0700601 (accessTicks << TR_33_PIO_ACCESS_SHIFT) |
602 (recTicks << TR_33_PIO_RECOVERY_SHIFT);
603 if (ebit)
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200604 t |= TR_33_PIO_E;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700605 break;
606 }
607 }
608
609#ifdef IDE_PMAC_DEBUG
610 printk(KERN_ERR "%s: Set PIO timing for mode %d, reg: 0x%08x\n",
611 drive->name, pio, *timings);
612#endif
613
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200614 *timings = t;
Bartlomiej Zolnierkiewiczc15d5d42007-10-11 23:54:01 +0200615 pmac_ide_do_update_timings(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700616}
617
618#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
619
620/*
621 * Calculate KeyLargo ATA/66 UDMA timings
622 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500623static int
Linus Torvalds1da177e2005-04-16 15:20:36 -0700624set_timings_udma_ata4(u32 *timings, u8 speed)
625{
626 unsigned rdyToPauseTicks, wrDataSetupTicks, addrTicks;
627
628 if (speed > XFER_UDMA_4)
629 return 1;
630
631 rdyToPauseTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].rdy2pause);
632 wrDataSetupTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].wrDataSetup);
633 addrTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].addrSetup);
634
635 *timings = ((*timings) & ~(TR_66_UDMA_MASK | TR_66_MDMA_MASK)) |
636 (wrDataSetupTicks << TR_66_UDMA_WRDATASETUP_SHIFT) |
637 (rdyToPauseTicks << TR_66_UDMA_RDY2PAUS_SHIFT) |
638 (addrTicks <<TR_66_UDMA_ADDRSETUP_SHIFT) |
639 TR_66_UDMA_EN;
640#ifdef IDE_PMAC_DEBUG
641 printk(KERN_ERR "ide_pmac: Set UDMA timing for mode %d, reg: 0x%08x\n",
642 speed & 0xf, *timings);
643#endif
644
645 return 0;
646}
647
648/*
649 * Calculate Kauai ATA/100 UDMA timings
650 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500651static int
Linus Torvalds1da177e2005-04-16 15:20:36 -0700652set_timings_udma_ata6(u32 *pio_timings, u32 *ultra_timings, u8 speed)
653{
654 struct ide_timing *t = ide_timing_find_mode(speed);
655 u32 tr;
656
657 if (speed > XFER_UDMA_5 || t == NULL)
658 return 1;
659 tr = kauai_lookup_timing(kauai_udma_timings, (int)t->udma);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700660 *ultra_timings = ((*ultra_timings) & ~TR_100_UDMAREG_UDMA_MASK) | tr;
661 *ultra_timings = (*ultra_timings) | TR_100_UDMAREG_UDMA_EN;
662
663 return 0;
664}
665
666/*
667 * Calculate Shasta ATA/133 UDMA timings
668 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500669static int
Linus Torvalds1da177e2005-04-16 15:20:36 -0700670set_timings_udma_shasta(u32 *pio_timings, u32 *ultra_timings, u8 speed)
671{
672 struct ide_timing *t = ide_timing_find_mode(speed);
673 u32 tr;
674
675 if (speed > XFER_UDMA_6 || t == NULL)
676 return 1;
677 tr = kauai_lookup_timing(shasta_udma133_timings, (int)t->udma);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700678 *ultra_timings = ((*ultra_timings) & ~TR_133_UDMAREG_UDMA_MASK) | tr;
679 *ultra_timings = (*ultra_timings) | TR_133_UDMAREG_UDMA_EN;
680
681 return 0;
682}
683
684/*
685 * Calculate MDMA timings for all cells
686 */
Bartlomiej Zolnierkiewicz90f72ec2007-10-13 17:47:48 +0200687static void
Linus Torvalds1da177e2005-04-16 15:20:36 -0700688set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2,
Bartlomiej Zolnierkiewicz90f72ec2007-10-13 17:47:48 +0200689 u8 speed)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700690{
691 int cycleTime, accessTime = 0, recTime = 0;
692 unsigned accessTicks, recTicks;
Bartlomiej Zolnierkiewicz90f72ec2007-10-13 17:47:48 +0200693 struct hd_driveid *id = drive->id;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700694 struct mdma_timings_t* tm = NULL;
695 int i;
696
697 /* Get default cycle time for mode */
698 switch(speed & 0xf) {
699 case 0: cycleTime = 480; break;
700 case 1: cycleTime = 150; break;
701 case 2: cycleTime = 120; break;
702 default:
Bartlomiej Zolnierkiewicz90f72ec2007-10-13 17:47:48 +0200703 BUG();
704 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700705 }
Bartlomiej Zolnierkiewicz90f72ec2007-10-13 17:47:48 +0200706
707 /* Check if drive provides explicit DMA cycle time */
708 if ((id->field_valid & 2) && id->eide_dma_time)
709 cycleTime = max_t(int, id->eide_dma_time, cycleTime);
710
Linus Torvalds1da177e2005-04-16 15:20:36 -0700711 /* OHare limits according to some old Apple sources */
712 if ((intf_type == controller_ohare) && (cycleTime < 150))
713 cycleTime = 150;
714 /* Get the proper timing array for this controller */
715 switch(intf_type) {
716 case controller_sh_ata6:
717 case controller_un_ata6:
718 case controller_k2_ata6:
719 break;
720 case controller_kl_ata4:
721 tm = mdma_timings_66;
722 break;
723 case controller_kl_ata3:
724 tm = mdma_timings_33k;
725 break;
726 default:
727 tm = mdma_timings_33;
728 break;
729 }
730 if (tm != NULL) {
731 /* Lookup matching access & recovery times */
732 i = -1;
733 for (;;) {
734 if (tm[i+1].cycleTime < cycleTime)
735 break;
736 i++;
737 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700738 cycleTime = tm[i].cycleTime;
739 accessTime = tm[i].accessTime;
740 recTime = tm[i].recoveryTime;
741
742#ifdef IDE_PMAC_DEBUG
743 printk(KERN_ERR "%s: MDMA, cycleTime: %d, accessTime: %d, recTime: %d\n",
744 drive->name, cycleTime, accessTime, recTime);
745#endif
746 }
747 switch(intf_type) {
748 case controller_sh_ata6: {
749 /* 133Mhz cell */
750 u32 tr = kauai_lookup_timing(shasta_mdma_timings, cycleTime);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700751 *timings = ((*timings) & ~TR_133_PIOREG_MDMA_MASK) | tr;
752 *timings2 = (*timings2) & ~TR_133_UDMAREG_UDMA_EN;
753 }
754 case controller_un_ata6:
755 case controller_k2_ata6: {
756 /* 100Mhz cell */
757 u32 tr = kauai_lookup_timing(kauai_mdma_timings, cycleTime);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700758 *timings = ((*timings) & ~TR_100_PIOREG_MDMA_MASK) | tr;
759 *timings2 = (*timings2) & ~TR_100_UDMAREG_UDMA_EN;
760 }
761 break;
762 case controller_kl_ata4:
763 /* 66Mhz cell */
764 accessTicks = SYSCLK_TICKS_66(accessTime);
765 accessTicks = min(accessTicks, 0x1fU);
766 accessTicks = max(accessTicks, 0x1U);
767 recTicks = SYSCLK_TICKS_66(recTime);
768 recTicks = min(recTicks, 0x1fU);
769 recTicks = max(recTicks, 0x3U);
770 /* Clear out mdma bits and disable udma */
771 *timings = ((*timings) & ~(TR_66_MDMA_MASK | TR_66_UDMA_MASK)) |
772 (accessTicks << TR_66_MDMA_ACCESS_SHIFT) |
773 (recTicks << TR_66_MDMA_RECOVERY_SHIFT);
774 break;
775 case controller_kl_ata3:
776 /* 33Mhz cell on KeyLargo */
777 accessTicks = SYSCLK_TICKS(accessTime);
778 accessTicks = max(accessTicks, 1U);
779 accessTicks = min(accessTicks, 0x1fU);
780 accessTime = accessTicks * IDE_SYSCLK_NS;
781 recTicks = SYSCLK_TICKS(recTime);
782 recTicks = max(recTicks, 1U);
783 recTicks = min(recTicks, 0x1fU);
784 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
785 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
786 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
787 break;
788 default: {
789 /* 33Mhz cell on others */
790 int halfTick = 0;
791 int origAccessTime = accessTime;
792 int origRecTime = recTime;
793
794 accessTicks = SYSCLK_TICKS(accessTime);
795 accessTicks = max(accessTicks, 1U);
796 accessTicks = min(accessTicks, 0x1fU);
797 accessTime = accessTicks * IDE_SYSCLK_NS;
798 recTicks = SYSCLK_TICKS(recTime);
799 recTicks = max(recTicks, 2U) - 1;
800 recTicks = min(recTicks, 0x1fU);
801 recTime = (recTicks + 1) * IDE_SYSCLK_NS;
802 if ((accessTicks > 1) &&
803 ((accessTime - IDE_SYSCLK_NS/2) >= origAccessTime) &&
804 ((recTime - IDE_SYSCLK_NS/2) >= origRecTime)) {
805 halfTick = 1;
806 accessTicks--;
807 }
808 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
809 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
810 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
811 if (halfTick)
812 *timings |= TR_33_MDMA_HALFTICK;
813 }
814 }
815#ifdef IDE_PMAC_DEBUG
816 printk(KERN_ERR "%s: Set MDMA timing for mode %d, reg: 0x%08x\n",
817 drive->name, speed & 0xf, *timings);
818#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700819}
820#endif /* #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC */
821
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200822static void pmac_ide_set_dma_mode(ide_drive_t *drive, const u8 speed)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700823{
824 int unit = (drive->select.b.unit & 0x01);
825 int ret = 0;
826 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
Bartlomiej Zolnierkiewicz085798b2007-10-13 17:47:48 +0200827 u32 *timings, *timings2, tl[2];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700828
Linus Torvalds1da177e2005-04-16 15:20:36 -0700829 timings = &pmif->timings[unit];
830 timings2 = &pmif->timings[unit+2];
Bartlomiej Zolnierkiewicz085798b2007-10-13 17:47:48 +0200831
832 /* Copy timings to local image */
833 tl[0] = *timings;
834 tl[1] = *timings2;
835
Linus Torvalds1da177e2005-04-16 15:20:36 -0700836 switch(speed) {
837#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
838 case XFER_UDMA_6:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700839 case XFER_UDMA_5:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700840 case XFER_UDMA_4:
841 case XFER_UDMA_3:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700842 case XFER_UDMA_2:
843 case XFER_UDMA_1:
844 case XFER_UDMA_0:
845 if (pmif->kind == controller_kl_ata4)
Bartlomiej Zolnierkiewicz085798b2007-10-13 17:47:48 +0200846 ret = set_timings_udma_ata4(&tl[0], speed);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700847 else if (pmif->kind == controller_un_ata6
848 || pmif->kind == controller_k2_ata6)
Bartlomiej Zolnierkiewicz085798b2007-10-13 17:47:48 +0200849 ret = set_timings_udma_ata6(&tl[0], &tl[1], speed);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700850 else if (pmif->kind == controller_sh_ata6)
Bartlomiej Zolnierkiewicz085798b2007-10-13 17:47:48 +0200851 ret = set_timings_udma_shasta(&tl[0], &tl[1], speed);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700852 else
Bartlomiej Zolnierkiewicz085798b2007-10-13 17:47:48 +0200853 ret = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700854 break;
855 case XFER_MW_DMA_2:
856 case XFER_MW_DMA_1:
857 case XFER_MW_DMA_0:
Bartlomiej Zolnierkiewicz90f72ec2007-10-13 17:47:48 +0200858 set_timings_mdma(drive, pmif->kind, &tl[0], &tl[1], speed);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700859 break;
860 case XFER_SW_DMA_2:
861 case XFER_SW_DMA_1:
862 case XFER_SW_DMA_0:
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200863 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700864#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700865 default:
866 ret = 1;
867 }
868 if (ret)
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200869 return;
Bartlomiej Zolnierkiewicz085798b2007-10-13 17:47:48 +0200870
871 /* Apply timings to controller */
872 *timings = tl[0];
873 *timings2 = tl[1];
874
Linus Torvalds1da177e2005-04-16 15:20:36 -0700875 pmac_ide_do_update_timings(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700876}
877
878/*
879 * Blast some well known "safe" values to the timing registers at init or
880 * wakeup from sleep time, before we do real calculation
881 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500882static void
Linus Torvalds1da177e2005-04-16 15:20:36 -0700883sanitize_timings(pmac_ide_hwif_t *pmif)
884{
885 unsigned int value, value2 = 0;
886
887 switch(pmif->kind) {
888 case controller_sh_ata6:
889 value = 0x0a820c97;
890 value2 = 0x00033031;
891 break;
892 case controller_un_ata6:
893 case controller_k2_ata6:
894 value = 0x08618a92;
895 value2 = 0x00002921;
896 break;
897 case controller_kl_ata4:
898 value = 0x0008438c;
899 break;
900 case controller_kl_ata3:
901 value = 0x00084526;
902 break;
903 case controller_heathrow:
904 case controller_ohare:
905 default:
906 value = 0x00074526;
907 break;
908 }
909 pmif->timings[0] = pmif->timings[1] = value;
910 pmif->timings[2] = pmif->timings[3] = value2;
911}
912
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500913unsigned long
Linus Torvalds1da177e2005-04-16 15:20:36 -0700914pmac_ide_get_base(int index)
915{
916 return pmac_ide[index].regbase;
917}
918
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500919int
Linus Torvalds1da177e2005-04-16 15:20:36 -0700920pmac_ide_check_base(unsigned long base)
921{
922 int ix;
923
924 for (ix = 0; ix < MAX_HWIFS; ++ix)
925 if (base == pmac_ide[ix].regbase)
926 return ix;
927 return -1;
928}
929
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500930int
Linus Torvalds1da177e2005-04-16 15:20:36 -0700931pmac_ide_get_irq(unsigned long base)
932{
933 int ix;
934
935 for (ix = 0; ix < MAX_HWIFS; ++ix)
936 if (base == pmac_ide[ix].regbase)
937 return pmac_ide[ix].irq;
938 return 0;
939}
940
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500941static int ide_majors[] = { 3, 22, 33, 34, 56, 57 };
Linus Torvalds1da177e2005-04-16 15:20:36 -0700942
943dev_t __init
944pmac_find_ide_boot(char *bootdevice, int n)
945{
946 int i;
947
948 /*
949 * Look through the list of IDE interfaces for this one.
950 */
951 for (i = 0; i < pmac_ide_count; ++i) {
952 char *name;
953 if (!pmac_ide[i].node || !pmac_ide[i].node->full_name)
954 continue;
955 name = pmac_ide[i].node->full_name;
956 if (memcmp(name, bootdevice, n) == 0 && name[n] == 0) {
957 /* XXX should cope with the 2nd drive as well... */
958 return MKDEV(ide_majors[i], 0);
959 }
960 }
961
962 return 0;
963}
964
965/* Suspend call back, should be called after the child devices
966 * have actually been suspended
967 */
968static int
969pmac_ide_do_suspend(ide_hwif_t *hwif)
970{
971 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
972
973 /* We clear the timings */
974 pmif->timings[0] = 0;
975 pmif->timings[1] = 0;
976
Benjamin Herrenschmidt616299a2005-05-01 08:58:41 -0700977 disable_irq(pmif->irq);
978
Linus Torvalds1da177e2005-04-16 15:20:36 -0700979 /* The media bay will handle itself just fine */
980 if (pmif->mediabay)
981 return 0;
982
983 /* Kauai has bus control FCRs directly here */
984 if (pmif->kauai_fcr) {
985 u32 fcr = readl(pmif->kauai_fcr);
986 fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE);
987 writel(fcr, pmif->kauai_fcr);
988 }
989
990 /* Disable the bus on older machines and the cell on kauai */
991 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id,
992 0);
993
994 return 0;
995}
996
997/* Resume call back, should be called before the child devices
998 * are resumed
999 */
1000static int
1001pmac_ide_do_resume(ide_hwif_t *hwif)
1002{
1003 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1004
1005 /* Hard reset & re-enable controller (do we really need to reset ? -BenH) */
1006 if (!pmif->mediabay) {
1007 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 1);
1008 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id, 1);
1009 msleep(10);
1010 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001011
1012 /* Kauai has it different */
1013 if (pmif->kauai_fcr) {
1014 u32 fcr = readl(pmif->kauai_fcr);
1015 fcr |= KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE;
1016 writel(fcr, pmif->kauai_fcr);
1017 }
Benjamin Herrenschmidt616299a2005-05-01 08:58:41 -07001018
1019 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001020 }
1021
1022 /* Sanitize drive timings */
1023 sanitize_timings(pmif);
1024
Benjamin Herrenschmidt616299a2005-05-01 08:58:41 -07001025 enable_irq(pmif->irq);
1026
Linus Torvalds1da177e2005-04-16 15:20:36 -07001027 return 0;
1028}
1029
1030/*
1031 * Setup, register & probe an IDE channel driven by this driver, this is
1032 * called by one of the 2 probe functions (macio or PCI). Note that a channel
1033 * that ends up beeing free of any device is not kept around by this driver
1034 * (it is kept in 2.4). This introduce an interface numbering change on some
1035 * rare machines unfortunately, but it's better this way.
1036 */
1037static int
1038pmac_ide_setup_device(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif)
1039{
1040 struct device_node *np = pmif->node;
Jeremy Kerr018a3d12006-07-12 15:40:29 +10001041 const int *bidp;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001042
1043 pmif->cable_80 = 0;
1044 pmif->broken_dma = pmif->broken_dma_warn = 0;
Stephen Rothwell55b61fe2007-05-03 17:26:52 +10001045 if (of_device_is_compatible(np, "shasta-ata"))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001046 pmif->kind = controller_sh_ata6;
Stephen Rothwell55b61fe2007-05-03 17:26:52 +10001047 else if (of_device_is_compatible(np, "kauai-ata"))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001048 pmif->kind = controller_un_ata6;
Stephen Rothwell55b61fe2007-05-03 17:26:52 +10001049 else if (of_device_is_compatible(np, "K2-UATA"))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001050 pmif->kind = controller_k2_ata6;
Stephen Rothwell55b61fe2007-05-03 17:26:52 +10001051 else if (of_device_is_compatible(np, "keylargo-ata")) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001052 if (strcmp(np->name, "ata-4") == 0)
1053 pmif->kind = controller_kl_ata4;
1054 else
1055 pmif->kind = controller_kl_ata3;
Stephen Rothwell55b61fe2007-05-03 17:26:52 +10001056 } else if (of_device_is_compatible(np, "heathrow-ata"))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001057 pmif->kind = controller_heathrow;
1058 else {
1059 pmif->kind = controller_ohare;
1060 pmif->broken_dma = 1;
1061 }
1062
Stephen Rothwell40cd3a42007-05-01 13:54:02 +10001063 bidp = of_get_property(np, "AAPL,bus-id", NULL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001064 pmif->aapl_bus_id = bidp ? *bidp : 0;
1065
1066 /* Get cable type from device-tree */
1067 if (pmif->kind == controller_kl_ata4 || pmif->kind == controller_un_ata6
1068 || pmif->kind == controller_k2_ata6
1069 || pmif->kind == controller_sh_ata6) {
Stephen Rothwell40cd3a42007-05-01 13:54:02 +10001070 const char* cable = of_get_property(np, "cable-type", NULL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001071 if (cable && !strncmp(cable, "80-", 3))
1072 pmif->cable_80 = 1;
1073 }
1074 /* G5's seem to have incorrect cable type in device-tree. Let's assume
1075 * they have a 80 conductor cable, this seem to be always the case unless
1076 * the user mucked around
1077 */
Stephen Rothwell55b61fe2007-05-03 17:26:52 +10001078 if (of_device_is_compatible(np, "K2-UATA") ||
1079 of_device_is_compatible(np, "shasta-ata"))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001080 pmif->cable_80 = 1;
1081
1082 /* On Kauai-type controllers, we make sure the FCR is correct */
1083 if (pmif->kauai_fcr)
1084 writel(KAUAI_FCR_UATA_MAGIC |
1085 KAUAI_FCR_UATA_RESET_N |
1086 KAUAI_FCR_UATA_ENABLE, pmif->kauai_fcr);
1087
1088 pmif->mediabay = 0;
1089
1090 /* Make sure we have sane timings */
1091 sanitize_timings(pmif);
1092
1093#ifndef CONFIG_PPC64
1094 /* XXX FIXME: Media bay stuff need re-organizing */
1095 if (np->parent && np->parent->name
1096 && strcasecmp(np->parent->name, "media-bay") == 0) {
Benjamin Herrenschmidt8c870932005-06-27 14:36:34 -07001097#ifdef CONFIG_PMAC_MEDIABAY
Linus Torvalds1da177e2005-04-16 15:20:36 -07001098 media_bay_set_ide_infos(np->parent, pmif->regbase, pmif->irq, hwif->index);
Benjamin Herrenschmidt8c870932005-06-27 14:36:34 -07001099#endif /* CONFIG_PMAC_MEDIABAY */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001100 pmif->mediabay = 1;
1101 if (!bidp)
1102 pmif->aapl_bus_id = 1;
1103 } else if (pmif->kind == controller_ohare) {
1104 /* The code below is having trouble on some ohare machines
1105 * (timing related ?). Until I can put my hand on one of these
1106 * units, I keep the old way
1107 */
1108 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, 0, 1);
1109 } else
1110#endif
1111 {
1112 /* This is necessary to enable IDE when net-booting */
1113 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 1);
1114 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, pmif->aapl_bus_id, 1);
1115 msleep(10);
1116 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 0);
1117 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
1118 }
1119
1120 /* Setup MMIO ops */
1121 default_hwif_mmiops(hwif);
1122 hwif->OUTBSYNC = pmac_outbsync;
1123
1124 /* Tell common code _not_ to mess with resources */
Bartlomiej Zolnierkiewicz2ad1e552007-02-17 02:40:25 +01001125 hwif->mmio = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001126 hwif->hwif_data = pmif;
1127 pmac_ide_init_hwif_ports(&hwif->hw, pmif->regbase, 0, &hwif->irq);
1128 memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->io_ports));
1129 hwif->chipset = ide_pmac;
1130 hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET] || pmif->mediabay;
1131 hwif->hold = pmif->mediabay;
Bartlomiej Zolnierkiewicz49521f92007-07-09 23:17:58 +02001132 hwif->cbl = pmif->cable_80 ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001133 hwif->drives[0].unmask = 1;
1134 hwif->drives[1].unmask = 1;
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +02001135 hwif->drives[0].autotune = IDE_TUNE_AUTO;
1136 hwif->drives[1].autotune = IDE_TUNE_AUTO;
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +02001137 hwif->host_flags = IDE_HFLAG_SET_PIO_MODE_KEEP_DMA |
1138 IDE_HFLAG_POST_SET_MODE;
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +02001139 hwif->pio_mask = ATA_PIO4;
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +02001140 hwif->set_pio_mode = pmac_ide_set_pio_mode;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001141 if (pmif->kind == controller_un_ata6
1142 || pmif->kind == controller_k2_ata6
1143 || pmif->kind == controller_sh_ata6)
1144 hwif->selectproc = pmac_ide_kauai_selectproc;
1145 else
1146 hwif->selectproc = pmac_ide_selectproc;
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +02001147 hwif->set_dma_mode = pmac_ide_set_dma_mode;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001148
Linus Torvalds1da177e2005-04-16 15:20:36 -07001149 printk(KERN_INFO "ide%d: Found Apple %s controller, bus ID %d%s, irq %d\n",
1150 hwif->index, model_name[pmif->kind], pmif->aapl_bus_id,
1151 pmif->mediabay ? " (mediabay)" : "", hwif->irq);
1152
Benjamin Herrenschmidt8c870932005-06-27 14:36:34 -07001153#ifdef CONFIG_PMAC_MEDIABAY
Linus Torvalds1da177e2005-04-16 15:20:36 -07001154 if (pmif->mediabay && check_media_bay_by_base(pmif->regbase, MB_CD) == 0)
1155 hwif->noprobe = 0;
Benjamin Herrenschmidt8c870932005-06-27 14:36:34 -07001156#endif /* CONFIG_PMAC_MEDIABAY */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001157
1158 hwif->sg_max_nents = MAX_DCMDS;
1159
1160#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1161 /* has a DBDMA controller channel */
1162 if (pmif->dma_regs)
1163 pmac_ide_setup_dma(pmif, hwif);
1164#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1165
1166 /* We probe the hwif now */
1167 probe_hwif_init(hwif);
1168
Bartlomiej Zolnierkiewicz5cbf79c2007-05-10 00:01:11 +02001169 ide_proc_register_port(hwif);
1170
Linus Torvalds1da177e2005-04-16 15:20:36 -07001171 return 0;
1172}
1173
1174/*
1175 * Attach to a macio probed interface
1176 */
1177static int __devinit
Jeff Mahoney5e655772005-07-06 15:44:41 -04001178pmac_ide_macio_attach(struct macio_dev *mdev, const struct of_device_id *match)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001179{
1180 void __iomem *base;
1181 unsigned long regbase;
1182 int irq;
1183 ide_hwif_t *hwif;
1184 pmac_ide_hwif_t *pmif;
1185 int i, rc;
1186
1187 i = 0;
1188 while (i < MAX_HWIFS && (ide_hwifs[i].io_ports[IDE_DATA_OFFSET] != 0
1189 || pmac_ide[i].node != NULL))
1190 ++i;
1191 if (i >= MAX_HWIFS) {
1192 printk(KERN_ERR "ide-pmac: MacIO interface attach with no slot\n");
1193 printk(KERN_ERR " %s\n", mdev->ofdev.node->full_name);
1194 return -ENODEV;
1195 }
1196
1197 pmif = &pmac_ide[i];
1198 hwif = &ide_hwifs[i];
1199
Benjamin Herrenschmidtcc5d0182005-12-13 18:01:21 +11001200 if (macio_resource_count(mdev) == 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001201 printk(KERN_WARNING "ide%d: no address for %s\n",
1202 i, mdev->ofdev.node->full_name);
1203 return -ENXIO;
1204 }
1205
1206 /* Request memory resource for IO ports */
1207 if (macio_request_resource(mdev, 0, "ide-pmac (ports)")) {
1208 printk(KERN_ERR "ide%d: can't request mmio resource !\n", i);
1209 return -EBUSY;
1210 }
1211
1212 /* XXX This is bogus. Should be fixed in the registry by checking
1213 * the kind of host interrupt controller, a bit like gatwick
1214 * fixes in irq.c. That works well enough for the single case
1215 * where that happens though...
1216 */
1217 if (macio_irq_count(mdev) == 0) {
1218 printk(KERN_WARNING "ide%d: no intrs for device %s, using 13\n",
1219 i, mdev->ofdev.node->full_name);
Benjamin Herrenschmidt69917c22006-09-22 12:56:30 +10001220 irq = irq_create_mapping(NULL, 13);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001221 } else
1222 irq = macio_irq(mdev, 0);
1223
1224 base = ioremap(macio_resource_start(mdev, 0), 0x400);
1225 regbase = (unsigned long) base;
1226
1227 hwif->pci_dev = mdev->bus->pdev;
1228 hwif->gendev.parent = &mdev->ofdev.dev;
1229
1230 pmif->mdev = mdev;
1231 pmif->node = mdev->ofdev.node;
1232 pmif->regbase = regbase;
1233 pmif->irq = irq;
1234 pmif->kauai_fcr = NULL;
1235#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1236 if (macio_resource_count(mdev) >= 2) {
1237 if (macio_request_resource(mdev, 1, "ide-pmac (dma)"))
1238 printk(KERN_WARNING "ide%d: can't request DMA resource !\n", i);
1239 else
1240 pmif->dma_regs = ioremap(macio_resource_start(mdev, 1), 0x1000);
1241 } else
1242 pmif->dma_regs = NULL;
1243#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1244 dev_set_drvdata(&mdev->ofdev.dev, hwif);
1245
1246 rc = pmac_ide_setup_device(pmif, hwif);
1247 if (rc != 0) {
1248 /* The inteface is released to the common IDE layer */
1249 dev_set_drvdata(&mdev->ofdev.dev, NULL);
1250 iounmap(base);
1251 if (pmif->dma_regs)
1252 iounmap(pmif->dma_regs);
1253 memset(pmif, 0, sizeof(*pmif));
1254 macio_release_resource(mdev, 0);
1255 if (pmif->dma_regs)
1256 macio_release_resource(mdev, 1);
1257 }
1258
1259 return rc;
1260}
1261
1262static int
David Brownell8b4b8a22006-08-14 23:11:03 -07001263pmac_ide_macio_suspend(struct macio_dev *mdev, pm_message_t mesg)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001264{
1265 ide_hwif_t *hwif = (ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1266 int rc = 0;
1267
David Brownell8b4b8a22006-08-14 23:11:03 -07001268 if (mesg.event != mdev->ofdev.dev.power.power_state.event
1269 && mesg.event == PM_EVENT_SUSPEND) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001270 rc = pmac_ide_do_suspend(hwif);
1271 if (rc == 0)
David Brownell8b4b8a22006-08-14 23:11:03 -07001272 mdev->ofdev.dev.power.power_state = mesg;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001273 }
1274
1275 return rc;
1276}
1277
1278static int
1279pmac_ide_macio_resume(struct macio_dev *mdev)
1280{
1281 ide_hwif_t *hwif = (ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1282 int rc = 0;
1283
Pavel Machekca078ba2005-09-03 15:56:57 -07001284 if (mdev->ofdev.dev.power.power_state.event != PM_EVENT_ON) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001285 rc = pmac_ide_do_resume(hwif);
1286 if (rc == 0)
Pavel Machek829ca9a2005-09-03 15:56:56 -07001287 mdev->ofdev.dev.power.power_state = PMSG_ON;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001288 }
1289
1290 return rc;
1291}
1292
1293/*
1294 * Attach to a PCI probed interface
1295 */
1296static int __devinit
1297pmac_ide_pci_attach(struct pci_dev *pdev, const struct pci_device_id *id)
1298{
1299 ide_hwif_t *hwif;
1300 struct device_node *np;
1301 pmac_ide_hwif_t *pmif;
1302 void __iomem *base;
1303 unsigned long rbase, rlen;
1304 int i, rc;
1305
1306 np = pci_device_to_OF_node(pdev);
1307 if (np == NULL) {
1308 printk(KERN_ERR "ide-pmac: cannot find MacIO node for Kauai ATA interface\n");
1309 return -ENODEV;
1310 }
1311 i = 0;
1312 while (i < MAX_HWIFS && (ide_hwifs[i].io_ports[IDE_DATA_OFFSET] != 0
1313 || pmac_ide[i].node != NULL))
1314 ++i;
1315 if (i >= MAX_HWIFS) {
1316 printk(KERN_ERR "ide-pmac: PCI interface attach with no slot\n");
1317 printk(KERN_ERR " %s\n", np->full_name);
1318 return -ENODEV;
1319 }
1320
1321 pmif = &pmac_ide[i];
1322 hwif = &ide_hwifs[i];
1323
1324 if (pci_enable_device(pdev)) {
1325 printk(KERN_WARNING "ide%i: Can't enable PCI device for %s\n",
1326 i, np->full_name);
1327 return -ENXIO;
1328 }
1329 pci_set_master(pdev);
1330
1331 if (pci_request_regions(pdev, "Kauai ATA")) {
1332 printk(KERN_ERR "ide%d: Cannot obtain PCI resources for %s\n",
1333 i, np->full_name);
1334 return -ENXIO;
1335 }
1336
1337 hwif->pci_dev = pdev;
1338 hwif->gendev.parent = &pdev->dev;
1339 pmif->mdev = NULL;
1340 pmif->node = np;
1341
1342 rbase = pci_resource_start(pdev, 0);
1343 rlen = pci_resource_len(pdev, 0);
1344
1345 base = ioremap(rbase, rlen);
1346 pmif->regbase = (unsigned long) base + 0x2000;
1347#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1348 pmif->dma_regs = base + 0x1000;
1349#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1350 pmif->kauai_fcr = base;
1351 pmif->irq = pdev->irq;
1352
1353 pci_set_drvdata(pdev, hwif);
1354
1355 rc = pmac_ide_setup_device(pmif, hwif);
1356 if (rc != 0) {
1357 /* The inteface is released to the common IDE layer */
1358 pci_set_drvdata(pdev, NULL);
1359 iounmap(base);
1360 memset(pmif, 0, sizeof(*pmif));
1361 pci_release_regions(pdev);
1362 }
1363
1364 return rc;
1365}
1366
1367static int
David Brownell8b4b8a22006-08-14 23:11:03 -07001368pmac_ide_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001369{
1370 ide_hwif_t *hwif = (ide_hwif_t *)pci_get_drvdata(pdev);
1371 int rc = 0;
1372
David Brownell8b4b8a22006-08-14 23:11:03 -07001373 if (mesg.event != pdev->dev.power.power_state.event
1374 && mesg.event == PM_EVENT_SUSPEND) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001375 rc = pmac_ide_do_suspend(hwif);
1376 if (rc == 0)
David Brownell8b4b8a22006-08-14 23:11:03 -07001377 pdev->dev.power.power_state = mesg;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001378 }
1379
1380 return rc;
1381}
1382
1383static int
1384pmac_ide_pci_resume(struct pci_dev *pdev)
1385{
1386 ide_hwif_t *hwif = (ide_hwif_t *)pci_get_drvdata(pdev);
1387 int rc = 0;
1388
Pavel Machekca078ba2005-09-03 15:56:57 -07001389 if (pdev->dev.power.power_state.event != PM_EVENT_ON) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001390 rc = pmac_ide_do_resume(hwif);
1391 if (rc == 0)
Pavel Machek829ca9a2005-09-03 15:56:56 -07001392 pdev->dev.power.power_state = PMSG_ON;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001393 }
1394
1395 return rc;
1396}
1397
Jeff Mahoney5e655772005-07-06 15:44:41 -04001398static struct of_device_id pmac_ide_macio_match[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -07001399{
1400 {
1401 .name = "IDE",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001402 },
1403 {
1404 .name = "ATA",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001405 },
1406 {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001407 .type = "ide",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001408 },
1409 {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001410 .type = "ata",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001411 },
1412 {},
1413};
1414
1415static struct macio_driver pmac_ide_macio_driver =
1416{
1417 .name = "ide-pmac",
1418 .match_table = pmac_ide_macio_match,
1419 .probe = pmac_ide_macio_attach,
1420 .suspend = pmac_ide_macio_suspend,
1421 .resume = pmac_ide_macio_resume,
1422};
1423
1424static struct pci_device_id pmac_ide_pci_match[] = {
Olof Johansson7fce2602005-11-13 16:06:48 -08001425 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA,
1426 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1427 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100,
1428 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1429 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100,
1430 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
Linus Torvalds1da177e2005-04-16 15:20:36 -07001431 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_SH_ATA,
1432 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
Olof Johansson7fce2602005-11-13 16:06:48 -08001433 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID2_ATA,
1434 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
Benjamin Herrenschmidt71e4eda2007-10-06 18:52:27 +10001435 {},
Linus Torvalds1da177e2005-04-16 15:20:36 -07001436};
1437
1438static struct pci_driver pmac_ide_pci_driver = {
1439 .name = "ide-pmac",
1440 .id_table = pmac_ide_pci_match,
1441 .probe = pmac_ide_pci_attach,
1442 .suspend = pmac_ide_pci_suspend,
1443 .resume = pmac_ide_pci_resume,
1444};
1445MODULE_DEVICE_TABLE(pci, pmac_ide_pci_match);
1446
Andrew Morton9e5755b2007-03-03 17:48:54 +01001447int __init pmac_ide_probe(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001448{
Andrew Morton9e5755b2007-03-03 17:48:54 +01001449 int error;
1450
Benjamin Herrenschmidte8222502006-03-28 23:15:54 +11001451 if (!machine_is(powermac))
Andrew Morton9e5755b2007-03-03 17:48:54 +01001452 return -ENODEV;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001453
1454#ifdef CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST
Andrew Morton9e5755b2007-03-03 17:48:54 +01001455 error = pci_register_driver(&pmac_ide_pci_driver);
1456 if (error)
1457 goto out;
1458 error = macio_register_driver(&pmac_ide_macio_driver);
1459 if (error) {
1460 pci_unregister_driver(&pmac_ide_pci_driver);
1461 goto out;
1462 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001463#else
Andrew Morton9e5755b2007-03-03 17:48:54 +01001464 error = macio_register_driver(&pmac_ide_macio_driver);
1465 if (error)
1466 goto out;
1467 error = pci_register_driver(&pmac_ide_pci_driver);
1468 if (error) {
1469 macio_unregister_driver(&pmac_ide_macio_driver);
1470 goto out;
1471 }
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +11001472#endif
Andrew Morton9e5755b2007-03-03 17:48:54 +01001473out:
1474 return error;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001475}
1476
1477#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1478
1479/*
1480 * pmac_ide_build_dmatable builds the DBDMA command list
1481 * for a transfer and sets the DBDMA channel to point to it.
1482 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -05001483static int
Linus Torvalds1da177e2005-04-16 15:20:36 -07001484pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq)
1485{
1486 struct dbdma_cmd *table;
1487 int i, count = 0;
1488 ide_hwif_t *hwif = HWIF(drive);
1489 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1490 volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1491 struct scatterlist *sg;
1492 int wr = (rq_data_dir(rq) == WRITE);
1493
1494 /* DMA table is already aligned */
1495 table = (struct dbdma_cmd *) pmif->dma_table_cpu;
1496
1497 /* Make sure DMA controller is stopped (necessary ?) */
1498 writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma->control);
1499 while (readl(&dma->status) & RUN)
1500 udelay(1);
1501
1502 hwif->sg_nents = i = ide_build_sglist(drive, rq);
1503
1504 if (!i)
1505 return 0;
1506
1507 /* Build DBDMA commands list */
1508 sg = hwif->sg_table;
1509 while (i && sg_dma_len(sg)) {
1510 u32 cur_addr;
1511 u32 cur_len;
1512
1513 cur_addr = sg_dma_address(sg);
1514 cur_len = sg_dma_len(sg);
1515
1516 if (pmif->broken_dma && cur_addr & (L1_CACHE_BYTES - 1)) {
1517 if (pmif->broken_dma_warn == 0) {
1518 printk(KERN_WARNING "%s: DMA on non aligned address,"
1519 "switching to PIO on Ohare chipset\n", drive->name);
1520 pmif->broken_dma_warn = 1;
1521 }
1522 goto use_pio_instead;
1523 }
1524 while (cur_len) {
1525 unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
1526
1527 if (count++ >= MAX_DCMDS) {
1528 printk(KERN_WARNING "%s: DMA table too small\n",
1529 drive->name);
1530 goto use_pio_instead;
1531 }
1532 st_le16(&table->command, wr? OUTPUT_MORE: INPUT_MORE);
1533 st_le16(&table->req_count, tc);
1534 st_le32(&table->phy_addr, cur_addr);
1535 table->cmd_dep = 0;
1536 table->xfer_status = 0;
1537 table->res_count = 0;
1538 cur_addr += tc;
1539 cur_len -= tc;
1540 ++table;
1541 }
1542 sg++;
1543 i--;
1544 }
1545
1546 /* convert the last command to an input/output last command */
1547 if (count) {
1548 st_le16(&table[-1].command, wr? OUTPUT_LAST: INPUT_LAST);
1549 /* add the stop command to the end of the list */
1550 memset(table, 0, sizeof(struct dbdma_cmd));
1551 st_le16(&table->command, DBDMA_STOP);
1552 mb();
1553 writel(hwif->dmatable_dma, &dma->cmdptr);
1554 return 1;
1555 }
1556
1557 printk(KERN_DEBUG "%s: empty DMA table?\n", drive->name);
1558 use_pio_instead:
1559 pci_unmap_sg(hwif->pci_dev,
1560 hwif->sg_table,
1561 hwif->sg_nents,
1562 hwif->sg_dma_direction);
1563 return 0; /* revert to PIO for this request */
1564}
1565
1566/* Teardown mappings after DMA has completed. */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -05001567static void
Linus Torvalds1da177e2005-04-16 15:20:36 -07001568pmac_ide_destroy_dmatable (ide_drive_t *drive)
1569{
1570 ide_hwif_t *hwif = drive->hwif;
1571 struct pci_dev *dev = HWIF(drive)->pci_dev;
1572 struct scatterlist *sg = hwif->sg_table;
1573 int nents = hwif->sg_nents;
1574
1575 if (nents) {
1576 pci_unmap_sg(dev, sg, nents, hwif->sg_dma_direction);
1577 hwif->sg_nents = 0;
1578 }
1579}
1580
1581/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001582 * Check what is the best DMA timing setting for the drive and
1583 * call appropriate functions to apply it.
1584 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -05001585static int
Linus Torvalds1da177e2005-04-16 15:20:36 -07001586pmac_ide_dma_check(ide_drive_t *drive)
1587{
Bartlomiej Zolnierkiewicz254bb552007-10-13 17:47:50 +02001588 if (ide_tune_dma(drive))
1589 return 0;
Bartlomiej Zolnierkiewiczfd553ce2007-10-13 17:47:49 +02001590
Bartlomiej Zolnierkiewicz254bb552007-10-13 17:47:50 +02001591 return -1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001592}
1593
1594/*
1595 * Prepare a DMA transfer. We build the DMA table, adjust the timings for
1596 * a read on KeyLargo ATA/66 and mark us as waiting for DMA completion
1597 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -05001598static int
Linus Torvalds1da177e2005-04-16 15:20:36 -07001599pmac_ide_dma_setup(ide_drive_t *drive)
1600{
1601 ide_hwif_t *hwif = HWIF(drive);
1602 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1603 struct request *rq = HWGROUP(drive)->rq;
1604 u8 unit = (drive->select.b.unit & 0x01);
1605 u8 ata4;
1606
1607 if (pmif == NULL)
1608 return 1;
1609 ata4 = (pmif->kind == controller_kl_ata4);
1610
1611 if (!pmac_ide_build_dmatable(drive, rq)) {
1612 ide_map_sg(drive, rq);
1613 return 1;
1614 }
1615
1616 /* Apple adds 60ns to wrDataSetup on reads */
1617 if (ata4 && (pmif->timings[unit] & TR_66_UDMA_EN)) {
1618 writel(pmif->timings[unit] + (!rq_data_dir(rq) ? 0x00800000UL : 0),
1619 PMAC_IDE_REG(IDE_TIMING_CONFIG));
1620 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
1621 }
1622
1623 drive->waiting_for_dma = 1;
1624
1625 return 0;
1626}
1627
Jon Loeligeraacaf9b2005-09-17 10:36:54 -05001628static void
Linus Torvalds1da177e2005-04-16 15:20:36 -07001629pmac_ide_dma_exec_cmd(ide_drive_t *drive, u8 command)
1630{
1631 /* issue cmd to drive */
1632 ide_execute_command(drive, command, &ide_dma_intr, 2*WAIT_CMD, NULL);
1633}
1634
1635/*
1636 * Kick the DMA controller into life after the DMA command has been issued
1637 * to the drive.
1638 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -05001639static void
Linus Torvalds1da177e2005-04-16 15:20:36 -07001640pmac_ide_dma_start(ide_drive_t *drive)
1641{
1642 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1643 volatile struct dbdma_regs __iomem *dma;
1644
1645 dma = pmif->dma_regs;
1646
1647 writel((RUN << 16) | RUN, &dma->control);
1648 /* Make sure it gets to the controller right now */
1649 (void)readl(&dma->control);
1650}
1651
1652/*
1653 * After a DMA transfer, make sure the controller is stopped
1654 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -05001655static int
Linus Torvalds1da177e2005-04-16 15:20:36 -07001656pmac_ide_dma_end (ide_drive_t *drive)
1657{
1658 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1659 volatile struct dbdma_regs __iomem *dma;
1660 u32 dstat;
1661
1662 if (pmif == NULL)
1663 return 0;
1664 dma = pmif->dma_regs;
1665
1666 drive->waiting_for_dma = 0;
1667 dstat = readl(&dma->status);
1668 writel(((RUN|WAKE|DEAD) << 16), &dma->control);
1669 pmac_ide_destroy_dmatable(drive);
1670 /* verify good dma status. we don't check for ACTIVE beeing 0. We should...
1671 * in theory, but with ATAPI decices doing buffer underruns, that would
1672 * cause us to disable DMA, which isn't what we want
1673 */
1674 return (dstat & (RUN|DEAD)) != RUN;
1675}
1676
1677/*
1678 * Check out that the interrupt we got was for us. We can't always know this
1679 * for sure with those Apple interfaces (well, we could on the recent ones but
1680 * that's not implemented yet), on the other hand, we don't have shared interrupts
1681 * so it's not really a problem
1682 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -05001683static int
Linus Torvalds1da177e2005-04-16 15:20:36 -07001684pmac_ide_dma_test_irq (ide_drive_t *drive)
1685{
1686 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1687 volatile struct dbdma_regs __iomem *dma;
1688 unsigned long status, timeout;
1689
1690 if (pmif == NULL)
1691 return 0;
1692 dma = pmif->dma_regs;
1693
1694 /* We have to things to deal with here:
1695 *
1696 * - The dbdma won't stop if the command was started
1697 * but completed with an error without transferring all
1698 * datas. This happens when bad blocks are met during
1699 * a multi-block transfer.
1700 *
1701 * - The dbdma fifo hasn't yet finished flushing to
1702 * to system memory when the disk interrupt occurs.
1703 *
1704 */
1705
1706 /* If ACTIVE is cleared, the STOP command have passed and
1707 * transfer is complete.
1708 */
1709 status = readl(&dma->status);
1710 if (!(status & ACTIVE))
1711 return 1;
1712 if (!drive->waiting_for_dma)
1713 printk(KERN_WARNING "ide%d, ide_dma_test_irq \
1714 called while not waiting\n", HWIF(drive)->index);
1715
1716 /* If dbdma didn't execute the STOP command yet, the
1717 * active bit is still set. We consider that we aren't
1718 * sharing interrupts (which is hopefully the case with
1719 * those controllers) and so we just try to flush the
1720 * channel for pending data in the fifo
1721 */
1722 udelay(1);
1723 writel((FLUSH << 16) | FLUSH, &dma->control);
1724 timeout = 0;
1725 for (;;) {
1726 udelay(1);
1727 status = readl(&dma->status);
1728 if ((status & FLUSH) == 0)
1729 break;
1730 if (++timeout > 100) {
1731 printk(KERN_WARNING "ide%d, ide_dma_test_irq \
1732 timeout flushing channel\n", HWIF(drive)->index);
1733 break;
1734 }
1735 }
1736 return 1;
1737}
1738
Bartlomiej Zolnierkiewicz7469aaf2007-02-17 02:40:26 +01001739static void pmac_ide_dma_host_off(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001740{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001741}
1742
Andrew Morton9e5755b2007-03-03 17:48:54 +01001743static void pmac_ide_dma_host_on(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001744{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001745}
1746
Sergei Shtylyov841d2a92007-07-09 23:17:54 +02001747static void
1748pmac_ide_dma_lost_irq (ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001749{
1750 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1751 volatile struct dbdma_regs __iomem *dma;
1752 unsigned long status;
1753
1754 if (pmif == NULL)
Sergei Shtylyov841d2a92007-07-09 23:17:54 +02001755 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001756 dma = pmif->dma_regs;
1757
1758 status = readl(&dma->status);
1759 printk(KERN_ERR "ide-pmac lost interrupt, dma status: %lx\n", status);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001760}
1761
1762/*
1763 * Allocate the data structures needed for using DMA with an interface
1764 * and fill the proper list of functions pointers
1765 */
1766static void __init
1767pmac_ide_setup_dma(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif)
1768{
1769 /* We won't need pci_dev if we switch to generic consistent
1770 * DMA routines ...
1771 */
1772 if (hwif->pci_dev == NULL)
1773 return;
1774 /*
1775 * Allocate space for the DBDMA commands.
1776 * The +2 is +1 for the stop command and +1 to allow for
1777 * aligning the start address to a multiple of 16 bytes.
1778 */
1779 pmif->dma_table_cpu = (struct dbdma_cmd*)pci_alloc_consistent(
1780 hwif->pci_dev,
1781 (MAX_DCMDS + 2) * sizeof(struct dbdma_cmd),
1782 &hwif->dmatable_dma);
1783 if (pmif->dma_table_cpu == NULL) {
1784 printk(KERN_ERR "%s: unable to allocate DMA command list\n",
1785 hwif->name);
1786 return;
1787 }
1788
Bartlomiej Zolnierkiewicz7469aaf2007-02-17 02:40:26 +01001789 hwif->dma_off_quietly = &ide_dma_off_quietly;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001790 hwif->ide_dma_on = &__ide_dma_on;
1791 hwif->ide_dma_check = &pmac_ide_dma_check;
1792 hwif->dma_setup = &pmac_ide_dma_setup;
1793 hwif->dma_exec_cmd = &pmac_ide_dma_exec_cmd;
1794 hwif->dma_start = &pmac_ide_dma_start;
1795 hwif->ide_dma_end = &pmac_ide_dma_end;
1796 hwif->ide_dma_test_irq = &pmac_ide_dma_test_irq;
Bartlomiej Zolnierkiewicz7469aaf2007-02-17 02:40:26 +01001797 hwif->dma_host_off = &pmac_ide_dma_host_off;
Bartlomiej Zolnierkiewiczccf35282007-02-17 02:40:26 +01001798 hwif->dma_host_on = &pmac_ide_dma_host_on;
Sergei Shtylyovc283f5d2007-07-09 23:17:54 +02001799 hwif->dma_timeout = &ide_dma_timeout;
Sergei Shtylyov841d2a92007-07-09 23:17:54 +02001800 hwif->dma_lost_irq = &pmac_ide_dma_lost_irq;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001801
1802 hwif->atapi_dma = 1;
1803 switch(pmif->kind) {
1804 case controller_sh_ata6:
1805 hwif->ultra_mask = pmif->cable_80 ? 0x7f : 0x07;
1806 hwif->mwdma_mask = 0x07;
1807 hwif->swdma_mask = 0x00;
1808 break;
1809 case controller_un_ata6:
1810 case controller_k2_ata6:
1811 hwif->ultra_mask = pmif->cable_80 ? 0x3f : 0x07;
1812 hwif->mwdma_mask = 0x07;
1813 hwif->swdma_mask = 0x00;
1814 break;
1815 case controller_kl_ata4:
1816 hwif->ultra_mask = pmif->cable_80 ? 0x1f : 0x07;
1817 hwif->mwdma_mask = 0x07;
1818 hwif->swdma_mask = 0x00;
1819 break;
1820 default:
1821 hwif->ultra_mask = 0x00;
1822 hwif->mwdma_mask = 0x07;
1823 hwif->swdma_mask = 0x00;
1824 break;
Bartlomiej Zolnierkiewicz254bb552007-10-13 17:47:50 +02001825 }
1826
1827 hwif->autodma = 1;
1828 hwif->drives[1].autodma = hwif->drives[0].autodma = hwif->autodma;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001829}
1830
1831#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */