| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* cpu-irqs.h: on-CPU peripheral irqs |
| 2 | * |
| 3 | * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved. |
| 4 | * Written by David Howells (dhowells@redhat.com) |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License |
| 8 | * as published by the Free Software Foundation; either version |
| 9 | * 2 of the License, or (at your option) any later version. |
| 10 | */ |
| 11 | |
| 12 | #ifndef _ASM_CPU_IRQS_H |
| 13 | #define _ASM_CPU_IRQS_H |
| 14 | |
| 15 | #ifndef __ASSEMBLY__ |
| 16 | |
| 17 | #include <asm/irq-routing.h> |
| 18 | |
| 19 | #define IRQ_BASE_CPU (NR_IRQ_ACTIONS_PER_GROUP * 0) |
| 20 | |
| 21 | /* IRQ IDs presented to drivers */ |
| 22 | enum { |
| 23 | IRQ_CPU__UNUSED = IRQ_BASE_CPU, |
| 24 | IRQ_CPU_UART0, |
| 25 | IRQ_CPU_UART1, |
| 26 | IRQ_CPU_TIMER0, |
| 27 | IRQ_CPU_TIMER1, |
| 28 | IRQ_CPU_TIMER2, |
| 29 | IRQ_CPU_DMA0, |
| 30 | IRQ_CPU_DMA1, |
| 31 | IRQ_CPU_DMA2, |
| 32 | IRQ_CPU_DMA3, |
| 33 | IRQ_CPU_DMA4, |
| 34 | IRQ_CPU_DMA5, |
| 35 | IRQ_CPU_DMA6, |
| 36 | IRQ_CPU_DMA7, |
| 37 | IRQ_CPU_EXTERNAL0, |
| 38 | IRQ_CPU_EXTERNAL1, |
| 39 | IRQ_CPU_EXTERNAL2, |
| 40 | IRQ_CPU_EXTERNAL3, |
| 41 | IRQ_CPU_EXTERNAL4, |
| 42 | IRQ_CPU_EXTERNAL5, |
| 43 | IRQ_CPU_EXTERNAL6, |
| 44 | IRQ_CPU_EXTERNAL7, |
| 45 | }; |
| 46 | |
| 47 | /* IRQ to level mappings */ |
| 48 | #define IRQ_GDBSTUB_LEVEL 15 |
| 49 | #define IRQ_UART_LEVEL 13 |
| 50 | |
| 51 | #ifdef CONFIG_GDBSTUB_UART0 |
| 52 | #define IRQ_UART0_LEVEL IRQ_GDBSTUB_LEVEL |
| 53 | #else |
| 54 | #define IRQ_UART0_LEVEL IRQ_UART_LEVEL |
| 55 | #endif |
| 56 | |
| 57 | #ifdef CONFIG_GDBSTUB_UART1 |
| 58 | #define IRQ_UART1_LEVEL IRQ_GDBSTUB_LEVEL |
| 59 | #else |
| 60 | #define IRQ_UART1_LEVEL IRQ_UART_LEVEL |
| 61 | #endif |
| 62 | |
| 63 | #define IRQ_DMA0_LEVEL 14 |
| 64 | #define IRQ_DMA1_LEVEL 14 |
| 65 | #define IRQ_DMA2_LEVEL 14 |
| 66 | #define IRQ_DMA3_LEVEL 14 |
| 67 | #define IRQ_DMA4_LEVEL 14 |
| 68 | #define IRQ_DMA5_LEVEL 14 |
| 69 | #define IRQ_DMA6_LEVEL 14 |
| 70 | #define IRQ_DMA7_LEVEL 14 |
| 71 | |
| 72 | #define IRQ_TIMER0_LEVEL 12 |
| 73 | #define IRQ_TIMER1_LEVEL 11 |
| 74 | #define IRQ_TIMER2_LEVEL 10 |
| 75 | |
| 76 | #define IRQ_XIRQ0_LEVEL 1 |
| 77 | #define IRQ_XIRQ1_LEVEL 2 |
| 78 | #define IRQ_XIRQ2_LEVEL 3 |
| 79 | #define IRQ_XIRQ3_LEVEL 4 |
| 80 | #define IRQ_XIRQ4_LEVEL 5 |
| 81 | #define IRQ_XIRQ5_LEVEL 6 |
| 82 | #define IRQ_XIRQ6_LEVEL 7 |
| 83 | #define IRQ_XIRQ7_LEVEL 8 |
| 84 | |
| 85 | #endif /* !__ASSEMBLY__ */ |
| 86 | |
| 87 | #endif /* _ASM_CPU_IRQS_H */ |