Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the "Software"), |
| 7 | * to deal in the Software without restriction, including without limitation |
| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
| 10 | * Software is furnished to do so, subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice shall be included in |
| 13 | * all copies or substantial portions of the Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 21 | * OTHER DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: Dave Airlie |
| 24 | * Alex Deucher |
| 25 | */ |
| 26 | #include <drm/drmP.h> |
| 27 | #include <drm/drm_crtc_helper.h> |
| 28 | #include <drm/radeon_drm.h> |
Ben Skeggs | 68adac5 | 2010-04-28 11:46:42 +1000 | [diff] [blame] | 29 | #include <drm/drm_fixed.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 30 | #include "radeon.h" |
| 31 | #include "atom.h" |
| 32 | #include "atom-bits.h" |
| 33 | |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 34 | static void atombios_overscan_setup(struct drm_crtc *crtc, |
| 35 | struct drm_display_mode *mode, |
| 36 | struct drm_display_mode *adjusted_mode) |
| 37 | { |
| 38 | struct drm_device *dev = crtc->dev; |
| 39 | struct radeon_device *rdev = dev->dev_private; |
| 40 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 41 | SET_CRTC_OVERSCAN_PS_ALLOCATION args; |
| 42 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan); |
| 43 | int a1, a2; |
| 44 | |
| 45 | memset(&args, 0, sizeof(args)); |
| 46 | |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 47 | args.ucCRTC = radeon_crtc->crtc_id; |
| 48 | |
| 49 | switch (radeon_crtc->rmx_type) { |
| 50 | case RMX_CENTER: |
Cédric Cano | 4589433 | 2011-02-11 19:45:37 -0500 | [diff] [blame] | 51 | args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); |
| 52 | args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); |
| 53 | args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); |
| 54 | args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 55 | break; |
| 56 | case RMX_ASPECT: |
| 57 | a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; |
| 58 | a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; |
| 59 | |
| 60 | if (a1 > a2) { |
Cédric Cano | 4589433 | 2011-02-11 19:45:37 -0500 | [diff] [blame] | 61 | args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); |
| 62 | args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 63 | } else if (a2 > a1) { |
Alex Deucher | 942b0e9 | 2011-03-14 23:18:00 -0400 | [diff] [blame] | 64 | args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); |
| 65 | args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 66 | } |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 67 | break; |
| 68 | case RMX_FULL: |
| 69 | default: |
Cédric Cano | 4589433 | 2011-02-11 19:45:37 -0500 | [diff] [blame] | 70 | args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border); |
| 71 | args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border); |
| 72 | args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border); |
| 73 | args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 74 | break; |
| 75 | } |
Alex Deucher | 5b1714d | 2010-08-03 19:59:20 -0400 | [diff] [blame] | 76 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 77 | } |
| 78 | |
| 79 | static void atombios_scaler_setup(struct drm_crtc *crtc) |
| 80 | { |
| 81 | struct drm_device *dev = crtc->dev; |
| 82 | struct radeon_device *rdev = dev->dev_private; |
| 83 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 84 | ENABLE_SCALER_PS_ALLOCATION args; |
| 85 | int index = GetIndexIntoMasterTable(COMMAND, EnableScaler); |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 86 | |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 87 | /* fixme - fill in enc_priv for atom dac */ |
| 88 | enum radeon_tv_std tv_std = TV_STD_NTSC; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 89 | bool is_tv = false, is_cv = false; |
| 90 | struct drm_encoder *encoder; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 91 | |
| 92 | if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) |
| 93 | return; |
| 94 | |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 95 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 96 | /* find tv std */ |
| 97 | if (encoder->crtc == crtc) { |
| 98 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 99 | if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { |
| 100 | struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; |
| 101 | tv_std = tv_dac->tv_std; |
| 102 | is_tv = true; |
| 103 | } |
| 104 | } |
| 105 | } |
| 106 | |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 107 | memset(&args, 0, sizeof(args)); |
| 108 | |
| 109 | args.ucScaler = radeon_crtc->crtc_id; |
| 110 | |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 111 | if (is_tv) { |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 112 | switch (tv_std) { |
| 113 | case TV_STD_NTSC: |
| 114 | default: |
| 115 | args.ucTVStandard = ATOM_TV_NTSC; |
| 116 | break; |
| 117 | case TV_STD_PAL: |
| 118 | args.ucTVStandard = ATOM_TV_PAL; |
| 119 | break; |
| 120 | case TV_STD_PAL_M: |
| 121 | args.ucTVStandard = ATOM_TV_PALM; |
| 122 | break; |
| 123 | case TV_STD_PAL_60: |
| 124 | args.ucTVStandard = ATOM_TV_PAL60; |
| 125 | break; |
| 126 | case TV_STD_NTSC_J: |
| 127 | args.ucTVStandard = ATOM_TV_NTSCJ; |
| 128 | break; |
| 129 | case TV_STD_SCART_PAL: |
| 130 | args.ucTVStandard = ATOM_TV_PAL; /* ??? */ |
| 131 | break; |
| 132 | case TV_STD_SECAM: |
| 133 | args.ucTVStandard = ATOM_TV_SECAM; |
| 134 | break; |
| 135 | case TV_STD_PAL_CN: |
| 136 | args.ucTVStandard = ATOM_TV_PALCN; |
| 137 | break; |
| 138 | } |
| 139 | args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 140 | } else if (is_cv) { |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 141 | args.ucTVStandard = ATOM_TV_CV; |
| 142 | args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; |
| 143 | } else { |
| 144 | switch (radeon_crtc->rmx_type) { |
| 145 | case RMX_FULL: |
| 146 | args.ucEnable = ATOM_SCALER_EXPANSION; |
| 147 | break; |
| 148 | case RMX_CENTER: |
| 149 | args.ucEnable = ATOM_SCALER_CENTER; |
| 150 | break; |
| 151 | case RMX_ASPECT: |
| 152 | args.ucEnable = ATOM_SCALER_EXPANSION; |
| 153 | break; |
| 154 | default: |
| 155 | if (ASIC_IS_AVIVO(rdev)) |
| 156 | args.ucEnable = ATOM_SCALER_DISABLE; |
| 157 | else |
| 158 | args.ucEnable = ATOM_SCALER_CENTER; |
| 159 | break; |
| 160 | } |
| 161 | } |
| 162 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 163 | if ((is_tv || is_cv) |
| 164 | && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) { |
| 165 | atom_rv515_force_tv_scaler(rdev, radeon_crtc); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 166 | } |
| 167 | } |
| 168 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 169 | static void atombios_lock_crtc(struct drm_crtc *crtc, int lock) |
| 170 | { |
| 171 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 172 | struct drm_device *dev = crtc->dev; |
| 173 | struct radeon_device *rdev = dev->dev_private; |
| 174 | int index = |
| 175 | GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters); |
| 176 | ENABLE_CRTC_PS_ALLOCATION args; |
| 177 | |
| 178 | memset(&args, 0, sizeof(args)); |
| 179 | |
| 180 | args.ucCRTC = radeon_crtc->crtc_id; |
| 181 | args.ucEnable = lock; |
| 182 | |
| 183 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 184 | } |
| 185 | |
| 186 | static void atombios_enable_crtc(struct drm_crtc *crtc, int state) |
| 187 | { |
| 188 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 189 | struct drm_device *dev = crtc->dev; |
| 190 | struct radeon_device *rdev = dev->dev_private; |
| 191 | int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC); |
| 192 | ENABLE_CRTC_PS_ALLOCATION args; |
| 193 | |
| 194 | memset(&args, 0, sizeof(args)); |
| 195 | |
| 196 | args.ucCRTC = radeon_crtc->crtc_id; |
| 197 | args.ucEnable = state; |
| 198 | |
| 199 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 200 | } |
| 201 | |
| 202 | static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state) |
| 203 | { |
| 204 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 205 | struct drm_device *dev = crtc->dev; |
| 206 | struct radeon_device *rdev = dev->dev_private; |
| 207 | int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq); |
| 208 | ENABLE_CRTC_PS_ALLOCATION args; |
| 209 | |
| 210 | memset(&args, 0, sizeof(args)); |
| 211 | |
| 212 | args.ucCRTC = radeon_crtc->crtc_id; |
| 213 | args.ucEnable = state; |
| 214 | |
| 215 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 216 | } |
| 217 | |
| 218 | static void atombios_blank_crtc(struct drm_crtc *crtc, int state) |
| 219 | { |
| 220 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 221 | struct drm_device *dev = crtc->dev; |
| 222 | struct radeon_device *rdev = dev->dev_private; |
| 223 | int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC); |
| 224 | BLANK_CRTC_PS_ALLOCATION args; |
| 225 | |
| 226 | memset(&args, 0, sizeof(args)); |
| 227 | |
| 228 | args.ucCRTC = radeon_crtc->crtc_id; |
| 229 | args.ucBlanking = state; |
| 230 | |
| 231 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 232 | } |
| 233 | |
| 234 | void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) |
| 235 | { |
| 236 | struct drm_device *dev = crtc->dev; |
| 237 | struct radeon_device *rdev = dev->dev_private; |
Alex Deucher | 500b758 | 2009-12-02 11:46:52 -0500 | [diff] [blame] | 238 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 239 | |
| 240 | switch (mode) { |
| 241 | case DRM_MODE_DPMS_ON: |
Alex Deucher | d731117 | 2010-05-03 01:13:14 -0400 | [diff] [blame] | 242 | radeon_crtc->enabled = true; |
| 243 | /* adjust pm to dpms changes BEFORE enabling crtcs */ |
| 244 | radeon_pm_compute_clocks(rdev); |
Alex Deucher | 37b4390 | 2010-02-09 12:04:43 -0500 | [diff] [blame] | 245 | atombios_enable_crtc(crtc, ATOM_ENABLE); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 246 | if (ASIC_IS_DCE3(rdev)) |
Alex Deucher | 37b4390 | 2010-02-09 12:04:43 -0500 | [diff] [blame] | 247 | atombios_enable_crtc_memreq(crtc, ATOM_ENABLE); |
| 248 | atombios_blank_crtc(crtc, ATOM_DISABLE); |
Alex Deucher | 45f9a39 | 2010-03-24 13:55:51 -0400 | [diff] [blame] | 249 | drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); |
Alex Deucher | 500b758 | 2009-12-02 11:46:52 -0500 | [diff] [blame] | 250 | radeon_crtc_load_lut(crtc); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 251 | break; |
| 252 | case DRM_MODE_DPMS_STANDBY: |
| 253 | case DRM_MODE_DPMS_SUSPEND: |
| 254 | case DRM_MODE_DPMS_OFF: |
Alex Deucher | 45f9a39 | 2010-03-24 13:55:51 -0400 | [diff] [blame] | 255 | drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); |
Alex Deucher | a93f344 | 2010-12-20 11:22:29 -0500 | [diff] [blame] | 256 | if (radeon_crtc->enabled) |
| 257 | atombios_blank_crtc(crtc, ATOM_ENABLE); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 258 | if (ASIC_IS_DCE3(rdev)) |
Alex Deucher | 37b4390 | 2010-02-09 12:04:43 -0500 | [diff] [blame] | 259 | atombios_enable_crtc_memreq(crtc, ATOM_DISABLE); |
| 260 | atombios_enable_crtc(crtc, ATOM_DISABLE); |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 261 | radeon_crtc->enabled = false; |
Alex Deucher | d731117 | 2010-05-03 01:13:14 -0400 | [diff] [blame] | 262 | /* adjust pm to dpms changes AFTER disabling crtcs */ |
| 263 | radeon_pm_compute_clocks(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 264 | break; |
| 265 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 266 | } |
| 267 | |
| 268 | static void |
| 269 | atombios_set_crtc_dtd_timing(struct drm_crtc *crtc, |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 270 | struct drm_display_mode *mode) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 271 | { |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 272 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 273 | struct drm_device *dev = crtc->dev; |
| 274 | struct radeon_device *rdev = dev->dev_private; |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 275 | SET_CRTC_USING_DTD_TIMING_PARAMETERS args; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 276 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming); |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 277 | u16 misc = 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 278 | |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 279 | memset(&args, 0, sizeof(args)); |
Alex Deucher | 5b1714d | 2010-08-03 19:59:20 -0400 | [diff] [blame] | 280 | args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2)); |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 281 | args.usH_Blanking_Time = |
Alex Deucher | 5b1714d | 2010-08-03 19:59:20 -0400 | [diff] [blame] | 282 | cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2)); |
| 283 | args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2)); |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 284 | args.usV_Blanking_Time = |
Alex Deucher | 5b1714d | 2010-08-03 19:59:20 -0400 | [diff] [blame] | 285 | cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2)); |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 286 | args.usH_SyncOffset = |
Alex Deucher | 5b1714d | 2010-08-03 19:59:20 -0400 | [diff] [blame] | 287 | cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border); |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 288 | args.usH_SyncWidth = |
| 289 | cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); |
| 290 | args.usV_SyncOffset = |
Alex Deucher | 5b1714d | 2010-08-03 19:59:20 -0400 | [diff] [blame] | 291 | cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border); |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 292 | args.usV_SyncWidth = |
| 293 | cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); |
Alex Deucher | 5b1714d | 2010-08-03 19:59:20 -0400 | [diff] [blame] | 294 | args.ucH_Border = radeon_crtc->h_border; |
| 295 | args.ucV_Border = radeon_crtc->v_border; |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 296 | |
| 297 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
| 298 | misc |= ATOM_VSYNC_POLARITY; |
| 299 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) |
| 300 | misc |= ATOM_HSYNC_POLARITY; |
| 301 | if (mode->flags & DRM_MODE_FLAG_CSYNC) |
| 302 | misc |= ATOM_COMPOSITESYNC; |
| 303 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
| 304 | misc |= ATOM_INTERLACE; |
| 305 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
| 306 | misc |= ATOM_DOUBLE_CLOCK_MODE; |
| 307 | |
| 308 | args.susModeMiscInfo.usAccess = cpu_to_le16(misc); |
| 309 | args.ucCRTC = radeon_crtc->crtc_id; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 310 | |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 311 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 312 | } |
| 313 | |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 314 | static void atombios_crtc_set_timing(struct drm_crtc *crtc, |
| 315 | struct drm_display_mode *mode) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 316 | { |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 317 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 318 | struct drm_device *dev = crtc->dev; |
| 319 | struct radeon_device *rdev = dev->dev_private; |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 320 | SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 321 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing); |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 322 | u16 misc = 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 323 | |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 324 | memset(&args, 0, sizeof(args)); |
| 325 | args.usH_Total = cpu_to_le16(mode->crtc_htotal); |
| 326 | args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay); |
| 327 | args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start); |
| 328 | args.usH_SyncWidth = |
| 329 | cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); |
| 330 | args.usV_Total = cpu_to_le16(mode->crtc_vtotal); |
| 331 | args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay); |
| 332 | args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start); |
| 333 | args.usV_SyncWidth = |
| 334 | cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); |
| 335 | |
Alex Deucher | 54bfe49 | 2010-09-03 15:52:53 -0400 | [diff] [blame] | 336 | args.ucOverscanRight = radeon_crtc->h_border; |
| 337 | args.ucOverscanLeft = radeon_crtc->h_border; |
| 338 | args.ucOverscanBottom = radeon_crtc->v_border; |
| 339 | args.ucOverscanTop = radeon_crtc->v_border; |
| 340 | |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 341 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
| 342 | misc |= ATOM_VSYNC_POLARITY; |
| 343 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) |
| 344 | misc |= ATOM_HSYNC_POLARITY; |
| 345 | if (mode->flags & DRM_MODE_FLAG_CSYNC) |
| 346 | misc |= ATOM_COMPOSITESYNC; |
| 347 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
| 348 | misc |= ATOM_INTERLACE; |
| 349 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
| 350 | misc |= ATOM_DOUBLE_CLOCK_MODE; |
| 351 | |
| 352 | args.susModeMiscInfo.usAccess = cpu_to_le16(misc); |
| 353 | args.ucCRTC = radeon_crtc->crtc_id; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 354 | |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 355 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 356 | } |
| 357 | |
Alex Deucher | b792210 | 2010-03-06 10:57:30 -0500 | [diff] [blame] | 358 | static void atombios_disable_ss(struct drm_crtc *crtc) |
| 359 | { |
| 360 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 361 | struct drm_device *dev = crtc->dev; |
| 362 | struct radeon_device *rdev = dev->dev_private; |
| 363 | u32 ss_cntl; |
| 364 | |
| 365 | if (ASIC_IS_DCE4(rdev)) { |
| 366 | switch (radeon_crtc->pll_id) { |
| 367 | case ATOM_PPLL1: |
| 368 | ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL); |
| 369 | ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; |
| 370 | WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl); |
| 371 | break; |
| 372 | case ATOM_PPLL2: |
| 373 | ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL); |
| 374 | ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; |
| 375 | WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl); |
| 376 | break; |
| 377 | case ATOM_DCPLL: |
| 378 | case ATOM_PPLL_INVALID: |
| 379 | return; |
| 380 | } |
| 381 | } else if (ASIC_IS_AVIVO(rdev)) { |
| 382 | switch (radeon_crtc->pll_id) { |
| 383 | case ATOM_PPLL1: |
| 384 | ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL); |
| 385 | ss_cntl &= ~1; |
| 386 | WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl); |
| 387 | break; |
| 388 | case ATOM_PPLL2: |
| 389 | ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL); |
| 390 | ss_cntl &= ~1; |
| 391 | WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl); |
| 392 | break; |
| 393 | case ATOM_DCPLL: |
| 394 | case ATOM_PPLL_INVALID: |
| 395 | return; |
| 396 | } |
| 397 | } |
| 398 | } |
| 399 | |
| 400 | |
Alex Deucher | 26b9fc3 | 2010-02-01 16:39:11 -0500 | [diff] [blame] | 401 | union atom_enable_ss { |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 402 | ENABLE_LVDS_SS_PARAMETERS lvds_ss; |
| 403 | ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2; |
Alex Deucher | 26b9fc3 | 2010-02-01 16:39:11 -0500 | [diff] [blame] | 404 | ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1; |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 405 | ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2; |
Alex Deucher | a572eaa | 2011-01-06 21:19:16 -0500 | [diff] [blame] | 406 | ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3; |
Alex Deucher | 26b9fc3 | 2010-02-01 16:39:11 -0500 | [diff] [blame] | 407 | }; |
| 408 | |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 409 | static void atombios_crtc_program_ss(struct drm_crtc *crtc, |
| 410 | int enable, |
| 411 | int pll_id, |
| 412 | struct radeon_atom_ss *ss) |
Alex Deucher | ebbe1cb | 2009-10-16 11:15:25 -0400 | [diff] [blame] | 413 | { |
Alex Deucher | ebbe1cb | 2009-10-16 11:15:25 -0400 | [diff] [blame] | 414 | struct drm_device *dev = crtc->dev; |
| 415 | struct radeon_device *rdev = dev->dev_private; |
Alex Deucher | ebbe1cb | 2009-10-16 11:15:25 -0400 | [diff] [blame] | 416 | int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL); |
Alex Deucher | 26b9fc3 | 2010-02-01 16:39:11 -0500 | [diff] [blame] | 417 | union atom_enable_ss args; |
Alex Deucher | ebbe1cb | 2009-10-16 11:15:25 -0400 | [diff] [blame] | 418 | |
Alex Deucher | 26b9fc3 | 2010-02-01 16:39:11 -0500 | [diff] [blame] | 419 | memset(&args, 0, sizeof(args)); |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 420 | |
Alex Deucher | a572eaa | 2011-01-06 21:19:16 -0500 | [diff] [blame] | 421 | if (ASIC_IS_DCE5(rdev)) { |
Cédric Cano | 4589433 | 2011-02-11 19:45:37 -0500 | [diff] [blame] | 422 | args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0); |
Alex Deucher | 8e8e523 | 2011-05-20 04:34:16 -0400 | [diff] [blame^] | 423 | args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
Alex Deucher | a572eaa | 2011-01-06 21:19:16 -0500 | [diff] [blame] | 424 | switch (pll_id) { |
| 425 | case ATOM_PPLL1: |
| 426 | args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL; |
Cédric Cano | 4589433 | 2011-02-11 19:45:37 -0500 | [diff] [blame] | 427 | args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); |
| 428 | args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); |
Alex Deucher | a572eaa | 2011-01-06 21:19:16 -0500 | [diff] [blame] | 429 | break; |
| 430 | case ATOM_PPLL2: |
| 431 | args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL; |
Cédric Cano | 4589433 | 2011-02-11 19:45:37 -0500 | [diff] [blame] | 432 | args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); |
| 433 | args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); |
Alex Deucher | a572eaa | 2011-01-06 21:19:16 -0500 | [diff] [blame] | 434 | break; |
| 435 | case ATOM_DCPLL: |
| 436 | args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL; |
Cédric Cano | 4589433 | 2011-02-11 19:45:37 -0500 | [diff] [blame] | 437 | args.v3.usSpreadSpectrumAmount = cpu_to_le16(0); |
| 438 | args.v3.usSpreadSpectrumStep = cpu_to_le16(0); |
Alex Deucher | a572eaa | 2011-01-06 21:19:16 -0500 | [diff] [blame] | 439 | break; |
| 440 | case ATOM_PPLL_INVALID: |
| 441 | return; |
| 442 | } |
| 443 | args.v2.ucEnable = enable; |
Alex Deucher | 8e8e523 | 2011-05-20 04:34:16 -0400 | [diff] [blame^] | 444 | if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK)) |
| 445 | args.v3.ucEnable = ATOM_DISABLE; |
Alex Deucher | a572eaa | 2011-01-06 21:19:16 -0500 | [diff] [blame] | 446 | } else if (ASIC_IS_DCE4(rdev)) { |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 447 | args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); |
Alex Deucher | 8e8e523 | 2011-05-20 04:34:16 -0400 | [diff] [blame^] | 448 | args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 449 | switch (pll_id) { |
| 450 | case ATOM_PPLL1: |
| 451 | args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL; |
Cédric Cano | 4589433 | 2011-02-11 19:45:37 -0500 | [diff] [blame] | 452 | args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); |
| 453 | args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step); |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 454 | break; |
| 455 | case ATOM_PPLL2: |
| 456 | args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL; |
Cédric Cano | 4589433 | 2011-02-11 19:45:37 -0500 | [diff] [blame] | 457 | args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); |
| 458 | args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step); |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 459 | break; |
| 460 | case ATOM_DCPLL: |
| 461 | args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL; |
Cédric Cano | 4589433 | 2011-02-11 19:45:37 -0500 | [diff] [blame] | 462 | args.v2.usSpreadSpectrumAmount = cpu_to_le16(0); |
| 463 | args.v2.usSpreadSpectrumStep = cpu_to_le16(0); |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 464 | break; |
| 465 | case ATOM_PPLL_INVALID: |
| 466 | return; |
| 467 | } |
| 468 | args.v2.ucEnable = enable; |
Alex Deucher | 8e8e523 | 2011-05-20 04:34:16 -0400 | [diff] [blame^] | 469 | if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK)) |
| 470 | args.v2.ucEnable = ATOM_DISABLE; |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 471 | } else if (ASIC_IS_DCE3(rdev)) { |
| 472 | args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); |
Alex Deucher | 8e8e523 | 2011-05-20 04:34:16 -0400 | [diff] [blame^] | 473 | args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 474 | args.v1.ucSpreadSpectrumStep = ss->step; |
| 475 | args.v1.ucSpreadSpectrumDelay = ss->delay; |
| 476 | args.v1.ucSpreadSpectrumRange = ss->range; |
| 477 | args.v1.ucPpll = pll_id; |
| 478 | args.v1.ucEnable = enable; |
| 479 | } else if (ASIC_IS_AVIVO(rdev)) { |
Alex Deucher | 8e8e523 | 2011-05-20 04:34:16 -0400 | [diff] [blame^] | 480 | if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || |
| 481 | (ss->type & ATOM_EXTERNAL_SS_MASK)) { |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 482 | atombios_disable_ss(crtc); |
| 483 | return; |
| 484 | } |
| 485 | args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); |
Alex Deucher | 8e8e523 | 2011-05-20 04:34:16 -0400 | [diff] [blame^] | 486 | args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 487 | args.lvds_ss_2.ucSpreadSpectrumStep = ss->step; |
| 488 | args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay; |
| 489 | args.lvds_ss_2.ucSpreadSpectrumRange = ss->range; |
| 490 | args.lvds_ss_2.ucEnable = enable; |
Alex Deucher | ebbe1cb | 2009-10-16 11:15:25 -0400 | [diff] [blame] | 491 | } else { |
Alex Deucher | 8e8e523 | 2011-05-20 04:34:16 -0400 | [diff] [blame^] | 492 | if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || |
| 493 | (ss->type & ATOM_EXTERNAL_SS_MASK)) { |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 494 | atombios_disable_ss(crtc); |
| 495 | return; |
| 496 | } |
| 497 | args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); |
Alex Deucher | 8e8e523 | 2011-05-20 04:34:16 -0400 | [diff] [blame^] | 498 | args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 499 | args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2; |
| 500 | args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4; |
| 501 | args.lvds_ss.ucEnable = enable; |
Alex Deucher | ebbe1cb | 2009-10-16 11:15:25 -0400 | [diff] [blame] | 502 | } |
Alex Deucher | 26b9fc3 | 2010-02-01 16:39:11 -0500 | [diff] [blame] | 503 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
Alex Deucher | ebbe1cb | 2009-10-16 11:15:25 -0400 | [diff] [blame] | 504 | } |
| 505 | |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 506 | union adjust_pixel_clock { |
| 507 | ADJUST_DISPLAY_PLL_PS_ALLOCATION v1; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 508 | ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3; |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 509 | }; |
| 510 | |
| 511 | static u32 atombios_adjust_pll(struct drm_crtc *crtc, |
| 512 | struct drm_display_mode *mode, |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 513 | struct radeon_pll *pll, |
| 514 | bool ss_enabled, |
| 515 | struct radeon_atom_ss *ss) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 516 | { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 517 | struct drm_device *dev = crtc->dev; |
| 518 | struct radeon_device *rdev = dev->dev_private; |
| 519 | struct drm_encoder *encoder = NULL; |
| 520 | struct radeon_encoder *radeon_encoder = NULL; |
Alex Deucher | df271be | 2011-05-20 04:34:15 -0400 | [diff] [blame] | 521 | struct drm_connector *connector = NULL; |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 522 | u32 adjusted_clock = mode->clock; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 523 | int encoder_mode = 0; |
Alex Deucher | fbee67a | 2010-08-16 12:44:47 -0400 | [diff] [blame] | 524 | u32 dp_clock = mode->clock; |
| 525 | int bpc = 8; |
Alex Deucher | fc10332 | 2010-01-19 17:16:10 -0500 | [diff] [blame] | 526 | |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 527 | /* reset the pll flags */ |
| 528 | pll->flags = 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 529 | |
| 530 | if (ASIC_IS_AVIVO(rdev)) { |
Alex Deucher | eb1300b | 2009-07-13 11:09:56 -0400 | [diff] [blame] | 531 | if ((rdev->family == CHIP_RS600) || |
| 532 | (rdev->family == CHIP_RS690) || |
| 533 | (rdev->family == CHIP_RS740)) |
Alex Deucher | 2ff776c | 2010-06-08 19:44:36 -0400 | [diff] [blame] | 534 | pll->flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/ |
Alex Deucher | fc10332 | 2010-01-19 17:16:10 -0500 | [diff] [blame] | 535 | RADEON_PLL_PREFER_CLOSEST_LOWER); |
Dave Airlie | 5480f72 | 2010-10-19 10:36:47 +1000 | [diff] [blame] | 536 | |
| 537 | if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */ |
| 538 | pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; |
| 539 | else |
| 540 | pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; |
Alex Deucher | 9bb09fa | 2011-04-07 10:31:25 -0400 | [diff] [blame] | 541 | |
Alex Deucher | 5785e53 | 2011-04-19 15:24:59 -0400 | [diff] [blame] | 542 | if (rdev->family < CHIP_RV770) |
Alex Deucher | 9bb09fa | 2011-04-07 10:31:25 -0400 | [diff] [blame] | 543 | pll->flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP; |
Dave Airlie | 5480f72 | 2010-10-19 10:36:47 +1000 | [diff] [blame] | 544 | } else { |
Alex Deucher | fc10332 | 2010-01-19 17:16:10 -0500 | [diff] [blame] | 545 | pll->flags |= RADEON_PLL_LEGACY; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 546 | |
Dave Airlie | 5480f72 | 2010-10-19 10:36:47 +1000 | [diff] [blame] | 547 | if (mode->clock > 200000) /* range limits??? */ |
| 548 | pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; |
| 549 | else |
| 550 | pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; |
Dave Airlie | 5480f72 | 2010-10-19 10:36:47 +1000 | [diff] [blame] | 551 | } |
| 552 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 553 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 554 | if (encoder->crtc == crtc) { |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 555 | radeon_encoder = to_radeon_encoder(encoder); |
Alex Deucher | df271be | 2011-05-20 04:34:15 -0400 | [diff] [blame] | 556 | connector = radeon_get_connector_for_encoder(encoder); |
| 557 | if (connector) |
| 558 | bpc = connector->display_info.bpc; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 559 | encoder_mode = atombios_get_encoder_mode(encoder); |
Alex Deucher | fbee67a | 2010-08-16 12:44:47 -0400 | [diff] [blame] | 560 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) { |
Alex Deucher | fbee67a | 2010-08-16 12:44:47 -0400 | [diff] [blame] | 561 | if (connector) { |
| 562 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
| 563 | struct radeon_connector_atom_dig *dig_connector = |
| 564 | radeon_connector->con_priv; |
| 565 | |
| 566 | dp_clock = dig_connector->dp_clock; |
| 567 | } |
| 568 | } |
Alex Deucher | 5b40ddf | 2011-02-14 11:43:11 -0500 | [diff] [blame] | 569 | |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 570 | /* use recommended ref_div for ss */ |
| 571 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
| 572 | if (ss_enabled) { |
| 573 | if (ss->refdiv) { |
| 574 | pll->flags |= RADEON_PLL_USE_REF_DIV; |
| 575 | pll->reference_div = ss->refdiv; |
Alex Deucher | 5b40ddf | 2011-02-14 11:43:11 -0500 | [diff] [blame] | 576 | if (ASIC_IS_AVIVO(rdev)) |
| 577 | pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV; |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 578 | } |
| 579 | } |
| 580 | } |
Alex Deucher | 5b40ddf | 2011-02-14 11:43:11 -0500 | [diff] [blame] | 581 | |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 582 | if (ASIC_IS_AVIVO(rdev)) { |
| 583 | /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ |
| 584 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) |
| 585 | adjusted_clock = mode->clock * 2; |
Alex Deucher | 48dfaae | 2010-09-29 11:37:41 -0400 | [diff] [blame] | 586 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
Alex Deucher | a1a4b23 | 2010-04-09 15:31:56 -0400 | [diff] [blame] | 587 | pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER; |
Alex Deucher | 5b40ddf | 2011-02-14 11:43:11 -0500 | [diff] [blame] | 588 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
| 589 | pll->flags |= RADEON_PLL_IS_LCD; |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 590 | } else { |
| 591 | if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) |
Alex Deucher | fc10332 | 2010-01-19 17:16:10 -0500 | [diff] [blame] | 592 | pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 593 | if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) |
Alex Deucher | fc10332 | 2010-01-19 17:16:10 -0500 | [diff] [blame] | 594 | pll->flags |= RADEON_PLL_USE_REF_DIV; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 595 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 596 | break; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 597 | } |
| 598 | } |
| 599 | |
Alex Deucher | 2606c88 | 2009-10-08 13:36:21 -0400 | [diff] [blame] | 600 | /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock |
| 601 | * accordingly based on the encoder/transmitter to work around |
| 602 | * special hw requirements. |
| 603 | */ |
| 604 | if (ASIC_IS_DCE3(rdev)) { |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 605 | union adjust_pixel_clock args; |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 606 | u8 frev, crev; |
| 607 | int index; |
Alex Deucher | 2606c88 | 2009-10-08 13:36:21 -0400 | [diff] [blame] | 608 | |
Alex Deucher | 2606c88 | 2009-10-08 13:36:21 -0400 | [diff] [blame] | 609 | index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll); |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 610 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, |
| 611 | &crev)) |
| 612 | return adjusted_clock; |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 613 | |
| 614 | memset(&args, 0, sizeof(args)); |
| 615 | |
| 616 | switch (frev) { |
| 617 | case 1: |
| 618 | switch (crev) { |
| 619 | case 1: |
| 620 | case 2: |
| 621 | args.v1.usPixelClock = cpu_to_le16(mode->clock / 10); |
| 622 | args.v1.ucTransmitterID = radeon_encoder->encoder_id; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 623 | args.v1.ucEncodeMode = encoder_mode; |
Alex Deucher | 8e8e523 | 2011-05-20 04:34:16 -0400 | [diff] [blame^] | 624 | if (ss_enabled && ss->percentage) |
Alex Deucher | fbee67a | 2010-08-16 12:44:47 -0400 | [diff] [blame] | 625 | args.v1.ucConfig |= |
| 626 | ADJUST_DISPLAY_CONFIG_SS_ENABLE; |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 627 | |
| 628 | atom_execute_table(rdev->mode_info.atom_context, |
| 629 | index, (uint32_t *)&args); |
| 630 | adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10; |
| 631 | break; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 632 | case 3: |
| 633 | args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10); |
| 634 | args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id; |
| 635 | args.v3.sInput.ucEncodeMode = encoder_mode; |
| 636 | args.v3.sInput.ucDispPllConfig = 0; |
Alex Deucher | 8e8e523 | 2011-05-20 04:34:16 -0400 | [diff] [blame^] | 637 | if (ss_enabled && ss->percentage) |
Alex Deucher | b526ce2 | 2011-01-20 23:35:58 +0000 | [diff] [blame] | 638 | args.v3.sInput.ucDispPllConfig |= |
| 639 | DISPPLL_CONFIG_SS_ENABLE; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 640 | if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
| 641 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
Alex Deucher | fbee67a | 2010-08-16 12:44:47 -0400 | [diff] [blame] | 642 | if (encoder_mode == ATOM_ENCODER_MODE_DP) { |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 643 | args.v3.sInput.ucDispPllConfig |= |
| 644 | DISPPLL_CONFIG_COHERENT_MODE; |
Alex Deucher | fbee67a | 2010-08-16 12:44:47 -0400 | [diff] [blame] | 645 | /* 16200 or 27000 */ |
| 646 | args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10); |
| 647 | } else { |
| 648 | if (encoder_mode == ATOM_ENCODER_MODE_HDMI) { |
| 649 | /* deep color support */ |
| 650 | args.v3.sInput.usPixelClock = |
| 651 | cpu_to_le16((mode->clock * bpc / 8) / 10); |
| 652 | } |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 653 | if (dig->coherent_mode) |
| 654 | args.v3.sInput.ucDispPllConfig |= |
| 655 | DISPPLL_CONFIG_COHERENT_MODE; |
| 656 | if (mode->clock > 165000) |
| 657 | args.v3.sInput.ucDispPllConfig |= |
| 658 | DISPPLL_CONFIG_DUAL_LINK; |
| 659 | } |
| 660 | } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
Alex Deucher | fbee67a | 2010-08-16 12:44:47 -0400 | [diff] [blame] | 661 | if (encoder_mode == ATOM_ENCODER_MODE_DP) { |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 662 | args.v3.sInput.ucDispPllConfig |= |
Alex Deucher | 9f998ad | 2010-03-29 21:37:08 -0400 | [diff] [blame] | 663 | DISPPLL_CONFIG_COHERENT_MODE; |
Alex Deucher | fbee67a | 2010-08-16 12:44:47 -0400 | [diff] [blame] | 664 | /* 16200 or 27000 */ |
| 665 | args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10); |
Alex Deucher | b526ce2 | 2011-01-20 23:35:58 +0000 | [diff] [blame] | 666 | } else if (encoder_mode != ATOM_ENCODER_MODE_LVDS) { |
Alex Deucher | 9f998ad | 2010-03-29 21:37:08 -0400 | [diff] [blame] | 667 | if (mode->clock > 165000) |
| 668 | args.v3.sInput.ucDispPllConfig |= |
| 669 | DISPPLL_CONFIG_DUAL_LINK; |
| 670 | } |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 671 | } |
| 672 | atom_execute_table(rdev->mode_info.atom_context, |
| 673 | index, (uint32_t *)&args); |
| 674 | adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10; |
| 675 | if (args.v3.sOutput.ucRefDiv) { |
Alex Deucher | 9f4283f | 2011-02-16 21:17:04 -0500 | [diff] [blame] | 676 | pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 677 | pll->flags |= RADEON_PLL_USE_REF_DIV; |
| 678 | pll->reference_div = args.v3.sOutput.ucRefDiv; |
| 679 | } |
| 680 | if (args.v3.sOutput.ucPostDiv) { |
Alex Deucher | 9f4283f | 2011-02-16 21:17:04 -0500 | [diff] [blame] | 681 | pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 682 | pll->flags |= RADEON_PLL_USE_POST_DIV; |
| 683 | pll->post_div = args.v3.sOutput.ucPostDiv; |
| 684 | } |
| 685 | break; |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 686 | default: |
| 687 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
| 688 | return adjusted_clock; |
| 689 | } |
| 690 | break; |
| 691 | default: |
| 692 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
| 693 | return adjusted_clock; |
| 694 | } |
Alex Deucher | d56ef9c | 2009-10-27 12:11:09 -0400 | [diff] [blame] | 695 | } |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 696 | return adjusted_clock; |
| 697 | } |
| 698 | |
| 699 | union set_pixel_clock { |
| 700 | SET_PIXEL_CLOCK_PS_ALLOCATION base; |
| 701 | PIXEL_CLOCK_PARAMETERS v1; |
| 702 | PIXEL_CLOCK_PARAMETERS_V2 v2; |
| 703 | PIXEL_CLOCK_PARAMETERS_V3 v3; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 704 | PIXEL_CLOCK_PARAMETERS_V5 v5; |
Alex Deucher | f82b3dd | 2011-01-06 21:19:15 -0500 | [diff] [blame] | 705 | PIXEL_CLOCK_PARAMETERS_V6 v6; |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 706 | }; |
| 707 | |
Alex Deucher | f82b3dd | 2011-01-06 21:19:15 -0500 | [diff] [blame] | 708 | /* on DCE5, make sure the voltage is high enough to support the |
| 709 | * required disp clk. |
| 710 | */ |
| 711 | static void atombios_crtc_set_dcpll(struct drm_crtc *crtc, |
| 712 | u32 dispclk) |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 713 | { |
| 714 | struct drm_device *dev = crtc->dev; |
| 715 | struct radeon_device *rdev = dev->dev_private; |
| 716 | u8 frev, crev; |
| 717 | int index; |
| 718 | union set_pixel_clock args; |
| 719 | |
| 720 | memset(&args, 0, sizeof(args)); |
| 721 | |
| 722 | index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 723 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, |
| 724 | &crev)) |
| 725 | return; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 726 | |
| 727 | switch (frev) { |
| 728 | case 1: |
| 729 | switch (crev) { |
| 730 | case 5: |
| 731 | /* if the default dcpll clock is specified, |
| 732 | * SetPixelClock provides the dividers |
| 733 | */ |
| 734 | args.v5.ucCRTC = ATOM_CRTC_INVALID; |
Cédric Cano | 4589433 | 2011-02-11 19:45:37 -0500 | [diff] [blame] | 735 | args.v5.usPixelClock = cpu_to_le16(dispclk); |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 736 | args.v5.ucPpll = ATOM_DCPLL; |
| 737 | break; |
Alex Deucher | f82b3dd | 2011-01-06 21:19:15 -0500 | [diff] [blame] | 738 | case 6: |
| 739 | /* if the default dcpll clock is specified, |
| 740 | * SetPixelClock provides the dividers |
| 741 | */ |
Alex Deucher | 265aa6c | 2011-02-14 16:16:22 -0500 | [diff] [blame] | 742 | args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk); |
Alex Deucher | f82b3dd | 2011-01-06 21:19:15 -0500 | [diff] [blame] | 743 | args.v6.ucPpll = ATOM_DCPLL; |
| 744 | break; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 745 | default: |
| 746 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
| 747 | return; |
| 748 | } |
| 749 | break; |
| 750 | default: |
| 751 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
| 752 | return; |
| 753 | } |
| 754 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 755 | } |
| 756 | |
Alex Deucher | 37f9003 | 2010-06-11 17:58:38 -0400 | [diff] [blame] | 757 | static void atombios_crtc_program_pll(struct drm_crtc *crtc, |
| 758 | int crtc_id, |
| 759 | int pll_id, |
| 760 | u32 encoder_mode, |
| 761 | u32 encoder_id, |
| 762 | u32 clock, |
| 763 | u32 ref_div, |
| 764 | u32 fb_div, |
| 765 | u32 frac_fb_div, |
Alex Deucher | df271be | 2011-05-20 04:34:15 -0400 | [diff] [blame] | 766 | u32 post_div, |
Alex Deucher | 8e8e523 | 2011-05-20 04:34:16 -0400 | [diff] [blame^] | 767 | int bpc, |
| 768 | bool ss_enabled, |
| 769 | struct radeon_atom_ss *ss) |
Alex Deucher | 37f9003 | 2010-06-11 17:58:38 -0400 | [diff] [blame] | 770 | { |
| 771 | struct drm_device *dev = crtc->dev; |
| 772 | struct radeon_device *rdev = dev->dev_private; |
| 773 | u8 frev, crev; |
| 774 | int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); |
| 775 | union set_pixel_clock args; |
| 776 | |
| 777 | memset(&args, 0, sizeof(args)); |
| 778 | |
| 779 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, |
| 780 | &crev)) |
| 781 | return; |
| 782 | |
| 783 | switch (frev) { |
| 784 | case 1: |
| 785 | switch (crev) { |
| 786 | case 1: |
| 787 | if (clock == ATOM_DISABLE) |
| 788 | return; |
| 789 | args.v1.usPixelClock = cpu_to_le16(clock / 10); |
| 790 | args.v1.usRefDiv = cpu_to_le16(ref_div); |
| 791 | args.v1.usFbDiv = cpu_to_le16(fb_div); |
| 792 | args.v1.ucFracFbDiv = frac_fb_div; |
| 793 | args.v1.ucPostDiv = post_div; |
| 794 | args.v1.ucPpll = pll_id; |
| 795 | args.v1.ucCRTC = crtc_id; |
| 796 | args.v1.ucRefDivSrc = 1; |
| 797 | break; |
| 798 | case 2: |
| 799 | args.v2.usPixelClock = cpu_to_le16(clock / 10); |
| 800 | args.v2.usRefDiv = cpu_to_le16(ref_div); |
| 801 | args.v2.usFbDiv = cpu_to_le16(fb_div); |
| 802 | args.v2.ucFracFbDiv = frac_fb_div; |
| 803 | args.v2.ucPostDiv = post_div; |
| 804 | args.v2.ucPpll = pll_id; |
| 805 | args.v2.ucCRTC = crtc_id; |
| 806 | args.v2.ucRefDivSrc = 1; |
| 807 | break; |
| 808 | case 3: |
| 809 | args.v3.usPixelClock = cpu_to_le16(clock / 10); |
| 810 | args.v3.usRefDiv = cpu_to_le16(ref_div); |
| 811 | args.v3.usFbDiv = cpu_to_le16(fb_div); |
| 812 | args.v3.ucFracFbDiv = frac_fb_div; |
| 813 | args.v3.ucPostDiv = post_div; |
| 814 | args.v3.ucPpll = pll_id; |
| 815 | args.v3.ucMiscInfo = (pll_id << 2); |
| 816 | args.v3.ucTransmitterId = encoder_id; |
| 817 | args.v3.ucEncoderMode = encoder_mode; |
| 818 | break; |
| 819 | case 5: |
| 820 | args.v5.ucCRTC = crtc_id; |
| 821 | args.v5.usPixelClock = cpu_to_le16(clock / 10); |
| 822 | args.v5.ucRefDiv = ref_div; |
| 823 | args.v5.usFbDiv = cpu_to_le16(fb_div); |
| 824 | args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); |
| 825 | args.v5.ucPostDiv = post_div; |
| 826 | args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */ |
Alex Deucher | 8e8e523 | 2011-05-20 04:34:16 -0400 | [diff] [blame^] | 827 | if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) |
| 828 | args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC; |
Alex Deucher | df271be | 2011-05-20 04:34:15 -0400 | [diff] [blame] | 829 | switch (bpc) { |
| 830 | case 8: |
| 831 | default: |
| 832 | args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP; |
| 833 | break; |
| 834 | case 10: |
| 835 | args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP; |
| 836 | break; |
| 837 | } |
Alex Deucher | 37f9003 | 2010-06-11 17:58:38 -0400 | [diff] [blame] | 838 | args.v5.ucTransmitterID = encoder_id; |
| 839 | args.v5.ucEncoderMode = encoder_mode; |
| 840 | args.v5.ucPpll = pll_id; |
| 841 | break; |
Alex Deucher | f82b3dd | 2011-01-06 21:19:15 -0500 | [diff] [blame] | 842 | case 6: |
| 843 | args.v6.ulCrtcPclkFreq.ucCRTC = crtc_id; |
| 844 | args.v6.ulCrtcPclkFreq.ulPixelClock = cpu_to_le32(clock / 10); |
| 845 | args.v6.ucRefDiv = ref_div; |
| 846 | args.v6.usFbDiv = cpu_to_le16(fb_div); |
| 847 | args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); |
| 848 | args.v6.ucPostDiv = post_div; |
| 849 | args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */ |
Alex Deucher | 8e8e523 | 2011-05-20 04:34:16 -0400 | [diff] [blame^] | 850 | if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) |
| 851 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC; |
Alex Deucher | df271be | 2011-05-20 04:34:15 -0400 | [diff] [blame] | 852 | switch (bpc) { |
| 853 | case 8: |
| 854 | default: |
| 855 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP; |
| 856 | break; |
| 857 | case 10: |
| 858 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP; |
| 859 | break; |
| 860 | case 12: |
| 861 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP; |
| 862 | break; |
| 863 | case 16: |
| 864 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP; |
| 865 | break; |
| 866 | } |
Alex Deucher | f82b3dd | 2011-01-06 21:19:15 -0500 | [diff] [blame] | 867 | args.v6.ucTransmitterID = encoder_id; |
| 868 | args.v6.ucEncoderMode = encoder_mode; |
| 869 | args.v6.ucPpll = pll_id; |
| 870 | break; |
Alex Deucher | 37f9003 | 2010-06-11 17:58:38 -0400 | [diff] [blame] | 871 | default: |
| 872 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
| 873 | return; |
| 874 | } |
| 875 | break; |
| 876 | default: |
| 877 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
| 878 | return; |
| 879 | } |
| 880 | |
| 881 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 882 | } |
| 883 | |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 884 | static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 885 | { |
| 886 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 887 | struct drm_device *dev = crtc->dev; |
| 888 | struct radeon_device *rdev = dev->dev_private; |
| 889 | struct drm_encoder *encoder = NULL; |
| 890 | struct radeon_encoder *radeon_encoder = NULL; |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 891 | u32 pll_clock = mode->clock; |
| 892 | u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; |
| 893 | struct radeon_pll *pll; |
| 894 | u32 adjusted_clock; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 895 | int encoder_mode = 0; |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 896 | struct radeon_atom_ss ss; |
| 897 | bool ss_enabled = false; |
Alex Deucher | df271be | 2011-05-20 04:34:15 -0400 | [diff] [blame] | 898 | int bpc = 8; |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 899 | |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 900 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 901 | if (encoder->crtc == crtc) { |
| 902 | radeon_encoder = to_radeon_encoder(encoder); |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 903 | encoder_mode = atombios_get_encoder_mode(encoder); |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 904 | break; |
| 905 | } |
| 906 | } |
| 907 | |
| 908 | if (!radeon_encoder) |
| 909 | return; |
| 910 | |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 911 | switch (radeon_crtc->pll_id) { |
| 912 | case ATOM_PPLL1: |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 913 | pll = &rdev->clock.p1pll; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 914 | break; |
| 915 | case ATOM_PPLL2: |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 916 | pll = &rdev->clock.p2pll; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 917 | break; |
| 918 | case ATOM_DCPLL: |
| 919 | case ATOM_PPLL_INVALID: |
Stefan Richter | 921d98b | 2010-05-26 10:27:44 +1000 | [diff] [blame] | 920 | default: |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 921 | pll = &rdev->clock.dcpll; |
| 922 | break; |
| 923 | } |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 924 | |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 925 | if (radeon_encoder->active_device & |
| 926 | (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) { |
| 927 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| 928 | struct drm_connector *connector = |
| 929 | radeon_get_connector_for_encoder(encoder); |
| 930 | struct radeon_connector *radeon_connector = |
| 931 | to_radeon_connector(connector); |
| 932 | struct radeon_connector_atom_dig *dig_connector = |
| 933 | radeon_connector->con_priv; |
| 934 | int dp_clock; |
Alex Deucher | df271be | 2011-05-20 04:34:15 -0400 | [diff] [blame] | 935 | bpc = connector->display_info.bpc; |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 936 | |
| 937 | switch (encoder_mode) { |
| 938 | case ATOM_ENCODER_MODE_DP: |
| 939 | /* DP/eDP */ |
| 940 | dp_clock = dig_connector->dp_clock / 10; |
| 941 | if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) { |
Alex Deucher | 8e8e523 | 2011-05-20 04:34:16 -0400 | [diff] [blame^] | 942 | if (ASIC_IS_DCE4(rdev)) { |
| 943 | /* first try ASIC_INTERNAL_SS_ON_DP */ |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 944 | ss_enabled = |
| 945 | radeon_atombios_get_asic_ss_info(rdev, &ss, |
Alex Deucher | 8e8e523 | 2011-05-20 04:34:16 -0400 | [diff] [blame^] | 946 | ASIC_INTERNAL_SS_ON_DP, |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 947 | dp_clock); |
Alex Deucher | 8e8e523 | 2011-05-20 04:34:16 -0400 | [diff] [blame^] | 948 | if (!ss_enabled) |
| 949 | ss_enabled = |
| 950 | radeon_atombios_get_asic_ss_info(rdev, &ss, |
| 951 | dig->lcd_ss_id, |
| 952 | dp_clock); |
| 953 | } else |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 954 | ss_enabled = |
| 955 | radeon_atombios_get_ppll_ss_info(rdev, &ss, |
| 956 | dig->lcd_ss_id); |
| 957 | } else { |
| 958 | if (ASIC_IS_DCE4(rdev)) |
| 959 | ss_enabled = |
| 960 | radeon_atombios_get_asic_ss_info(rdev, &ss, |
| 961 | ASIC_INTERNAL_SS_ON_DP, |
| 962 | dp_clock); |
| 963 | else { |
| 964 | if (dp_clock == 16200) { |
| 965 | ss_enabled = |
| 966 | radeon_atombios_get_ppll_ss_info(rdev, &ss, |
| 967 | ATOM_DP_SS_ID2); |
| 968 | if (!ss_enabled) |
| 969 | ss_enabled = |
| 970 | radeon_atombios_get_ppll_ss_info(rdev, &ss, |
| 971 | ATOM_DP_SS_ID1); |
| 972 | } else |
| 973 | ss_enabled = |
| 974 | radeon_atombios_get_ppll_ss_info(rdev, &ss, |
| 975 | ATOM_DP_SS_ID1); |
| 976 | } |
| 977 | } |
| 978 | break; |
| 979 | case ATOM_ENCODER_MODE_LVDS: |
| 980 | if (ASIC_IS_DCE4(rdev)) |
| 981 | ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss, |
| 982 | dig->lcd_ss_id, |
| 983 | mode->clock / 10); |
| 984 | else |
| 985 | ss_enabled = radeon_atombios_get_ppll_ss_info(rdev, &ss, |
| 986 | dig->lcd_ss_id); |
| 987 | break; |
| 988 | case ATOM_ENCODER_MODE_DVI: |
| 989 | if (ASIC_IS_DCE4(rdev)) |
| 990 | ss_enabled = |
| 991 | radeon_atombios_get_asic_ss_info(rdev, &ss, |
| 992 | ASIC_INTERNAL_SS_ON_TMDS, |
| 993 | mode->clock / 10); |
| 994 | break; |
| 995 | case ATOM_ENCODER_MODE_HDMI: |
| 996 | if (ASIC_IS_DCE4(rdev)) |
| 997 | ss_enabled = |
| 998 | radeon_atombios_get_asic_ss_info(rdev, &ss, |
| 999 | ASIC_INTERNAL_SS_ON_HDMI, |
| 1000 | mode->clock / 10); |
| 1001 | break; |
| 1002 | default: |
| 1003 | break; |
| 1004 | } |
| 1005 | } |
| 1006 | |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 1007 | /* adjust pixel clock as needed */ |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 1008 | adjusted_clock = atombios_adjust_pll(crtc, mode, pll, ss_enabled, &ss); |
Alex Deucher | 2606c88 | 2009-10-08 13:36:21 -0400 | [diff] [blame] | 1009 | |
Alex Deucher | 64146f8 | 2011-03-22 01:46:12 -0400 | [diff] [blame] | 1010 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
| 1011 | /* TV seems to prefer the legacy algo on some boards */ |
| 1012 | radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div, |
| 1013 | &ref_div, &post_div); |
| 1014 | else if (ASIC_IS_AVIVO(rdev)) |
Alex Deucher | 619efb1 | 2011-01-31 16:48:53 -0500 | [diff] [blame] | 1015 | radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div, |
| 1016 | &ref_div, &post_div); |
| 1017 | else |
| 1018 | radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div, |
| 1019 | &ref_div, &post_div); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1020 | |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 1021 | atombios_crtc_program_ss(crtc, ATOM_DISABLE, radeon_crtc->pll_id, &ss); |
| 1022 | |
Alex Deucher | 37f9003 | 2010-06-11 17:58:38 -0400 | [diff] [blame] | 1023 | atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, |
| 1024 | encoder_mode, radeon_encoder->encoder_id, mode->clock, |
Alex Deucher | 8e8e523 | 2011-05-20 04:34:16 -0400 | [diff] [blame^] | 1025 | ref_div, fb_div, frac_fb_div, post_div, bpc, ss_enabled, &ss); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1026 | |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 1027 | if (ss_enabled) { |
| 1028 | /* calculate ss amount and step size */ |
| 1029 | if (ASIC_IS_DCE4(rdev)) { |
| 1030 | u32 step_size; |
| 1031 | u32 amount = (((fb_div * 10) + frac_fb_div) * ss.percentage) / 10000; |
| 1032 | ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK; |
Alex Deucher | 8e8e523 | 2011-05-20 04:34:16 -0400 | [diff] [blame^] | 1033 | ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) & |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 1034 | ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK; |
| 1035 | if (ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD) |
| 1036 | step_size = (4 * amount * ref_div * (ss.rate * 2048)) / |
| 1037 | (125 * 25 * pll->reference_freq / 100); |
| 1038 | else |
| 1039 | step_size = (2 * amount * ref_div * (ss.rate * 2048)) / |
| 1040 | (125 * 25 * pll->reference_freq / 100); |
| 1041 | ss.step = step_size; |
| 1042 | } |
| 1043 | |
| 1044 | atombios_crtc_program_ss(crtc, ATOM_ENABLE, radeon_crtc->pll_id, &ss); |
| 1045 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1046 | } |
| 1047 | |
Alex Deucher | c9417bd | 2011-02-06 14:23:26 -0500 | [diff] [blame] | 1048 | static int dce4_crtc_do_set_base(struct drm_crtc *crtc, |
| 1049 | struct drm_framebuffer *fb, |
| 1050 | int x, int y, int atomic) |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1051 | { |
| 1052 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 1053 | struct drm_device *dev = crtc->dev; |
| 1054 | struct radeon_device *rdev = dev->dev_private; |
| 1055 | struct radeon_framebuffer *radeon_fb; |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1056 | struct drm_framebuffer *target_fb; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1057 | struct drm_gem_object *obj; |
| 1058 | struct radeon_bo *rbo; |
| 1059 | uint64_t fb_location; |
| 1060 | uint32_t fb_format, fb_pitch_pixels, tiling_flags; |
Alex Deucher | fa6bee4 | 2011-01-25 11:55:50 -0500 | [diff] [blame] | 1061 | u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE); |
Alex Deucher | fb9674b | 2011-04-02 09:15:50 -0400 | [diff] [blame] | 1062 | u32 tmp; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1063 | int r; |
| 1064 | |
| 1065 | /* no fb bound */ |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1066 | if (!atomic && !crtc->fb) { |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 1067 | DRM_DEBUG_KMS("No FB bound\n"); |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1068 | return 0; |
| 1069 | } |
| 1070 | |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1071 | if (atomic) { |
| 1072 | radeon_fb = to_radeon_framebuffer(fb); |
| 1073 | target_fb = fb; |
| 1074 | } |
| 1075 | else { |
| 1076 | radeon_fb = to_radeon_framebuffer(crtc->fb); |
| 1077 | target_fb = crtc->fb; |
| 1078 | } |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1079 | |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1080 | /* If atomic, assume fb object is pinned & idle & fenced and |
| 1081 | * just update base pointers |
| 1082 | */ |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1083 | obj = radeon_fb->obj; |
Daniel Vetter | 7e4d15d | 2011-02-18 17:59:17 +0100 | [diff] [blame] | 1084 | rbo = gem_to_radeon_bo(obj); |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1085 | r = radeon_bo_reserve(rbo, false); |
| 1086 | if (unlikely(r != 0)) |
| 1087 | return r; |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1088 | |
| 1089 | if (atomic) |
| 1090 | fb_location = radeon_bo_gpu_offset(rbo); |
| 1091 | else { |
| 1092 | r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); |
| 1093 | if (unlikely(r != 0)) { |
| 1094 | radeon_bo_unreserve(rbo); |
| 1095 | return -EINVAL; |
| 1096 | } |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1097 | } |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1098 | |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1099 | radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); |
| 1100 | radeon_bo_unreserve(rbo); |
| 1101 | |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1102 | switch (target_fb->bits_per_pixel) { |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1103 | case 8: |
| 1104 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) | |
| 1105 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED)); |
| 1106 | break; |
| 1107 | case 15: |
| 1108 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | |
| 1109 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555)); |
| 1110 | break; |
| 1111 | case 16: |
| 1112 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | |
| 1113 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565)); |
Alex Deucher | fa6bee4 | 2011-01-25 11:55:50 -0500 | [diff] [blame] | 1114 | #ifdef __BIG_ENDIAN |
| 1115 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); |
| 1116 | #endif |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1117 | break; |
| 1118 | case 24: |
| 1119 | case 32: |
| 1120 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | |
| 1121 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); |
Alex Deucher | fa6bee4 | 2011-01-25 11:55:50 -0500 | [diff] [blame] | 1122 | #ifdef __BIG_ENDIAN |
| 1123 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); |
| 1124 | #endif |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1125 | break; |
| 1126 | default: |
| 1127 | DRM_ERROR("Unsupported screen depth %d\n", |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1128 | target_fb->bits_per_pixel); |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1129 | return -EINVAL; |
| 1130 | } |
| 1131 | |
Alex Deucher | 97d6632 | 2010-05-20 12:12:48 -0400 | [diff] [blame] | 1132 | if (tiling_flags & RADEON_TILING_MACRO) |
| 1133 | fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1); |
| 1134 | else if (tiling_flags & RADEON_TILING_MICRO) |
| 1135 | fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1); |
| 1136 | |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1137 | switch (radeon_crtc->crtc_id) { |
| 1138 | case 0: |
| 1139 | WREG32(AVIVO_D1VGA_CONTROL, 0); |
| 1140 | break; |
| 1141 | case 1: |
| 1142 | WREG32(AVIVO_D2VGA_CONTROL, 0); |
| 1143 | break; |
| 1144 | case 2: |
| 1145 | WREG32(EVERGREEN_D3VGA_CONTROL, 0); |
| 1146 | break; |
| 1147 | case 3: |
| 1148 | WREG32(EVERGREEN_D4VGA_CONTROL, 0); |
| 1149 | break; |
| 1150 | case 4: |
| 1151 | WREG32(EVERGREEN_D5VGA_CONTROL, 0); |
| 1152 | break; |
| 1153 | case 5: |
| 1154 | WREG32(EVERGREEN_D6VGA_CONTROL, 0); |
| 1155 | break; |
| 1156 | default: |
| 1157 | break; |
| 1158 | } |
| 1159 | |
| 1160 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, |
| 1161 | upper_32_bits(fb_location)); |
| 1162 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, |
| 1163 | upper_32_bits(fb_location)); |
| 1164 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
| 1165 | (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); |
| 1166 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
| 1167 | (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); |
| 1168 | WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); |
Alex Deucher | fa6bee4 | 2011-01-25 11:55:50 -0500 | [diff] [blame] | 1169 | WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1170 | |
| 1171 | WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); |
| 1172 | WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); |
| 1173 | WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0); |
| 1174 | WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0); |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1175 | WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); |
| 1176 | WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1177 | |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1178 | fb_pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8); |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1179 | WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); |
| 1180 | WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1); |
| 1181 | |
| 1182 | WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, |
| 1183 | crtc->mode.vdisplay); |
| 1184 | x &= ~3; |
| 1185 | y &= ~1; |
| 1186 | WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, |
| 1187 | (x << 16) | y); |
| 1188 | WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, |
| 1189 | (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay); |
| 1190 | |
Alex Deucher | fb9674b | 2011-04-02 09:15:50 -0400 | [diff] [blame] | 1191 | /* pageflip setup */ |
| 1192 | /* make sure flip is at vb rather than hb */ |
| 1193 | tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); |
| 1194 | tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN; |
| 1195 | WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); |
| 1196 | |
| 1197 | /* set pageflip to happen anywhere in vblank interval */ |
| 1198 | WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0); |
| 1199 | |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1200 | if (!atomic && fb && fb != crtc->fb) { |
| 1201 | radeon_fb = to_radeon_framebuffer(fb); |
Daniel Vetter | 7e4d15d | 2011-02-18 17:59:17 +0100 | [diff] [blame] | 1202 | rbo = gem_to_radeon_bo(radeon_fb->obj); |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1203 | r = radeon_bo_reserve(rbo, false); |
| 1204 | if (unlikely(r != 0)) |
| 1205 | return r; |
| 1206 | radeon_bo_unpin(rbo); |
| 1207 | radeon_bo_unreserve(rbo); |
| 1208 | } |
| 1209 | |
| 1210 | /* Bytes per pixel may have changed */ |
| 1211 | radeon_bandwidth_update(rdev); |
| 1212 | |
| 1213 | return 0; |
| 1214 | } |
| 1215 | |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1216 | static int avivo_crtc_do_set_base(struct drm_crtc *crtc, |
| 1217 | struct drm_framebuffer *fb, |
| 1218 | int x, int y, int atomic) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1219 | { |
| 1220 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 1221 | struct drm_device *dev = crtc->dev; |
| 1222 | struct radeon_device *rdev = dev->dev_private; |
| 1223 | struct radeon_framebuffer *radeon_fb; |
| 1224 | struct drm_gem_object *obj; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1225 | struct radeon_bo *rbo; |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1226 | struct drm_framebuffer *target_fb; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1227 | uint64_t fb_location; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 1228 | uint32_t fb_format, fb_pitch_pixels, tiling_flags; |
Alex Deucher | fa6bee4 | 2011-01-25 11:55:50 -0500 | [diff] [blame] | 1229 | u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE; |
Alex Deucher | fb9674b | 2011-04-02 09:15:50 -0400 | [diff] [blame] | 1230 | u32 tmp; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1231 | int r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1232 | |
Jerome Glisse | 2de3b48 | 2009-11-17 14:08:55 -0800 | [diff] [blame] | 1233 | /* no fb bound */ |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1234 | if (!atomic && !crtc->fb) { |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 1235 | DRM_DEBUG_KMS("No FB bound\n"); |
Jerome Glisse | 2de3b48 | 2009-11-17 14:08:55 -0800 | [diff] [blame] | 1236 | return 0; |
| 1237 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1238 | |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1239 | if (atomic) { |
| 1240 | radeon_fb = to_radeon_framebuffer(fb); |
| 1241 | target_fb = fb; |
| 1242 | } |
| 1243 | else { |
| 1244 | radeon_fb = to_radeon_framebuffer(crtc->fb); |
| 1245 | target_fb = crtc->fb; |
| 1246 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1247 | |
| 1248 | obj = radeon_fb->obj; |
Daniel Vetter | 7e4d15d | 2011-02-18 17:59:17 +0100 | [diff] [blame] | 1249 | rbo = gem_to_radeon_bo(obj); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1250 | r = radeon_bo_reserve(rbo, false); |
| 1251 | if (unlikely(r != 0)) |
| 1252 | return r; |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1253 | |
| 1254 | /* If atomic, assume fb object is pinned & idle & fenced and |
| 1255 | * just update base pointers |
| 1256 | */ |
| 1257 | if (atomic) |
| 1258 | fb_location = radeon_bo_gpu_offset(rbo); |
| 1259 | else { |
| 1260 | r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); |
| 1261 | if (unlikely(r != 0)) { |
| 1262 | radeon_bo_unreserve(rbo); |
| 1263 | return -EINVAL; |
| 1264 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1265 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1266 | radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); |
| 1267 | radeon_bo_unreserve(rbo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1268 | |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1269 | switch (target_fb->bits_per_pixel) { |
Dave Airlie | 41456df | 2009-09-16 10:15:21 +1000 | [diff] [blame] | 1270 | case 8: |
| 1271 | fb_format = |
| 1272 | AVIVO_D1GRPH_CONTROL_DEPTH_8BPP | |
| 1273 | AVIVO_D1GRPH_CONTROL_8BPP_INDEXED; |
| 1274 | break; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1275 | case 15: |
| 1276 | fb_format = |
| 1277 | AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | |
| 1278 | AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; |
| 1279 | break; |
| 1280 | case 16: |
| 1281 | fb_format = |
| 1282 | AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | |
| 1283 | AVIVO_D1GRPH_CONTROL_16BPP_RGB565; |
Alex Deucher | fa6bee4 | 2011-01-25 11:55:50 -0500 | [diff] [blame] | 1284 | #ifdef __BIG_ENDIAN |
| 1285 | fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; |
| 1286 | #endif |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1287 | break; |
| 1288 | case 24: |
| 1289 | case 32: |
| 1290 | fb_format = |
| 1291 | AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | |
| 1292 | AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; |
Alex Deucher | fa6bee4 | 2011-01-25 11:55:50 -0500 | [diff] [blame] | 1293 | #ifdef __BIG_ENDIAN |
| 1294 | fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT; |
| 1295 | #endif |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1296 | break; |
| 1297 | default: |
| 1298 | DRM_ERROR("Unsupported screen depth %d\n", |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1299 | target_fb->bits_per_pixel); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1300 | return -EINVAL; |
| 1301 | } |
| 1302 | |
Alex Deucher | 40c4ac1 | 2010-05-20 12:04:59 -0400 | [diff] [blame] | 1303 | if (rdev->family >= CHIP_R600) { |
| 1304 | if (tiling_flags & RADEON_TILING_MACRO) |
| 1305 | fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1; |
| 1306 | else if (tiling_flags & RADEON_TILING_MICRO) |
| 1307 | fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1; |
| 1308 | } else { |
| 1309 | if (tiling_flags & RADEON_TILING_MACRO) |
| 1310 | fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE; |
Dave Airlie | cf2f05d | 2009-12-08 15:45:13 +1000 | [diff] [blame] | 1311 | |
Alex Deucher | 40c4ac1 | 2010-05-20 12:04:59 -0400 | [diff] [blame] | 1312 | if (tiling_flags & RADEON_TILING_MICRO) |
| 1313 | fb_format |= AVIVO_D1GRPH_TILED; |
| 1314 | } |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 1315 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1316 | if (radeon_crtc->crtc_id == 0) |
| 1317 | WREG32(AVIVO_D1VGA_CONTROL, 0); |
| 1318 | else |
| 1319 | WREG32(AVIVO_D2VGA_CONTROL, 0); |
Alex Deucher | c290dad | 2009-10-22 16:12:34 -0400 | [diff] [blame] | 1320 | |
| 1321 | if (rdev->family >= CHIP_RV770) { |
| 1322 | if (radeon_crtc->crtc_id) { |
Alex Deucher | 9534787 | 2010-09-01 17:20:42 -0400 | [diff] [blame] | 1323 | WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); |
| 1324 | WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); |
Alex Deucher | c290dad | 2009-10-22 16:12:34 -0400 | [diff] [blame] | 1325 | } else { |
Alex Deucher | 9534787 | 2010-09-01 17:20:42 -0400 | [diff] [blame] | 1326 | WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); |
| 1327 | WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); |
Alex Deucher | c290dad | 2009-10-22 16:12:34 -0400 | [diff] [blame] | 1328 | } |
| 1329 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1330 | WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
| 1331 | (u32) fb_location); |
| 1332 | WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + |
| 1333 | radeon_crtc->crtc_offset, (u32) fb_location); |
| 1334 | WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); |
Alex Deucher | fa6bee4 | 2011-01-25 11:55:50 -0500 | [diff] [blame] | 1335 | if (rdev->family >= CHIP_R600) |
| 1336 | WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1337 | |
| 1338 | WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); |
| 1339 | WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); |
| 1340 | WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); |
| 1341 | WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1342 | WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); |
| 1343 | WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1344 | |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1345 | fb_pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1346 | WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); |
| 1347 | WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); |
| 1348 | |
| 1349 | WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, |
| 1350 | crtc->mode.vdisplay); |
| 1351 | x &= ~3; |
| 1352 | y &= ~1; |
| 1353 | WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, |
| 1354 | (x << 16) | y); |
| 1355 | WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, |
| 1356 | (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay); |
| 1357 | |
Alex Deucher | fb9674b | 2011-04-02 09:15:50 -0400 | [diff] [blame] | 1358 | /* pageflip setup */ |
| 1359 | /* make sure flip is at vb rather than hb */ |
| 1360 | tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); |
| 1361 | tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN; |
| 1362 | WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); |
| 1363 | |
| 1364 | /* set pageflip to happen anywhere in vblank interval */ |
| 1365 | WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0); |
| 1366 | |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1367 | if (!atomic && fb && fb != crtc->fb) { |
| 1368 | radeon_fb = to_radeon_framebuffer(fb); |
Daniel Vetter | 7e4d15d | 2011-02-18 17:59:17 +0100 | [diff] [blame] | 1369 | rbo = gem_to_radeon_bo(radeon_fb->obj); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1370 | r = radeon_bo_reserve(rbo, false); |
| 1371 | if (unlikely(r != 0)) |
| 1372 | return r; |
| 1373 | radeon_bo_unpin(rbo); |
| 1374 | radeon_bo_unreserve(rbo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1375 | } |
Michel Dänzer | f30f37d | 2009-10-08 10:44:09 +0200 | [diff] [blame] | 1376 | |
| 1377 | /* Bytes per pixel may have changed */ |
| 1378 | radeon_bandwidth_update(rdev); |
| 1379 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1380 | return 0; |
| 1381 | } |
| 1382 | |
Alex Deucher | 54f088a | 2010-01-19 16:34:01 -0500 | [diff] [blame] | 1383 | int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
| 1384 | struct drm_framebuffer *old_fb) |
| 1385 | { |
| 1386 | struct drm_device *dev = crtc->dev; |
| 1387 | struct radeon_device *rdev = dev->dev_private; |
| 1388 | |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1389 | if (ASIC_IS_DCE4(rdev)) |
Alex Deucher | c9417bd | 2011-02-06 14:23:26 -0500 | [diff] [blame] | 1390 | return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0); |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1391 | else if (ASIC_IS_AVIVO(rdev)) |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1392 | return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0); |
Alex Deucher | 54f088a | 2010-01-19 16:34:01 -0500 | [diff] [blame] | 1393 | else |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1394 | return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0); |
| 1395 | } |
| 1396 | |
| 1397 | int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, |
| 1398 | struct drm_framebuffer *fb, |
Jason Wessel | 21c74a8 | 2010-10-13 14:09:44 -0500 | [diff] [blame] | 1399 | int x, int y, enum mode_set_atomic state) |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1400 | { |
| 1401 | struct drm_device *dev = crtc->dev; |
| 1402 | struct radeon_device *rdev = dev->dev_private; |
| 1403 | |
| 1404 | if (ASIC_IS_DCE4(rdev)) |
Alex Deucher | c9417bd | 2011-02-06 14:23:26 -0500 | [diff] [blame] | 1405 | return dce4_crtc_do_set_base(crtc, fb, x, y, 1); |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1406 | else if (ASIC_IS_AVIVO(rdev)) |
| 1407 | return avivo_crtc_do_set_base(crtc, fb, x, y, 1); |
| 1408 | else |
| 1409 | return radeon_crtc_do_set_base(crtc, fb, x, y, 1); |
Alex Deucher | 54f088a | 2010-01-19 16:34:01 -0500 | [diff] [blame] | 1410 | } |
| 1411 | |
Alex Deucher | 615e0cb | 2010-01-20 16:22:53 -0500 | [diff] [blame] | 1412 | /* properly set additional regs when using atombios */ |
| 1413 | static void radeon_legacy_atom_fixup(struct drm_crtc *crtc) |
| 1414 | { |
| 1415 | struct drm_device *dev = crtc->dev; |
| 1416 | struct radeon_device *rdev = dev->dev_private; |
| 1417 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 1418 | u32 disp_merge_cntl; |
| 1419 | |
| 1420 | switch (radeon_crtc->crtc_id) { |
| 1421 | case 0: |
| 1422 | disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); |
| 1423 | disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; |
| 1424 | WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); |
| 1425 | break; |
| 1426 | case 1: |
| 1427 | disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); |
| 1428 | disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; |
| 1429 | WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl); |
| 1430 | WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID)); |
| 1431 | WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID)); |
| 1432 | break; |
| 1433 | } |
| 1434 | } |
| 1435 | |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1436 | static int radeon_atom_pick_pll(struct drm_crtc *crtc) |
| 1437 | { |
| 1438 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 1439 | struct drm_device *dev = crtc->dev; |
| 1440 | struct radeon_device *rdev = dev->dev_private; |
| 1441 | struct drm_encoder *test_encoder; |
| 1442 | struct drm_crtc *test_crtc; |
| 1443 | uint32_t pll_in_use = 0; |
| 1444 | |
| 1445 | if (ASIC_IS_DCE4(rdev)) { |
| 1446 | /* if crtc is driving DP and we have an ext clock, use that */ |
| 1447 | list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { |
| 1448 | if (test_encoder->crtc && (test_encoder->crtc == crtc)) { |
| 1449 | if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) { |
| 1450 | if (rdev->clock.dp_extclk) |
| 1451 | return ATOM_PPLL_INVALID; |
| 1452 | } |
| 1453 | } |
| 1454 | } |
| 1455 | |
| 1456 | /* otherwise, pick one of the plls */ |
| 1457 | list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { |
| 1458 | struct radeon_crtc *radeon_test_crtc; |
| 1459 | |
| 1460 | if (crtc == test_crtc) |
| 1461 | continue; |
| 1462 | |
| 1463 | radeon_test_crtc = to_radeon_crtc(test_crtc); |
| 1464 | if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) && |
| 1465 | (radeon_test_crtc->pll_id <= ATOM_PPLL2)) |
| 1466 | pll_in_use |= (1 << radeon_test_crtc->pll_id); |
| 1467 | } |
| 1468 | if (!(pll_in_use & 1)) |
| 1469 | return ATOM_PPLL1; |
| 1470 | return ATOM_PPLL2; |
| 1471 | } else |
| 1472 | return radeon_crtc->crtc_id; |
| 1473 | |
| 1474 | } |
| 1475 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1476 | int atombios_crtc_mode_set(struct drm_crtc *crtc, |
| 1477 | struct drm_display_mode *mode, |
| 1478 | struct drm_display_mode *adjusted_mode, |
| 1479 | int x, int y, struct drm_framebuffer *old_fb) |
| 1480 | { |
| 1481 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 1482 | struct drm_device *dev = crtc->dev; |
| 1483 | struct radeon_device *rdev = dev->dev_private; |
Alex Deucher | 54bfe49 | 2010-09-03 15:52:53 -0400 | [diff] [blame] | 1484 | struct drm_encoder *encoder; |
| 1485 | bool is_tvcv = false; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1486 | |
Alex Deucher | 54bfe49 | 2010-09-03 15:52:53 -0400 | [diff] [blame] | 1487 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 1488 | /* find tv std */ |
| 1489 | if (encoder->crtc == crtc) { |
| 1490 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 1491 | if (radeon_encoder->active_device & |
| 1492 | (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) |
| 1493 | is_tvcv = true; |
| 1494 | } |
| 1495 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1496 | |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1497 | /* always set DCPLL */ |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 1498 | if (ASIC_IS_DCE4(rdev)) { |
| 1499 | struct radeon_atom_ss ss; |
| 1500 | bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss, |
| 1501 | ASIC_INTERNAL_SS_ON_DCPLL, |
| 1502 | rdev->clock.default_dispclk); |
| 1503 | if (ss_enabled) |
| 1504 | atombios_crtc_program_ss(crtc, ATOM_DISABLE, ATOM_DCPLL, &ss); |
Alex Deucher | f82b3dd | 2011-01-06 21:19:15 -0500 | [diff] [blame] | 1505 | /* XXX: DCE5, make sure voltage, dispclk is high enough */ |
| 1506 | atombios_crtc_set_dcpll(crtc, rdev->clock.default_dispclk); |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 1507 | if (ss_enabled) |
| 1508 | atombios_crtc_program_ss(crtc, ATOM_ENABLE, ATOM_DCPLL, &ss); |
| 1509 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1510 | atombios_crtc_set_pll(crtc, adjusted_mode); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1511 | |
Alex Deucher | 54bfe49 | 2010-09-03 15:52:53 -0400 | [diff] [blame] | 1512 | if (ASIC_IS_DCE4(rdev)) |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1513 | atombios_set_crtc_dtd_timing(crtc, adjusted_mode); |
Alex Deucher | 54bfe49 | 2010-09-03 15:52:53 -0400 | [diff] [blame] | 1514 | else if (ASIC_IS_AVIVO(rdev)) { |
| 1515 | if (is_tvcv) |
| 1516 | atombios_crtc_set_timing(crtc, adjusted_mode); |
| 1517 | else |
| 1518 | atombios_set_crtc_dtd_timing(crtc, adjusted_mode); |
| 1519 | } else { |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1520 | atombios_crtc_set_timing(crtc, adjusted_mode); |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 1521 | if (radeon_crtc->crtc_id == 0) |
| 1522 | atombios_set_crtc_dtd_timing(crtc, adjusted_mode); |
Alex Deucher | 615e0cb | 2010-01-20 16:22:53 -0500 | [diff] [blame] | 1523 | radeon_legacy_atom_fixup(crtc); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1524 | } |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1525 | atombios_crtc_set_base(crtc, x, y, old_fb); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1526 | atombios_overscan_setup(crtc, mode, adjusted_mode); |
| 1527 | atombios_scaler_setup(crtc); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1528 | return 0; |
| 1529 | } |
| 1530 | |
| 1531 | static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc, |
| 1532 | struct drm_display_mode *mode, |
| 1533 | struct drm_display_mode *adjusted_mode) |
| 1534 | { |
Alex Deucher | 03214bd | 2010-03-16 17:42:46 -0400 | [diff] [blame] | 1535 | struct drm_device *dev = crtc->dev; |
| 1536 | struct radeon_device *rdev = dev->dev_private; |
| 1537 | |
| 1538 | /* adjust pm to upcoming mode change */ |
| 1539 | radeon_pm_compute_clocks(rdev); |
| 1540 | |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1541 | if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) |
| 1542 | return false; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1543 | return true; |
| 1544 | } |
| 1545 | |
| 1546 | static void atombios_crtc_prepare(struct drm_crtc *crtc) |
| 1547 | { |
Alex Deucher | 267364a | 2010-03-08 17:10:41 -0500 | [diff] [blame] | 1548 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 1549 | |
| 1550 | /* pick pll */ |
| 1551 | radeon_crtc->pll_id = radeon_atom_pick_pll(crtc); |
| 1552 | |
Alex Deucher | 37b4390 | 2010-02-09 12:04:43 -0500 | [diff] [blame] | 1553 | atombios_lock_crtc(crtc, ATOM_ENABLE); |
Alex Deucher | a348c84 | 2010-01-21 16:50:30 -0500 | [diff] [blame] | 1554 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1555 | } |
| 1556 | |
| 1557 | static void atombios_crtc_commit(struct drm_crtc *crtc) |
| 1558 | { |
| 1559 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON); |
Alex Deucher | 37b4390 | 2010-02-09 12:04:43 -0500 | [diff] [blame] | 1560 | atombios_lock_crtc(crtc, ATOM_DISABLE); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1561 | } |
| 1562 | |
Alex Deucher | 37f9003 | 2010-06-11 17:58:38 -0400 | [diff] [blame] | 1563 | static void atombios_crtc_disable(struct drm_crtc *crtc) |
| 1564 | { |
| 1565 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
Alex Deucher | 8e8e523 | 2011-05-20 04:34:16 -0400 | [diff] [blame^] | 1566 | struct radeon_atom_ss ss; |
| 1567 | |
Alex Deucher | 37f9003 | 2010-06-11 17:58:38 -0400 | [diff] [blame] | 1568 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
| 1569 | |
| 1570 | switch (radeon_crtc->pll_id) { |
| 1571 | case ATOM_PPLL1: |
| 1572 | case ATOM_PPLL2: |
| 1573 | /* disable the ppll */ |
| 1574 | atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, |
Alex Deucher | 8e8e523 | 2011-05-20 04:34:16 -0400 | [diff] [blame^] | 1575 | 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); |
Alex Deucher | 37f9003 | 2010-06-11 17:58:38 -0400 | [diff] [blame] | 1576 | break; |
| 1577 | default: |
| 1578 | break; |
| 1579 | } |
| 1580 | radeon_crtc->pll_id = -1; |
| 1581 | } |
| 1582 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1583 | static const struct drm_crtc_helper_funcs atombios_helper_funcs = { |
| 1584 | .dpms = atombios_crtc_dpms, |
| 1585 | .mode_fixup = atombios_crtc_mode_fixup, |
| 1586 | .mode_set = atombios_crtc_mode_set, |
| 1587 | .mode_set_base = atombios_crtc_set_base, |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1588 | .mode_set_base_atomic = atombios_crtc_set_base_atomic, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1589 | .prepare = atombios_crtc_prepare, |
| 1590 | .commit = atombios_crtc_commit, |
Dave Airlie | 068143d | 2009-10-05 09:58:02 +1000 | [diff] [blame] | 1591 | .load_lut = radeon_crtc_load_lut, |
Alex Deucher | 37f9003 | 2010-06-11 17:58:38 -0400 | [diff] [blame] | 1592 | .disable = atombios_crtc_disable, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1593 | }; |
| 1594 | |
| 1595 | void radeon_atombios_init_crtc(struct drm_device *dev, |
| 1596 | struct radeon_crtc *radeon_crtc) |
| 1597 | { |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1598 | struct radeon_device *rdev = dev->dev_private; |
| 1599 | |
| 1600 | if (ASIC_IS_DCE4(rdev)) { |
| 1601 | switch (radeon_crtc->crtc_id) { |
| 1602 | case 0: |
| 1603 | default: |
Alex Deucher | 12d7798 | 2010-02-09 17:18:48 -0500 | [diff] [blame] | 1604 | radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1605 | break; |
| 1606 | case 1: |
Alex Deucher | 12d7798 | 2010-02-09 17:18:48 -0500 | [diff] [blame] | 1607 | radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1608 | break; |
| 1609 | case 2: |
Alex Deucher | 12d7798 | 2010-02-09 17:18:48 -0500 | [diff] [blame] | 1610 | radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1611 | break; |
| 1612 | case 3: |
Alex Deucher | 12d7798 | 2010-02-09 17:18:48 -0500 | [diff] [blame] | 1613 | radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1614 | break; |
| 1615 | case 4: |
Alex Deucher | 12d7798 | 2010-02-09 17:18:48 -0500 | [diff] [blame] | 1616 | radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1617 | break; |
| 1618 | case 5: |
Alex Deucher | 12d7798 | 2010-02-09 17:18:48 -0500 | [diff] [blame] | 1619 | radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1620 | break; |
| 1621 | } |
| 1622 | } else { |
| 1623 | if (radeon_crtc->crtc_id == 1) |
| 1624 | radeon_crtc->crtc_offset = |
| 1625 | AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; |
| 1626 | else |
| 1627 | radeon_crtc->crtc_offset = 0; |
| 1628 | } |
| 1629 | radeon_crtc->pll_id = -1; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1630 | drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); |
| 1631 | } |