| Sathish Ambley | 4149e84 | 2012-03-23 11:53:55 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. |
| Sathish Ambley | 5b2ec0a | 2011-10-08 23:03:26 -0700 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| Abhimanyu Kapur | 90ced6e | 2012-06-26 17:41:25 -0700 | [diff] [blame^] | 13 | #ifndef __ASM_ARCH_MSM_IRQS_8974_H |
| 14 | #define __ASM_ARCH_MSM_IRQS_8974_H |
| Sathish Ambley | 5b2ec0a | 2011-10-08 23:03:26 -0700 | [diff] [blame] | 15 | |
| 16 | /* MSM ACPU Interrupt Numbers */ |
| 17 | |
| 18 | /* |
| 19 | * 0-15: STI/SGI (software triggered/generated interrupts) |
| 20 | * 16-31: PPI (private peripheral interrupts) |
| 21 | * 32+: SPI (shared peripheral interrupts) |
| 22 | */ |
| 23 | |
| 24 | #define GIC_PPI_START 16 |
| 25 | #define GIC_SPI_START 32 |
| 26 | |
| Sathish Ambley | 5b2ec0a | 2011-10-08 23:03:26 -0700 | [diff] [blame] | 27 | #define AVS_SVICINT (GIC_PPI_START + 6) |
| 28 | #define AVS_SVICINTSWDONE (GIC_PPI_START + 7) |
| 29 | #define INT_ARMQC_PERFMON (GIC_PPI_START + 10) |
| 30 | /* PPI 15 is unused */ |
| 31 | |
| 32 | #define APCC_QGICL2PERFMONIRPTREQ (GIC_SPI_START + 1) |
| 33 | #define SC_SICL2PERFMONIRPTREQ APCC_QGICL2PERFMONIRPTREQ |
| Sathish Ambley | e3154b4 | 2012-04-09 10:59:09 -0700 | [diff] [blame] | 34 | #define TLMM_MSM_SUMMARY_IRQ (GIC_SPI_START + 208) |
| Sathish Ambley | 5b2ec0a | 2011-10-08 23:03:26 -0700 | [diff] [blame] | 35 | #define SPS_BAM_DMA_IRQ (GIC_SPI_START + 105) |
| 36 | |
| Michael Bohan | 3372c0d | 2012-01-11 18:28:45 -0800 | [diff] [blame] | 37 | #define NR_MSM_IRQS 1020 /* Should be 256 - but higher due to bug in sim */ |
| Sathish Ambley | 4149e84 | 2012-03-23 11:53:55 -0700 | [diff] [blame] | 38 | #define NR_GPIO_IRQS 146 |
| Michael Bohan | 115cf65 | 2012-01-05 14:32:59 -0800 | [diff] [blame] | 39 | #define NR_QPNP_IRQS 32768 /* SPARSE_IRQ is required to support this */ |
| 40 | #define NR_BOARD_IRQS NR_QPNP_IRQS |
| Sathish Ambley | 5b2ec0a | 2011-10-08 23:03:26 -0700 | [diff] [blame] | 41 | #define NR_TLMM_MSM_DIR_CONN_IRQ 8 |
| 42 | #define NR_MSM_GPIOS NR_GPIO_IRQS |
| 43 | |
| 44 | #endif |
| 45 | |