| Greg Ungerer | 910ce39 | 2005-09-09 09:32:14 +1000 | [diff] [blame] | 1 | /****************************************************************************/ |
| 2 | |
| 3 | /* |
| 4 | * m523xsim.h -- ColdFire 523x System Integration Module support. |
| 5 | * |
| 6 | * (C) Copyright 2003-2005, Greg Ungerer <gerg@snapgear.com> |
| 7 | */ |
| 8 | |
| 9 | /****************************************************************************/ |
| 10 | #ifndef m523xsim_h |
| 11 | #define m523xsim_h |
| 12 | /****************************************************************************/ |
| 13 | |
| Greg Ungerer | 910ce39 | 2005-09-09 09:32:14 +1000 | [diff] [blame] | 14 | |
| 15 | /* |
| 16 | * Define the 523x SIM register set addresses. |
| 17 | */ |
| 18 | #define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */ |
| 19 | #define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 0 */ |
| 20 | #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ |
| 21 | #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ |
| 22 | #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ |
| 23 | #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ |
| 24 | #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ |
| 25 | #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ |
| 26 | #define MCFINTC_IRLR 0x18 /* */ |
| 27 | #define MCFINTC_IACKL 0x19 /* */ |
| 28 | #define MCFINTC_ICR0 0x40 /* Base ICR register */ |
| 29 | |
| 30 | #define MCFINT_VECBASE 64 /* Vector base number */ |
| 31 | #define MCFINT_UART0 13 /* Interrupt number for UART0 */ |
| 32 | #define MCFINT_PIT1 36 /* Interrupt number for PIT1 */ |
| 33 | #define MCFINT_QSPI 18 /* Interrupt number for QSPI */ |
| 34 | |
| 35 | /* |
| 36 | * SDRAM configuration registers. |
| 37 | */ |
| 38 | #define MCFSIM_DCR 0x44 /* SDRAM control */ |
| 39 | #define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */ |
| 40 | #define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */ |
| 41 | #define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */ |
| 42 | #define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */ |
| 43 | |
| Greg Ungerer | 55b33f3 | 2009-04-30 22:58:35 +1000 | [diff] [blame] | 44 | /* |
| 45 | * Reset Controll Unit (relative to IPSBAR). |
| 46 | */ |
| 47 | #define MCF_RCR 0x110000 |
| 48 | #define MCF_RSR 0x110001 |
| 49 | |
| 50 | #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ |
| 51 | #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ |
| 52 | |
| sfking@fdwdc.com | a03ce7d | 2009-06-19 18:11:04 -0700 | [diff] [blame] | 53 | #define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000) |
| 54 | #define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001) |
| 55 | #define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002) |
| 56 | #define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100003) |
| 57 | #define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100004) |
| 58 | #define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100005) |
| 59 | #define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x100006) |
| 60 | #define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x100007) |
| 61 | #define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100008) |
| 62 | #define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100009) |
| 63 | #define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000A) |
| 64 | #define MCFGPIO_PODR_TIMER (MCF_IPSBAR + 0x10000B) |
| 65 | #define MCFGPIO_PODR_ETPU (MCF_IPSBAR + 0x10000C) |
| 66 | |
| 67 | #define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100010) |
| 68 | #define MCFGPIO_PDDR_DATAH (MCF_IPSBAR + 0x100011) |
| 69 | #define MCFGPIO_PDDR_DATAL (MCF_IPSBAR + 0x100012) |
| 70 | #define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100013) |
| 71 | #define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100014) |
| 72 | #define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100015) |
| 73 | #define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x100016) |
| 74 | #define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100017) |
| 75 | #define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100018) |
| 76 | #define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x100019) |
| 77 | #define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x10001A) |
| 78 | #define MCFGPIO_PDDR_TIMER (MCF_IPSBAR + 0x10001B) |
| 79 | #define MCFGPIO_PDDR_ETPU (MCF_IPSBAR + 0x10001C) |
| 80 | |
| 81 | #define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x100020) |
| 82 | #define MCFGPIO_PPDSDR_DATAH (MCF_IPSBAR + 0x100021) |
| 83 | #define MCFGPIO_PPDSDR_DATAL (MCF_IPSBAR + 0x100022) |
| 84 | #define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x100023) |
| 85 | #define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x100024) |
| 86 | #define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100025) |
| 87 | #define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100026) |
| 88 | #define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100027) |
| 89 | #define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100028) |
| 90 | #define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100029) |
| 91 | #define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x10002A) |
| 92 | #define MCFGPIO_PPDSDR_TIMER (MCF_IPSBAR + 0x10002B) |
| 93 | #define MCFGPIO_PPDSDR_ETPU (MCF_IPSBAR + 0x10002C) |
| 94 | |
| 95 | #define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100030) |
| 96 | #define MCFGPIO_PCLRR_DATAH (MCF_IPSBAR + 0x100031) |
| 97 | #define MCFGPIO_PCLRR_DATAL (MCF_IPSBAR + 0x100032) |
| 98 | #define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100033) |
| 99 | #define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100034) |
| 100 | #define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x100035) |
| 101 | #define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100036) |
| 102 | #define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100037) |
| 103 | #define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x100038) |
| 104 | #define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100039) |
| 105 | #define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x10003A) |
| 106 | #define MCFGPIO_PCLRR_TIMER (MCF_IPSBAR + 0x10003B) |
| 107 | #define MCFGPIO_PCLRR_ETPU (MCF_IPSBAR + 0x10003C) |
| 108 | |
| 109 | /* |
| 110 | * EPort |
| 111 | */ |
| 112 | |
| 113 | #define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002) |
| 114 | #define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004) |
| 115 | #define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005) |
| 116 | |
| 117 | /* |
| 118 | * Generic GPIO support |
| 119 | */ |
| 120 | #define MCFGPIO_PODR MCFGPIO_PODR_ADDR |
| 121 | #define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR |
| 122 | #define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR |
| 123 | #define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR |
| 124 | #define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR |
| 125 | |
| 126 | #define MCFGPIO_PIN_MAX 107 |
| 127 | #define MCFGPIO_IRQ_MAX 8 |
| 128 | #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE |
| 129 | |
| Greg Ungerer | 910ce39 | 2005-09-09 09:32:14 +1000 | [diff] [blame] | 130 | /****************************************************************************/ |
| 131 | #endif /* m523xsim_h */ |