Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 1 | /* |
| 2 | * TI DA830/OMAP L137 chip specific setup |
| 3 | * |
| 4 | * Author: Mark A. Greer <mgreer@mvista.com> |
| 5 | * |
| 6 | * 2009 (c) MontaVista Software, Inc. This file is licensed under |
| 7 | * the terms of the GNU General Public License version 2. This program |
| 8 | * is licensed "as is" without any warranty of any kind, whether express |
| 9 | * or implied. |
| 10 | */ |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 11 | #include <linux/init.h> |
| 12 | #include <linux/clk.h> |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 13 | |
| 14 | #include <asm/mach/map.h> |
| 15 | |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 16 | #include <mach/psc.h> |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 17 | #include <mach/irqs.h> |
| 18 | #include <mach/cputype.h> |
| 19 | #include <mach/common.h> |
| 20 | #include <mach/time.h> |
| 21 | #include <mach/da8xx.h> |
Cyril Chemparathy | 686b634 | 2010-05-01 18:37:54 -0400 | [diff] [blame] | 22 | #include <mach/gpio.h> |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 23 | |
| 24 | #include "clock.h" |
| 25 | #include "mux.h" |
| 26 | |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 27 | /* Offsets of the 8 compare registers on the da830 */ |
| 28 | #define DA830_CMP12_0 0x60 |
| 29 | #define DA830_CMP12_1 0x64 |
| 30 | #define DA830_CMP12_2 0x68 |
| 31 | #define DA830_CMP12_3 0x6c |
| 32 | #define DA830_CMP12_4 0x70 |
| 33 | #define DA830_CMP12_5 0x74 |
| 34 | #define DA830_CMP12_6 0x78 |
| 35 | #define DA830_CMP12_7 0x7c |
| 36 | |
| 37 | #define DA830_REF_FREQ 24000000 |
| 38 | |
| 39 | static struct pll_data pll0_data = { |
| 40 | .num = 1, |
Rajashekhara, Sudhakar | bea238f | 2009-07-10 02:08:31 -0400 | [diff] [blame] | 41 | .phys_base = DA8XX_PLL0_BASE, |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 42 | .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV, |
| 43 | }; |
| 44 | |
| 45 | static struct clk ref_clk = { |
| 46 | .name = "ref_clk", |
| 47 | .rate = DA830_REF_FREQ, |
| 48 | }; |
| 49 | |
| 50 | static struct clk pll0_clk = { |
| 51 | .name = "pll0", |
| 52 | .parent = &ref_clk, |
| 53 | .pll_data = &pll0_data, |
| 54 | .flags = CLK_PLL, |
| 55 | }; |
| 56 | |
| 57 | static struct clk pll0_aux_clk = { |
| 58 | .name = "pll0_aux_clk", |
| 59 | .parent = &pll0_clk, |
| 60 | .flags = CLK_PLL | PRE_PLL, |
| 61 | }; |
| 62 | |
| 63 | static struct clk pll0_sysclk2 = { |
| 64 | .name = "pll0_sysclk2", |
| 65 | .parent = &pll0_clk, |
| 66 | .flags = CLK_PLL, |
| 67 | .div_reg = PLLDIV2, |
| 68 | }; |
| 69 | |
| 70 | static struct clk pll0_sysclk3 = { |
| 71 | .name = "pll0_sysclk3", |
| 72 | .parent = &pll0_clk, |
| 73 | .flags = CLK_PLL, |
| 74 | .div_reg = PLLDIV3, |
| 75 | }; |
| 76 | |
| 77 | static struct clk pll0_sysclk4 = { |
| 78 | .name = "pll0_sysclk4", |
| 79 | .parent = &pll0_clk, |
| 80 | .flags = CLK_PLL, |
| 81 | .div_reg = PLLDIV4, |
| 82 | }; |
| 83 | |
| 84 | static struct clk pll0_sysclk5 = { |
| 85 | .name = "pll0_sysclk5", |
| 86 | .parent = &pll0_clk, |
| 87 | .flags = CLK_PLL, |
| 88 | .div_reg = PLLDIV5, |
| 89 | }; |
| 90 | |
| 91 | static struct clk pll0_sysclk6 = { |
| 92 | .name = "pll0_sysclk6", |
| 93 | .parent = &pll0_clk, |
| 94 | .flags = CLK_PLL, |
| 95 | .div_reg = PLLDIV6, |
| 96 | }; |
| 97 | |
| 98 | static struct clk pll0_sysclk7 = { |
| 99 | .name = "pll0_sysclk7", |
| 100 | .parent = &pll0_clk, |
| 101 | .flags = CLK_PLL, |
| 102 | .div_reg = PLLDIV7, |
| 103 | }; |
| 104 | |
| 105 | static struct clk i2c0_clk = { |
| 106 | .name = "i2c0", |
| 107 | .parent = &pll0_aux_clk, |
| 108 | }; |
| 109 | |
| 110 | static struct clk timerp64_0_clk = { |
| 111 | .name = "timer0", |
| 112 | .parent = &pll0_aux_clk, |
| 113 | }; |
| 114 | |
| 115 | static struct clk timerp64_1_clk = { |
| 116 | .name = "timer1", |
| 117 | .parent = &pll0_aux_clk, |
| 118 | }; |
| 119 | |
| 120 | static struct clk arm_rom_clk = { |
| 121 | .name = "arm_rom", |
| 122 | .parent = &pll0_sysclk2, |
| 123 | .lpsc = DA8XX_LPSC0_ARM_RAM_ROM, |
| 124 | .flags = ALWAYS_ENABLED, |
| 125 | }; |
| 126 | |
| 127 | static struct clk scr0_ss_clk = { |
| 128 | .name = "scr0_ss", |
| 129 | .parent = &pll0_sysclk2, |
| 130 | .lpsc = DA8XX_LPSC0_SCR0_SS, |
| 131 | .flags = ALWAYS_ENABLED, |
| 132 | }; |
| 133 | |
| 134 | static struct clk scr1_ss_clk = { |
| 135 | .name = "scr1_ss", |
| 136 | .parent = &pll0_sysclk2, |
| 137 | .lpsc = DA8XX_LPSC0_SCR1_SS, |
| 138 | .flags = ALWAYS_ENABLED, |
| 139 | }; |
| 140 | |
| 141 | static struct clk scr2_ss_clk = { |
| 142 | .name = "scr2_ss", |
| 143 | .parent = &pll0_sysclk2, |
| 144 | .lpsc = DA8XX_LPSC0_SCR2_SS, |
| 145 | .flags = ALWAYS_ENABLED, |
| 146 | }; |
| 147 | |
| 148 | static struct clk dmax_clk = { |
| 149 | .name = "dmax", |
| 150 | .parent = &pll0_sysclk2, |
| 151 | .lpsc = DA8XX_LPSC0_DMAX, |
| 152 | .flags = ALWAYS_ENABLED, |
| 153 | }; |
| 154 | |
| 155 | static struct clk tpcc_clk = { |
| 156 | .name = "tpcc", |
| 157 | .parent = &pll0_sysclk2, |
| 158 | .lpsc = DA8XX_LPSC0_TPCC, |
| 159 | .flags = ALWAYS_ENABLED | CLK_PSC, |
| 160 | }; |
| 161 | |
| 162 | static struct clk tptc0_clk = { |
| 163 | .name = "tptc0", |
| 164 | .parent = &pll0_sysclk2, |
| 165 | .lpsc = DA8XX_LPSC0_TPTC0, |
| 166 | .flags = ALWAYS_ENABLED, |
| 167 | }; |
| 168 | |
| 169 | static struct clk tptc1_clk = { |
| 170 | .name = "tptc1", |
| 171 | .parent = &pll0_sysclk2, |
| 172 | .lpsc = DA8XX_LPSC0_TPTC1, |
| 173 | .flags = ALWAYS_ENABLED, |
| 174 | }; |
| 175 | |
| 176 | static struct clk mmcsd_clk = { |
| 177 | .name = "mmcsd", |
| 178 | .parent = &pll0_sysclk2, |
| 179 | .lpsc = DA8XX_LPSC0_MMC_SD, |
| 180 | }; |
| 181 | |
| 182 | static struct clk uart0_clk = { |
| 183 | .name = "uart0", |
| 184 | .parent = &pll0_sysclk2, |
| 185 | .lpsc = DA8XX_LPSC0_UART0, |
| 186 | }; |
| 187 | |
| 188 | static struct clk uart1_clk = { |
| 189 | .name = "uart1", |
| 190 | .parent = &pll0_sysclk2, |
| 191 | .lpsc = DA8XX_LPSC1_UART1, |
Sergei Shtylyov | 789a785 | 2009-09-30 19:48:03 +0400 | [diff] [blame] | 192 | .gpsc = 1, |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 193 | }; |
| 194 | |
| 195 | static struct clk uart2_clk = { |
| 196 | .name = "uart2", |
| 197 | .parent = &pll0_sysclk2, |
| 198 | .lpsc = DA8XX_LPSC1_UART2, |
Sergei Shtylyov | 789a785 | 2009-09-30 19:48:03 +0400 | [diff] [blame] | 199 | .gpsc = 1, |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 200 | }; |
| 201 | |
| 202 | static struct clk spi0_clk = { |
| 203 | .name = "spi0", |
| 204 | .parent = &pll0_sysclk2, |
| 205 | .lpsc = DA8XX_LPSC0_SPI0, |
| 206 | }; |
| 207 | |
| 208 | static struct clk spi1_clk = { |
| 209 | .name = "spi1", |
| 210 | .parent = &pll0_sysclk2, |
| 211 | .lpsc = DA8XX_LPSC1_SPI1, |
Sergei Shtylyov | 789a785 | 2009-09-30 19:48:03 +0400 | [diff] [blame] | 212 | .gpsc = 1, |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 213 | }; |
| 214 | |
| 215 | static struct clk ecap0_clk = { |
| 216 | .name = "ecap0", |
| 217 | .parent = &pll0_sysclk2, |
| 218 | .lpsc = DA8XX_LPSC1_ECAP, |
Sergei Shtylyov | 789a785 | 2009-09-30 19:48:03 +0400 | [diff] [blame] | 219 | .gpsc = 1, |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 220 | }; |
| 221 | |
| 222 | static struct clk ecap1_clk = { |
| 223 | .name = "ecap1", |
| 224 | .parent = &pll0_sysclk2, |
| 225 | .lpsc = DA8XX_LPSC1_ECAP, |
Sergei Shtylyov | 789a785 | 2009-09-30 19:48:03 +0400 | [diff] [blame] | 226 | .gpsc = 1, |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 227 | }; |
| 228 | |
| 229 | static struct clk ecap2_clk = { |
| 230 | .name = "ecap2", |
| 231 | .parent = &pll0_sysclk2, |
| 232 | .lpsc = DA8XX_LPSC1_ECAP, |
Sergei Shtylyov | 789a785 | 2009-09-30 19:48:03 +0400 | [diff] [blame] | 233 | .gpsc = 1, |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 234 | }; |
| 235 | |
| 236 | static struct clk pwm0_clk = { |
| 237 | .name = "pwm0", |
| 238 | .parent = &pll0_sysclk2, |
| 239 | .lpsc = DA8XX_LPSC1_PWM, |
Sergei Shtylyov | 789a785 | 2009-09-30 19:48:03 +0400 | [diff] [blame] | 240 | .gpsc = 1, |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 241 | }; |
| 242 | |
| 243 | static struct clk pwm1_clk = { |
| 244 | .name = "pwm1", |
| 245 | .parent = &pll0_sysclk2, |
| 246 | .lpsc = DA8XX_LPSC1_PWM, |
Sergei Shtylyov | 789a785 | 2009-09-30 19:48:03 +0400 | [diff] [blame] | 247 | .gpsc = 1, |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 248 | }; |
| 249 | |
| 250 | static struct clk pwm2_clk = { |
| 251 | .name = "pwm2", |
| 252 | .parent = &pll0_sysclk2, |
| 253 | .lpsc = DA8XX_LPSC1_PWM, |
Sergei Shtylyov | 789a785 | 2009-09-30 19:48:03 +0400 | [diff] [blame] | 254 | .gpsc = 1, |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 255 | }; |
| 256 | |
| 257 | static struct clk eqep0_clk = { |
| 258 | .name = "eqep0", |
| 259 | .parent = &pll0_sysclk2, |
| 260 | .lpsc = DA830_LPSC1_EQEP, |
Sergei Shtylyov | 789a785 | 2009-09-30 19:48:03 +0400 | [diff] [blame] | 261 | .gpsc = 1, |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 262 | }; |
| 263 | |
| 264 | static struct clk eqep1_clk = { |
| 265 | .name = "eqep1", |
| 266 | .parent = &pll0_sysclk2, |
| 267 | .lpsc = DA830_LPSC1_EQEP, |
Sergei Shtylyov | 789a785 | 2009-09-30 19:48:03 +0400 | [diff] [blame] | 268 | .gpsc = 1, |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 269 | }; |
| 270 | |
| 271 | static struct clk lcdc_clk = { |
| 272 | .name = "lcdc", |
| 273 | .parent = &pll0_sysclk2, |
| 274 | .lpsc = DA8XX_LPSC1_LCDC, |
Sergei Shtylyov | 789a785 | 2009-09-30 19:48:03 +0400 | [diff] [blame] | 275 | .gpsc = 1, |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 276 | }; |
| 277 | |
| 278 | static struct clk mcasp0_clk = { |
| 279 | .name = "mcasp0", |
| 280 | .parent = &pll0_sysclk2, |
| 281 | .lpsc = DA8XX_LPSC1_McASP0, |
Sergei Shtylyov | 789a785 | 2009-09-30 19:48:03 +0400 | [diff] [blame] | 282 | .gpsc = 1, |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 283 | }; |
| 284 | |
| 285 | static struct clk mcasp1_clk = { |
| 286 | .name = "mcasp1", |
| 287 | .parent = &pll0_sysclk2, |
| 288 | .lpsc = DA830_LPSC1_McASP1, |
Sergei Shtylyov | 789a785 | 2009-09-30 19:48:03 +0400 | [diff] [blame] | 289 | .gpsc = 1, |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 290 | }; |
| 291 | |
| 292 | static struct clk mcasp2_clk = { |
| 293 | .name = "mcasp2", |
| 294 | .parent = &pll0_sysclk2, |
| 295 | .lpsc = DA830_LPSC1_McASP2, |
Sergei Shtylyov | 789a785 | 2009-09-30 19:48:03 +0400 | [diff] [blame] | 296 | .gpsc = 1, |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 297 | }; |
| 298 | |
| 299 | static struct clk usb20_clk = { |
| 300 | .name = "usb20", |
| 301 | .parent = &pll0_sysclk2, |
| 302 | .lpsc = DA8XX_LPSC1_USB20, |
Sergei Shtylyov | 789a785 | 2009-09-30 19:48:03 +0400 | [diff] [blame] | 303 | .gpsc = 1, |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 304 | }; |
| 305 | |
| 306 | static struct clk aemif_clk = { |
| 307 | .name = "aemif", |
| 308 | .parent = &pll0_sysclk3, |
| 309 | .lpsc = DA8XX_LPSC0_EMIF25, |
| 310 | .flags = ALWAYS_ENABLED, |
| 311 | }; |
| 312 | |
| 313 | static struct clk aintc_clk = { |
| 314 | .name = "aintc", |
| 315 | .parent = &pll0_sysclk4, |
| 316 | .lpsc = DA8XX_LPSC0_AINTC, |
| 317 | .flags = ALWAYS_ENABLED, |
| 318 | }; |
| 319 | |
| 320 | static struct clk secu_mgr_clk = { |
| 321 | .name = "secu_mgr", |
| 322 | .parent = &pll0_sysclk4, |
| 323 | .lpsc = DA8XX_LPSC0_SECU_MGR, |
| 324 | .flags = ALWAYS_ENABLED, |
| 325 | }; |
| 326 | |
| 327 | static struct clk emac_clk = { |
| 328 | .name = "emac", |
| 329 | .parent = &pll0_sysclk4, |
| 330 | .lpsc = DA8XX_LPSC1_CPGMAC, |
Sergei Shtylyov | 789a785 | 2009-09-30 19:48:03 +0400 | [diff] [blame] | 331 | .gpsc = 1, |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 332 | }; |
| 333 | |
| 334 | static struct clk gpio_clk = { |
| 335 | .name = "gpio", |
| 336 | .parent = &pll0_sysclk4, |
| 337 | .lpsc = DA8XX_LPSC1_GPIO, |
Sergei Shtylyov | 789a785 | 2009-09-30 19:48:03 +0400 | [diff] [blame] | 338 | .gpsc = 1, |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 339 | }; |
| 340 | |
| 341 | static struct clk i2c1_clk = { |
| 342 | .name = "i2c1", |
| 343 | .parent = &pll0_sysclk4, |
| 344 | .lpsc = DA8XX_LPSC1_I2C, |
Sergei Shtylyov | 789a785 | 2009-09-30 19:48:03 +0400 | [diff] [blame] | 345 | .gpsc = 1, |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 346 | }; |
| 347 | |
| 348 | static struct clk usb11_clk = { |
| 349 | .name = "usb11", |
| 350 | .parent = &pll0_sysclk4, |
| 351 | .lpsc = DA8XX_LPSC1_USB11, |
Sergei Shtylyov | 789a785 | 2009-09-30 19:48:03 +0400 | [diff] [blame] | 352 | .gpsc = 1, |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 353 | }; |
| 354 | |
| 355 | static struct clk emif3_clk = { |
| 356 | .name = "emif3", |
| 357 | .parent = &pll0_sysclk5, |
| 358 | .lpsc = DA8XX_LPSC1_EMIF3C, |
Sergei Shtylyov | 789a785 | 2009-09-30 19:48:03 +0400 | [diff] [blame] | 359 | .gpsc = 1, |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 360 | .flags = ALWAYS_ENABLED, |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 361 | }; |
| 362 | |
| 363 | static struct clk arm_clk = { |
| 364 | .name = "arm", |
| 365 | .parent = &pll0_sysclk6, |
| 366 | .lpsc = DA8XX_LPSC0_ARM, |
| 367 | .flags = ALWAYS_ENABLED, |
| 368 | }; |
| 369 | |
| 370 | static struct clk rmii_clk = { |
| 371 | .name = "rmii", |
| 372 | .parent = &pll0_sysclk7, |
| 373 | }; |
| 374 | |
Kevin Hilman | 08aca08 | 2010-01-11 08:22:23 -0800 | [diff] [blame] | 375 | static struct clk_lookup da830_clks[] = { |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 376 | CLK(NULL, "ref", &ref_clk), |
| 377 | CLK(NULL, "pll0", &pll0_clk), |
| 378 | CLK(NULL, "pll0_aux", &pll0_aux_clk), |
| 379 | CLK(NULL, "pll0_sysclk2", &pll0_sysclk2), |
| 380 | CLK(NULL, "pll0_sysclk3", &pll0_sysclk3), |
| 381 | CLK(NULL, "pll0_sysclk4", &pll0_sysclk4), |
| 382 | CLK(NULL, "pll0_sysclk5", &pll0_sysclk5), |
| 383 | CLK(NULL, "pll0_sysclk6", &pll0_sysclk6), |
| 384 | CLK(NULL, "pll0_sysclk7", &pll0_sysclk7), |
| 385 | CLK("i2c_davinci.1", NULL, &i2c0_clk), |
| 386 | CLK(NULL, "timer0", &timerp64_0_clk), |
| 387 | CLK("watchdog", NULL, &timerp64_1_clk), |
| 388 | CLK(NULL, "arm_rom", &arm_rom_clk), |
| 389 | CLK(NULL, "scr0_ss", &scr0_ss_clk), |
| 390 | CLK(NULL, "scr1_ss", &scr1_ss_clk), |
| 391 | CLK(NULL, "scr2_ss", &scr2_ss_clk), |
| 392 | CLK(NULL, "dmax", &dmax_clk), |
| 393 | CLK(NULL, "tpcc", &tpcc_clk), |
| 394 | CLK(NULL, "tptc0", &tptc0_clk), |
| 395 | CLK(NULL, "tptc1", &tptc1_clk), |
| 396 | CLK("davinci_mmc.0", NULL, &mmcsd_clk), |
| 397 | CLK(NULL, "uart0", &uart0_clk), |
| 398 | CLK(NULL, "uart1", &uart1_clk), |
| 399 | CLK(NULL, "uart2", &uart2_clk), |
| 400 | CLK("dm_spi.0", NULL, &spi0_clk), |
| 401 | CLK("dm_spi.1", NULL, &spi1_clk), |
| 402 | CLK(NULL, "ecap0", &ecap0_clk), |
| 403 | CLK(NULL, "ecap1", &ecap1_clk), |
| 404 | CLK(NULL, "ecap2", &ecap2_clk), |
| 405 | CLK(NULL, "pwm0", &pwm0_clk), |
| 406 | CLK(NULL, "pwm1", &pwm1_clk), |
| 407 | CLK(NULL, "pwm2", &pwm2_clk), |
| 408 | CLK("eqep.0", NULL, &eqep0_clk), |
| 409 | CLK("eqep.1", NULL, &eqep1_clk), |
Steve Chen | 13e1f04 | 2009-09-15 18:15:06 -0700 | [diff] [blame] | 410 | CLK("da8xx_lcdc.0", NULL, &lcdc_clk), |
Chaithrika U S | e33ef5e | 2009-08-11 17:01:59 -0400 | [diff] [blame] | 411 | CLK("davinci-mcasp.0", NULL, &mcasp0_clk), |
| 412 | CLK("davinci-mcasp.1", NULL, &mcasp1_clk), |
| 413 | CLK("davinci-mcasp.2", NULL, &mcasp2_clk), |
Sergei Shtylyov | b9af5dd | 2010-05-13 22:51:51 +0400 | [diff] [blame] | 414 | CLK(NULL, "usb20", &usb20_clk), |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 415 | CLK(NULL, "aemif", &aemif_clk), |
| 416 | CLK(NULL, "aintc", &aintc_clk), |
| 417 | CLK(NULL, "secu_mgr", &secu_mgr_clk), |
| 418 | CLK("davinci_emac.1", NULL, &emac_clk), |
| 419 | CLK(NULL, "gpio", &gpio_clk), |
| 420 | CLK("i2c_davinci.2", NULL, &i2c1_clk), |
| 421 | CLK(NULL, "usb11", &usb11_clk), |
| 422 | CLK(NULL, "emif3", &emif3_clk), |
| 423 | CLK(NULL, "arm", &arm_clk), |
| 424 | CLK(NULL, "rmii", &rmii_clk), |
| 425 | CLK(NULL, NULL, NULL), |
| 426 | }; |
| 427 | |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 428 | /* |
| 429 | * Device specific mux setup |
| 430 | * |
| 431 | * soc description mux mode mode mux dbg |
| 432 | * reg offset mask mode |
| 433 | */ |
| 434 | static const struct mux_config da830_pins[] = { |
| 435 | #ifdef CONFIG_DAVINCI_MUX |
| 436 | MUX_CFG(DA830, GPIO7_14, 0, 0, 0xf, 1, false) |
| 437 | MUX_CFG(DA830, RTCK, 0, 0, 0xf, 8, false) |
| 438 | MUX_CFG(DA830, GPIO7_15, 0, 4, 0xf, 1, false) |
| 439 | MUX_CFG(DA830, EMU_0, 0, 4, 0xf, 8, false) |
| 440 | MUX_CFG(DA830, EMB_SDCKE, 0, 8, 0xf, 1, false) |
| 441 | MUX_CFG(DA830, EMB_CLK_GLUE, 0, 12, 0xf, 1, false) |
| 442 | MUX_CFG(DA830, EMB_CLK, 0, 12, 0xf, 2, false) |
| 443 | MUX_CFG(DA830, NEMB_CS_0, 0, 16, 0xf, 1, false) |
| 444 | MUX_CFG(DA830, NEMB_CAS, 0, 20, 0xf, 1, false) |
| 445 | MUX_CFG(DA830, NEMB_RAS, 0, 24, 0xf, 1, false) |
| 446 | MUX_CFG(DA830, NEMB_WE, 0, 28, 0xf, 1, false) |
| 447 | MUX_CFG(DA830, EMB_BA_1, 1, 0, 0xf, 1, false) |
| 448 | MUX_CFG(DA830, EMB_BA_0, 1, 4, 0xf, 1, false) |
| 449 | MUX_CFG(DA830, EMB_A_0, 1, 8, 0xf, 1, false) |
| 450 | MUX_CFG(DA830, EMB_A_1, 1, 12, 0xf, 1, false) |
| 451 | MUX_CFG(DA830, EMB_A_2, 1, 16, 0xf, 1, false) |
| 452 | MUX_CFG(DA830, EMB_A_3, 1, 20, 0xf, 1, false) |
| 453 | MUX_CFG(DA830, EMB_A_4, 1, 24, 0xf, 1, false) |
| 454 | MUX_CFG(DA830, EMB_A_5, 1, 28, 0xf, 1, false) |
| 455 | MUX_CFG(DA830, GPIO7_0, 1, 0, 0xf, 8, false) |
| 456 | MUX_CFG(DA830, GPIO7_1, 1, 4, 0xf, 8, false) |
| 457 | MUX_CFG(DA830, GPIO7_2, 1, 8, 0xf, 8, false) |
| 458 | MUX_CFG(DA830, GPIO7_3, 1, 12, 0xf, 8, false) |
| 459 | MUX_CFG(DA830, GPIO7_4, 1, 16, 0xf, 8, false) |
| 460 | MUX_CFG(DA830, GPIO7_5, 1, 20, 0xf, 8, false) |
| 461 | MUX_CFG(DA830, GPIO7_6, 1, 24, 0xf, 8, false) |
| 462 | MUX_CFG(DA830, GPIO7_7, 1, 28, 0xf, 8, false) |
| 463 | MUX_CFG(DA830, EMB_A_6, 2, 0, 0xf, 1, false) |
| 464 | MUX_CFG(DA830, EMB_A_7, 2, 4, 0xf, 1, false) |
| 465 | MUX_CFG(DA830, EMB_A_8, 2, 8, 0xf, 1, false) |
| 466 | MUX_CFG(DA830, EMB_A_9, 2, 12, 0xf, 1, false) |
| 467 | MUX_CFG(DA830, EMB_A_10, 2, 16, 0xf, 1, false) |
| 468 | MUX_CFG(DA830, EMB_A_11, 2, 20, 0xf, 1, false) |
| 469 | MUX_CFG(DA830, EMB_A_12, 2, 24, 0xf, 1, false) |
| 470 | MUX_CFG(DA830, EMB_D_31, 2, 28, 0xf, 1, false) |
| 471 | MUX_CFG(DA830, GPIO7_8, 2, 0, 0xf, 8, false) |
| 472 | MUX_CFG(DA830, GPIO7_9, 2, 4, 0xf, 8, false) |
| 473 | MUX_CFG(DA830, GPIO7_10, 2, 8, 0xf, 8, false) |
| 474 | MUX_CFG(DA830, GPIO7_11, 2, 12, 0xf, 8, false) |
| 475 | MUX_CFG(DA830, GPIO7_12, 2, 16, 0xf, 8, false) |
| 476 | MUX_CFG(DA830, GPIO7_13, 2, 20, 0xf, 8, false) |
| 477 | MUX_CFG(DA830, GPIO3_13, 2, 24, 0xf, 8, false) |
| 478 | MUX_CFG(DA830, EMB_D_30, 3, 0, 0xf, 1, false) |
| 479 | MUX_CFG(DA830, EMB_D_29, 3, 4, 0xf, 1, false) |
| 480 | MUX_CFG(DA830, EMB_D_28, 3, 8, 0xf, 1, false) |
| 481 | MUX_CFG(DA830, EMB_D_27, 3, 12, 0xf, 1, false) |
| 482 | MUX_CFG(DA830, EMB_D_26, 3, 16, 0xf, 1, false) |
| 483 | MUX_CFG(DA830, EMB_D_25, 3, 20, 0xf, 1, false) |
| 484 | MUX_CFG(DA830, EMB_D_24, 3, 24, 0xf, 1, false) |
| 485 | MUX_CFG(DA830, EMB_D_23, 3, 28, 0xf, 1, false) |
| 486 | MUX_CFG(DA830, EMB_D_22, 4, 0, 0xf, 1, false) |
| 487 | MUX_CFG(DA830, EMB_D_21, 4, 4, 0xf, 1, false) |
| 488 | MUX_CFG(DA830, EMB_D_20, 4, 8, 0xf, 1, false) |
| 489 | MUX_CFG(DA830, EMB_D_19, 4, 12, 0xf, 1, false) |
| 490 | MUX_CFG(DA830, EMB_D_18, 4, 16, 0xf, 1, false) |
| 491 | MUX_CFG(DA830, EMB_D_17, 4, 20, 0xf, 1, false) |
| 492 | MUX_CFG(DA830, EMB_D_16, 4, 24, 0xf, 1, false) |
| 493 | MUX_CFG(DA830, NEMB_WE_DQM_3, 4, 28, 0xf, 1, false) |
| 494 | MUX_CFG(DA830, NEMB_WE_DQM_2, 5, 0, 0xf, 1, false) |
| 495 | MUX_CFG(DA830, EMB_D_0, 5, 4, 0xf, 1, false) |
| 496 | MUX_CFG(DA830, EMB_D_1, 5, 8, 0xf, 1, false) |
| 497 | MUX_CFG(DA830, EMB_D_2, 5, 12, 0xf, 1, false) |
| 498 | MUX_CFG(DA830, EMB_D_3, 5, 16, 0xf, 1, false) |
| 499 | MUX_CFG(DA830, EMB_D_4, 5, 20, 0xf, 1, false) |
| 500 | MUX_CFG(DA830, EMB_D_5, 5, 24, 0xf, 1, false) |
| 501 | MUX_CFG(DA830, EMB_D_6, 5, 28, 0xf, 1, false) |
| 502 | MUX_CFG(DA830, GPIO6_0, 5, 4, 0xf, 8, false) |
| 503 | MUX_CFG(DA830, GPIO6_1, 5, 8, 0xf, 8, false) |
| 504 | MUX_CFG(DA830, GPIO6_2, 5, 12, 0xf, 8, false) |
| 505 | MUX_CFG(DA830, GPIO6_3, 5, 16, 0xf, 8, false) |
| 506 | MUX_CFG(DA830, GPIO6_4, 5, 20, 0xf, 8, false) |
| 507 | MUX_CFG(DA830, GPIO6_5, 5, 24, 0xf, 8, false) |
| 508 | MUX_CFG(DA830, GPIO6_6, 5, 28, 0xf, 8, false) |
| 509 | MUX_CFG(DA830, EMB_D_7, 6, 0, 0xf, 1, false) |
| 510 | MUX_CFG(DA830, EMB_D_8, 6, 4, 0xf, 1, false) |
| 511 | MUX_CFG(DA830, EMB_D_9, 6, 8, 0xf, 1, false) |
| 512 | MUX_CFG(DA830, EMB_D_10, 6, 12, 0xf, 1, false) |
| 513 | MUX_CFG(DA830, EMB_D_11, 6, 16, 0xf, 1, false) |
| 514 | MUX_CFG(DA830, EMB_D_12, 6, 20, 0xf, 1, false) |
| 515 | MUX_CFG(DA830, EMB_D_13, 6, 24, 0xf, 1, false) |
| 516 | MUX_CFG(DA830, EMB_D_14, 6, 28, 0xf, 1, false) |
| 517 | MUX_CFG(DA830, GPIO6_7, 6, 0, 0xf, 8, false) |
| 518 | MUX_CFG(DA830, GPIO6_8, 6, 4, 0xf, 8, false) |
| 519 | MUX_CFG(DA830, GPIO6_9, 6, 8, 0xf, 8, false) |
| 520 | MUX_CFG(DA830, GPIO6_10, 6, 12, 0xf, 8, false) |
| 521 | MUX_CFG(DA830, GPIO6_11, 6, 16, 0xf, 8, false) |
| 522 | MUX_CFG(DA830, GPIO6_12, 6, 20, 0xf, 8, false) |
| 523 | MUX_CFG(DA830, GPIO6_13, 6, 24, 0xf, 8, false) |
| 524 | MUX_CFG(DA830, GPIO6_14, 6, 28, 0xf, 8, false) |
| 525 | MUX_CFG(DA830, EMB_D_15, 7, 0, 0xf, 1, false) |
| 526 | MUX_CFG(DA830, NEMB_WE_DQM_1, 7, 4, 0xf, 1, false) |
| 527 | MUX_CFG(DA830, NEMB_WE_DQM_0, 7, 8, 0xf, 1, false) |
| 528 | MUX_CFG(DA830, SPI0_SOMI_0, 7, 12, 0xf, 1, false) |
| 529 | MUX_CFG(DA830, SPI0_SIMO_0, 7, 16, 0xf, 1, false) |
| 530 | MUX_CFG(DA830, SPI0_CLK, 7, 20, 0xf, 1, false) |
| 531 | MUX_CFG(DA830, NSPI0_ENA, 7, 24, 0xf, 1, false) |
| 532 | MUX_CFG(DA830, NSPI0_SCS_0, 7, 28, 0xf, 1, false) |
| 533 | MUX_CFG(DA830, EQEP0I, 7, 12, 0xf, 2, false) |
| 534 | MUX_CFG(DA830, EQEP0S, 7, 16, 0xf, 2, false) |
| 535 | MUX_CFG(DA830, EQEP1I, 7, 20, 0xf, 2, false) |
| 536 | MUX_CFG(DA830, NUART0_CTS, 7, 24, 0xf, 2, false) |
| 537 | MUX_CFG(DA830, NUART0_RTS, 7, 28, 0xf, 2, false) |
| 538 | MUX_CFG(DA830, EQEP0A, 7, 24, 0xf, 4, false) |
| 539 | MUX_CFG(DA830, EQEP0B, 7, 28, 0xf, 4, false) |
| 540 | MUX_CFG(DA830, GPIO6_15, 7, 0, 0xf, 8, false) |
| 541 | MUX_CFG(DA830, GPIO5_14, 7, 4, 0xf, 8, false) |
| 542 | MUX_CFG(DA830, GPIO5_15, 7, 8, 0xf, 8, false) |
| 543 | MUX_CFG(DA830, GPIO5_0, 7, 12, 0xf, 8, false) |
| 544 | MUX_CFG(DA830, GPIO5_1, 7, 16, 0xf, 8, false) |
| 545 | MUX_CFG(DA830, GPIO5_2, 7, 20, 0xf, 8, false) |
| 546 | MUX_CFG(DA830, GPIO5_3, 7, 24, 0xf, 8, false) |
| 547 | MUX_CFG(DA830, GPIO5_4, 7, 28, 0xf, 8, false) |
| 548 | MUX_CFG(DA830, SPI1_SOMI_0, 8, 0, 0xf, 1, false) |
| 549 | MUX_CFG(DA830, SPI1_SIMO_0, 8, 4, 0xf, 1, false) |
| 550 | MUX_CFG(DA830, SPI1_CLK, 8, 8, 0xf, 1, false) |
| 551 | MUX_CFG(DA830, UART0_RXD, 8, 12, 0xf, 1, false) |
| 552 | MUX_CFG(DA830, UART0_TXD, 8, 16, 0xf, 1, false) |
| 553 | MUX_CFG(DA830, AXR1_10, 8, 20, 0xf, 1, false) |
| 554 | MUX_CFG(DA830, AXR1_11, 8, 24, 0xf, 1, false) |
| 555 | MUX_CFG(DA830, NSPI1_ENA, 8, 28, 0xf, 1, false) |
| 556 | MUX_CFG(DA830, I2C1_SCL, 8, 0, 0xf, 2, false) |
| 557 | MUX_CFG(DA830, I2C1_SDA, 8, 4, 0xf, 2, false) |
| 558 | MUX_CFG(DA830, EQEP1S, 8, 8, 0xf, 2, false) |
| 559 | MUX_CFG(DA830, I2C0_SDA, 8, 12, 0xf, 2, false) |
| 560 | MUX_CFG(DA830, I2C0_SCL, 8, 16, 0xf, 2, false) |
| 561 | MUX_CFG(DA830, UART2_RXD, 8, 28, 0xf, 2, false) |
| 562 | MUX_CFG(DA830, TM64P0_IN12, 8, 12, 0xf, 4, false) |
| 563 | MUX_CFG(DA830, TM64P0_OUT12, 8, 16, 0xf, 4, false) |
| 564 | MUX_CFG(DA830, GPIO5_5, 8, 0, 0xf, 8, false) |
| 565 | MUX_CFG(DA830, GPIO5_6, 8, 4, 0xf, 8, false) |
| 566 | MUX_CFG(DA830, GPIO5_7, 8, 8, 0xf, 8, false) |
| 567 | MUX_CFG(DA830, GPIO5_8, 8, 12, 0xf, 8, false) |
| 568 | MUX_CFG(DA830, GPIO5_9, 8, 16, 0xf, 8, false) |
| 569 | MUX_CFG(DA830, GPIO5_10, 8, 20, 0xf, 8, false) |
| 570 | MUX_CFG(DA830, GPIO5_11, 8, 24, 0xf, 8, false) |
| 571 | MUX_CFG(DA830, GPIO5_12, 8, 28, 0xf, 8, false) |
| 572 | MUX_CFG(DA830, NSPI1_SCS_0, 9, 0, 0xf, 1, false) |
| 573 | MUX_CFG(DA830, USB0_DRVVBUS, 9, 4, 0xf, 1, false) |
| 574 | MUX_CFG(DA830, AHCLKX0, 9, 8, 0xf, 1, false) |
| 575 | MUX_CFG(DA830, ACLKX0, 9, 12, 0xf, 1, false) |
| 576 | MUX_CFG(DA830, AFSX0, 9, 16, 0xf, 1, false) |
| 577 | MUX_CFG(DA830, AHCLKR0, 9, 20, 0xf, 1, false) |
| 578 | MUX_CFG(DA830, ACLKR0, 9, 24, 0xf, 1, false) |
| 579 | MUX_CFG(DA830, AFSR0, 9, 28, 0xf, 1, false) |
| 580 | MUX_CFG(DA830, UART2_TXD, 9, 0, 0xf, 2, false) |
| 581 | MUX_CFG(DA830, AHCLKX2, 9, 8, 0xf, 2, false) |
| 582 | MUX_CFG(DA830, ECAP0_APWM0, 9, 12, 0xf, 2, false) |
| 583 | MUX_CFG(DA830, RMII_MHZ_50_CLK, 9, 20, 0xf, 2, false) |
| 584 | MUX_CFG(DA830, ECAP1_APWM1, 9, 24, 0xf, 2, false) |
| 585 | MUX_CFG(DA830, USB_REFCLKIN, 9, 8, 0xf, 4, false) |
| 586 | MUX_CFG(DA830, GPIO5_13, 9, 0, 0xf, 8, false) |
| 587 | MUX_CFG(DA830, GPIO4_15, 9, 4, 0xf, 8, false) |
| 588 | MUX_CFG(DA830, GPIO2_11, 9, 8, 0xf, 8, false) |
| 589 | MUX_CFG(DA830, GPIO2_12, 9, 12, 0xf, 8, false) |
| 590 | MUX_CFG(DA830, GPIO2_13, 9, 16, 0xf, 8, false) |
| 591 | MUX_CFG(DA830, GPIO2_14, 9, 20, 0xf, 8, false) |
| 592 | MUX_CFG(DA830, GPIO2_15, 9, 24, 0xf, 8, false) |
| 593 | MUX_CFG(DA830, GPIO3_12, 9, 28, 0xf, 8, false) |
| 594 | MUX_CFG(DA830, AMUTE0, 10, 0, 0xf, 1, false) |
| 595 | MUX_CFG(DA830, AXR0_0, 10, 4, 0xf, 1, false) |
| 596 | MUX_CFG(DA830, AXR0_1, 10, 8, 0xf, 1, false) |
| 597 | MUX_CFG(DA830, AXR0_2, 10, 12, 0xf, 1, false) |
| 598 | MUX_CFG(DA830, AXR0_3, 10, 16, 0xf, 1, false) |
| 599 | MUX_CFG(DA830, AXR0_4, 10, 20, 0xf, 1, false) |
| 600 | MUX_CFG(DA830, AXR0_5, 10, 24, 0xf, 1, false) |
| 601 | MUX_CFG(DA830, AXR0_6, 10, 28, 0xf, 1, false) |
| 602 | MUX_CFG(DA830, RMII_TXD_0, 10, 4, 0xf, 2, false) |
| 603 | MUX_CFG(DA830, RMII_TXD_1, 10, 8, 0xf, 2, false) |
| 604 | MUX_CFG(DA830, RMII_TXEN, 10, 12, 0xf, 2, false) |
| 605 | MUX_CFG(DA830, RMII_CRS_DV, 10, 16, 0xf, 2, false) |
| 606 | MUX_CFG(DA830, RMII_RXD_0, 10, 20, 0xf, 2, false) |
| 607 | MUX_CFG(DA830, RMII_RXD_1, 10, 24, 0xf, 2, false) |
| 608 | MUX_CFG(DA830, RMII_RXER, 10, 28, 0xf, 2, false) |
| 609 | MUX_CFG(DA830, AFSR2, 10, 4, 0xf, 4, false) |
| 610 | MUX_CFG(DA830, ACLKX2, 10, 8, 0xf, 4, false) |
| 611 | MUX_CFG(DA830, AXR2_3, 10, 12, 0xf, 4, false) |
| 612 | MUX_CFG(DA830, AXR2_2, 10, 16, 0xf, 4, false) |
| 613 | MUX_CFG(DA830, AXR2_1, 10, 20, 0xf, 4, false) |
| 614 | MUX_CFG(DA830, AFSX2, 10, 24, 0xf, 4, false) |
| 615 | MUX_CFG(DA830, ACLKR2, 10, 28, 0xf, 4, false) |
| 616 | MUX_CFG(DA830, NRESETOUT, 10, 0, 0xf, 8, false) |
| 617 | MUX_CFG(DA830, GPIO3_0, 10, 4, 0xf, 8, false) |
| 618 | MUX_CFG(DA830, GPIO3_1, 10, 8, 0xf, 8, false) |
| 619 | MUX_CFG(DA830, GPIO3_2, 10, 12, 0xf, 8, false) |
| 620 | MUX_CFG(DA830, GPIO3_3, 10, 16, 0xf, 8, false) |
| 621 | MUX_CFG(DA830, GPIO3_4, 10, 20, 0xf, 8, false) |
| 622 | MUX_CFG(DA830, GPIO3_5, 10, 24, 0xf, 8, false) |
| 623 | MUX_CFG(DA830, GPIO3_6, 10, 28, 0xf, 8, false) |
| 624 | MUX_CFG(DA830, AXR0_7, 11, 0, 0xf, 1, false) |
| 625 | MUX_CFG(DA830, AXR0_8, 11, 4, 0xf, 1, false) |
| 626 | MUX_CFG(DA830, UART1_RXD, 11, 8, 0xf, 1, false) |
| 627 | MUX_CFG(DA830, UART1_TXD, 11, 12, 0xf, 1, false) |
| 628 | MUX_CFG(DA830, AXR0_11, 11, 16, 0xf, 1, false) |
| 629 | MUX_CFG(DA830, AHCLKX1, 11, 20, 0xf, 1, false) |
| 630 | MUX_CFG(DA830, ACLKX1, 11, 24, 0xf, 1, false) |
| 631 | MUX_CFG(DA830, AFSX1, 11, 28, 0xf, 1, false) |
| 632 | MUX_CFG(DA830, MDIO_CLK, 11, 0, 0xf, 2, false) |
| 633 | MUX_CFG(DA830, MDIO_D, 11, 4, 0xf, 2, false) |
| 634 | MUX_CFG(DA830, AXR0_9, 11, 8, 0xf, 2, false) |
| 635 | MUX_CFG(DA830, AXR0_10, 11, 12, 0xf, 2, false) |
| 636 | MUX_CFG(DA830, EPWM0B, 11, 20, 0xf, 2, false) |
| 637 | MUX_CFG(DA830, EPWM0A, 11, 24, 0xf, 2, false) |
| 638 | MUX_CFG(DA830, EPWMSYNCI, 11, 28, 0xf, 2, false) |
| 639 | MUX_CFG(DA830, AXR2_0, 11, 16, 0xf, 4, false) |
| 640 | MUX_CFG(DA830, EPWMSYNC0, 11, 28, 0xf, 4, false) |
| 641 | MUX_CFG(DA830, GPIO3_7, 11, 0, 0xf, 8, false) |
| 642 | MUX_CFG(DA830, GPIO3_8, 11, 4, 0xf, 8, false) |
| 643 | MUX_CFG(DA830, GPIO3_9, 11, 8, 0xf, 8, false) |
| 644 | MUX_CFG(DA830, GPIO3_10, 11, 12, 0xf, 8, false) |
| 645 | MUX_CFG(DA830, GPIO3_11, 11, 16, 0xf, 8, false) |
| 646 | MUX_CFG(DA830, GPIO3_14, 11, 20, 0xf, 8, false) |
| 647 | MUX_CFG(DA830, GPIO3_15, 11, 24, 0xf, 8, false) |
| 648 | MUX_CFG(DA830, GPIO4_10, 11, 28, 0xf, 8, false) |
| 649 | MUX_CFG(DA830, AHCLKR1, 12, 0, 0xf, 1, false) |
| 650 | MUX_CFG(DA830, ACLKR1, 12, 4, 0xf, 1, false) |
| 651 | MUX_CFG(DA830, AFSR1, 12, 8, 0xf, 1, false) |
| 652 | MUX_CFG(DA830, AMUTE1, 12, 12, 0xf, 1, false) |
| 653 | MUX_CFG(DA830, AXR1_0, 12, 16, 0xf, 1, false) |
| 654 | MUX_CFG(DA830, AXR1_1, 12, 20, 0xf, 1, false) |
| 655 | MUX_CFG(DA830, AXR1_2, 12, 24, 0xf, 1, false) |
| 656 | MUX_CFG(DA830, AXR1_3, 12, 28, 0xf, 1, false) |
| 657 | MUX_CFG(DA830, ECAP2_APWM2, 12, 4, 0xf, 2, false) |
| 658 | MUX_CFG(DA830, EHRPWMGLUETZ, 12, 12, 0xf, 2, false) |
| 659 | MUX_CFG(DA830, EQEP1A, 12, 28, 0xf, 2, false) |
| 660 | MUX_CFG(DA830, GPIO4_11, 12, 0, 0xf, 8, false) |
| 661 | MUX_CFG(DA830, GPIO4_12, 12, 4, 0xf, 8, false) |
| 662 | MUX_CFG(DA830, GPIO4_13, 12, 8, 0xf, 8, false) |
| 663 | MUX_CFG(DA830, GPIO4_14, 12, 12, 0xf, 8, false) |
| 664 | MUX_CFG(DA830, GPIO4_0, 12, 16, 0xf, 8, false) |
| 665 | MUX_CFG(DA830, GPIO4_1, 12, 20, 0xf, 8, false) |
| 666 | MUX_CFG(DA830, GPIO4_2, 12, 24, 0xf, 8, false) |
| 667 | MUX_CFG(DA830, GPIO4_3, 12, 28, 0xf, 8, false) |
| 668 | MUX_CFG(DA830, AXR1_4, 13, 0, 0xf, 1, false) |
| 669 | MUX_CFG(DA830, AXR1_5, 13, 4, 0xf, 1, false) |
| 670 | MUX_CFG(DA830, AXR1_6, 13, 8, 0xf, 1, false) |
| 671 | MUX_CFG(DA830, AXR1_7, 13, 12, 0xf, 1, false) |
| 672 | MUX_CFG(DA830, AXR1_8, 13, 16, 0xf, 1, false) |
| 673 | MUX_CFG(DA830, AXR1_9, 13, 20, 0xf, 1, false) |
| 674 | MUX_CFG(DA830, EMA_D_0, 13, 24, 0xf, 1, false) |
| 675 | MUX_CFG(DA830, EMA_D_1, 13, 28, 0xf, 1, false) |
| 676 | MUX_CFG(DA830, EQEP1B, 13, 0, 0xf, 2, false) |
| 677 | MUX_CFG(DA830, EPWM2B, 13, 4, 0xf, 2, false) |
| 678 | MUX_CFG(DA830, EPWM2A, 13, 8, 0xf, 2, false) |
| 679 | MUX_CFG(DA830, EPWM1B, 13, 12, 0xf, 2, false) |
| 680 | MUX_CFG(DA830, EPWM1A, 13, 16, 0xf, 2, false) |
| 681 | MUX_CFG(DA830, MMCSD_DAT_0, 13, 24, 0xf, 2, false) |
| 682 | MUX_CFG(DA830, MMCSD_DAT_1, 13, 28, 0xf, 2, false) |
| 683 | MUX_CFG(DA830, UHPI_HD_0, 13, 24, 0xf, 4, false) |
| 684 | MUX_CFG(DA830, UHPI_HD_1, 13, 28, 0xf, 4, false) |
| 685 | MUX_CFG(DA830, GPIO4_4, 13, 0, 0xf, 8, false) |
| 686 | MUX_CFG(DA830, GPIO4_5, 13, 4, 0xf, 8, false) |
| 687 | MUX_CFG(DA830, GPIO4_6, 13, 8, 0xf, 8, false) |
| 688 | MUX_CFG(DA830, GPIO4_7, 13, 12, 0xf, 8, false) |
| 689 | MUX_CFG(DA830, GPIO4_8, 13, 16, 0xf, 8, false) |
| 690 | MUX_CFG(DA830, GPIO4_9, 13, 20, 0xf, 8, false) |
| 691 | MUX_CFG(DA830, GPIO0_0, 13, 24, 0xf, 8, false) |
| 692 | MUX_CFG(DA830, GPIO0_1, 13, 28, 0xf, 8, false) |
| 693 | MUX_CFG(DA830, EMA_D_2, 14, 0, 0xf, 1, false) |
| 694 | MUX_CFG(DA830, EMA_D_3, 14, 4, 0xf, 1, false) |
| 695 | MUX_CFG(DA830, EMA_D_4, 14, 8, 0xf, 1, false) |
| 696 | MUX_CFG(DA830, EMA_D_5, 14, 12, 0xf, 1, false) |
| 697 | MUX_CFG(DA830, EMA_D_6, 14, 16, 0xf, 1, false) |
| 698 | MUX_CFG(DA830, EMA_D_7, 14, 20, 0xf, 1, false) |
| 699 | MUX_CFG(DA830, EMA_D_8, 14, 24, 0xf, 1, false) |
| 700 | MUX_CFG(DA830, EMA_D_9, 14, 28, 0xf, 1, false) |
| 701 | MUX_CFG(DA830, MMCSD_DAT_2, 14, 0, 0xf, 2, false) |
| 702 | MUX_CFG(DA830, MMCSD_DAT_3, 14, 4, 0xf, 2, false) |
| 703 | MUX_CFG(DA830, MMCSD_DAT_4, 14, 8, 0xf, 2, false) |
| 704 | MUX_CFG(DA830, MMCSD_DAT_5, 14, 12, 0xf, 2, false) |
| 705 | MUX_CFG(DA830, MMCSD_DAT_6, 14, 16, 0xf, 2, false) |
| 706 | MUX_CFG(DA830, MMCSD_DAT_7, 14, 20, 0xf, 2, false) |
| 707 | MUX_CFG(DA830, UHPI_HD_8, 14, 24, 0xf, 2, false) |
| 708 | MUX_CFG(DA830, UHPI_HD_9, 14, 28, 0xf, 2, false) |
| 709 | MUX_CFG(DA830, UHPI_HD_2, 14, 0, 0xf, 4, false) |
| 710 | MUX_CFG(DA830, UHPI_HD_3, 14, 4, 0xf, 4, false) |
| 711 | MUX_CFG(DA830, UHPI_HD_4, 14, 8, 0xf, 4, false) |
| 712 | MUX_CFG(DA830, UHPI_HD_5, 14, 12, 0xf, 4, false) |
| 713 | MUX_CFG(DA830, UHPI_HD_6, 14, 16, 0xf, 4, false) |
| 714 | MUX_CFG(DA830, UHPI_HD_7, 14, 20, 0xf, 4, false) |
| 715 | MUX_CFG(DA830, LCD_D_8, 14, 24, 0xf, 4, false) |
| 716 | MUX_CFG(DA830, LCD_D_9, 14, 28, 0xf, 4, false) |
| 717 | MUX_CFG(DA830, GPIO0_2, 14, 0, 0xf, 8, false) |
| 718 | MUX_CFG(DA830, GPIO0_3, 14, 4, 0xf, 8, false) |
| 719 | MUX_CFG(DA830, GPIO0_4, 14, 8, 0xf, 8, false) |
| 720 | MUX_CFG(DA830, GPIO0_5, 14, 12, 0xf, 8, false) |
| 721 | MUX_CFG(DA830, GPIO0_6, 14, 16, 0xf, 8, false) |
| 722 | MUX_CFG(DA830, GPIO0_7, 14, 20, 0xf, 8, false) |
| 723 | MUX_CFG(DA830, GPIO0_8, 14, 24, 0xf, 8, false) |
| 724 | MUX_CFG(DA830, GPIO0_9, 14, 28, 0xf, 8, false) |
| 725 | MUX_CFG(DA830, EMA_D_10, 15, 0, 0xf, 1, false) |
| 726 | MUX_CFG(DA830, EMA_D_11, 15, 4, 0xf, 1, false) |
| 727 | MUX_CFG(DA830, EMA_D_12, 15, 8, 0xf, 1, false) |
| 728 | MUX_CFG(DA830, EMA_D_13, 15, 12, 0xf, 1, false) |
| 729 | MUX_CFG(DA830, EMA_D_14, 15, 16, 0xf, 1, false) |
| 730 | MUX_CFG(DA830, EMA_D_15, 15, 20, 0xf, 1, false) |
| 731 | MUX_CFG(DA830, EMA_A_0, 15, 24, 0xf, 1, false) |
| 732 | MUX_CFG(DA830, EMA_A_1, 15, 28, 0xf, 1, false) |
| 733 | MUX_CFG(DA830, UHPI_HD_10, 15, 0, 0xf, 2, false) |
| 734 | MUX_CFG(DA830, UHPI_HD_11, 15, 4, 0xf, 2, false) |
| 735 | MUX_CFG(DA830, UHPI_HD_12, 15, 8, 0xf, 2, false) |
| 736 | MUX_CFG(DA830, UHPI_HD_13, 15, 12, 0xf, 2, false) |
| 737 | MUX_CFG(DA830, UHPI_HD_14, 15, 16, 0xf, 2, false) |
| 738 | MUX_CFG(DA830, UHPI_HD_15, 15, 20, 0xf, 2, false) |
| 739 | MUX_CFG(DA830, LCD_D_7, 15, 24, 0xf, 2, false) |
| 740 | MUX_CFG(DA830, MMCSD_CLK, 15, 28, 0xf, 2, false) |
| 741 | MUX_CFG(DA830, LCD_D_10, 15, 0, 0xf, 4, false) |
| 742 | MUX_CFG(DA830, LCD_D_11, 15, 4, 0xf, 4, false) |
| 743 | MUX_CFG(DA830, LCD_D_12, 15, 8, 0xf, 4, false) |
| 744 | MUX_CFG(DA830, LCD_D_13, 15, 12, 0xf, 4, false) |
| 745 | MUX_CFG(DA830, LCD_D_14, 15, 16, 0xf, 4, false) |
| 746 | MUX_CFG(DA830, LCD_D_15, 15, 20, 0xf, 4, false) |
| 747 | MUX_CFG(DA830, UHPI_HCNTL0, 15, 28, 0xf, 4, false) |
| 748 | MUX_CFG(DA830, GPIO0_10, 15, 0, 0xf, 8, false) |
| 749 | MUX_CFG(DA830, GPIO0_11, 15, 4, 0xf, 8, false) |
| 750 | MUX_CFG(DA830, GPIO0_12, 15, 8, 0xf, 8, false) |
| 751 | MUX_CFG(DA830, GPIO0_13, 15, 12, 0xf, 8, false) |
| 752 | MUX_CFG(DA830, GPIO0_14, 15, 16, 0xf, 8, false) |
| 753 | MUX_CFG(DA830, GPIO0_15, 15, 20, 0xf, 8, false) |
| 754 | MUX_CFG(DA830, GPIO1_0, 15, 24, 0xf, 8, false) |
| 755 | MUX_CFG(DA830, GPIO1_1, 15, 28, 0xf, 8, false) |
| 756 | MUX_CFG(DA830, EMA_A_2, 16, 0, 0xf, 1, false) |
| 757 | MUX_CFG(DA830, EMA_A_3, 16, 4, 0xf, 1, false) |
| 758 | MUX_CFG(DA830, EMA_A_4, 16, 8, 0xf, 1, false) |
| 759 | MUX_CFG(DA830, EMA_A_5, 16, 12, 0xf, 1, false) |
| 760 | MUX_CFG(DA830, EMA_A_6, 16, 16, 0xf, 1, false) |
| 761 | MUX_CFG(DA830, EMA_A_7, 16, 20, 0xf, 1, false) |
| 762 | MUX_CFG(DA830, EMA_A_8, 16, 24, 0xf, 1, false) |
| 763 | MUX_CFG(DA830, EMA_A_9, 16, 28, 0xf, 1, false) |
| 764 | MUX_CFG(DA830, MMCSD_CMD, 16, 0, 0xf, 2, false) |
| 765 | MUX_CFG(DA830, LCD_D_6, 16, 4, 0xf, 2, false) |
| 766 | MUX_CFG(DA830, LCD_D_3, 16, 8, 0xf, 2, false) |
| 767 | MUX_CFG(DA830, LCD_D_2, 16, 12, 0xf, 2, false) |
| 768 | MUX_CFG(DA830, LCD_D_1, 16, 16, 0xf, 2, false) |
| 769 | MUX_CFG(DA830, LCD_D_0, 16, 20, 0xf, 2, false) |
| 770 | MUX_CFG(DA830, LCD_PCLK, 16, 24, 0xf, 2, false) |
| 771 | MUX_CFG(DA830, LCD_HSYNC, 16, 28, 0xf, 2, false) |
| 772 | MUX_CFG(DA830, UHPI_HCNTL1, 16, 0, 0xf, 4, false) |
| 773 | MUX_CFG(DA830, GPIO1_2, 16, 0, 0xf, 8, false) |
| 774 | MUX_CFG(DA830, GPIO1_3, 16, 4, 0xf, 8, false) |
| 775 | MUX_CFG(DA830, GPIO1_4, 16, 8, 0xf, 8, false) |
| 776 | MUX_CFG(DA830, GPIO1_5, 16, 12, 0xf, 8, false) |
| 777 | MUX_CFG(DA830, GPIO1_6, 16, 16, 0xf, 8, false) |
| 778 | MUX_CFG(DA830, GPIO1_7, 16, 20, 0xf, 8, false) |
| 779 | MUX_CFG(DA830, GPIO1_8, 16, 24, 0xf, 8, false) |
| 780 | MUX_CFG(DA830, GPIO1_9, 16, 28, 0xf, 8, false) |
| 781 | MUX_CFG(DA830, EMA_A_10, 17, 0, 0xf, 1, false) |
| 782 | MUX_CFG(DA830, EMA_A_11, 17, 4, 0xf, 1, false) |
| 783 | MUX_CFG(DA830, EMA_A_12, 17, 8, 0xf, 1, false) |
| 784 | MUX_CFG(DA830, EMA_BA_1, 17, 12, 0xf, 1, false) |
| 785 | MUX_CFG(DA830, EMA_BA_0, 17, 16, 0xf, 1, false) |
| 786 | MUX_CFG(DA830, EMA_CLK, 17, 20, 0xf, 1, false) |
| 787 | MUX_CFG(DA830, EMA_SDCKE, 17, 24, 0xf, 1, false) |
| 788 | MUX_CFG(DA830, NEMA_CAS, 17, 28, 0xf, 1, false) |
| 789 | MUX_CFG(DA830, LCD_VSYNC, 17, 0, 0xf, 2, false) |
| 790 | MUX_CFG(DA830, NLCD_AC_ENB_CS, 17, 4, 0xf, 2, false) |
| 791 | MUX_CFG(DA830, LCD_MCLK, 17, 8, 0xf, 2, false) |
| 792 | MUX_CFG(DA830, LCD_D_5, 17, 12, 0xf, 2, false) |
| 793 | MUX_CFG(DA830, LCD_D_4, 17, 16, 0xf, 2, false) |
| 794 | MUX_CFG(DA830, OBSCLK, 17, 20, 0xf, 2, false) |
| 795 | MUX_CFG(DA830, NEMA_CS_4, 17, 28, 0xf, 2, false) |
| 796 | MUX_CFG(DA830, UHPI_HHWIL, 17, 12, 0xf, 4, false) |
| 797 | MUX_CFG(DA830, AHCLKR2, 17, 20, 0xf, 4, false) |
| 798 | MUX_CFG(DA830, GPIO1_10, 17, 0, 0xf, 8, false) |
| 799 | MUX_CFG(DA830, GPIO1_11, 17, 4, 0xf, 8, false) |
| 800 | MUX_CFG(DA830, GPIO1_12, 17, 8, 0xf, 8, false) |
| 801 | MUX_CFG(DA830, GPIO1_13, 17, 12, 0xf, 8, false) |
| 802 | MUX_CFG(DA830, GPIO1_14, 17, 16, 0xf, 8, false) |
| 803 | MUX_CFG(DA830, GPIO1_15, 17, 20, 0xf, 8, false) |
| 804 | MUX_CFG(DA830, GPIO2_0, 17, 24, 0xf, 8, false) |
| 805 | MUX_CFG(DA830, GPIO2_1, 17, 28, 0xf, 8, false) |
| 806 | MUX_CFG(DA830, NEMA_RAS, 18, 0, 0xf, 1, false) |
| 807 | MUX_CFG(DA830, NEMA_WE, 18, 4, 0xf, 1, false) |
| 808 | MUX_CFG(DA830, NEMA_CS_0, 18, 8, 0xf, 1, false) |
| 809 | MUX_CFG(DA830, NEMA_CS_2, 18, 12, 0xf, 1, false) |
| 810 | MUX_CFG(DA830, NEMA_CS_3, 18, 16, 0xf, 1, false) |
| 811 | MUX_CFG(DA830, NEMA_OE, 18, 20, 0xf, 1, false) |
| 812 | MUX_CFG(DA830, NEMA_WE_DQM_1, 18, 24, 0xf, 1, false) |
| 813 | MUX_CFG(DA830, NEMA_WE_DQM_0, 18, 28, 0xf, 1, false) |
| 814 | MUX_CFG(DA830, NEMA_CS_5, 18, 0, 0xf, 2, false) |
| 815 | MUX_CFG(DA830, UHPI_HRNW, 18, 4, 0xf, 2, false) |
| 816 | MUX_CFG(DA830, NUHPI_HAS, 18, 8, 0xf, 2, false) |
| 817 | MUX_CFG(DA830, NUHPI_HCS, 18, 12, 0xf, 2, false) |
| 818 | MUX_CFG(DA830, NUHPI_HDS1, 18, 20, 0xf, 2, false) |
| 819 | MUX_CFG(DA830, NUHPI_HDS2, 18, 24, 0xf, 2, false) |
| 820 | MUX_CFG(DA830, NUHPI_HINT, 18, 28, 0xf, 2, false) |
| 821 | MUX_CFG(DA830, AXR0_12, 18, 4, 0xf, 4, false) |
| 822 | MUX_CFG(DA830, AMUTE2, 18, 16, 0xf, 4, false) |
| 823 | MUX_CFG(DA830, AXR0_13, 18, 20, 0xf, 4, false) |
| 824 | MUX_CFG(DA830, AXR0_14, 18, 24, 0xf, 4, false) |
| 825 | MUX_CFG(DA830, AXR0_15, 18, 28, 0xf, 4, false) |
| 826 | MUX_CFG(DA830, GPIO2_2, 18, 0, 0xf, 8, false) |
| 827 | MUX_CFG(DA830, GPIO2_3, 18, 4, 0xf, 8, false) |
| 828 | MUX_CFG(DA830, GPIO2_4, 18, 8, 0xf, 8, false) |
| 829 | MUX_CFG(DA830, GPIO2_5, 18, 12, 0xf, 8, false) |
| 830 | MUX_CFG(DA830, GPIO2_6, 18, 16, 0xf, 8, false) |
| 831 | MUX_CFG(DA830, GPIO2_7, 18, 20, 0xf, 8, false) |
| 832 | MUX_CFG(DA830, GPIO2_8, 18, 24, 0xf, 8, false) |
| 833 | MUX_CFG(DA830, GPIO2_9, 18, 28, 0xf, 8, false) |
| 834 | MUX_CFG(DA830, EMA_WAIT_0, 19, 0, 0xf, 1, false) |
| 835 | MUX_CFG(DA830, NUHPI_HRDY, 19, 0, 0xf, 2, false) |
| 836 | MUX_CFG(DA830, GPIO2_10, 19, 0, 0xf, 8, false) |
| 837 | #endif |
| 838 | }; |
| 839 | |
| 840 | const short da830_emif25_pins[] __initdata = { |
| 841 | DA830_EMA_D_0, DA830_EMA_D_1, DA830_EMA_D_2, DA830_EMA_D_3, |
| 842 | DA830_EMA_D_4, DA830_EMA_D_5, DA830_EMA_D_6, DA830_EMA_D_7, |
| 843 | DA830_EMA_D_8, DA830_EMA_D_9, DA830_EMA_D_10, DA830_EMA_D_11, |
| 844 | DA830_EMA_D_12, DA830_EMA_D_13, DA830_EMA_D_14, DA830_EMA_D_15, |
| 845 | DA830_EMA_A_0, DA830_EMA_A_1, DA830_EMA_A_2, DA830_EMA_A_3, |
| 846 | DA830_EMA_A_4, DA830_EMA_A_5, DA830_EMA_A_6, DA830_EMA_A_7, |
| 847 | DA830_EMA_A_8, DA830_EMA_A_9, DA830_EMA_A_10, DA830_EMA_A_11, |
| 848 | DA830_EMA_A_12, DA830_EMA_BA_0, DA830_EMA_BA_1, DA830_EMA_CLK, |
| 849 | DA830_EMA_SDCKE, DA830_NEMA_CS_4, DA830_NEMA_CS_5, DA830_NEMA_WE, |
| 850 | DA830_NEMA_CS_0, DA830_NEMA_CS_2, DA830_NEMA_CS_3, DA830_NEMA_OE, |
| 851 | DA830_NEMA_WE_DQM_1, DA830_NEMA_WE_DQM_0, DA830_EMA_WAIT_0, |
| 852 | -1 |
| 853 | }; |
| 854 | |
| 855 | const short da830_spi0_pins[] __initdata = { |
| 856 | DA830_SPI0_SOMI_0, DA830_SPI0_SIMO_0, DA830_SPI0_CLK, DA830_NSPI0_ENA, |
| 857 | DA830_NSPI0_SCS_0, |
| 858 | -1 |
| 859 | }; |
| 860 | |
| 861 | const short da830_spi1_pins[] __initdata = { |
| 862 | DA830_SPI1_SOMI_0, DA830_SPI1_SIMO_0, DA830_SPI1_CLK, DA830_NSPI1_ENA, |
| 863 | DA830_NSPI1_SCS_0, |
| 864 | -1 |
| 865 | }; |
| 866 | |
| 867 | const short da830_mmc_sd_pins[] __initdata = { |
| 868 | DA830_MMCSD_DAT_0, DA830_MMCSD_DAT_1, DA830_MMCSD_DAT_2, |
| 869 | DA830_MMCSD_DAT_3, DA830_MMCSD_DAT_4, DA830_MMCSD_DAT_5, |
| 870 | DA830_MMCSD_DAT_6, DA830_MMCSD_DAT_7, DA830_MMCSD_CLK, |
| 871 | DA830_MMCSD_CMD, |
| 872 | -1 |
| 873 | }; |
| 874 | |
| 875 | const short da830_uart0_pins[] __initdata = { |
| 876 | DA830_NUART0_CTS, DA830_NUART0_RTS, DA830_UART0_RXD, DA830_UART0_TXD, |
| 877 | -1 |
| 878 | }; |
| 879 | |
| 880 | const short da830_uart1_pins[] __initdata = { |
| 881 | DA830_UART1_RXD, DA830_UART1_TXD, |
| 882 | -1 |
| 883 | }; |
| 884 | |
| 885 | const short da830_uart2_pins[] __initdata = { |
| 886 | DA830_UART2_RXD, DA830_UART2_TXD, |
| 887 | -1 |
| 888 | }; |
| 889 | |
| 890 | const short da830_usb20_pins[] __initdata = { |
| 891 | DA830_USB0_DRVVBUS, DA830_USB_REFCLKIN, |
| 892 | -1 |
| 893 | }; |
| 894 | |
| 895 | const short da830_usb11_pins[] __initdata = { |
| 896 | DA830_USB_REFCLKIN, |
| 897 | -1 |
| 898 | }; |
| 899 | |
| 900 | const short da830_uhpi_pins[] __initdata = { |
| 901 | DA830_UHPI_HD_0, DA830_UHPI_HD_1, DA830_UHPI_HD_2, DA830_UHPI_HD_3, |
| 902 | DA830_UHPI_HD_4, DA830_UHPI_HD_5, DA830_UHPI_HD_6, DA830_UHPI_HD_7, |
| 903 | DA830_UHPI_HD_8, DA830_UHPI_HD_9, DA830_UHPI_HD_10, DA830_UHPI_HD_11, |
| 904 | DA830_UHPI_HD_12, DA830_UHPI_HD_13, DA830_UHPI_HD_14, DA830_UHPI_HD_15, |
| 905 | DA830_UHPI_HCNTL0, DA830_UHPI_HCNTL1, DA830_UHPI_HHWIL, DA830_UHPI_HRNW, |
| 906 | DA830_NUHPI_HAS, DA830_NUHPI_HCS, DA830_NUHPI_HDS1, DA830_NUHPI_HDS2, |
| 907 | DA830_NUHPI_HINT, DA830_NUHPI_HRDY, |
| 908 | -1 |
| 909 | }; |
| 910 | |
| 911 | const short da830_cpgmac_pins[] __initdata = { |
| 912 | DA830_RMII_TXD_0, DA830_RMII_TXD_1, DA830_RMII_TXEN, DA830_RMII_CRS_DV, |
| 913 | DA830_RMII_RXD_0, DA830_RMII_RXD_1, DA830_RMII_RXER, DA830_MDIO_CLK, |
| 914 | DA830_MDIO_D, |
| 915 | -1 |
| 916 | }; |
| 917 | |
| 918 | const short da830_emif3c_pins[] __initdata = { |
| 919 | DA830_EMB_SDCKE, DA830_EMB_CLK_GLUE, DA830_EMB_CLK, DA830_NEMB_CS_0, |
| 920 | DA830_NEMB_CAS, DA830_NEMB_RAS, DA830_NEMB_WE, DA830_EMB_BA_1, |
| 921 | DA830_EMB_BA_0, DA830_EMB_A_0, DA830_EMB_A_1, DA830_EMB_A_2, |
| 922 | DA830_EMB_A_3, DA830_EMB_A_4, DA830_EMB_A_5, DA830_EMB_A_6, |
| 923 | DA830_EMB_A_7, DA830_EMB_A_8, DA830_EMB_A_9, DA830_EMB_A_10, |
| 924 | DA830_EMB_A_11, DA830_EMB_A_12, DA830_NEMB_WE_DQM_3, |
| 925 | DA830_NEMB_WE_DQM_2, DA830_EMB_D_0, DA830_EMB_D_1, DA830_EMB_D_2, |
| 926 | DA830_EMB_D_3, DA830_EMB_D_4, DA830_EMB_D_5, DA830_EMB_D_6, |
| 927 | DA830_EMB_D_7, DA830_EMB_D_8, DA830_EMB_D_9, DA830_EMB_D_10, |
| 928 | DA830_EMB_D_11, DA830_EMB_D_12, DA830_EMB_D_13, DA830_EMB_D_14, |
| 929 | DA830_EMB_D_15, DA830_EMB_D_16, DA830_EMB_D_17, DA830_EMB_D_18, |
| 930 | DA830_EMB_D_19, DA830_EMB_D_20, DA830_EMB_D_21, DA830_EMB_D_22, |
| 931 | DA830_EMB_D_23, DA830_EMB_D_24, DA830_EMB_D_25, DA830_EMB_D_26, |
| 932 | DA830_EMB_D_27, DA830_EMB_D_28, DA830_EMB_D_29, DA830_EMB_D_30, |
| 933 | DA830_EMB_D_31, DA830_NEMB_WE_DQM_1, DA830_NEMB_WE_DQM_0, |
| 934 | -1 |
| 935 | }; |
| 936 | |
| 937 | const short da830_mcasp0_pins[] __initdata = { |
| 938 | DA830_AHCLKX0, DA830_ACLKX0, DA830_AFSX0, |
| 939 | DA830_AHCLKR0, DA830_ACLKR0, DA830_AFSR0, DA830_AMUTE0, |
| 940 | DA830_AXR0_0, DA830_AXR0_1, DA830_AXR0_2, DA830_AXR0_3, |
| 941 | DA830_AXR0_4, DA830_AXR0_5, DA830_AXR0_6, DA830_AXR0_7, |
| 942 | DA830_AXR0_8, DA830_AXR0_9, DA830_AXR0_10, DA830_AXR0_11, |
| 943 | DA830_AXR0_12, DA830_AXR0_13, DA830_AXR0_14, DA830_AXR0_15, |
| 944 | -1 |
| 945 | }; |
| 946 | |
| 947 | const short da830_mcasp1_pins[] __initdata = { |
| 948 | DA830_AHCLKX1, DA830_ACLKX1, DA830_AFSX1, |
| 949 | DA830_AHCLKR1, DA830_ACLKR1, DA830_AFSR1, DA830_AMUTE1, |
| 950 | DA830_AXR1_0, DA830_AXR1_1, DA830_AXR1_2, DA830_AXR1_3, |
| 951 | DA830_AXR1_4, DA830_AXR1_5, DA830_AXR1_6, DA830_AXR1_7, |
| 952 | DA830_AXR1_8, DA830_AXR1_9, DA830_AXR1_10, DA830_AXR1_11, |
| 953 | -1 |
| 954 | }; |
| 955 | |
| 956 | const short da830_mcasp2_pins[] __initdata = { |
| 957 | DA830_AHCLKX2, DA830_ACLKX2, DA830_AFSX2, |
| 958 | DA830_AHCLKR2, DA830_ACLKR2, DA830_AFSR2, DA830_AMUTE2, |
| 959 | DA830_AXR2_0, DA830_AXR2_1, DA830_AXR2_2, DA830_AXR2_3, |
| 960 | -1 |
| 961 | }; |
| 962 | |
| 963 | const short da830_i2c0_pins[] __initdata = { |
| 964 | DA830_I2C0_SDA, DA830_I2C0_SCL, |
| 965 | -1 |
| 966 | }; |
| 967 | |
| 968 | const short da830_i2c1_pins[] __initdata = { |
| 969 | DA830_I2C1_SCL, DA830_I2C1_SDA, |
| 970 | -1 |
| 971 | }; |
| 972 | |
| 973 | const short da830_lcdcntl_pins[] __initdata = { |
| 974 | DA830_LCD_D_0, DA830_LCD_D_1, DA830_LCD_D_2, DA830_LCD_D_3, |
| 975 | DA830_LCD_D_4, DA830_LCD_D_5, DA830_LCD_D_6, DA830_LCD_D_7, |
| 976 | DA830_LCD_D_8, DA830_LCD_D_9, DA830_LCD_D_10, DA830_LCD_D_11, |
| 977 | DA830_LCD_D_12, DA830_LCD_D_13, DA830_LCD_D_14, DA830_LCD_D_15, |
| 978 | DA830_LCD_PCLK, DA830_LCD_HSYNC, DA830_LCD_VSYNC, DA830_NLCD_AC_ENB_CS, |
| 979 | DA830_LCD_MCLK, |
| 980 | -1 |
| 981 | }; |
| 982 | |
| 983 | const short da830_pwm_pins[] __initdata = { |
| 984 | DA830_ECAP0_APWM0, DA830_ECAP1_APWM1, DA830_EPWM0B, DA830_EPWM0A, |
| 985 | DA830_EPWMSYNCI, DA830_EPWMSYNC0, DA830_ECAP2_APWM2, DA830_EHRPWMGLUETZ, |
| 986 | DA830_EPWM2B, DA830_EPWM2A, DA830_EPWM1B, DA830_EPWM1A, |
| 987 | -1 |
| 988 | }; |
| 989 | |
| 990 | const short da830_ecap0_pins[] __initdata = { |
| 991 | DA830_ECAP0_APWM0, |
| 992 | -1 |
| 993 | }; |
| 994 | |
| 995 | const short da830_ecap1_pins[] __initdata = { |
| 996 | DA830_ECAP1_APWM1, |
| 997 | -1 |
| 998 | }; |
| 999 | |
| 1000 | const short da830_ecap2_pins[] __initdata = { |
| 1001 | DA830_ECAP2_APWM2, |
| 1002 | -1 |
| 1003 | }; |
| 1004 | |
| 1005 | const short da830_eqep0_pins[] __initdata = { |
| 1006 | DA830_EQEP0I, DA830_EQEP0S, DA830_EQEP0A, DA830_EQEP0B, |
| 1007 | -1 |
| 1008 | }; |
| 1009 | |
| 1010 | const short da830_eqep1_pins[] __initdata = { |
| 1011 | DA830_EQEP1I, DA830_EQEP1S, DA830_EQEP1A, DA830_EQEP1B, |
| 1012 | -1 |
| 1013 | }; |
| 1014 | |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 1015 | /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */ |
| 1016 | static u8 da830_default_priorities[DA830_N_CP_INTC_IRQ] = { |
| 1017 | [IRQ_DA8XX_COMMTX] = 7, |
| 1018 | [IRQ_DA8XX_COMMRX] = 7, |
| 1019 | [IRQ_DA8XX_NINT] = 7, |
| 1020 | [IRQ_DA8XX_EVTOUT0] = 7, |
| 1021 | [IRQ_DA8XX_EVTOUT1] = 7, |
| 1022 | [IRQ_DA8XX_EVTOUT2] = 7, |
| 1023 | [IRQ_DA8XX_EVTOUT3] = 7, |
| 1024 | [IRQ_DA8XX_EVTOUT4] = 7, |
| 1025 | [IRQ_DA8XX_EVTOUT5] = 7, |
| 1026 | [IRQ_DA8XX_EVTOUT6] = 7, |
| 1027 | [IRQ_DA8XX_EVTOUT6] = 7, |
| 1028 | [IRQ_DA8XX_EVTOUT7] = 7, |
| 1029 | [IRQ_DA8XX_CCINT0] = 7, |
| 1030 | [IRQ_DA8XX_CCERRINT] = 7, |
| 1031 | [IRQ_DA8XX_TCERRINT0] = 7, |
| 1032 | [IRQ_DA8XX_AEMIFINT] = 7, |
| 1033 | [IRQ_DA8XX_I2CINT0] = 7, |
| 1034 | [IRQ_DA8XX_MMCSDINT0] = 7, |
| 1035 | [IRQ_DA8XX_MMCSDINT1] = 7, |
| 1036 | [IRQ_DA8XX_ALLINT0] = 7, |
| 1037 | [IRQ_DA8XX_RTC] = 7, |
| 1038 | [IRQ_DA8XX_SPINT0] = 7, |
| 1039 | [IRQ_DA8XX_TINT12_0] = 7, |
| 1040 | [IRQ_DA8XX_TINT34_0] = 7, |
| 1041 | [IRQ_DA8XX_TINT12_1] = 7, |
| 1042 | [IRQ_DA8XX_TINT34_1] = 7, |
| 1043 | [IRQ_DA8XX_UARTINT0] = 7, |
| 1044 | [IRQ_DA8XX_KEYMGRINT] = 7, |
| 1045 | [IRQ_DA8XX_SECINT] = 7, |
| 1046 | [IRQ_DA8XX_SECKEYERR] = 7, |
| 1047 | [IRQ_DA830_MPUERR] = 7, |
| 1048 | [IRQ_DA830_IOPUERR] = 7, |
| 1049 | [IRQ_DA830_BOOTCFGERR] = 7, |
| 1050 | [IRQ_DA8XX_CHIPINT0] = 7, |
| 1051 | [IRQ_DA8XX_CHIPINT1] = 7, |
| 1052 | [IRQ_DA8XX_CHIPINT2] = 7, |
| 1053 | [IRQ_DA8XX_CHIPINT3] = 7, |
| 1054 | [IRQ_DA8XX_TCERRINT1] = 7, |
| 1055 | [IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7, |
| 1056 | [IRQ_DA8XX_C0_RX_PULSE] = 7, |
| 1057 | [IRQ_DA8XX_C0_TX_PULSE] = 7, |
| 1058 | [IRQ_DA8XX_C0_MISC_PULSE] = 7, |
| 1059 | [IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7, |
| 1060 | [IRQ_DA8XX_C1_RX_PULSE] = 7, |
| 1061 | [IRQ_DA8XX_C1_TX_PULSE] = 7, |
| 1062 | [IRQ_DA8XX_C1_MISC_PULSE] = 7, |
| 1063 | [IRQ_DA8XX_MEMERR] = 7, |
| 1064 | [IRQ_DA8XX_GPIO0] = 7, |
| 1065 | [IRQ_DA8XX_GPIO1] = 7, |
| 1066 | [IRQ_DA8XX_GPIO2] = 7, |
| 1067 | [IRQ_DA8XX_GPIO3] = 7, |
| 1068 | [IRQ_DA8XX_GPIO4] = 7, |
| 1069 | [IRQ_DA8XX_GPIO5] = 7, |
| 1070 | [IRQ_DA8XX_GPIO6] = 7, |
| 1071 | [IRQ_DA8XX_GPIO7] = 7, |
| 1072 | [IRQ_DA8XX_GPIO8] = 7, |
| 1073 | [IRQ_DA8XX_I2CINT1] = 7, |
| 1074 | [IRQ_DA8XX_LCDINT] = 7, |
| 1075 | [IRQ_DA8XX_UARTINT1] = 7, |
| 1076 | [IRQ_DA8XX_MCASPINT] = 7, |
| 1077 | [IRQ_DA8XX_ALLINT1] = 7, |
| 1078 | [IRQ_DA8XX_SPINT1] = 7, |
| 1079 | [IRQ_DA8XX_UHPI_INT1] = 7, |
| 1080 | [IRQ_DA8XX_USB_INT] = 7, |
| 1081 | [IRQ_DA8XX_IRQN] = 7, |
| 1082 | [IRQ_DA8XX_RWAKEUP] = 7, |
| 1083 | [IRQ_DA8XX_UARTINT2] = 7, |
| 1084 | [IRQ_DA8XX_DFTSSINT] = 7, |
| 1085 | [IRQ_DA8XX_EHRPWM0] = 7, |
| 1086 | [IRQ_DA8XX_EHRPWM0TZ] = 7, |
| 1087 | [IRQ_DA8XX_EHRPWM1] = 7, |
| 1088 | [IRQ_DA8XX_EHRPWM1TZ] = 7, |
| 1089 | [IRQ_DA830_EHRPWM2] = 7, |
| 1090 | [IRQ_DA830_EHRPWM2TZ] = 7, |
| 1091 | [IRQ_DA8XX_ECAP0] = 7, |
| 1092 | [IRQ_DA8XX_ECAP1] = 7, |
| 1093 | [IRQ_DA8XX_ECAP2] = 7, |
| 1094 | [IRQ_DA830_EQEP0] = 7, |
| 1095 | [IRQ_DA830_EQEP1] = 7, |
| 1096 | [IRQ_DA830_T12CMPINT0_0] = 7, |
| 1097 | [IRQ_DA830_T12CMPINT1_0] = 7, |
| 1098 | [IRQ_DA830_T12CMPINT2_0] = 7, |
| 1099 | [IRQ_DA830_T12CMPINT3_0] = 7, |
| 1100 | [IRQ_DA830_T12CMPINT4_0] = 7, |
| 1101 | [IRQ_DA830_T12CMPINT5_0] = 7, |
| 1102 | [IRQ_DA830_T12CMPINT6_0] = 7, |
| 1103 | [IRQ_DA830_T12CMPINT7_0] = 7, |
| 1104 | [IRQ_DA830_T12CMPINT0_1] = 7, |
| 1105 | [IRQ_DA830_T12CMPINT1_1] = 7, |
| 1106 | [IRQ_DA830_T12CMPINT2_1] = 7, |
| 1107 | [IRQ_DA830_T12CMPINT3_1] = 7, |
| 1108 | [IRQ_DA830_T12CMPINT4_1] = 7, |
| 1109 | [IRQ_DA830_T12CMPINT5_1] = 7, |
| 1110 | [IRQ_DA830_T12CMPINT6_1] = 7, |
| 1111 | [IRQ_DA830_T12CMPINT7_1] = 7, |
| 1112 | [IRQ_DA8XX_ARMCLKSTOPREQ] = 7, |
| 1113 | }; |
| 1114 | |
| 1115 | static struct map_desc da830_io_desc[] = { |
| 1116 | { |
| 1117 | .virtual = IO_VIRT, |
| 1118 | .pfn = __phys_to_pfn(IO_PHYS), |
| 1119 | .length = IO_SIZE, |
| 1120 | .type = MT_DEVICE |
| 1121 | }, |
| 1122 | { |
| 1123 | .virtual = DA8XX_CP_INTC_VIRT, |
| 1124 | .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE), |
| 1125 | .length = DA8XX_CP_INTC_SIZE, |
| 1126 | .type = MT_DEVICE |
| 1127 | }, |
| 1128 | }; |
| 1129 | |
Cyril Chemparathy | e4c822c | 2010-05-07 17:06:36 -0400 | [diff] [blame] | 1130 | static u32 da830_psc_bases[] = { DA8XX_PSC0_BASE, DA8XX_PSC1_BASE }; |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 1131 | |
| 1132 | /* Contents of JTAG ID register used to identify exact cpu type */ |
| 1133 | static struct davinci_id da830_ids[] = { |
| 1134 | { |
| 1135 | .variant = 0x0, |
| 1136 | .part_no = 0xb7df, |
| 1137 | .manufacturer = 0x017, /* 0x02f >> 1 */ |
| 1138 | .cpu_id = DAVINCI_CPU_ID_DA830, |
Kevin Hilman | f2024a9 | 2009-09-29 11:09:21 -0700 | [diff] [blame] | 1139 | .name = "da830/omap-l137 rev1.0", |
| 1140 | }, |
| 1141 | { |
| 1142 | .variant = 0x8, |
| 1143 | .part_no = 0xb7df, |
| 1144 | .manufacturer = 0x017, |
| 1145 | .cpu_id = DAVINCI_CPU_ID_DA830, |
| 1146 | .name = "da830/omap-l137 rev1.1", |
| 1147 | }, |
| 1148 | { |
| 1149 | .variant = 0x9, |
| 1150 | .part_no = 0xb7df, |
| 1151 | .manufacturer = 0x017, |
| 1152 | .cpu_id = DAVINCI_CPU_ID_DA830, |
| 1153 | .name = "da830/omap-l137 rev2.0", |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 1154 | }, |
| 1155 | }; |
| 1156 | |
| 1157 | static struct davinci_timer_instance da830_timer_instance[2] = { |
| 1158 | { |
Cyril Chemparathy | 1bcd38a | 2010-05-07 17:06:35 -0400 | [diff] [blame] | 1159 | .base = DA8XX_TIMER64P0_BASE, |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 1160 | .bottom_irq = IRQ_DA8XX_TINT12_0, |
| 1161 | .top_irq = IRQ_DA8XX_TINT34_0, |
| 1162 | .cmp_off = DA830_CMP12_0, |
| 1163 | .cmp_irq = IRQ_DA830_T12CMPINT0_0, |
| 1164 | }, |
| 1165 | { |
Cyril Chemparathy | 1bcd38a | 2010-05-07 17:06:35 -0400 | [diff] [blame] | 1166 | .base = DA8XX_TIMER64P1_BASE, |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 1167 | .bottom_irq = IRQ_DA8XX_TINT12_1, |
| 1168 | .top_irq = IRQ_DA8XX_TINT34_1, |
| 1169 | .cmp_off = DA830_CMP12_0, |
| 1170 | .cmp_irq = IRQ_DA830_T12CMPINT0_1, |
| 1171 | }, |
| 1172 | }; |
| 1173 | |
| 1174 | /* |
| 1175 | * T0_BOT: Timer 0, bottom : Used for clock_event & clocksource |
| 1176 | * T0_TOP: Timer 0, top : Used by DSP |
| 1177 | * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer |
| 1178 | */ |
| 1179 | static struct davinci_timer_info da830_timer_info = { |
| 1180 | .timers = da830_timer_instance, |
| 1181 | .clockevent_id = T0_BOT, |
| 1182 | .clocksource_id = T0_BOT, |
| 1183 | }; |
| 1184 | |
| 1185 | static struct davinci_soc_info davinci_soc_info_da830 = { |
| 1186 | .io_desc = da830_io_desc, |
| 1187 | .io_desc_num = ARRAY_SIZE(da830_io_desc), |
Cyril Chemparathy | 3347db8 | 2010-05-07 17:06:34 -0400 | [diff] [blame] | 1188 | .jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG, |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 1189 | .ids = da830_ids, |
| 1190 | .ids_num = ARRAY_SIZE(da830_ids), |
| 1191 | .cpu_clks = da830_clks, |
| 1192 | .psc_bases = da830_psc_bases, |
| 1193 | .psc_bases_num = ARRAY_SIZE(da830_psc_bases), |
Cyril Chemparathy | 779b0d5 | 2010-05-07 17:06:38 -0400 | [diff] [blame] | 1194 | .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120, |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 1195 | .pinmux_pins = da830_pins, |
| 1196 | .pinmux_pins_num = ARRAY_SIZE(da830_pins), |
Cyril Chemparathy | bd80894 | 2010-05-07 17:06:37 -0400 | [diff] [blame] | 1197 | .intc_base = DA8XX_CP_INTC_BASE, |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 1198 | .intc_type = DAVINCI_INTC_TYPE_CP_INTC, |
| 1199 | .intc_irq_prios = da830_default_priorities, |
| 1200 | .intc_irq_num = DA830_N_CP_INTC_IRQ, |
| 1201 | .timer_info = &da830_timer_info, |
Cyril Chemparathy | 686b634 | 2010-05-01 18:37:54 -0400 | [diff] [blame] | 1202 | .gpio_type = GPIO_TYPE_DAVINCI, |
Cyril Chemparathy | b8d4429 | 2010-05-07 17:06:32 -0400 | [diff] [blame] | 1203 | .gpio_base = DA8XX_GPIO_BASE, |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 1204 | .gpio_num = 128, |
| 1205 | .gpio_irq = IRQ_DA8XX_GPIO0, |
| 1206 | .serial_dev = &da8xx_serial_device, |
| 1207 | .emac_pdata = &da8xx_emac_pdata, |
Cyril Chemparathy | c78a5bc | 2010-05-01 18:38:28 -0400 | [diff] [blame] | 1208 | .reset_device = &da8xx_wdt_device, |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 1209 | }; |
| 1210 | |
| 1211 | void __init da830_init(void) |
| 1212 | { |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 1213 | davinci_common_init(&davinci_soc_info_da830); |
Cyril Chemparathy | bcd6a1c | 2010-05-07 17:06:39 -0400 | [diff] [blame] | 1214 | |
| 1215 | da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K); |
| 1216 | WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"); |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 1217 | } |