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Kevin Hilman7c6337e2007-04-30 19:37:19 +01001/*
2 * DaVinci timer subsystem
3 *
4 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
5 *
6 * 2007 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/clocksource.h>
16#include <linux/clockchips.h>
Russell Kingfced80c2008-09-06 12:10:45 +010017#include <linux/io.h>
Kevin Hilmanf5c122d2009-04-14 07:04:16 -050018#include <linux/clk.h>
19#include <linux/err.h>
Kevin Hilmanfb631382009-04-29 16:23:59 -070020#include <linux/platform_device.h>
Kevin Hilman7c6337e2007-04-30 19:37:19 +010021
Russell Kinga09e64f2008-08-05 16:14:15 +010022#include <mach/hardware.h>
Kevin Hilman7c6337e2007-04-30 19:37:19 +010023#include <asm/mach/irq.h>
24#include <asm/mach/time.h>
Kevin Hilmanf5c122d2009-04-14 07:04:16 -050025#include <mach/cputype.h>
Mark A. Greerf64691b2009-04-15 12:40:11 -070026#include <mach/time.h>
Kevin Hilmanf5c122d2009-04-14 07:04:16 -050027#include "clock.h"
Kevin Hilman7c6337e2007-04-30 19:37:19 +010028
29static struct clock_event_device clockevent_davinci;
Kevin Hilmane6099002009-04-14 07:06:37 -050030static unsigned int davinci_clock_tick_rate;
Kevin Hilman7c6337e2007-04-30 19:37:19 +010031
Kevin Hilman7c6337e2007-04-30 19:37:19 +010032/*
33 * This driver configures the 2 64-bit count-up timers as 4 independent
34 * 32-bit count-up timers used as follows:
Kevin Hilman7c6337e2007-04-30 19:37:19 +010035 */
Mark A. Greerf64691b2009-04-15 12:40:11 -070036
37enum {
38 TID_CLOCKEVENT,
39 TID_CLOCKSOURCE,
40};
Kevin Hilman7c6337e2007-04-30 19:37:19 +010041
42/* Timer register offsets */
Mark A. Greer3abd5ac2009-04-15 12:41:54 -070043#define PID12 0x0
44#define TIM12 0x10
45#define TIM34 0x14
46#define PRD12 0x18
47#define PRD34 0x1c
48#define TCR 0x20
49#define TGCR 0x24
50#define WDTCR 0x28
51
52/* Offsets of the 8 compare registers */
53#define CMP12_0 0x60
54#define CMP12_1 0x64
55#define CMP12_2 0x68
56#define CMP12_3 0x6c
57#define CMP12_4 0x70
58#define CMP12_5 0x74
59#define CMP12_6 0x78
60#define CMP12_7 0x7c
Kevin Hilman7c6337e2007-04-30 19:37:19 +010061
62/* Timer register bitfields */
63#define TCR_ENAMODE_DISABLE 0x0
64#define TCR_ENAMODE_ONESHOT 0x1
65#define TCR_ENAMODE_PERIODIC 0x2
66#define TCR_ENAMODE_MASK 0x3
67
68#define TGCR_TIMMODE_SHIFT 2
69#define TGCR_TIMMODE_64BIT_GP 0x0
70#define TGCR_TIMMODE_32BIT_UNCHAINED 0x1
71#define TGCR_TIMMODE_64BIT_WDOG 0x2
72#define TGCR_TIMMODE_32BIT_CHAINED 0x3
73
74#define TGCR_TIM12RS_SHIFT 0
75#define TGCR_TIM34RS_SHIFT 1
76#define TGCR_RESET 0x0
77#define TGCR_UNRESET 0x1
78#define TGCR_RESET_MASK 0x3
79
80#define WDTCR_WDEN_SHIFT 14
81#define WDTCR_WDEN_DISABLE 0x0
82#define WDTCR_WDEN_ENABLE 0x1
83#define WDTCR_WDKEY_SHIFT 16
84#define WDTCR_WDKEY_SEQ0 0xa5c6
85#define WDTCR_WDKEY_SEQ1 0xda7e
86
87struct timer_s {
88 char *name;
89 unsigned int id;
90 unsigned long period;
91 unsigned long opts;
Mark A. Greer3abd5ac2009-04-15 12:41:54 -070092 unsigned long flags;
Kevin Hilmanf5c122d2009-04-14 07:04:16 -050093 void __iomem *base;
94 unsigned long tim_off;
95 unsigned long prd_off;
Kevin Hilman7c6337e2007-04-30 19:37:19 +010096 unsigned long enamode_shift;
97 struct irqaction irqaction;
98};
99static struct timer_s timers[];
100
101/* values for 'opts' field of struct timer_s */
Mark A. Greer3abd5ac2009-04-15 12:41:54 -0700102#define TIMER_OPTS_DISABLED 0x01
103#define TIMER_OPTS_ONESHOT 0x02
104#define TIMER_OPTS_PERIODIC 0x04
105#define TIMER_OPTS_STATE_MASK 0x07
106
107#define TIMER_OPTS_USE_COMPARE 0x80000000
108#define USING_COMPARE(t) ((t)->opts & TIMER_OPTS_USE_COMPARE)
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100109
Mark A. Greerf64691b2009-04-15 12:40:11 -0700110static char *id_to_name[] = {
111 [T0_BOT] = "timer0_0",
112 [T0_TOP] = "timer0_1",
113 [T1_BOT] = "timer1_0",
114 [T1_TOP] = "timer1_1",
115};
116
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100117static int timer32_config(struct timer_s *t)
118{
Mark A. Greer3abd5ac2009-04-15 12:41:54 -0700119 u32 tcr;
Mark A. Greer55700782009-04-15 12:42:06 -0700120 struct davinci_soc_info *soc_info = &davinci_soc_info;
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100121
Mark A. Greer3abd5ac2009-04-15 12:41:54 -0700122 if (USING_COMPARE(t)) {
123 struct davinci_timer_instance *dtip =
124 soc_info->timer_info->timers;
125 int event_timer = ID_TO_TIMER(timers[TID_CLOCKEVENT].id);
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100126
Mark A. Greer3abd5ac2009-04-15 12:41:54 -0700127 /*
128 * Next interrupt should be the current time reg value plus
129 * the new period (using 32-bit unsigned addition/wrapping
130 * to 0 on overflow). This assumes that the clocksource
131 * is setup to count to 2^32-1 before wrapping around to 0.
132 */
133 __raw_writel(__raw_readl(t->base + t->tim_off) + t->period,
134 t->base + dtip[event_timer].cmp_off);
135 } else {
136 tcr = __raw_readl(t->base + TCR);
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100137
Mark A. Greer3abd5ac2009-04-15 12:41:54 -0700138 /* disable timer */
139 tcr &= ~(TCR_ENAMODE_MASK << t->enamode_shift);
140 __raw_writel(tcr, t->base + TCR);
141
142 /* reset counter to zero, set new period */
143 __raw_writel(0, t->base + t->tim_off);
144 __raw_writel(t->period, t->base + t->prd_off);
145
146 /* Set enable mode */
147 if (t->opts & TIMER_OPTS_ONESHOT)
148 tcr |= TCR_ENAMODE_ONESHOT << t->enamode_shift;
149 else if (t->opts & TIMER_OPTS_PERIODIC)
150 tcr |= TCR_ENAMODE_PERIODIC << t->enamode_shift;
151
152 __raw_writel(tcr, t->base + TCR);
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100153 }
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100154 return 0;
155}
156
157static inline u32 timer32_read(struct timer_s *t)
158{
Kevin Hilmanf5c122d2009-04-14 07:04:16 -0500159 return __raw_readl(t->base + t->tim_off);
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100160}
161
162static irqreturn_t timer_interrupt(int irq, void *dev_id)
163{
164 struct clock_event_device *evt = &clockevent_davinci;
165
166 evt->event_handler(evt);
167 return IRQ_HANDLED;
168}
169
170/* called when 32-bit counter wraps */
171static irqreturn_t freerun_interrupt(int irq, void *dev_id)
172{
173 return IRQ_HANDLED;
174}
175
176static struct timer_s timers[] = {
177 [TID_CLOCKEVENT] = {
178 .name = "clockevent",
179 .opts = TIMER_OPTS_DISABLED,
180 .irqaction = {
181 .flags = IRQF_DISABLED | IRQF_TIMER,
182 .handler = timer_interrupt,
183 }
184 },
185 [TID_CLOCKSOURCE] = {
186 .name = "free-run counter",
187 .period = ~0,
188 .opts = TIMER_OPTS_PERIODIC,
189 .irqaction = {
190 .flags = IRQF_DISABLED | IRQF_TIMER,
191 .handler = freerun_interrupt,
192 }
193 },
194};
195
196static void __init timer_init(void)
197{
Mark A. Greerf64691b2009-04-15 12:40:11 -0700198 struct davinci_soc_info *soc_info = &davinci_soc_info;
199 struct davinci_timer_instance *dtip = soc_info->timer_info->timers;
Cyril Chemparathy1bcd38a2010-05-07 17:06:35 -0400200 void __iomem *base[2];
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100201 int i;
202
203 /* Global init of each 64-bit timer as a whole */
204 for(i=0; i<2; i++) {
Kevin Hilmanf5c122d2009-04-14 07:04:16 -0500205 u32 tgcr;
Cyril Chemparathy1bcd38a2010-05-07 17:06:35 -0400206
207 base[i] = ioremap(dtip[i].base, SZ_4K);
208 if (WARN_ON(!base[i]))
209 continue;
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100210
211 /* Disabled, Internal clock source */
Cyril Chemparathy1bcd38a2010-05-07 17:06:35 -0400212 __raw_writel(0, base[i] + TCR);
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100213
214 /* reset both timers, no pre-scaler for timer34 */
215 tgcr = 0;
Cyril Chemparathy1bcd38a2010-05-07 17:06:35 -0400216 __raw_writel(tgcr, base[i] + TGCR);
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100217
218 /* Set both timers to unchained 32-bit */
219 tgcr = TGCR_TIMMODE_32BIT_UNCHAINED << TGCR_TIMMODE_SHIFT;
Cyril Chemparathy1bcd38a2010-05-07 17:06:35 -0400220 __raw_writel(tgcr, base[i] + TGCR);
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100221
222 /* Unreset timers */
223 tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
224 (TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
Cyril Chemparathy1bcd38a2010-05-07 17:06:35 -0400225 __raw_writel(tgcr, base[i] + TGCR);
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100226
227 /* Init both counters to zero */
Cyril Chemparathy1bcd38a2010-05-07 17:06:35 -0400228 __raw_writel(0, base[i] + TIM12);
229 __raw_writel(0, base[i] + TIM34);
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100230 }
231
232 /* Init of each timer as a 32-bit timer */
233 for (i=0; i< ARRAY_SIZE(timers); i++) {
234 struct timer_s *t = &timers[i];
Mark A. Greerf64691b2009-04-15 12:40:11 -0700235 int timer = ID_TO_TIMER(t->id);
236 u32 irq;
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100237
Cyril Chemparathy1bcd38a2010-05-07 17:06:35 -0400238 t->base = base[timer];
239 if (!t->base)
240 continue;
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100241
Mark A. Greerf64691b2009-04-15 12:40:11 -0700242 if (IS_TIMER_BOT(t->id)) {
243 t->enamode_shift = 6;
244 t->tim_off = TIM12;
245 t->prd_off = PRD12;
246 irq = dtip[timer].bottom_irq;
247 } else {
248 t->enamode_shift = 22;
249 t->tim_off = TIM34;
250 t->prd_off = PRD34;
251 irq = dtip[timer].top_irq;
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100252 }
Mark A. Greerf64691b2009-04-15 12:40:11 -0700253
254 /* Register interrupt */
255 t->irqaction.name = t->name;
256 t->irqaction.dev_id = (void *)t;
Mark A. Greer3abd5ac2009-04-15 12:41:54 -0700257
258 if (t->irqaction.handler != NULL) {
259 irq = USING_COMPARE(t) ? dtip[i].cmp_irq : irq;
Mark A. Greerf64691b2009-04-15 12:40:11 -0700260 setup_irq(irq, &t->irqaction);
Mark A. Greer3abd5ac2009-04-15 12:41:54 -0700261 }
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100262 }
263}
264
265/*
266 * clocksource
267 */
Magnus Damm8e196082009-04-21 12:24:00 -0700268static cycle_t read_cycles(struct clocksource *cs)
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100269{
270 struct timer_s *t = &timers[TID_CLOCKSOURCE];
271
272 return (cycles_t)timer32_read(t);
273}
274
275static struct clocksource clocksource_davinci = {
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100276 .rating = 300,
277 .read = read_cycles,
278 .mask = CLOCKSOURCE_MASK(32),
279 .shift = 24,
280 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
281};
282
283/*
284 * clockevent
285 */
286static int davinci_set_next_event(unsigned long cycles,
287 struct clock_event_device *evt)
288{
289 struct timer_s *t = &timers[TID_CLOCKEVENT];
290
291 t->period = cycles;
292 timer32_config(t);
293 return 0;
294}
295
296static void davinci_set_mode(enum clock_event_mode mode,
297 struct clock_event_device *evt)
298{
299 struct timer_s *t = &timers[TID_CLOCKEVENT];
300
301 switch (mode) {
302 case CLOCK_EVT_MODE_PERIODIC:
Kevin Hilmane6099002009-04-14 07:06:37 -0500303 t->period = davinci_clock_tick_rate / (HZ);
Mark A. Greer3abd5ac2009-04-15 12:41:54 -0700304 t->opts &= ~TIMER_OPTS_STATE_MASK;
305 t->opts |= TIMER_OPTS_PERIODIC;
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100306 timer32_config(t);
307 break;
308 case CLOCK_EVT_MODE_ONESHOT:
Mark A. Greer3abd5ac2009-04-15 12:41:54 -0700309 t->opts &= ~TIMER_OPTS_STATE_MASK;
310 t->opts |= TIMER_OPTS_ONESHOT;
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100311 break;
312 case CLOCK_EVT_MODE_UNUSED:
313 case CLOCK_EVT_MODE_SHUTDOWN:
Mark A. Greer3abd5ac2009-04-15 12:41:54 -0700314 t->opts &= ~TIMER_OPTS_STATE_MASK;
315 t->opts |= TIMER_OPTS_DISABLED;
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100316 break;
Thomas Gleixner18de5bc2007-07-21 04:37:34 -0700317 case CLOCK_EVT_MODE_RESUME:
318 break;
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100319 }
320}
321
322static struct clock_event_device clockevent_davinci = {
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100323 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
324 .shift = 32,
325 .set_next_event = davinci_set_next_event,
326 .set_mode = davinci_set_mode,
327};
328
329
330static void __init davinci_timer_init(void)
331{
Kevin Hilmane6099002009-04-14 07:06:37 -0500332 struct clk *timer_clk;
Mark A. Greerf64691b2009-04-15 12:40:11 -0700333 struct davinci_soc_info *soc_info = &davinci_soc_info;
Mark A. Greer3abd5ac2009-04-15 12:41:54 -0700334 unsigned int clockevent_id;
335 unsigned int clocksource_id;
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100336 static char err[] __initdata = KERN_ERR
337 "%s: can't register clocksource!\n";
Kevin Hilmand99c3872010-03-11 14:57:35 -0800338 int i;
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100339
Mark A. Greer3abd5ac2009-04-15 12:41:54 -0700340 clockevent_id = soc_info->timer_info->clockevent_id;
341 clocksource_id = soc_info->timer_info->clocksource_id;
342
343 timers[TID_CLOCKEVENT].id = clockevent_id;
344 timers[TID_CLOCKSOURCE].id = clocksource_id;
345
346 /*
347 * If using same timer for both clock events & clocksource,
348 * a compare register must be used to generate an event interrupt.
349 * This is equivalent to a oneshot timer only (not periodic).
350 */
351 if (clockevent_id == clocksource_id) {
352 struct davinci_timer_instance *dtip =
353 soc_info->timer_info->timers;
354 int event_timer = ID_TO_TIMER(clockevent_id);
355
356 /* Only bottom timers can use compare regs */
357 if (IS_TIMER_TOP(clockevent_id))
358 pr_warning("davinci_timer_init: Invalid use"
359 " of system timers. Results unpredictable.\n");
360 else if ((dtip[event_timer].cmp_off == 0)
361 || (dtip[event_timer].cmp_irq == 0))
362 pr_warning("davinci_timer_init: Invalid timer instance"
363 " setup. Results unpredictable.\n");
364 else {
365 timers[TID_CLOCKEVENT].opts |= TIMER_OPTS_USE_COMPARE;
366 clockevent_davinci.features = CLOCK_EVT_FEAT_ONESHOT;
367 }
368 }
Mark A. Greerf64691b2009-04-15 12:40:11 -0700369
Kevin Hilmane6099002009-04-14 07:06:37 -0500370 timer_clk = clk_get(NULL, "timer0");
371 BUG_ON(IS_ERR(timer_clk));
372 clk_enable(timer_clk);
373
Cyril Chemparathy8ca2e592010-03-25 17:43:45 -0400374 /* init timer hw */
375 timer_init();
376
Kevin Hilmane6099002009-04-14 07:06:37 -0500377 davinci_clock_tick_rate = clk_get_rate(timer_clk);
378
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100379 /* setup clocksource */
Mark A. Greer3abd5ac2009-04-15 12:41:54 -0700380 clocksource_davinci.name = id_to_name[clocksource_id];
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100381 clocksource_davinci.mult =
Kevin Hilmane6099002009-04-14 07:06:37 -0500382 clocksource_khz2mult(davinci_clock_tick_rate/1000,
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100383 clocksource_davinci.shift);
384 if (clocksource_register(&clocksource_davinci))
385 printk(err, clocksource_davinci.name);
386
387 /* setup clockevent */
Mark A. Greerf64691b2009-04-15 12:40:11 -0700388 clockevent_davinci.name = id_to_name[timers[TID_CLOCKEVENT].id];
Kevin Hilmane6099002009-04-14 07:06:37 -0500389 clockevent_davinci.mult = div_sc(davinci_clock_tick_rate, NSEC_PER_SEC,
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100390 clockevent_davinci.shift);
391 clockevent_davinci.max_delta_ns =
392 clockevent_delta2ns(0xfffffffe, &clockevent_davinci);
Mark A. Greer3abd5ac2009-04-15 12:41:54 -0700393 clockevent_davinci.min_delta_ns = 50000; /* 50 usec */
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100394
Rusty Russell320ab2b2008-12-13 21:20:26 +1030395 clockevent_davinci.cpumask = cpumask_of(0);
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100396 clockevents_register_device(&clockevent_davinci);
Kevin Hilmand99c3872010-03-11 14:57:35 -0800397
398 for (i=0; i< ARRAY_SIZE(timers); i++)
399 timer32_config(&timers[i]);
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100400}
401
402struct sys_timer davinci_timer = {
403 .init = davinci_timer_init,
404};
405
406
407/* reset board using watchdog timer */
Cyril Chemparathyc78a5bc2010-05-01 18:38:28 -0400408void davinci_watchdog_reset(struct platform_device *pdev)
Kevin Hilmanfb631382009-04-29 16:23:59 -0700409{
Kevin Hilmanf5c122d2009-04-14 07:04:16 -0500410 u32 tgcr, wdtcr;
Cyril Chemparathyc78a5bc2010-05-01 18:38:28 -0400411 void __iomem *base;
Kevin Hilmane6099002009-04-14 07:06:37 -0500412 struct clk *wd_clk;
Kevin Hilmane6099002009-04-14 07:06:37 -0500413
Cyril Chemparathyc78a5bc2010-05-01 18:38:28 -0400414 base = ioremap(pdev->resource[0].start, SZ_4K);
415 if (WARN_ON(!base))
416 return;
417
Kevin Hilman5fcd2942009-06-03 12:24:50 -0700418 wd_clk = clk_get(&pdev->dev, NULL);
Kevin Hilmane6099002009-04-14 07:06:37 -0500419 if (WARN_ON(IS_ERR(wd_clk)))
420 return;
421 clk_enable(wd_clk);
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100422
423 /* disable, internal clock source */
Kevin Hilmanf5c122d2009-04-14 07:04:16 -0500424 __raw_writel(0, base + TCR);
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100425
426 /* reset timer, set mode to 64-bit watchdog, and unreset */
427 tgcr = 0;
David Griegoa23f7dc2009-06-01 11:41:54 -0700428 __raw_writel(tgcr, base + TGCR);
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100429 tgcr = TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT;
430 tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
431 (TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
David Griegoa23f7dc2009-06-01 11:41:54 -0700432 __raw_writel(tgcr, base + TGCR);
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100433
434 /* clear counter and period regs */
Kevin Hilmanf5c122d2009-04-14 07:04:16 -0500435 __raw_writel(0, base + TIM12);
436 __raw_writel(0, base + TIM34);
437 __raw_writel(0, base + PRD12);
438 __raw_writel(0, base + PRD34);
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100439
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100440 /* put watchdog in pre-active state */
David Griegoa23f7dc2009-06-01 11:41:54 -0700441 wdtcr = __raw_readl(base + WDTCR);
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100442 wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) |
443 (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
Kevin Hilmanf5c122d2009-04-14 07:04:16 -0500444 __raw_writel(wdtcr, base + WDTCR);
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100445
446 /* put watchdog in active state */
447 wdtcr = (WDTCR_WDKEY_SEQ1 << WDTCR_WDKEY_SHIFT) |
448 (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
Kevin Hilmanf5c122d2009-04-14 07:04:16 -0500449 __raw_writel(wdtcr, base + WDTCR);
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100450
451 /* write an invalid value to the WDKEY field to trigger
452 * a watchdog reset */
453 wdtcr = 0x00004000;
Kevin Hilmanf5c122d2009-04-14 07:04:16 -0500454 __raw_writel(wdtcr, base + WDTCR);
Kevin Hilman7c6337e2007-04-30 19:37:19 +0100455}