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Paulius Zaleckascfca8b52008-11-14 11:01:38 +01001/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
4 *
5 * This file may be distributed under the terms of the GNU General
6 * Public License, version 2.
7 */
8
9#ifndef __ARCH_ARM_MACH_MX1_CRM_REGS_H__
10#define __ARCH_ARM_MACH_MX1_CRM_REGS_H__
11
12#define CCM_BASE IO_ADDRESS(CCM_BASE_ADDR)
13#define SCM_BASE IO_ADDRESS(SCM_BASE_ADDR)
14
15/* CCM register addresses */
16#define CCM_CSCR (CCM_BASE + 0x0)
17#define CCM_MPCTL0 (CCM_BASE + 0x4)
18#define CCM_MPCTL1 (CCM_BASE + 0x8)
19#define CCM_SPCTL0 (CCM_BASE + 0xC)
20#define CCM_SPCTL1 (CCM_BASE + 0x10)
21#define CCM_PCDR (CCM_BASE + 0x20)
22
23#define CCM_CSCR_CLKO_OFFSET 29
24#define CCM_CSCR_CLKO_MASK (0x7 << 29)
25#define CCM_CSCR_USB_OFFSET 26
26#define CCM_CSCR_USB_MASK (0x7 << 26)
27#define CCM_CSCR_SPLL_RESTART (1 << 22)
28#define CCM_CSCR_MPLL_RESTART (1 << 21)
29#define CCM_CSCR_OSC_EN_SHIFT 17
30#define CCM_CSCR_SYSTEM_SEL (1 << 16)
31#define CCM_CSCR_BCLK_OFFSET 10
32#define CCM_CSCR_BCLK_MASK (0xF << 10)
33#define CCM_CSCR_PRESC (1 << 15)
34#define CCM_CSCR_SPEN (1 << 1)
35#define CCM_CSCR_MPEN (1 << 0)
36
37#define CCM_PCDR_PCLK3_OFFSET 16
38#define CCM_PCDR_PCLK3_MASK (0x7F << 16)
39#define CCM_PCDR_PCLK2_OFFSET 4
40#define CCM_PCDR_PCLK2_MASK (0xF << 4)
41#define CCM_PCDR_PCLK1_OFFSET 0
42#define CCM_PCDR_PCLK1_MASK 0xF
43
44/* SCM register addresses */
45#define SCM_SIDR (SCM_BASE + 0x0)
46#define SCM_FMCR (SCM_BASE + 0x4)
47#define SCM_GPCR (SCM_BASE + 0x8)
48#define SCM_GCCR (SCM_BASE + 0xC)
49
50#define SCM_GCCR_DMA_CLK_EN_OFFSET 3
51#define SCM_GCCR_CSI_CLK_EN_OFFSET 2
52#define SCM_GCCR_MMA_CLK_EN_OFFSET 1
53#define SCM_GCCR_USBD_CLK_EN_OFFSET 0
54
55#endif /* __ARCH_ARM_MACH_MX2_CRM_REGS_H__ */