blob: 7523a2429d09507c448199db38d319f25145212f [file] [log] [blame]
Mingkai Hu8b60d6c2010-10-12 18:18:32 +08001/*
2 * Freescale eSPI controller driver.
3 *
4 * Copyright 2010 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11#include <linux/module.h>
12#include <linux/delay.h>
13#include <linux/irq.h>
14#include <linux/spi/spi.h>
15#include <linux/platform_device.h>
16#include <linux/fsl_devices.h>
17#include <linux/mm.h>
18#include <linux/of.h>
19#include <linux/of_platform.h>
20#include <linux/of_spi.h>
21#include <linux/interrupt.h>
22#include <linux/err.h>
23#include <sysdev/fsl_soc.h>
24
Grant Likelyca632f52011-06-06 01:16:30 -060025#include "spi-fsl-lib.h"
Mingkai Hu8b60d6c2010-10-12 18:18:32 +080026
27/* eSPI Controller registers */
28struct fsl_espi_reg {
29 __be32 mode; /* 0x000 - eSPI mode register */
30 __be32 event; /* 0x004 - eSPI event register */
31 __be32 mask; /* 0x008 - eSPI mask register */
32 __be32 command; /* 0x00c - eSPI command register */
33 __be32 transmit; /* 0x010 - eSPI transmit FIFO access register*/
34 __be32 receive; /* 0x014 - eSPI receive FIFO access register*/
35 u8 res[8]; /* 0x018 - 0x01c reserved */
36 __be32 csmode[4]; /* 0x020 - 0x02c eSPI cs mode register */
37};
38
39struct fsl_espi_transfer {
40 const void *tx_buf;
41 void *rx_buf;
42 unsigned len;
43 unsigned n_tx;
44 unsigned n_rx;
45 unsigned actual_length;
46 int status;
47};
48
49/* eSPI Controller mode register definitions */
50#define SPMODE_ENABLE (1 << 31)
51#define SPMODE_LOOP (1 << 30)
52#define SPMODE_TXTHR(x) ((x) << 8)
53#define SPMODE_RXTHR(x) ((x) << 0)
54
55/* eSPI Controller CS mode register definitions */
56#define CSMODE_CI_INACTIVEHIGH (1 << 31)
57#define CSMODE_CP_BEGIN_EDGECLK (1 << 30)
58#define CSMODE_REV (1 << 29)
59#define CSMODE_DIV16 (1 << 28)
60#define CSMODE_PM(x) ((x) << 24)
61#define CSMODE_POL_1 (1 << 20)
62#define CSMODE_LEN(x) ((x) << 16)
63#define CSMODE_BEF(x) ((x) << 12)
64#define CSMODE_AFT(x) ((x) << 8)
65#define CSMODE_CG(x) ((x) << 3)
66
67/* Default mode/csmode for eSPI controller */
68#define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(3))
69#define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \
70 | CSMODE_AFT(0) | CSMODE_CG(1))
71
72/* SPIE register values */
73#define SPIE_NE 0x00000200 /* Not empty */
74#define SPIE_NF 0x00000100 /* Not full */
75
76/* SPIM register values */
77#define SPIM_NE 0x00000200 /* Not empty */
78#define SPIM_NF 0x00000100 /* Not full */
79#define SPIE_RXCNT(reg) ((reg >> 24) & 0x3F)
80#define SPIE_TXCNT(reg) ((reg >> 16) & 0x3F)
81
82/* SPCOM register values */
83#define SPCOM_CS(x) ((x) << 30)
84#define SPCOM_TRANLEN(x) ((x) << 0)
85#define SPCOM_TRANLEN_MAX 0xFFFF /* Max transaction length */
86
87static void fsl_espi_change_mode(struct spi_device *spi)
88{
89 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
90 struct spi_mpc8xxx_cs *cs = spi->controller_state;
91 struct fsl_espi_reg *reg_base = mspi->reg_base;
92 __be32 __iomem *mode = &reg_base->csmode[spi->chip_select];
93 __be32 __iomem *espi_mode = &reg_base->mode;
94 u32 tmp;
95 unsigned long flags;
96
97 /* Turn off IRQs locally to minimize time that SPI is disabled. */
98 local_irq_save(flags);
99
100 /* Turn off SPI unit prior changing mode */
101 tmp = mpc8xxx_spi_read_reg(espi_mode);
102 mpc8xxx_spi_write_reg(espi_mode, tmp & ~SPMODE_ENABLE);
103 mpc8xxx_spi_write_reg(mode, cs->hw_mode);
104 mpc8xxx_spi_write_reg(espi_mode, tmp);
105
106 local_irq_restore(flags);
107}
108
109static u32 fsl_espi_tx_buf_lsb(struct mpc8xxx_spi *mpc8xxx_spi)
110{
111 u32 data;
112 u16 data_h;
113 u16 data_l;
114 const u32 *tx = mpc8xxx_spi->tx;
115
116 if (!tx)
117 return 0;
118
119 data = *tx++ << mpc8xxx_spi->tx_shift;
120 data_l = data & 0xffff;
121 data_h = (data >> 16) & 0xffff;
122 swab16s(&data_l);
123 swab16s(&data_h);
124 data = data_h | data_l;
125
126 mpc8xxx_spi->tx = tx;
127 return data;
128}
129
130static int fsl_espi_setup_transfer(struct spi_device *spi,
131 struct spi_transfer *t)
132{
133 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
134 int bits_per_word = 0;
135 u8 pm;
136 u32 hz = 0;
137 struct spi_mpc8xxx_cs *cs = spi->controller_state;
138
139 if (t) {
140 bits_per_word = t->bits_per_word;
141 hz = t->speed_hz;
142 }
143
144 /* spi_transfer level calls that work per-word */
145 if (!bits_per_word)
146 bits_per_word = spi->bits_per_word;
147
148 /* Make sure its a bit width we support [4..16] */
149 if ((bits_per_word < 4) || (bits_per_word > 16))
150 return -EINVAL;
151
152 if (!hz)
153 hz = spi->max_speed_hz;
154
155 cs->rx_shift = 0;
156 cs->tx_shift = 0;
157 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
158 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
159 if (bits_per_word <= 8) {
160 cs->rx_shift = 8 - bits_per_word;
161 } else if (bits_per_word <= 16) {
162 cs->rx_shift = 16 - bits_per_word;
163 if (spi->mode & SPI_LSB_FIRST)
164 cs->get_tx = fsl_espi_tx_buf_lsb;
165 } else {
166 return -EINVAL;
167 }
168
169 mpc8xxx_spi->rx_shift = cs->rx_shift;
170 mpc8xxx_spi->tx_shift = cs->tx_shift;
171 mpc8xxx_spi->get_rx = cs->get_rx;
172 mpc8xxx_spi->get_tx = cs->get_tx;
173
174 bits_per_word = bits_per_word - 1;
175
176 /* mask out bits we are going to set */
177 cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF));
178
179 cs->hw_mode |= CSMODE_LEN(bits_per_word);
180
181 if ((mpc8xxx_spi->spibrg / hz) > 64) {
182 cs->hw_mode |= CSMODE_DIV16;
Sebastian Andrzej Siewior35faa552012-03-15 18:42:31 +0100183 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4);
Mingkai Hu8b60d6c2010-10-12 18:18:32 +0800184
Sebastian Andrzej Siewior87bf5ab2012-03-15 18:42:32 +0100185 WARN_ONCE(pm > 33, "%s: Requested speed is too low: %d Hz. "
Mingkai Hu8b60d6c2010-10-12 18:18:32 +0800186 "Will use %d Hz instead.\n", dev_name(&spi->dev),
Sebastian Andrzej Siewior87bf5ab2012-03-15 18:42:32 +0100187 hz, mpc8xxx_spi->spibrg / (4 * 16 * (32 + 1)));
188 if (pm > 33)
189 pm = 33;
Mingkai Hu8b60d6c2010-10-12 18:18:32 +0800190 } else {
Sebastian Andrzej Siewior35faa552012-03-15 18:42:31 +0100191 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4);
Mingkai Hu8b60d6c2010-10-12 18:18:32 +0800192 }
193 if (pm)
194 pm--;
Sebastian Andrzej Siewior87bf5ab2012-03-15 18:42:32 +0100195 if (pm < 2)
196 pm = 2;
Mingkai Hu8b60d6c2010-10-12 18:18:32 +0800197
198 cs->hw_mode |= CSMODE_PM(pm);
199
200 fsl_espi_change_mode(spi);
201 return 0;
202}
203
204static int fsl_espi_cpu_bufs(struct mpc8xxx_spi *mspi, struct spi_transfer *t,
205 unsigned int len)
206{
207 u32 word;
208 struct fsl_espi_reg *reg_base = mspi->reg_base;
209
210 mspi->count = len;
211
212 /* enable rx ints */
213 mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE);
214
215 /* transmit word */
216 word = mspi->get_tx(mspi);
217 mpc8xxx_spi_write_reg(&reg_base->transmit, word);
218
219 return 0;
220}
221
222static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t)
223{
224 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
225 struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
226 unsigned int len = t->len;
227 u8 bits_per_word;
228 int ret;
229
230 bits_per_word = spi->bits_per_word;
231 if (t->bits_per_word)
232 bits_per_word = t->bits_per_word;
233
234 mpc8xxx_spi->len = t->len;
235 len = roundup(len, 4) / 4;
236
237 mpc8xxx_spi->tx = t->tx_buf;
238 mpc8xxx_spi->rx = t->rx_buf;
239
240 INIT_COMPLETION(mpc8xxx_spi->done);
241
242 /* Set SPCOM[CS] and SPCOM[TRANLEN] field */
243 if ((t->len - 1) > SPCOM_TRANLEN_MAX) {
244 dev_err(mpc8xxx_spi->dev, "Transaction length (%d)"
245 " beyond the SPCOM[TRANLEN] field\n", t->len);
246 return -EINVAL;
247 }
248 mpc8xxx_spi_write_reg(&reg_base->command,
249 (SPCOM_CS(spi->chip_select) | SPCOM_TRANLEN(t->len - 1)));
250
251 ret = fsl_espi_cpu_bufs(mpc8xxx_spi, t, len);
252 if (ret)
253 return ret;
254
255 wait_for_completion(&mpc8xxx_spi->done);
256
257 /* disable rx ints */
258 mpc8xxx_spi_write_reg(&reg_base->mask, 0);
259
260 return mpc8xxx_spi->count;
261}
262
Mingkai Hu0dd2c962010-12-21 09:27:02 +0800263static inline void fsl_espi_addr2cmd(unsigned int addr, u8 *cmd)
Mingkai Hu8b60d6c2010-10-12 18:18:32 +0800264{
Mingkai Hu0dd2c962010-12-21 09:27:02 +0800265 if (cmd) {
Mingkai Hu8b60d6c2010-10-12 18:18:32 +0800266 cmd[1] = (u8)(addr >> 16);
267 cmd[2] = (u8)(addr >> 8);
268 cmd[3] = (u8)(addr >> 0);
269 }
270}
271
Mingkai Hu0dd2c962010-12-21 09:27:02 +0800272static inline unsigned int fsl_espi_cmd2addr(u8 *cmd)
Mingkai Hu8b60d6c2010-10-12 18:18:32 +0800273{
Mingkai Hu0dd2c962010-12-21 09:27:02 +0800274 if (cmd)
Mingkai Hu8b60d6c2010-10-12 18:18:32 +0800275 return cmd[1] << 16 | cmd[2] << 8 | cmd[3] << 0;
276
277 return 0;
278}
279
280static void fsl_espi_do_trans(struct spi_message *m,
281 struct fsl_espi_transfer *tr)
282{
283 struct spi_device *spi = m->spi;
284 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
285 struct fsl_espi_transfer *espi_trans = tr;
286 struct spi_message message;
287 struct spi_transfer *t, *first, trans;
288 int status = 0;
289
290 spi_message_init(&message);
291 memset(&trans, 0, sizeof(trans));
292
293 first = list_first_entry(&m->transfers, struct spi_transfer,
294 transfer_list);
295 list_for_each_entry(t, &m->transfers, transfer_list) {
296 if ((first->bits_per_word != t->bits_per_word) ||
297 (first->speed_hz != t->speed_hz)) {
298 espi_trans->status = -EINVAL;
299 dev_err(mspi->dev, "bits_per_word/speed_hz should be"
300 " same for the same SPI transfer\n");
301 return;
302 }
303
304 trans.speed_hz = t->speed_hz;
305 trans.bits_per_word = t->bits_per_word;
306 trans.delay_usecs = max(first->delay_usecs, t->delay_usecs);
307 }
308
309 trans.len = espi_trans->len;
310 trans.tx_buf = espi_trans->tx_buf;
311 trans.rx_buf = espi_trans->rx_buf;
312 spi_message_add_tail(&trans, &message);
313
314 list_for_each_entry(t, &message.transfers, transfer_list) {
315 if (t->bits_per_word || t->speed_hz) {
316 status = -EINVAL;
317
318 status = fsl_espi_setup_transfer(spi, t);
319 if (status < 0)
320 break;
321 }
322
323 if (t->len)
324 status = fsl_espi_bufs(spi, t);
325
326 if (status) {
327 status = -EMSGSIZE;
328 break;
329 }
330
331 if (t->delay_usecs)
332 udelay(t->delay_usecs);
333 }
334
335 espi_trans->status = status;
336 fsl_espi_setup_transfer(spi, NULL);
337}
338
339static void fsl_espi_cmd_trans(struct spi_message *m,
340 struct fsl_espi_transfer *trans, u8 *rx_buff)
341{
342 struct spi_transfer *t;
343 u8 *local_buf;
344 int i = 0;
345 struct fsl_espi_transfer *espi_trans = trans;
346
347 local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
348 if (!local_buf) {
349 espi_trans->status = -ENOMEM;
350 return;
351 }
352
353 list_for_each_entry(t, &m->transfers, transfer_list) {
354 if (t->tx_buf) {
355 memcpy(local_buf + i, t->tx_buf, t->len);
356 i += t->len;
357 }
358 }
359
360 espi_trans->tx_buf = local_buf;
361 espi_trans->rx_buf = local_buf + espi_trans->n_tx;
362 fsl_espi_do_trans(m, espi_trans);
363
364 espi_trans->actual_length = espi_trans->len;
365 kfree(local_buf);
366}
367
368static void fsl_espi_rw_trans(struct spi_message *m,
369 struct fsl_espi_transfer *trans, u8 *rx_buff)
370{
371 struct fsl_espi_transfer *espi_trans = trans;
372 unsigned int n_tx = espi_trans->n_tx;
373 unsigned int n_rx = espi_trans->n_rx;
374 struct spi_transfer *t;
375 u8 *local_buf;
376 u8 *rx_buf = rx_buff;
377 unsigned int trans_len;
378 unsigned int addr;
379 int i, pos, loop;
380
381 local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
382 if (!local_buf) {
383 espi_trans->status = -ENOMEM;
384 return;
385 }
386
387 for (pos = 0, loop = 0; pos < n_rx; pos += trans_len, loop++) {
388 trans_len = n_rx - pos;
389 if (trans_len > SPCOM_TRANLEN_MAX - n_tx)
390 trans_len = SPCOM_TRANLEN_MAX - n_tx;
391
392 i = 0;
393 list_for_each_entry(t, &m->transfers, transfer_list) {
394 if (t->tx_buf) {
395 memcpy(local_buf + i, t->tx_buf, t->len);
396 i += t->len;
397 }
398 }
399
Mingkai Hu0dd2c962010-12-21 09:27:02 +0800400 if (pos > 0) {
401 addr = fsl_espi_cmd2addr(local_buf);
402 addr += pos;
403 fsl_espi_addr2cmd(addr, local_buf);
404 }
Mingkai Hu8b60d6c2010-10-12 18:18:32 +0800405
406 espi_trans->n_tx = n_tx;
407 espi_trans->n_rx = trans_len;
408 espi_trans->len = trans_len + n_tx;
409 espi_trans->tx_buf = local_buf;
410 espi_trans->rx_buf = local_buf + n_tx;
411 fsl_espi_do_trans(m, espi_trans);
412
413 memcpy(rx_buf + pos, espi_trans->rx_buf + n_tx, trans_len);
414
415 if (loop > 0)
416 espi_trans->actual_length += espi_trans->len - n_tx;
417 else
418 espi_trans->actual_length += espi_trans->len;
419 }
420
421 kfree(local_buf);
422}
423
424static void fsl_espi_do_one_msg(struct spi_message *m)
425{
426 struct spi_transfer *t;
427 u8 *rx_buf = NULL;
428 unsigned int n_tx = 0;
429 unsigned int n_rx = 0;
430 struct fsl_espi_transfer espi_trans;
431
432 list_for_each_entry(t, &m->transfers, transfer_list) {
433 if (t->tx_buf)
434 n_tx += t->len;
435 if (t->rx_buf) {
436 n_rx += t->len;
437 rx_buf = t->rx_buf;
438 }
439 }
440
441 espi_trans.n_tx = n_tx;
442 espi_trans.n_rx = n_rx;
443 espi_trans.len = n_tx + n_rx;
444 espi_trans.actual_length = 0;
445 espi_trans.status = 0;
446
447 if (!rx_buf)
448 fsl_espi_cmd_trans(m, &espi_trans, NULL);
449 else
450 fsl_espi_rw_trans(m, &espi_trans, rx_buf);
451
452 m->actual_length = espi_trans.actual_length;
453 m->status = espi_trans.status;
454 m->complete(m->context);
455}
456
457static int fsl_espi_setup(struct spi_device *spi)
458{
459 struct mpc8xxx_spi *mpc8xxx_spi;
460 struct fsl_espi_reg *reg_base;
461 int retval;
462 u32 hw_mode;
463 u32 loop_mode;
464 struct spi_mpc8xxx_cs *cs = spi->controller_state;
465
466 if (!spi->max_speed_hz)
467 return -EINVAL;
468
469 if (!cs) {
470 cs = kzalloc(sizeof *cs, GFP_KERNEL);
471 if (!cs)
472 return -ENOMEM;
473 spi->controller_state = cs;
474 }
475
476 mpc8xxx_spi = spi_master_get_devdata(spi->master);
477 reg_base = mpc8xxx_spi->reg_base;
478
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300479 hw_mode = cs->hw_mode; /* Save original settings */
Mingkai Hu8b60d6c2010-10-12 18:18:32 +0800480 cs->hw_mode = mpc8xxx_spi_read_reg(
481 &reg_base->csmode[spi->chip_select]);
482 /* mask out bits we are going to set */
483 cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH
484 | CSMODE_REV);
485
486 if (spi->mode & SPI_CPHA)
487 cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK;
488 if (spi->mode & SPI_CPOL)
489 cs->hw_mode |= CSMODE_CI_INACTIVEHIGH;
490 if (!(spi->mode & SPI_LSB_FIRST))
491 cs->hw_mode |= CSMODE_REV;
492
493 /* Handle the loop mode */
494 loop_mode = mpc8xxx_spi_read_reg(&reg_base->mode);
495 loop_mode &= ~SPMODE_LOOP;
496 if (spi->mode & SPI_LOOP)
497 loop_mode |= SPMODE_LOOP;
498 mpc8xxx_spi_write_reg(&reg_base->mode, loop_mode);
499
500 retval = fsl_espi_setup_transfer(spi, NULL);
501 if (retval < 0) {
502 cs->hw_mode = hw_mode; /* Restore settings */
503 return retval;
504 }
505 return 0;
506}
507
508void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
509{
510 struct fsl_espi_reg *reg_base = mspi->reg_base;
511
512 /* We need handle RX first */
513 if (events & SPIE_NE) {
Mingkai Hue6289d62010-12-21 09:26:07 +0800514 u32 rx_data, tmp;
515 u8 rx_data_8;
Mingkai Hu8b60d6c2010-10-12 18:18:32 +0800516
517 /* Spin until RX is done */
518 while (SPIE_RXCNT(events) < min(4, mspi->len)) {
519 cpu_relax();
520 events = mpc8xxx_spi_read_reg(&reg_base->event);
521 }
Mingkai Hu8b60d6c2010-10-12 18:18:32 +0800522
Mingkai Hue6289d62010-12-21 09:26:07 +0800523 if (mspi->len >= 4) {
524 rx_data = mpc8xxx_spi_read_reg(&reg_base->receive);
525 } else {
526 tmp = mspi->len;
527 rx_data = 0;
528 while (tmp--) {
529 rx_data_8 = in_8((u8 *)&reg_base->receive);
530 rx_data |= (rx_data_8 << (tmp * 8));
531 }
532
533 rx_data <<= (4 - mspi->len) * 8;
534 }
535
536 mspi->len -= 4;
Mingkai Hu8b60d6c2010-10-12 18:18:32 +0800537
538 if (mspi->rx)
539 mspi->get_rx(rx_data, mspi);
540 }
541
542 if (!(events & SPIE_NF)) {
543 int ret;
544
545 /* spin until TX is done */
546 ret = spin_event_timeout(((events = mpc8xxx_spi_read_reg(
547 &reg_base->event)) & SPIE_NF) == 0, 1000, 0);
548 if (!ret) {
549 dev_err(mspi->dev, "tired waiting for SPIE_NF\n");
550 return;
551 }
552 }
553
554 /* Clear the events */
555 mpc8xxx_spi_write_reg(&reg_base->event, events);
556
557 mspi->count -= 1;
558 if (mspi->count) {
559 u32 word = mspi->get_tx(mspi);
560
561 mpc8xxx_spi_write_reg(&reg_base->transmit, word);
562 } else {
563 complete(&mspi->done);
564 }
565}
566
567static irqreturn_t fsl_espi_irq(s32 irq, void *context_data)
568{
569 struct mpc8xxx_spi *mspi = context_data;
570 struct fsl_espi_reg *reg_base = mspi->reg_base;
571 irqreturn_t ret = IRQ_NONE;
572 u32 events;
573
574 /* Get interrupt events(tx/rx) */
575 events = mpc8xxx_spi_read_reg(&reg_base->event);
576 if (events)
577 ret = IRQ_HANDLED;
578
579 dev_vdbg(mspi->dev, "%s: events %x\n", __func__, events);
580
581 fsl_espi_cpu_irq(mspi, events);
582
583 return ret;
584}
585
586static void fsl_espi_remove(struct mpc8xxx_spi *mspi)
587{
588 iounmap(mspi->reg_base);
589}
590
591static struct spi_master * __devinit fsl_espi_probe(struct device *dev,
592 struct resource *mem, unsigned int irq)
593{
594 struct fsl_spi_platform_data *pdata = dev->platform_data;
595 struct spi_master *master;
596 struct mpc8xxx_spi *mpc8xxx_spi;
597 struct fsl_espi_reg *reg_base;
598 u32 regval;
599 int i, ret = 0;
600
601 master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
602 if (!master) {
603 ret = -ENOMEM;
604 goto err;
605 }
606
607 dev_set_drvdata(dev, master);
608
609 ret = mpc8xxx_spi_probe(dev, mem, irq);
610 if (ret)
611 goto err_probe;
612
613 master->setup = fsl_espi_setup;
614
615 mpc8xxx_spi = spi_master_get_devdata(master);
616 mpc8xxx_spi->spi_do_one_msg = fsl_espi_do_one_msg;
617 mpc8xxx_spi->spi_remove = fsl_espi_remove;
618
619 mpc8xxx_spi->reg_base = ioremap(mem->start, resource_size(mem));
620 if (!mpc8xxx_spi->reg_base) {
621 ret = -ENOMEM;
622 goto err_probe;
623 }
624
625 reg_base = mpc8xxx_spi->reg_base;
626
627 /* Register for SPI Interrupt */
628 ret = request_irq(mpc8xxx_spi->irq, fsl_espi_irq,
629 0, "fsl_espi", mpc8xxx_spi);
630 if (ret)
631 goto free_irq;
632
633 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
634 mpc8xxx_spi->rx_shift = 16;
635 mpc8xxx_spi->tx_shift = 24;
636 }
637
638 /* SPI controller initializations */
639 mpc8xxx_spi_write_reg(&reg_base->mode, 0);
640 mpc8xxx_spi_write_reg(&reg_base->mask, 0);
641 mpc8xxx_spi_write_reg(&reg_base->command, 0);
642 mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);
643
644 /* Init eSPI CS mode register */
645 for (i = 0; i < pdata->max_chipselect; i++)
646 mpc8xxx_spi_write_reg(&reg_base->csmode[i], CSMODE_INIT_VAL);
647
648 /* Enable SPI interface */
649 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
650
651 mpc8xxx_spi_write_reg(&reg_base->mode, regval);
652
653 ret = spi_register_master(master);
654 if (ret < 0)
655 goto unreg_master;
656
657 dev_info(dev, "at 0x%p (irq = %d)\n", reg_base, mpc8xxx_spi->irq);
658
659 return master;
660
661unreg_master:
662 free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
663free_irq:
664 iounmap(mpc8xxx_spi->reg_base);
665err_probe:
666 spi_master_put(master);
667err:
668 return ERR_PTR(ret);
669}
670
671static int of_fsl_espi_get_chipselects(struct device *dev)
672{
673 struct device_node *np = dev->of_node;
674 struct fsl_spi_platform_data *pdata = dev->platform_data;
675 const u32 *prop;
676 int len;
677
678 prop = of_get_property(np, "fsl,espi-num-chipselects", &len);
679 if (!prop || len < sizeof(*prop)) {
680 dev_err(dev, "No 'fsl,espi-num-chipselects' property\n");
681 return -EINVAL;
682 }
683
684 pdata->max_chipselect = *prop;
685 pdata->cs_control = NULL;
686
687 return 0;
688}
689
Grant Likely18d306d2011-02-22 21:02:43 -0700690static int __devinit of_fsl_espi_probe(struct platform_device *ofdev)
Mingkai Hu8b60d6c2010-10-12 18:18:32 +0800691{
692 struct device *dev = &ofdev->dev;
693 struct device_node *np = ofdev->dev.of_node;
694 struct spi_master *master;
695 struct resource mem;
696 struct resource irq;
697 int ret = -ENOMEM;
698
Grant Likely18d306d2011-02-22 21:02:43 -0700699 ret = of_mpc8xxx_spi_probe(ofdev);
Mingkai Hu8b60d6c2010-10-12 18:18:32 +0800700 if (ret)
701 return ret;
702
703 ret = of_fsl_espi_get_chipselects(dev);
704 if (ret)
705 goto err;
706
707 ret = of_address_to_resource(np, 0, &mem);
708 if (ret)
709 goto err;
710
711 ret = of_irq_to_resource(np, 0, &irq);
712 if (!ret) {
713 ret = -EINVAL;
714 goto err;
715 }
716
717 master = fsl_espi_probe(dev, &mem, irq.start);
718 if (IS_ERR(master)) {
719 ret = PTR_ERR(master);
720 goto err;
721 }
722
723 return 0;
724
725err:
726 return ret;
727}
728
729static int __devexit of_fsl_espi_remove(struct platform_device *dev)
730{
731 return mpc8xxx_spi_remove(&dev->dev);
732}
733
734static const struct of_device_id of_fsl_espi_match[] = {
735 { .compatible = "fsl,mpc8536-espi" },
736 {}
737};
738MODULE_DEVICE_TABLE(of, of_fsl_espi_match);
739
Grant Likely18d306d2011-02-22 21:02:43 -0700740static struct platform_driver fsl_espi_driver = {
Mingkai Hu8b60d6c2010-10-12 18:18:32 +0800741 .driver = {
742 .name = "fsl_espi",
743 .owner = THIS_MODULE,
744 .of_match_table = of_fsl_espi_match,
745 },
746 .probe = of_fsl_espi_probe,
747 .remove = __devexit_p(of_fsl_espi_remove),
748};
Grant Likely940ab882011-10-05 11:29:49 -0600749module_platform_driver(fsl_espi_driver);
Mingkai Hu8b60d6c2010-10-12 18:18:32 +0800750
751MODULE_AUTHOR("Mingkai Hu");
752MODULE_DESCRIPTION("Enhanced Freescale SPI Driver");
753MODULE_LICENSE("GPL");