blob: 12c64e1a7e31955b3cf20257cfb0501152a7db92 [file] [log] [blame]
Dan Williams5cbafa62009-08-26 13:01:44 -07001/*
2 * Intel I/OAT DMA Linux driver
3 * Copyright(c) 2004 - 2009 Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 */
22
23/*
24 * This driver supports an Intel I/OAT DMA engine (versions >= 2), which
25 * does asynchronous data movement and checksumming operations.
26 */
27
28#include <linux/init.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/interrupt.h>
32#include <linux/dmaengine.h>
33#include <linux/delay.h>
34#include <linux/dma-mapping.h>
35#include <linux/workqueue.h>
36#include <linux/i7300_idle.h>
37#include "dma.h"
38#include "dma_v2.h"
39#include "registers.h"
40#include "hw.h"
41
Dan Williamsbf40a682009-09-08 17:42:55 -070042int ioat_ring_alloc_order = 8;
Dan Williams5cbafa62009-08-26 13:01:44 -070043module_param(ioat_ring_alloc_order, int, 0644);
44MODULE_PARM_DESC(ioat_ring_alloc_order,
45 "ioat2+: allocate 2^n descriptors per channel (default: n=8)");
Dan Williamsa3092182009-09-08 12:02:01 -070046static int ioat_ring_max_alloc_order = IOAT_MAX_ORDER;
47module_param(ioat_ring_max_alloc_order, int, 0644);
48MODULE_PARM_DESC(ioat_ring_max_alloc_order,
49 "ioat2+: upper limit for dynamic ring resizing (default: n=16)");
Dan Williams5cbafa62009-08-26 13:01:44 -070050
Dan Williamsb094ad32009-09-08 17:42:57 -070051void __ioat2_issue_pending(struct ioat2_dma_chan *ioat)
Dan Williams5cbafa62009-08-26 13:01:44 -070052{
53 void * __iomem reg_base = ioat->base.reg_base;
54
55 ioat->pending = 0;
Dan Williams09c8a5b2009-09-08 12:01:49 -070056 ioat->dmacount += ioat2_ring_pending(ioat);;
Dan Williams5cbafa62009-08-26 13:01:44 -070057 ioat->issued = ioat->head;
58 /* make descriptor updates globally visible before notifying channel */
59 wmb();
60 writew(ioat->dmacount, reg_base + IOAT_CHAN_DMACOUNT_OFFSET);
Dan Williams6df91832009-09-08 12:00:55 -070061 dev_dbg(to_dev(&ioat->base),
62 "%s: head: %#x tail: %#x issued: %#x count: %#x\n",
63 __func__, ioat->head, ioat->tail, ioat->issued, ioat->dmacount);
Dan Williams5cbafa62009-08-26 13:01:44 -070064}
65
Dan Williamsbf40a682009-09-08 17:42:55 -070066void ioat2_issue_pending(struct dma_chan *chan)
Dan Williams5cbafa62009-08-26 13:01:44 -070067{
68 struct ioat2_dma_chan *ioat = to_ioat2_chan(chan);
69
70 spin_lock_bh(&ioat->ring_lock);
71 if (ioat->pending == 1)
72 __ioat2_issue_pending(ioat);
73 spin_unlock_bh(&ioat->ring_lock);
74}
75
76/**
77 * ioat2_update_pending - log pending descriptors
78 * @ioat: ioat2+ channel
79 *
80 * set pending to '1' unless pending is already set to '2', pending == 2
81 * indicates that submission is temporarily blocked due to an in-flight
82 * reset. If we are already above the ioat_pending_level threshold then
83 * just issue pending.
84 *
85 * called with ring_lock held
86 */
87static void ioat2_update_pending(struct ioat2_dma_chan *ioat)
88{
89 if (unlikely(ioat->pending == 2))
90 return;
91 else if (ioat2_ring_pending(ioat) > ioat_pending_level)
92 __ioat2_issue_pending(ioat);
93 else
94 ioat->pending = 1;
95}
96
97static void __ioat2_start_null_desc(struct ioat2_dma_chan *ioat)
98{
Dan Williams5cbafa62009-08-26 13:01:44 -070099 struct ioat_ring_ent *desc;
100 struct ioat_dma_descriptor *hw;
101 int idx;
102
103 if (ioat2_ring_space(ioat) < 1) {
104 dev_err(to_dev(&ioat->base),
105 "Unable to start null desc - ring full\n");
106 return;
107 }
108
Dan Williams6df91832009-09-08 12:00:55 -0700109 dev_dbg(to_dev(&ioat->base), "%s: head: %#x tail: %#x issued: %#x\n",
110 __func__, ioat->head, ioat->tail, ioat->issued);
Dan Williams5cbafa62009-08-26 13:01:44 -0700111 idx = ioat2_desc_alloc(ioat, 1);
112 desc = ioat2_get_ring_ent(ioat, idx);
113
114 hw = desc->hw;
115 hw->ctl = 0;
116 hw->ctl_f.null = 1;
117 hw->ctl_f.int_en = 1;
118 hw->ctl_f.compl_write = 1;
119 /* set size to non-zero value (channel returns error when size is 0) */
120 hw->size = NULL_DESC_BUFFER_SIZE;
121 hw->src_addr = 0;
122 hw->dst_addr = 0;
123 async_tx_ack(&desc->txd);
Dan Williams09c8a5b2009-09-08 12:01:49 -0700124 ioat2_set_chainaddr(ioat, desc->txd.phys);
Dan Williams6df91832009-09-08 12:00:55 -0700125 dump_desc_dbg(ioat, desc);
Dan Williams5cbafa62009-08-26 13:01:44 -0700126 __ioat2_issue_pending(ioat);
127}
128
129static void ioat2_start_null_desc(struct ioat2_dma_chan *ioat)
130{
131 spin_lock_bh(&ioat->ring_lock);
132 __ioat2_start_null_desc(ioat);
133 spin_unlock_bh(&ioat->ring_lock);
134}
135
Dan Williams09c8a5b2009-09-08 12:01:49 -0700136static void __cleanup(struct ioat2_dma_chan *ioat, unsigned long phys_complete)
Dan Williams5cbafa62009-08-26 13:01:44 -0700137{
138 struct ioat_chan_common *chan = &ioat->base;
Dan Williams09c8a5b2009-09-08 12:01:49 -0700139 struct dma_async_tx_descriptor *tx;
Dan Williams5cbafa62009-08-26 13:01:44 -0700140 struct ioat_ring_ent *desc;
141 bool seen_current = false;
142 u16 active;
143 int i;
Dan Williams5cbafa62009-08-26 13:01:44 -0700144
Dan Williams6df91832009-09-08 12:00:55 -0700145 dev_dbg(to_dev(chan), "%s: head: %#x tail: %#x issued: %#x\n",
146 __func__, ioat->head, ioat->tail, ioat->issued);
147
Dan Williams5cbafa62009-08-26 13:01:44 -0700148 active = ioat2_ring_active(ioat);
149 for (i = 0; i < active && !seen_current; i++) {
150 prefetch(ioat2_get_ring_ent(ioat, ioat->tail + i + 1));
151 desc = ioat2_get_ring_ent(ioat, ioat->tail + i);
152 tx = &desc->txd;
Dan Williams6df91832009-09-08 12:00:55 -0700153 dump_desc_dbg(ioat, desc);
Dan Williams5cbafa62009-08-26 13:01:44 -0700154 if (tx->cookie) {
155 ioat_dma_unmap(chan, tx->flags, desc->len, desc->hw);
156 chan->completed_cookie = tx->cookie;
157 tx->cookie = 0;
158 if (tx->callback) {
159 tx->callback(tx->callback_param);
160 tx->callback = NULL;
161 }
162 }
163
164 if (tx->phys == phys_complete)
165 seen_current = true;
166 }
167 ioat->tail += i;
168 BUG_ON(!seen_current); /* no active descs have written a completion? */
Dan Williams5cbafa62009-08-26 13:01:44 -0700169
170 chan->last_completion = phys_complete;
Dan Williams09c8a5b2009-09-08 12:01:49 -0700171 if (ioat->head == ioat->tail) {
172 dev_dbg(to_dev(chan), "%s: cancel completion timeout\n",
173 __func__);
174 clear_bit(IOAT_COMPLETION_PENDING, &chan->state);
Dan Williamsa3092182009-09-08 12:02:01 -0700175 mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT);
Dan Williams09c8a5b2009-09-08 12:01:49 -0700176 }
177}
Dan Williams5cbafa62009-08-26 13:01:44 -0700178
Dan Williams09c8a5b2009-09-08 12:01:49 -0700179/**
180 * ioat2_cleanup - clean finished descriptors (advance tail pointer)
181 * @chan: ioat channel to be cleaned up
182 */
183static void ioat2_cleanup(struct ioat2_dma_chan *ioat)
184{
185 struct ioat_chan_common *chan = &ioat->base;
186 unsigned long phys_complete;
187
188 prefetch(chan->completion);
189
190 if (!spin_trylock_bh(&chan->cleanup_lock))
191 return;
192
193 if (!ioat_cleanup_preamble(chan, &phys_complete)) {
194 spin_unlock_bh(&chan->cleanup_lock);
195 return;
196 }
197
198 if (!spin_trylock_bh(&ioat->ring_lock)) {
199 spin_unlock_bh(&chan->cleanup_lock);
200 return;
201 }
202
203 __cleanup(ioat, phys_complete);
204
205 spin_unlock_bh(&ioat->ring_lock);
Dan Williams5cbafa62009-08-26 13:01:44 -0700206 spin_unlock_bh(&chan->cleanup_lock);
207}
208
209static void ioat2_cleanup_tasklet(unsigned long data)
210{
211 struct ioat2_dma_chan *ioat = (void *) data;
212
213 ioat2_cleanup(ioat);
Dan Williamsf6ab95b2009-09-08 12:01:21 -0700214 writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET);
Dan Williams5cbafa62009-08-26 13:01:44 -0700215}
216
Dan Williamsbf40a682009-09-08 17:42:55 -0700217void __ioat2_restart_chan(struct ioat2_dma_chan *ioat)
Dan Williams09c8a5b2009-09-08 12:01:49 -0700218{
219 struct ioat_chan_common *chan = &ioat->base;
220
221 /* set the tail to be re-issued */
222 ioat->issued = ioat->tail;
223 ioat->dmacount = 0;
224 set_bit(IOAT_COMPLETION_PENDING, &chan->state);
225 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
226
227 dev_dbg(to_dev(chan),
228 "%s: head: %#x tail: %#x issued: %#x count: %#x\n",
229 __func__, ioat->head, ioat->tail, ioat->issued, ioat->dmacount);
230
231 if (ioat2_ring_pending(ioat)) {
232 struct ioat_ring_ent *desc;
233
234 desc = ioat2_get_ring_ent(ioat, ioat->tail);
235 ioat2_set_chainaddr(ioat, desc->txd.phys);
236 __ioat2_issue_pending(ioat);
237 } else
238 __ioat2_start_null_desc(ioat);
239}
240
241static void ioat2_restart_channel(struct ioat2_dma_chan *ioat)
242{
243 struct ioat_chan_common *chan = &ioat->base;
244 unsigned long phys_complete;
245 u32 status;
246
247 status = ioat_chansts(chan);
248 if (is_ioat_active(status) || is_ioat_idle(status))
249 ioat_suspend(chan);
250 while (is_ioat_active(status) || is_ioat_idle(status)) {
251 status = ioat_chansts(chan);
252 cpu_relax();
253 }
254
255 if (ioat_cleanup_preamble(chan, &phys_complete))
256 __cleanup(ioat, phys_complete);
257
Dan Williamsbf40a682009-09-08 17:42:55 -0700258 __ioat2_restart_chan(ioat);
Dan Williams09c8a5b2009-09-08 12:01:49 -0700259}
260
261static void ioat2_timer_event(unsigned long data)
262{
263 struct ioat2_dma_chan *ioat = (void *) data;
264 struct ioat_chan_common *chan = &ioat->base;
265
266 spin_lock_bh(&chan->cleanup_lock);
267 if (test_bit(IOAT_COMPLETION_PENDING, &chan->state)) {
268 unsigned long phys_complete;
269 u64 status;
270
271 spin_lock_bh(&ioat->ring_lock);
272 status = ioat_chansts(chan);
273
274 /* when halted due to errors check for channel
275 * programming errors before advancing the completion state
276 */
277 if (is_ioat_halted(status)) {
278 u32 chanerr;
279
280 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
281 BUG_ON(is_ioat_bug(chanerr));
282 }
283
284 /* if we haven't made progress and we have already
285 * acknowledged a pending completion once, then be more
286 * forceful with a restart
287 */
288 if (ioat_cleanup_preamble(chan, &phys_complete))
289 __cleanup(ioat, phys_complete);
290 else if (test_bit(IOAT_COMPLETION_ACK, &chan->state))
291 ioat2_restart_channel(ioat);
292 else {
293 set_bit(IOAT_COMPLETION_ACK, &chan->state);
294 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
295 }
296 spin_unlock_bh(&ioat->ring_lock);
Dan Williamsa3092182009-09-08 12:02:01 -0700297 } else {
298 u16 active;
299
300 /* if the ring is idle, empty, and oversized try to step
301 * down the size
302 */
303 spin_lock_bh(&ioat->ring_lock);
304 active = ioat2_ring_active(ioat);
305 if (active == 0 && ioat->alloc_order > ioat_get_alloc_order())
306 reshape_ring(ioat, ioat->alloc_order-1);
307 spin_unlock_bh(&ioat->ring_lock);
308
309 /* keep shrinking until we get back to our minimum
310 * default size
311 */
312 if (ioat->alloc_order > ioat_get_alloc_order())
313 mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT);
Dan Williams09c8a5b2009-09-08 12:01:49 -0700314 }
315 spin_unlock_bh(&chan->cleanup_lock);
316}
317
Dan Williams5cbafa62009-08-26 13:01:44 -0700318/**
319 * ioat2_enumerate_channels - find and initialize the device's channels
320 * @device: the device to be enumerated
321 */
Dan Williamsbf40a682009-09-08 17:42:55 -0700322int ioat2_enumerate_channels(struct ioatdma_device *device)
Dan Williams5cbafa62009-08-26 13:01:44 -0700323{
324 struct ioat2_dma_chan *ioat;
325 struct device *dev = &device->pdev->dev;
326 struct dma_device *dma = &device->common;
327 u8 xfercap_log;
328 int i;
329
330 INIT_LIST_HEAD(&dma->channels);
331 dma->chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET);
Dan Williamsbb320782009-09-08 12:01:14 -0700332 dma->chancnt &= 0x1f; /* bits [4:0] valid */
333 if (dma->chancnt > ARRAY_SIZE(device->idx)) {
334 dev_warn(dev, "(%d) exceeds max supported channels (%zu)\n",
335 dma->chancnt, ARRAY_SIZE(device->idx));
336 dma->chancnt = ARRAY_SIZE(device->idx);
337 }
Dan Williams5cbafa62009-08-26 13:01:44 -0700338 xfercap_log = readb(device->reg_base + IOAT_XFERCAP_OFFSET);
Dan Williamsbb320782009-09-08 12:01:14 -0700339 xfercap_log &= 0x1f; /* bits [4:0] valid */
Dan Williams5cbafa62009-08-26 13:01:44 -0700340 if (xfercap_log == 0)
341 return 0;
Dan Williams6df91832009-09-08 12:00:55 -0700342 dev_dbg(dev, "%s: xfercap = %d\n", __func__, 1 << xfercap_log);
Dan Williams5cbafa62009-08-26 13:01:44 -0700343
344 /* FIXME which i/oat version is i7300? */
345#ifdef CONFIG_I7300_IDLE_IOAT_CHANNEL
346 if (i7300_idle_platform_probe(NULL, NULL, 1) == 0)
347 dma->chancnt--;
348#endif
349 for (i = 0; i < dma->chancnt; i++) {
350 ioat = devm_kzalloc(dev, sizeof(*ioat), GFP_KERNEL);
351 if (!ioat)
352 break;
353
354 ioat_init_channel(device, &ioat->base, i,
Dan Williamsbf40a682009-09-08 17:42:55 -0700355 device->timer_fn,
356 device->cleanup_tasklet,
Dan Williams5cbafa62009-08-26 13:01:44 -0700357 (unsigned long) ioat);
358 ioat->xfercap_log = xfercap_log;
359 spin_lock_init(&ioat->ring_lock);
360 }
361 dma->chancnt = i;
362 return i;
363}
364
365static dma_cookie_t ioat2_tx_submit_unlock(struct dma_async_tx_descriptor *tx)
366{
367 struct dma_chan *c = tx->chan;
368 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
Dan Williams09c8a5b2009-09-08 12:01:49 -0700369 struct ioat_chan_common *chan = &ioat->base;
Dan Williams5cbafa62009-08-26 13:01:44 -0700370 dma_cookie_t cookie = c->cookie;
371
372 cookie++;
373 if (cookie < 0)
374 cookie = 1;
375 tx->cookie = cookie;
376 c->cookie = cookie;
Dan Williams6df91832009-09-08 12:00:55 -0700377 dev_dbg(to_dev(&ioat->base), "%s: cookie: %d\n", __func__, cookie);
378
Dan Williams09c8a5b2009-09-08 12:01:49 -0700379 if (!test_and_set_bit(IOAT_COMPLETION_PENDING, &chan->state))
380 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
Dan Williams5cbafa62009-08-26 13:01:44 -0700381 ioat2_update_pending(ioat);
382 spin_unlock_bh(&ioat->ring_lock);
383
384 return cookie;
385}
386
Dan Williamsa3092182009-09-08 12:02:01 -0700387static struct ioat_ring_ent *ioat2_alloc_ring_ent(struct dma_chan *chan, gfp_t flags)
Dan Williams5cbafa62009-08-26 13:01:44 -0700388{
389 struct ioat_dma_descriptor *hw;
390 struct ioat_ring_ent *desc;
391 struct ioatdma_device *dma;
392 dma_addr_t phys;
393
394 dma = to_ioatdma_device(chan->device);
Dan Williamsa3092182009-09-08 12:02:01 -0700395 hw = pci_pool_alloc(dma->dma_pool, flags, &phys);
Dan Williams5cbafa62009-08-26 13:01:44 -0700396 if (!hw)
397 return NULL;
398 memset(hw, 0, sizeof(*hw));
399
Dan Williamsa3092182009-09-08 12:02:01 -0700400 desc = kzalloc(sizeof(*desc), flags);
Dan Williams5cbafa62009-08-26 13:01:44 -0700401 if (!desc) {
402 pci_pool_free(dma->dma_pool, hw, phys);
403 return NULL;
404 }
405
406 dma_async_tx_descriptor_init(&desc->txd, chan);
407 desc->txd.tx_submit = ioat2_tx_submit_unlock;
408 desc->hw = hw;
409 desc->txd.phys = phys;
410 return desc;
411}
412
413static void ioat2_free_ring_ent(struct ioat_ring_ent *desc, struct dma_chan *chan)
414{
415 struct ioatdma_device *dma;
416
417 dma = to_ioatdma_device(chan->device);
418 pci_pool_free(dma->dma_pool, desc->hw, desc->txd.phys);
419 kfree(desc);
420}
421
Dan Williamsa3092182009-09-08 12:02:01 -0700422static struct ioat_ring_ent **ioat2_alloc_ring(struct dma_chan *c, int order, gfp_t flags)
423{
424 struct ioat_ring_ent **ring;
425 int descs = 1 << order;
426 int i;
427
428 if (order > ioat_get_max_alloc_order())
429 return NULL;
430
431 /* allocate the array to hold the software ring */
432 ring = kcalloc(descs, sizeof(*ring), flags);
433 if (!ring)
434 return NULL;
435 for (i = 0; i < descs; i++) {
436 ring[i] = ioat2_alloc_ring_ent(c, flags);
437 if (!ring[i]) {
438 while (i--)
439 ioat2_free_ring_ent(ring[i], c);
440 kfree(ring);
441 return NULL;
442 }
443 set_desc_id(ring[i], i);
444 }
445
446 /* link descs */
447 for (i = 0; i < descs-1; i++) {
448 struct ioat_ring_ent *next = ring[i+1];
449 struct ioat_dma_descriptor *hw = ring[i]->hw;
450
451 hw->next = next->txd.phys;
452 }
453 ring[i]->hw->next = ring[0]->txd.phys;
454
455 return ring;
456}
457
Dan Williams5cbafa62009-08-26 13:01:44 -0700458/* ioat2_alloc_chan_resources - allocate/initialize ioat2 descriptor ring
459 * @chan: channel to be initialized
460 */
Dan Williamsbf40a682009-09-08 17:42:55 -0700461int ioat2_alloc_chan_resources(struct dma_chan *c)
Dan Williams5cbafa62009-08-26 13:01:44 -0700462{
463 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
464 struct ioat_chan_common *chan = &ioat->base;
465 struct ioat_ring_ent **ring;
Dan Williams5cbafa62009-08-26 13:01:44 -0700466 u32 chanerr;
Dan Williamsa3092182009-09-08 12:02:01 -0700467 int order;
Dan Williams5cbafa62009-08-26 13:01:44 -0700468
469 /* have we already been set up? */
470 if (ioat->ring)
471 return 1 << ioat->alloc_order;
472
473 /* Setup register to interrupt and write completion status on error */
Dan Williamsf6ab95b2009-09-08 12:01:21 -0700474 writew(IOAT_CHANCTRL_RUN, chan->reg_base + IOAT_CHANCTRL_OFFSET);
Dan Williams5cbafa62009-08-26 13:01:44 -0700475
476 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
477 if (chanerr) {
478 dev_err(to_dev(chan), "CHANERR = %x, clearing\n", chanerr);
479 writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET);
480 }
481
482 /* allocate a completion writeback area */
483 /* doing 2 32bit writes to mmio since 1 64b write doesn't work */
Dan Williams4fb9b9e2009-09-08 12:01:04 -0700484 chan->completion = pci_pool_alloc(chan->device->completion_pool,
485 GFP_KERNEL, &chan->completion_dma);
486 if (!chan->completion)
Dan Williams5cbafa62009-08-26 13:01:44 -0700487 return -ENOMEM;
488
Dan Williams4fb9b9e2009-09-08 12:01:04 -0700489 memset(chan->completion, 0, sizeof(*chan->completion));
490 writel(((u64) chan->completion_dma) & 0x00000000FFFFFFFF,
Dan Williams5cbafa62009-08-26 13:01:44 -0700491 chan->reg_base + IOAT_CHANCMP_OFFSET_LOW);
Dan Williams4fb9b9e2009-09-08 12:01:04 -0700492 writel(((u64) chan->completion_dma) >> 32,
Dan Williams5cbafa62009-08-26 13:01:44 -0700493 chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH);
494
Dan Williamsa3092182009-09-08 12:02:01 -0700495 order = ioat_get_alloc_order();
496 ring = ioat2_alloc_ring(c, order, GFP_KERNEL);
Dan Williams5cbafa62009-08-26 13:01:44 -0700497 if (!ring)
498 return -ENOMEM;
Dan Williams5cbafa62009-08-26 13:01:44 -0700499
500 spin_lock_bh(&ioat->ring_lock);
501 ioat->ring = ring;
502 ioat->head = 0;
503 ioat->issued = 0;
504 ioat->tail = 0;
505 ioat->pending = 0;
Dan Williamsa3092182009-09-08 12:02:01 -0700506 ioat->alloc_order = order;
Dan Williams5cbafa62009-08-26 13:01:44 -0700507 spin_unlock_bh(&ioat->ring_lock);
508
509 tasklet_enable(&chan->cleanup_task);
510 ioat2_start_null_desc(ioat);
511
Dan Williamsa3092182009-09-08 12:02:01 -0700512 return 1 << ioat->alloc_order;
513}
514
Dan Williamsbf40a682009-09-08 17:42:55 -0700515bool reshape_ring(struct ioat2_dma_chan *ioat, int order)
Dan Williamsa3092182009-09-08 12:02:01 -0700516{
517 /* reshape differs from normal ring allocation in that we want
518 * to allocate a new software ring while only
519 * extending/truncating the hardware ring
520 */
521 struct ioat_chan_common *chan = &ioat->base;
522 struct dma_chan *c = &chan->common;
523 const u16 curr_size = ioat2_ring_mask(ioat) + 1;
524 const u16 active = ioat2_ring_active(ioat);
525 const u16 new_size = 1 << order;
526 struct ioat_ring_ent **ring;
527 u16 i;
528
529 if (order > ioat_get_max_alloc_order())
530 return false;
531
532 /* double check that we have at least 1 free descriptor */
533 if (active == curr_size)
534 return false;
535
536 /* when shrinking, verify that we can hold the current active
537 * set in the new ring
538 */
539 if (active >= new_size)
540 return false;
541
542 /* allocate the array to hold the software ring */
543 ring = kcalloc(new_size, sizeof(*ring), GFP_NOWAIT);
544 if (!ring)
545 return false;
546
547 /* allocate/trim descriptors as needed */
548 if (new_size > curr_size) {
549 /* copy current descriptors to the new ring */
550 for (i = 0; i < curr_size; i++) {
551 u16 curr_idx = (ioat->tail+i) & (curr_size-1);
552 u16 new_idx = (ioat->tail+i) & (new_size-1);
553
554 ring[new_idx] = ioat->ring[curr_idx];
555 set_desc_id(ring[new_idx], new_idx);
556 }
557
558 /* add new descriptors to the ring */
559 for (i = curr_size; i < new_size; i++) {
560 u16 new_idx = (ioat->tail+i) & (new_size-1);
561
562 ring[new_idx] = ioat2_alloc_ring_ent(c, GFP_NOWAIT);
563 if (!ring[new_idx]) {
564 while (i--) {
565 u16 new_idx = (ioat->tail+i) & (new_size-1);
566
567 ioat2_free_ring_ent(ring[new_idx], c);
568 }
569 kfree(ring);
570 return false;
571 }
572 set_desc_id(ring[new_idx], new_idx);
573 }
574
575 /* hw link new descriptors */
576 for (i = curr_size-1; i < new_size; i++) {
577 u16 new_idx = (ioat->tail+i) & (new_size-1);
578 struct ioat_ring_ent *next = ring[(new_idx+1) & (new_size-1)];
579 struct ioat_dma_descriptor *hw = ring[new_idx]->hw;
580
581 hw->next = next->txd.phys;
582 }
583 } else {
584 struct ioat_dma_descriptor *hw;
585 struct ioat_ring_ent *next;
586
587 /* copy current descriptors to the new ring, dropping the
588 * removed descriptors
589 */
590 for (i = 0; i < new_size; i++) {
591 u16 curr_idx = (ioat->tail+i) & (curr_size-1);
592 u16 new_idx = (ioat->tail+i) & (new_size-1);
593
594 ring[new_idx] = ioat->ring[curr_idx];
595 set_desc_id(ring[new_idx], new_idx);
596 }
597
598 /* free deleted descriptors */
599 for (i = new_size; i < curr_size; i++) {
600 struct ioat_ring_ent *ent;
601
602 ent = ioat2_get_ring_ent(ioat, ioat->tail+i);
603 ioat2_free_ring_ent(ent, c);
604 }
605
606 /* fix up hardware ring */
607 hw = ring[(ioat->tail+new_size-1) & (new_size-1)]->hw;
608 next = ring[(ioat->tail+new_size) & (new_size-1)];
609 hw->next = next->txd.phys;
610 }
611
612 dev_dbg(to_dev(chan), "%s: allocated %d descriptors\n",
613 __func__, new_size);
614
615 kfree(ioat->ring);
616 ioat->ring = ring;
617 ioat->alloc_order = order;
618
619 return true;
Dan Williams5cbafa62009-08-26 13:01:44 -0700620}
621
622/**
623 * ioat2_alloc_and_lock - common descriptor alloc boilerplate for ioat2,3 ops
624 * @idx: gets starting descriptor index on successful allocation
625 * @ioat: ioat2,3 channel (ring) to operate on
626 * @num_descs: allocation length
627 */
Dan Williamsbf40a682009-09-08 17:42:55 -0700628int ioat2_alloc_and_lock(u16 *idx, struct ioat2_dma_chan *ioat, int num_descs)
Dan Williams5cbafa62009-08-26 13:01:44 -0700629{
630 struct ioat_chan_common *chan = &ioat->base;
631
632 spin_lock_bh(&ioat->ring_lock);
Dan Williamsa3092182009-09-08 12:02:01 -0700633 /* never allow the last descriptor to be consumed, we need at
634 * least one free at all times to allow for on-the-fly ring
635 * resizing.
636 */
637 while (unlikely(ioat2_ring_space(ioat) <= num_descs)) {
638 if (reshape_ring(ioat, ioat->alloc_order + 1) &&
639 ioat2_ring_space(ioat) > num_descs)
640 break;
641
Dan Williams5cbafa62009-08-26 13:01:44 -0700642 if (printk_ratelimit())
643 dev_dbg(to_dev(chan),
644 "%s: ring full! num_descs: %d (%x:%x:%x)\n",
645 __func__, num_descs, ioat->head, ioat->tail,
646 ioat->issued);
647 spin_unlock_bh(&ioat->ring_lock);
648
Dan Williams09c8a5b2009-09-08 12:01:49 -0700649 /* progress reclaim in the allocation failure case we
650 * may be called under bh_disabled so we need to trigger
651 * the timer event directly
652 */
653 spin_lock_bh(&chan->cleanup_lock);
654 if (jiffies > chan->timer.expires &&
655 timer_pending(&chan->timer)) {
Dan Williamsbf40a682009-09-08 17:42:55 -0700656 struct ioatdma_device *device = chan->device;
657
Dan Williams09c8a5b2009-09-08 12:01:49 -0700658 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
659 spin_unlock_bh(&chan->cleanup_lock);
Dan Williamsbf40a682009-09-08 17:42:55 -0700660 device->timer_fn((unsigned long) ioat);
Dan Williams09c8a5b2009-09-08 12:01:49 -0700661 } else
662 spin_unlock_bh(&chan->cleanup_lock);
Dan Williams5cbafa62009-08-26 13:01:44 -0700663 return -ENOMEM;
664 }
665
666 dev_dbg(to_dev(chan), "%s: num_descs: %d (%x:%x:%x)\n",
667 __func__, num_descs, ioat->head, ioat->tail, ioat->issued);
668
669 *idx = ioat2_desc_alloc(ioat, num_descs);
670 return 0; /* with ioat->ring_lock held */
671}
672
Dan Williamsbf40a682009-09-08 17:42:55 -0700673struct dma_async_tx_descriptor *
Dan Williams5cbafa62009-08-26 13:01:44 -0700674ioat2_dma_prep_memcpy_lock(struct dma_chan *c, dma_addr_t dma_dest,
675 dma_addr_t dma_src, size_t len, unsigned long flags)
676{
677 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
678 struct ioat_dma_descriptor *hw;
679 struct ioat_ring_ent *desc;
680 dma_addr_t dst = dma_dest;
681 dma_addr_t src = dma_src;
682 size_t total_len = len;
683 int num_descs;
684 u16 idx;
685 int i;
686
687 num_descs = ioat2_xferlen_to_descs(ioat, len);
688 if (likely(num_descs) &&
689 ioat2_alloc_and_lock(&idx, ioat, num_descs) == 0)
690 /* pass */;
691 else
692 return NULL;
693 for (i = 0; i < num_descs; i++) {
694 size_t copy = min_t(size_t, len, 1 << ioat->xfercap_log);
695
696 desc = ioat2_get_ring_ent(ioat, idx + i);
697 hw = desc->hw;
698
699 hw->size = copy;
700 hw->ctl = 0;
701 hw->src_addr = src;
702 hw->dst_addr = dst;
703
704 len -= copy;
705 dst += copy;
706 src += copy;
Dan Williams6df91832009-09-08 12:00:55 -0700707 dump_desc_dbg(ioat, desc);
Dan Williams5cbafa62009-08-26 13:01:44 -0700708 }
709
710 desc->txd.flags = flags;
711 desc->len = total_len;
712 hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
Dan Williams128f2d52009-09-08 17:42:53 -0700713 hw->ctl_f.fence = !!(flags & DMA_PREP_FENCE);
Dan Williams5cbafa62009-08-26 13:01:44 -0700714 hw->ctl_f.compl_write = 1;
Dan Williams6df91832009-09-08 12:00:55 -0700715 dump_desc_dbg(ioat, desc);
Dan Williams5cbafa62009-08-26 13:01:44 -0700716 /* we leave the channel locked to ensure in order submission */
717
718 return &desc->txd;
719}
720
721/**
722 * ioat2_free_chan_resources - release all the descriptors
723 * @chan: the channel to be cleaned
724 */
Dan Williamsbf40a682009-09-08 17:42:55 -0700725void ioat2_free_chan_resources(struct dma_chan *c)
Dan Williams5cbafa62009-08-26 13:01:44 -0700726{
727 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
728 struct ioat_chan_common *chan = &ioat->base;
Dan Williamsbf40a682009-09-08 17:42:55 -0700729 struct ioatdma_device *device = chan->device;
Dan Williams5cbafa62009-08-26 13:01:44 -0700730 struct ioat_ring_ent *desc;
731 const u16 total_descs = 1 << ioat->alloc_order;
732 int descs;
733 int i;
734
735 /* Before freeing channel resources first check
736 * if they have been previously allocated for this channel.
737 */
738 if (!ioat->ring)
739 return;
740
741 tasklet_disable(&chan->cleanup_task);
Dan Williams09c8a5b2009-09-08 12:01:49 -0700742 del_timer_sync(&chan->timer);
Dan Williamsbf40a682009-09-08 17:42:55 -0700743 device->cleanup_tasklet((unsigned long) ioat);
Dan Williams5cbafa62009-08-26 13:01:44 -0700744
745 /* Delay 100ms after reset to allow internal DMA logic to quiesce
746 * before removing DMA descriptor resources.
747 */
748 writeb(IOAT_CHANCMD_RESET,
749 chan->reg_base + IOAT_CHANCMD_OFFSET(chan->device->version));
750 mdelay(100);
751
752 spin_lock_bh(&ioat->ring_lock);
753 descs = ioat2_ring_space(ioat);
Dan Williams6df91832009-09-08 12:00:55 -0700754 dev_dbg(to_dev(chan), "freeing %d idle descriptors\n", descs);
Dan Williams5cbafa62009-08-26 13:01:44 -0700755 for (i = 0; i < descs; i++) {
756 desc = ioat2_get_ring_ent(ioat, ioat->head + i);
757 ioat2_free_ring_ent(desc, c);
758 }
759
760 if (descs < total_descs)
761 dev_err(to_dev(chan), "Freeing %d in use descriptors!\n",
762 total_descs - descs);
763
764 for (i = 0; i < total_descs - descs; i++) {
765 desc = ioat2_get_ring_ent(ioat, ioat->tail + i);
Dan Williams6df91832009-09-08 12:00:55 -0700766 dump_desc_dbg(ioat, desc);
Dan Williams5cbafa62009-08-26 13:01:44 -0700767 ioat2_free_ring_ent(desc, c);
768 }
769
770 kfree(ioat->ring);
771 ioat->ring = NULL;
772 ioat->alloc_order = 0;
Dan Williamsbf40a682009-09-08 17:42:55 -0700773 pci_pool_free(device->completion_pool, chan->completion,
Dan Williams4fb9b9e2009-09-08 12:01:04 -0700774 chan->completion_dma);
Dan Williams5cbafa62009-08-26 13:01:44 -0700775 spin_unlock_bh(&ioat->ring_lock);
776
777 chan->last_completion = 0;
Dan Williams4fb9b9e2009-09-08 12:01:04 -0700778 chan->completion_dma = 0;
Dan Williams5cbafa62009-08-26 13:01:44 -0700779 ioat->pending = 0;
780 ioat->dmacount = 0;
Dan Williams5cbafa62009-08-26 13:01:44 -0700781}
782
Dan Williamsbf40a682009-09-08 17:42:55 -0700783enum dma_status
Dan Williams5cbafa62009-08-26 13:01:44 -0700784ioat2_is_complete(struct dma_chan *c, dma_cookie_t cookie,
785 dma_cookie_t *done, dma_cookie_t *used)
786{
787 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
Dan Williamsbf40a682009-09-08 17:42:55 -0700788 struct ioatdma_device *device = ioat->base.device;
Dan Williams5cbafa62009-08-26 13:01:44 -0700789
790 if (ioat_is_complete(c, cookie, done, used) == DMA_SUCCESS)
791 return DMA_SUCCESS;
792
Dan Williamsbf40a682009-09-08 17:42:55 -0700793 device->cleanup_tasklet((unsigned long) ioat);
Dan Williams5cbafa62009-08-26 13:01:44 -0700794
795 return ioat_is_complete(c, cookie, done, used);
796}
797
Dan Williams5669e312009-09-08 17:42:56 -0700798static ssize_t ring_size_show(struct dma_chan *c, char *page)
799{
800 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
801
802 return sprintf(page, "%d\n", (1 << ioat->alloc_order) & ~1);
803}
804static struct ioat_sysfs_entry ring_size_attr = __ATTR_RO(ring_size);
805
806static ssize_t ring_active_show(struct dma_chan *c, char *page)
807{
808 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
809
810 /* ...taken outside the lock, no need to be precise */
811 return sprintf(page, "%d\n", ioat2_ring_active(ioat));
812}
813static struct ioat_sysfs_entry ring_active_attr = __ATTR_RO(ring_active);
814
815static struct attribute *ioat2_attrs[] = {
816 &ring_size_attr.attr,
817 &ring_active_attr.attr,
818 &ioat_cap_attr.attr,
819 &ioat_version_attr.attr,
820 NULL,
821};
822
823struct kobj_type ioat2_ktype = {
824 .sysfs_ops = &ioat_sysfs_ops,
825 .default_attrs = ioat2_attrs,
826};
827
Dan Williams345d8522009-09-08 12:01:30 -0700828int __devinit ioat2_dma_probe(struct ioatdma_device *device, int dca)
Dan Williams5cbafa62009-08-26 13:01:44 -0700829{
830 struct pci_dev *pdev = device->pdev;
831 struct dma_device *dma;
832 struct dma_chan *c;
833 struct ioat_chan_common *chan;
834 int err;
835
836 device->enumerate_channels = ioat2_enumerate_channels;
Dan Williamsbf40a682009-09-08 17:42:55 -0700837 device->cleanup_tasklet = ioat2_cleanup_tasklet;
838 device->timer_fn = ioat2_timer_event;
Dan Williams9de6fc72009-09-08 17:42:58 -0700839 device->self_test = ioat_dma_self_test;
Dan Williams5cbafa62009-08-26 13:01:44 -0700840 dma = &device->common;
841 dma->device_prep_dma_memcpy = ioat2_dma_prep_memcpy_lock;
842 dma->device_issue_pending = ioat2_issue_pending;
843 dma->device_alloc_chan_resources = ioat2_alloc_chan_resources;
844 dma->device_free_chan_resources = ioat2_free_chan_resources;
845 dma->device_is_tx_complete = ioat2_is_complete;
846
847 err = ioat_probe(device);
848 if (err)
849 return err;
850 ioat_set_tcp_copy_break(2048);
851
852 list_for_each_entry(c, &dma->channels, device_node) {
853 chan = to_chan_common(c);
854 writel(IOAT_DCACTRL_CMPL_WRITE_ENABLE | IOAT_DMA_DCA_ANY_CPU,
855 chan->reg_base + IOAT_DCACTRL_OFFSET);
856 }
857
858 err = ioat_register(device);
859 if (err)
860 return err;
Dan Williams5669e312009-09-08 17:42:56 -0700861
862 ioat_kobject_add(device, &ioat2_ktype);
863
Dan Williams5cbafa62009-08-26 13:01:44 -0700864 if (dca)
865 device->dca = ioat2_dca_init(pdev, device->reg_base);
866
Dan Williams5cbafa62009-08-26 13:01:44 -0700867 return err;
868}