Timur Tabi | d7584ed | 2008-01-15 09:56:13 -0600 | [diff] [blame] | 1 | /* |
| 2 | * Freescale QUICC Engine UART device driver |
| 3 | * |
| 4 | * Author: Timur Tabi <timur@freescale.com> |
| 5 | * |
| 6 | * Copyright 2007 Freescale Semiconductor, Inc. This file is licensed under |
| 7 | * the terms of the GNU General Public License version 2. This program |
| 8 | * is licensed "as is" without any warranty of any kind, whether express |
| 9 | * or implied. |
| 10 | * |
| 11 | * This driver adds support for UART devices via Freescale's QUICC Engine |
| 12 | * found on some Freescale SOCs. |
| 13 | * |
| 14 | * If Soft-UART support is needed but not already present, then this driver |
| 15 | * will request and upload the "Soft-UART" microcode upon probe. The |
| 16 | * filename of the microcode should be fsl_qe_ucode_uart_X_YZ.bin, where "X" |
| 17 | * is the name of the SOC (e.g. 8323), and YZ is the revision of the SOC, |
| 18 | * (e.g. "11" for 1.1). |
| 19 | */ |
| 20 | |
| 21 | #include <linux/module.h> |
| 22 | #include <linux/serial.h> |
| 23 | #include <linux/serial_core.h> |
| 24 | #include <linux/io.h> |
| 25 | #include <linux/of_platform.h> |
| 26 | #include <linux/dma-mapping.h> |
| 27 | |
| 28 | #include <linux/fs_uart_pd.h> |
| 29 | #include <asm/ucc_slow.h> |
| 30 | |
| 31 | #include <linux/firmware.h> |
| 32 | #include <asm/reg.h> |
| 33 | |
| 34 | /* |
| 35 | * The GUMR flag for Soft UART. This would normally be defined in qe.h, |
| 36 | * but Soft-UART is a hack and we want to keep everything related to it in |
| 37 | * this file. |
| 38 | */ |
| 39 | #define UCC_SLOW_GUMR_H_SUART 0x00004000 /* Soft-UART */ |
| 40 | |
| 41 | /* |
| 42 | * soft_uart is 1 if we need to use Soft-UART mode |
| 43 | */ |
| 44 | static int soft_uart; |
| 45 | /* |
| 46 | * firmware_loaded is 1 if the firmware has been loaded, 0 otherwise. |
| 47 | */ |
| 48 | static int firmware_loaded; |
| 49 | |
| 50 | /* Enable this macro to configure all serial ports in internal loopback |
| 51 | mode */ |
| 52 | /* #define LOOPBACK */ |
| 53 | |
| 54 | /* The major and minor device numbers are defined in |
| 55 | * http://www.lanana.org/docs/device-list/devices-2.6+.txt. For the QE |
| 56 | * UART, we have major number 204 and minor numbers 46 - 49, which are the |
| 57 | * same as for the CPM2. This decision was made because no Freescale part |
| 58 | * has both a CPM and a QE. |
| 59 | */ |
| 60 | #define SERIAL_QE_MAJOR 204 |
| 61 | #define SERIAL_QE_MINOR 46 |
| 62 | |
| 63 | /* Since we only have minor numbers 46 - 49, there is a hard limit of 4 ports */ |
| 64 | #define UCC_MAX_UART 4 |
| 65 | |
| 66 | /* The number of buffer descriptors for receiving characters. */ |
| 67 | #define RX_NUM_FIFO 4 |
| 68 | |
| 69 | /* The number of buffer descriptors for transmitting characters. */ |
| 70 | #define TX_NUM_FIFO 4 |
| 71 | |
| 72 | /* The maximum size of the character buffer for a single RX BD. */ |
| 73 | #define RX_BUF_SIZE 32 |
| 74 | |
| 75 | /* The maximum size of the character buffer for a single TX BD. */ |
| 76 | #define TX_BUF_SIZE 32 |
| 77 | |
| 78 | /* |
| 79 | * The number of jiffies to wait after receiving a close command before the |
| 80 | * device is actually closed. This allows the last few characters to be |
| 81 | * sent over the wire. |
| 82 | */ |
| 83 | #define UCC_WAIT_CLOSING 100 |
| 84 | |
| 85 | struct ucc_uart_pram { |
| 86 | struct ucc_slow_pram common; |
| 87 | u8 res1[8]; /* reserved */ |
| 88 | __be16 maxidl; /* Maximum idle chars */ |
| 89 | __be16 idlc; /* temp idle counter */ |
| 90 | __be16 brkcr; /* Break count register */ |
| 91 | __be16 parec; /* receive parity error counter */ |
| 92 | __be16 frmec; /* receive framing error counter */ |
| 93 | __be16 nosec; /* receive noise counter */ |
| 94 | __be16 brkec; /* receive break condition counter */ |
| 95 | __be16 brkln; /* last received break length */ |
| 96 | __be16 uaddr[2]; /* UART address character 1 & 2 */ |
| 97 | __be16 rtemp; /* Temp storage */ |
| 98 | __be16 toseq; /* Transmit out of sequence char */ |
| 99 | __be16 cchars[8]; /* control characters 1-8 */ |
| 100 | __be16 rccm; /* receive control character mask */ |
| 101 | __be16 rccr; /* receive control character register */ |
| 102 | __be16 rlbc; /* receive last break character */ |
| 103 | __be16 res2; /* reserved */ |
| 104 | __be32 res3; /* reserved, should be cleared */ |
| 105 | u8 res4; /* reserved, should be cleared */ |
| 106 | u8 res5[3]; /* reserved, should be cleared */ |
| 107 | __be32 res6; /* reserved, should be cleared */ |
| 108 | __be32 res7; /* reserved, should be cleared */ |
| 109 | __be32 res8; /* reserved, should be cleared */ |
| 110 | __be32 res9; /* reserved, should be cleared */ |
| 111 | __be32 res10; /* reserved, should be cleared */ |
| 112 | __be32 res11; /* reserved, should be cleared */ |
| 113 | __be32 res12; /* reserved, should be cleared */ |
| 114 | __be32 res13; /* reserved, should be cleared */ |
| 115 | /* The rest is for Soft-UART only */ |
| 116 | __be16 supsmr; /* 0x90, Shadow UPSMR */ |
| 117 | __be16 res92; /* 0x92, reserved, initialize to 0 */ |
| 118 | __be32 rx_state; /* 0x94, RX state, initialize to 0 */ |
| 119 | __be32 rx_cnt; /* 0x98, RX count, initialize to 0 */ |
| 120 | u8 rx_length; /* 0x9C, Char length, set to 1+CL+PEN+1+SL */ |
| 121 | u8 rx_bitmark; /* 0x9D, reserved, initialize to 0 */ |
| 122 | u8 rx_temp_dlst_qe; /* 0x9E, reserved, initialize to 0 */ |
| 123 | u8 res14[0xBC - 0x9F]; /* reserved */ |
| 124 | __be32 dump_ptr; /* 0xBC, Dump pointer */ |
| 125 | __be32 rx_frame_rem; /* 0xC0, reserved, initialize to 0 */ |
| 126 | u8 rx_frame_rem_size; /* 0xC4, reserved, initialize to 0 */ |
| 127 | u8 tx_mode; /* 0xC5, mode, 0=AHDLC, 1=UART */ |
| 128 | __be16 tx_state; /* 0xC6, TX state */ |
| 129 | u8 res15[0xD0 - 0xC8]; /* reserved */ |
| 130 | __be32 resD0; /* 0xD0, reserved, initialize to 0 */ |
| 131 | u8 resD4; /* 0xD4, reserved, initialize to 0 */ |
| 132 | __be16 resD5; /* 0xD5, reserved, initialize to 0 */ |
| 133 | } __attribute__ ((packed)); |
| 134 | |
| 135 | /* SUPSMR definitions, for Soft-UART only */ |
| 136 | #define UCC_UART_SUPSMR_SL 0x8000 |
| 137 | #define UCC_UART_SUPSMR_RPM_MASK 0x6000 |
| 138 | #define UCC_UART_SUPSMR_RPM_ODD 0x0000 |
| 139 | #define UCC_UART_SUPSMR_RPM_LOW 0x2000 |
| 140 | #define UCC_UART_SUPSMR_RPM_EVEN 0x4000 |
| 141 | #define UCC_UART_SUPSMR_RPM_HIGH 0x6000 |
| 142 | #define UCC_UART_SUPSMR_PEN 0x1000 |
| 143 | #define UCC_UART_SUPSMR_TPM_MASK 0x0C00 |
| 144 | #define UCC_UART_SUPSMR_TPM_ODD 0x0000 |
| 145 | #define UCC_UART_SUPSMR_TPM_LOW 0x0400 |
| 146 | #define UCC_UART_SUPSMR_TPM_EVEN 0x0800 |
| 147 | #define UCC_UART_SUPSMR_TPM_HIGH 0x0C00 |
| 148 | #define UCC_UART_SUPSMR_FRZ 0x0100 |
| 149 | #define UCC_UART_SUPSMR_UM_MASK 0x00c0 |
| 150 | #define UCC_UART_SUPSMR_UM_NORMAL 0x0000 |
| 151 | #define UCC_UART_SUPSMR_UM_MAN_MULTI 0x0040 |
| 152 | #define UCC_UART_SUPSMR_UM_AUTO_MULTI 0x00c0 |
| 153 | #define UCC_UART_SUPSMR_CL_MASK 0x0030 |
| 154 | #define UCC_UART_SUPSMR_CL_8 0x0030 |
| 155 | #define UCC_UART_SUPSMR_CL_7 0x0020 |
| 156 | #define UCC_UART_SUPSMR_CL_6 0x0010 |
| 157 | #define UCC_UART_SUPSMR_CL_5 0x0000 |
| 158 | |
| 159 | #define UCC_UART_TX_STATE_AHDLC 0x00 |
| 160 | #define UCC_UART_TX_STATE_UART 0x01 |
| 161 | #define UCC_UART_TX_STATE_X1 0x00 |
| 162 | #define UCC_UART_TX_STATE_X16 0x80 |
| 163 | |
| 164 | #define UCC_UART_PRAM_ALIGNMENT 0x100 |
| 165 | |
| 166 | #define UCC_UART_SIZE_OF_BD UCC_SLOW_SIZE_OF_BD |
| 167 | #define NUM_CONTROL_CHARS 8 |
| 168 | |
| 169 | /* Private per-port data structure */ |
| 170 | struct uart_qe_port { |
| 171 | struct uart_port port; |
| 172 | struct ucc_slow __iomem *uccp; |
| 173 | struct ucc_uart_pram __iomem *uccup; |
| 174 | struct ucc_slow_info us_info; |
| 175 | struct ucc_slow_private *us_private; |
| 176 | struct device_node *np; |
| 177 | unsigned int ucc_num; /* First ucc is 0, not 1 */ |
| 178 | |
| 179 | u16 rx_nrfifos; |
| 180 | u16 rx_fifosize; |
| 181 | u16 tx_nrfifos; |
| 182 | u16 tx_fifosize; |
| 183 | int wait_closing; |
| 184 | u32 flags; |
| 185 | struct qe_bd *rx_bd_base; |
| 186 | struct qe_bd *rx_cur; |
| 187 | struct qe_bd *tx_bd_base; |
| 188 | struct qe_bd *tx_cur; |
| 189 | unsigned char *tx_buf; |
| 190 | unsigned char *rx_buf; |
| 191 | void *bd_virt; /* virtual address of the BD buffers */ |
| 192 | dma_addr_t bd_dma_addr; /* bus address of the BD buffers */ |
| 193 | unsigned int bd_size; /* size of BD buffer space */ |
| 194 | }; |
| 195 | |
| 196 | static struct uart_driver ucc_uart_driver = { |
| 197 | .owner = THIS_MODULE, |
Anton Vorontsov | 4feead7 | 2008-06-05 22:45:58 -0700 | [diff] [blame] | 198 | .driver_name = "ucc_uart", |
Timur Tabi | d7584ed | 2008-01-15 09:56:13 -0600 | [diff] [blame] | 199 | .dev_name = "ttyQE", |
| 200 | .major = SERIAL_QE_MAJOR, |
| 201 | .minor = SERIAL_QE_MINOR, |
| 202 | .nr = UCC_MAX_UART, |
| 203 | }; |
| 204 | |
| 205 | /* |
| 206 | * Virtual to physical address translation. |
| 207 | * |
| 208 | * Given the virtual address for a character buffer, this function returns |
| 209 | * the physical (DMA) equivalent. |
| 210 | */ |
| 211 | static inline dma_addr_t cpu2qe_addr(void *addr, struct uart_qe_port *qe_port) |
| 212 | { |
| 213 | if (likely((addr >= qe_port->bd_virt)) && |
| 214 | (addr < (qe_port->bd_virt + qe_port->bd_size))) |
| 215 | return qe_port->bd_dma_addr + (addr - qe_port->bd_virt); |
| 216 | |
| 217 | /* something nasty happened */ |
Harvey Harrison | 71cc2c2 | 2008-04-30 00:55:10 -0700 | [diff] [blame] | 218 | printk(KERN_ERR "%s: addr=%p\n", __func__, addr); |
Timur Tabi | d7584ed | 2008-01-15 09:56:13 -0600 | [diff] [blame] | 219 | BUG(); |
| 220 | return 0; |
| 221 | } |
| 222 | |
| 223 | /* |
| 224 | * Physical to virtual address translation. |
| 225 | * |
| 226 | * Given the physical (DMA) address for a character buffer, this function |
| 227 | * returns the virtual equivalent. |
| 228 | */ |
| 229 | static inline void *qe2cpu_addr(dma_addr_t addr, struct uart_qe_port *qe_port) |
| 230 | { |
| 231 | /* sanity check */ |
| 232 | if (likely((addr >= qe_port->bd_dma_addr) && |
| 233 | (addr < (qe_port->bd_dma_addr + qe_port->bd_size)))) |
| 234 | return qe_port->bd_virt + (addr - qe_port->bd_dma_addr); |
| 235 | |
| 236 | /* something nasty happened */ |
Harvey Harrison | 71cc2c2 | 2008-04-30 00:55:10 -0700 | [diff] [blame] | 237 | printk(KERN_ERR "%s: addr=%x\n", __func__, addr); |
Timur Tabi | d7584ed | 2008-01-15 09:56:13 -0600 | [diff] [blame] | 238 | BUG(); |
| 239 | return NULL; |
| 240 | } |
| 241 | |
| 242 | /* |
| 243 | * Return 1 if the QE is done transmitting all buffers for this port |
| 244 | * |
| 245 | * This function scans each BD in sequence. If we find a BD that is not |
| 246 | * ready (READY=1), then we return 0 indicating that the QE is still sending |
| 247 | * data. If we reach the last BD (WRAP=1), then we know we've scanned |
| 248 | * the entire list, and all BDs are done. |
| 249 | */ |
| 250 | static unsigned int qe_uart_tx_empty(struct uart_port *port) |
| 251 | { |
| 252 | struct uart_qe_port *qe_port = |
| 253 | container_of(port, struct uart_qe_port, port); |
| 254 | struct qe_bd *bdp = qe_port->tx_bd_base; |
| 255 | |
| 256 | while (1) { |
| 257 | if (in_be16(&bdp->status) & BD_SC_READY) |
| 258 | /* This BD is not done, so return "not done" */ |
| 259 | return 0; |
| 260 | |
| 261 | if (in_be16(&bdp->status) & BD_SC_WRAP) |
| 262 | /* |
| 263 | * This BD is done and it's the last one, so return |
| 264 | * "done" |
| 265 | */ |
| 266 | return 1; |
| 267 | |
| 268 | bdp++; |
| 269 | }; |
| 270 | } |
| 271 | |
| 272 | /* |
| 273 | * Set the modem control lines |
| 274 | * |
| 275 | * Although the QE can control the modem control lines (e.g. CTS), we |
| 276 | * don't need that support. This function must exist, however, otherwise |
| 277 | * the kernel will panic. |
| 278 | */ |
| 279 | void qe_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) |
| 280 | { |
| 281 | } |
| 282 | |
| 283 | /* |
| 284 | * Get the current modem control line status |
| 285 | * |
| 286 | * Although the QE can control the modem control lines (e.g. CTS), this |
| 287 | * driver currently doesn't support that, so we always return Carrier |
| 288 | * Detect, Data Set Ready, and Clear To Send. |
| 289 | */ |
| 290 | static unsigned int qe_uart_get_mctrl(struct uart_port *port) |
| 291 | { |
| 292 | return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; |
| 293 | } |
| 294 | |
| 295 | /* |
| 296 | * Disable the transmit interrupt. |
| 297 | * |
| 298 | * Although this function is called "stop_tx", it does not actually stop |
| 299 | * transmission of data. Instead, it tells the QE to not generate an |
| 300 | * interrupt when the UCC is finished sending characters. |
| 301 | */ |
| 302 | static void qe_uart_stop_tx(struct uart_port *port) |
| 303 | { |
| 304 | struct uart_qe_port *qe_port = |
| 305 | container_of(port, struct uart_qe_port, port); |
| 306 | |
| 307 | clrbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX); |
| 308 | } |
| 309 | |
| 310 | /* |
| 311 | * Transmit as many characters to the HW as possible. |
| 312 | * |
| 313 | * This function will attempt to stuff of all the characters from the |
| 314 | * kernel's transmit buffer into TX BDs. |
| 315 | * |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 316 | * A return value of non-zero indicates that it successfully stuffed all |
Timur Tabi | d7584ed | 2008-01-15 09:56:13 -0600 | [diff] [blame] | 317 | * characters from the kernel buffer. |
| 318 | * |
| 319 | * A return value of zero indicates that there are still characters in the |
| 320 | * kernel's buffer that have not been transmitted, but there are no more BDs |
| 321 | * available. This function should be called again after a BD has been made |
| 322 | * available. |
| 323 | */ |
| 324 | static int qe_uart_tx_pump(struct uart_qe_port *qe_port) |
| 325 | { |
| 326 | struct qe_bd *bdp; |
| 327 | unsigned char *p; |
| 328 | unsigned int count; |
| 329 | struct uart_port *port = &qe_port->port; |
Alan Cox | ebd2c8f | 2009-09-19 13:13:28 -0700 | [diff] [blame] | 330 | struct circ_buf *xmit = &port->state->xmit; |
Timur Tabi | d7584ed | 2008-01-15 09:56:13 -0600 | [diff] [blame] | 331 | |
| 332 | bdp = qe_port->rx_cur; |
| 333 | |
| 334 | /* Handle xon/xoff */ |
| 335 | if (port->x_char) { |
| 336 | /* Pick next descriptor and fill from buffer */ |
| 337 | bdp = qe_port->tx_cur; |
| 338 | |
| 339 | p = qe2cpu_addr(bdp->buf, qe_port); |
| 340 | |
| 341 | *p++ = port->x_char; |
| 342 | out_be16(&bdp->length, 1); |
| 343 | setbits16(&bdp->status, BD_SC_READY); |
| 344 | /* Get next BD. */ |
| 345 | if (in_be16(&bdp->status) & BD_SC_WRAP) |
| 346 | bdp = qe_port->tx_bd_base; |
| 347 | else |
| 348 | bdp++; |
| 349 | qe_port->tx_cur = bdp; |
| 350 | |
| 351 | port->icount.tx++; |
| 352 | port->x_char = 0; |
| 353 | return 1; |
| 354 | } |
| 355 | |
| 356 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { |
| 357 | qe_uart_stop_tx(port); |
| 358 | return 0; |
| 359 | } |
| 360 | |
| 361 | /* Pick next descriptor and fill from buffer */ |
| 362 | bdp = qe_port->tx_cur; |
| 363 | |
| 364 | while (!(in_be16(&bdp->status) & BD_SC_READY) && |
| 365 | (xmit->tail != xmit->head)) { |
| 366 | count = 0; |
| 367 | p = qe2cpu_addr(bdp->buf, qe_port); |
| 368 | while (count < qe_port->tx_fifosize) { |
| 369 | *p++ = xmit->buf[xmit->tail]; |
| 370 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); |
| 371 | port->icount.tx++; |
| 372 | count++; |
| 373 | if (xmit->head == xmit->tail) |
| 374 | break; |
| 375 | } |
| 376 | |
| 377 | out_be16(&bdp->length, count); |
| 378 | setbits16(&bdp->status, BD_SC_READY); |
| 379 | |
| 380 | /* Get next BD. */ |
| 381 | if (in_be16(&bdp->status) & BD_SC_WRAP) |
| 382 | bdp = qe_port->tx_bd_base; |
| 383 | else |
| 384 | bdp++; |
| 385 | } |
| 386 | qe_port->tx_cur = bdp; |
| 387 | |
| 388 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
| 389 | uart_write_wakeup(port); |
| 390 | |
| 391 | if (uart_circ_empty(xmit)) { |
| 392 | /* The kernel buffer is empty, so turn off TX interrupts. We |
| 393 | don't need to be told when the QE is finished transmitting |
| 394 | the data. */ |
| 395 | qe_uart_stop_tx(port); |
| 396 | return 0; |
| 397 | } |
| 398 | |
| 399 | return 1; |
| 400 | } |
| 401 | |
| 402 | /* |
| 403 | * Start transmitting data |
| 404 | * |
| 405 | * This function will start transmitting any available data, if the port |
| 406 | * isn't already transmitting data. |
| 407 | */ |
| 408 | static void qe_uart_start_tx(struct uart_port *port) |
| 409 | { |
| 410 | struct uart_qe_port *qe_port = |
| 411 | container_of(port, struct uart_qe_port, port); |
| 412 | |
| 413 | /* If we currently are transmitting, then just return */ |
| 414 | if (in_be16(&qe_port->uccp->uccm) & UCC_UART_UCCE_TX) |
| 415 | return; |
| 416 | |
| 417 | /* Otherwise, pump the port and start transmission */ |
| 418 | if (qe_uart_tx_pump(qe_port)) |
| 419 | setbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX); |
| 420 | } |
| 421 | |
| 422 | /* |
| 423 | * Stop transmitting data |
| 424 | */ |
| 425 | static void qe_uart_stop_rx(struct uart_port *port) |
| 426 | { |
| 427 | struct uart_qe_port *qe_port = |
| 428 | container_of(port, struct uart_qe_port, port); |
| 429 | |
| 430 | clrbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX); |
| 431 | } |
| 432 | |
| 433 | /* |
| 434 | * Enable status change interrupts |
| 435 | * |
| 436 | * We don't support status change interrupts, but we need to define this |
| 437 | * function otherwise the kernel will panic. |
| 438 | */ |
| 439 | static void qe_uart_enable_ms(struct uart_port *port) |
| 440 | { |
| 441 | } |
| 442 | |
| 443 | /* Start or stop sending break signal |
| 444 | * |
| 445 | * This function controls the sending of a break signal. If break_state=1, |
| 446 | * then we start sending a break signal. If break_state=0, then we stop |
| 447 | * sending the break signal. |
| 448 | */ |
| 449 | static void qe_uart_break_ctl(struct uart_port *port, int break_state) |
| 450 | { |
| 451 | struct uart_qe_port *qe_port = |
| 452 | container_of(port, struct uart_qe_port, port); |
| 453 | |
| 454 | if (break_state) |
| 455 | ucc_slow_stop_tx(qe_port->us_private); |
| 456 | else |
| 457 | ucc_slow_restart_tx(qe_port->us_private); |
| 458 | } |
| 459 | |
| 460 | /* ISR helper function for receiving character. |
| 461 | * |
| 462 | * This function is called by the ISR to handling receiving characters |
| 463 | */ |
| 464 | static void qe_uart_int_rx(struct uart_qe_port *qe_port) |
| 465 | { |
| 466 | int i; |
| 467 | unsigned char ch, *cp; |
| 468 | struct uart_port *port = &qe_port->port; |
Alan Cox | ebd2c8f | 2009-09-19 13:13:28 -0700 | [diff] [blame] | 469 | struct tty_struct *tty = port->state->port.tty; |
Timur Tabi | d7584ed | 2008-01-15 09:56:13 -0600 | [diff] [blame] | 470 | struct qe_bd *bdp; |
| 471 | u16 status; |
| 472 | unsigned int flg; |
| 473 | |
| 474 | /* Just loop through the closed BDs and copy the characters into |
| 475 | * the buffer. |
| 476 | */ |
| 477 | bdp = qe_port->rx_cur; |
| 478 | while (1) { |
| 479 | status = in_be16(&bdp->status); |
| 480 | |
| 481 | /* If this one is empty, then we assume we've read them all */ |
| 482 | if (status & BD_SC_EMPTY) |
| 483 | break; |
| 484 | |
| 485 | /* get number of characters, and check space in RX buffer */ |
| 486 | i = in_be16(&bdp->length); |
| 487 | |
| 488 | /* If we don't have enough room in RX buffer for the entire BD, |
| 489 | * then we try later, which will be the next RX interrupt. |
| 490 | */ |
| 491 | if (tty_buffer_request_room(tty, i) < i) { |
| 492 | dev_dbg(port->dev, "ucc-uart: no room in RX buffer\n"); |
| 493 | return; |
| 494 | } |
| 495 | |
| 496 | /* get pointer */ |
| 497 | cp = qe2cpu_addr(bdp->buf, qe_port); |
| 498 | |
| 499 | /* loop through the buffer */ |
| 500 | while (i-- > 0) { |
| 501 | ch = *cp++; |
| 502 | port->icount.rx++; |
| 503 | flg = TTY_NORMAL; |
| 504 | |
| 505 | if (!i && status & |
| 506 | (BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV)) |
| 507 | goto handle_error; |
| 508 | if (uart_handle_sysrq_char(port, ch)) |
| 509 | continue; |
| 510 | |
| 511 | error_return: |
| 512 | tty_insert_flip_char(tty, ch, flg); |
| 513 | |
| 514 | } |
| 515 | |
| 516 | /* This BD is ready to be used again. Clear status. get next */ |
| 517 | clrsetbits_be16(&bdp->status, BD_SC_BR | BD_SC_FR | BD_SC_PR | |
| 518 | BD_SC_OV | BD_SC_ID, BD_SC_EMPTY); |
| 519 | if (in_be16(&bdp->status) & BD_SC_WRAP) |
| 520 | bdp = qe_port->rx_bd_base; |
| 521 | else |
| 522 | bdp++; |
| 523 | |
| 524 | } |
| 525 | |
| 526 | /* Write back buffer pointer */ |
| 527 | qe_port->rx_cur = bdp; |
| 528 | |
| 529 | /* Activate BH processing */ |
| 530 | tty_flip_buffer_push(tty); |
| 531 | |
| 532 | return; |
| 533 | |
| 534 | /* Error processing */ |
| 535 | |
| 536 | handle_error: |
| 537 | /* Statistics */ |
| 538 | if (status & BD_SC_BR) |
| 539 | port->icount.brk++; |
| 540 | if (status & BD_SC_PR) |
| 541 | port->icount.parity++; |
| 542 | if (status & BD_SC_FR) |
| 543 | port->icount.frame++; |
| 544 | if (status & BD_SC_OV) |
| 545 | port->icount.overrun++; |
| 546 | |
| 547 | /* Mask out ignored conditions */ |
| 548 | status &= port->read_status_mask; |
| 549 | |
| 550 | /* Handle the remaining ones */ |
| 551 | if (status & BD_SC_BR) |
| 552 | flg = TTY_BREAK; |
| 553 | else if (status & BD_SC_PR) |
| 554 | flg = TTY_PARITY; |
| 555 | else if (status & BD_SC_FR) |
| 556 | flg = TTY_FRAME; |
| 557 | |
| 558 | /* Overrun does not affect the current character ! */ |
| 559 | if (status & BD_SC_OV) |
| 560 | tty_insert_flip_char(tty, 0, TTY_OVERRUN); |
| 561 | #ifdef SUPPORT_SYSRQ |
| 562 | port->sysrq = 0; |
| 563 | #endif |
| 564 | goto error_return; |
| 565 | } |
| 566 | |
| 567 | /* Interrupt handler |
| 568 | * |
| 569 | * This interrupt handler is called after a BD is processed. |
| 570 | */ |
| 571 | static irqreturn_t qe_uart_int(int irq, void *data) |
| 572 | { |
| 573 | struct uart_qe_port *qe_port = (struct uart_qe_port *) data; |
| 574 | struct ucc_slow __iomem *uccp = qe_port->uccp; |
| 575 | u16 events; |
| 576 | |
| 577 | /* Clear the interrupts */ |
| 578 | events = in_be16(&uccp->ucce); |
| 579 | out_be16(&uccp->ucce, events); |
| 580 | |
| 581 | if (events & UCC_UART_UCCE_BRKE) |
| 582 | uart_handle_break(&qe_port->port); |
| 583 | |
| 584 | if (events & UCC_UART_UCCE_RX) |
| 585 | qe_uart_int_rx(qe_port); |
| 586 | |
| 587 | if (events & UCC_UART_UCCE_TX) |
| 588 | qe_uart_tx_pump(qe_port); |
| 589 | |
| 590 | return events ? IRQ_HANDLED : IRQ_NONE; |
| 591 | } |
| 592 | |
| 593 | /* Initialize buffer descriptors |
| 594 | * |
| 595 | * This function initializes all of the RX and TX buffer descriptors. |
| 596 | */ |
| 597 | static void qe_uart_initbd(struct uart_qe_port *qe_port) |
| 598 | { |
| 599 | int i; |
| 600 | void *bd_virt; |
| 601 | struct qe_bd *bdp; |
| 602 | |
| 603 | /* Set the physical address of the host memory buffers in the buffer |
| 604 | * descriptors, and the virtual address for us to work with. |
| 605 | */ |
| 606 | bd_virt = qe_port->bd_virt; |
| 607 | bdp = qe_port->rx_bd_base; |
| 608 | qe_port->rx_cur = qe_port->rx_bd_base; |
| 609 | for (i = 0; i < (qe_port->rx_nrfifos - 1); i++) { |
| 610 | out_be16(&bdp->status, BD_SC_EMPTY | BD_SC_INTRPT); |
| 611 | out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port)); |
| 612 | out_be16(&bdp->length, 0); |
| 613 | bd_virt += qe_port->rx_fifosize; |
| 614 | bdp++; |
| 615 | } |
| 616 | |
| 617 | /* */ |
| 618 | out_be16(&bdp->status, BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT); |
| 619 | out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port)); |
| 620 | out_be16(&bdp->length, 0); |
| 621 | |
| 622 | /* Set the physical address of the host memory |
| 623 | * buffers in the buffer descriptors, and the |
| 624 | * virtual address for us to work with. |
| 625 | */ |
| 626 | bd_virt = qe_port->bd_virt + |
| 627 | L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize); |
| 628 | qe_port->tx_cur = qe_port->tx_bd_base; |
| 629 | bdp = qe_port->tx_bd_base; |
| 630 | for (i = 0; i < (qe_port->tx_nrfifos - 1); i++) { |
| 631 | out_be16(&bdp->status, BD_SC_INTRPT); |
| 632 | out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port)); |
| 633 | out_be16(&bdp->length, 0); |
| 634 | bd_virt += qe_port->tx_fifosize; |
| 635 | bdp++; |
| 636 | } |
| 637 | |
| 638 | /* Loopback requires the preamble bit to be set on the first TX BD */ |
| 639 | #ifdef LOOPBACK |
| 640 | setbits16(&qe_port->tx_cur->status, BD_SC_P); |
| 641 | #endif |
| 642 | |
| 643 | out_be16(&bdp->status, BD_SC_WRAP | BD_SC_INTRPT); |
| 644 | out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port)); |
| 645 | out_be16(&bdp->length, 0); |
| 646 | } |
| 647 | |
| 648 | /* |
| 649 | * Initialize a UCC for UART. |
| 650 | * |
| 651 | * This function configures a given UCC to be used as a UART device. Basic |
| 652 | * UCC initialization is handled in qe_uart_request_port(). This function |
| 653 | * does all the UART-specific stuff. |
| 654 | */ |
| 655 | static void qe_uart_init_ucc(struct uart_qe_port *qe_port) |
| 656 | { |
| 657 | u32 cecr_subblock; |
| 658 | struct ucc_slow __iomem *uccp = qe_port->uccp; |
| 659 | struct ucc_uart_pram *uccup = qe_port->uccup; |
| 660 | |
| 661 | unsigned int i; |
| 662 | |
| 663 | /* First, disable TX and RX in the UCC */ |
| 664 | ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX); |
| 665 | |
| 666 | /* Program the UCC UART parameter RAM */ |
| 667 | out_8(&uccup->common.rbmr, UCC_BMR_GBL | UCC_BMR_BO_BE); |
| 668 | out_8(&uccup->common.tbmr, UCC_BMR_GBL | UCC_BMR_BO_BE); |
| 669 | out_be16(&uccup->common.mrblr, qe_port->rx_fifosize); |
| 670 | out_be16(&uccup->maxidl, 0x10); |
| 671 | out_be16(&uccup->brkcr, 1); |
| 672 | out_be16(&uccup->parec, 0); |
| 673 | out_be16(&uccup->frmec, 0); |
| 674 | out_be16(&uccup->nosec, 0); |
| 675 | out_be16(&uccup->brkec, 0); |
| 676 | out_be16(&uccup->uaddr[0], 0); |
| 677 | out_be16(&uccup->uaddr[1], 0); |
| 678 | out_be16(&uccup->toseq, 0); |
| 679 | for (i = 0; i < 8; i++) |
| 680 | out_be16(&uccup->cchars[i], 0xC000); |
| 681 | out_be16(&uccup->rccm, 0xc0ff); |
| 682 | |
| 683 | /* Configure the GUMR registers for UART */ |
Dave Liu | b45cc9e | 2009-06-08 22:24:36 +0800 | [diff] [blame] | 684 | if (soft_uart) { |
Timur Tabi | d7584ed | 2008-01-15 09:56:13 -0600 | [diff] [blame] | 685 | /* Soft-UART requires a 1X multiplier for TX */ |
| 686 | clrsetbits_be32(&uccp->gumr_l, |
| 687 | UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | |
| 688 | UCC_SLOW_GUMR_L_RDCR_MASK, |
| 689 | UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_1 | |
| 690 | UCC_SLOW_GUMR_L_RDCR_16); |
Dave Liu | b45cc9e | 2009-06-08 22:24:36 +0800 | [diff] [blame] | 691 | |
| 692 | clrsetbits_be32(&uccp->gumr_h, UCC_SLOW_GUMR_H_RFW, |
| 693 | UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX); |
| 694 | } else { |
Timur Tabi | d7584ed | 2008-01-15 09:56:13 -0600 | [diff] [blame] | 695 | clrsetbits_be32(&uccp->gumr_l, |
| 696 | UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | |
| 697 | UCC_SLOW_GUMR_L_RDCR_MASK, |
| 698 | UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_16 | |
| 699 | UCC_SLOW_GUMR_L_RDCR_16); |
| 700 | |
Dave Liu | b45cc9e | 2009-06-08 22:24:36 +0800 | [diff] [blame] | 701 | clrsetbits_be32(&uccp->gumr_h, |
| 702 | UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX, |
| 703 | UCC_SLOW_GUMR_H_RFW); |
| 704 | } |
Timur Tabi | d7584ed | 2008-01-15 09:56:13 -0600 | [diff] [blame] | 705 | |
| 706 | #ifdef LOOPBACK |
| 707 | clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK, |
| 708 | UCC_SLOW_GUMR_L_DIAG_LOOP); |
| 709 | clrsetbits_be32(&uccp->gumr_h, |
| 710 | UCC_SLOW_GUMR_H_CTSP | UCC_SLOW_GUMR_H_RSYN, |
| 711 | UCC_SLOW_GUMR_H_CDS); |
| 712 | #endif |
| 713 | |
Dave Liu | b45cc9e | 2009-06-08 22:24:36 +0800 | [diff] [blame] | 714 | /* Disable rx interrupts and clear all pending events. */ |
Timur Tabi | d7584ed | 2008-01-15 09:56:13 -0600 | [diff] [blame] | 715 | out_be16(&uccp->uccm, 0); |
| 716 | out_be16(&uccp->ucce, 0xffff); |
| 717 | out_be16(&uccp->udsr, 0x7e7e); |
| 718 | |
| 719 | /* Initialize UPSMR */ |
| 720 | out_be16(&uccp->upsmr, 0); |
| 721 | |
| 722 | if (soft_uart) { |
| 723 | out_be16(&uccup->supsmr, 0x30); |
| 724 | out_be16(&uccup->res92, 0); |
| 725 | out_be32(&uccup->rx_state, 0); |
| 726 | out_be32(&uccup->rx_cnt, 0); |
| 727 | out_8(&uccup->rx_bitmark, 0); |
| 728 | out_8(&uccup->rx_length, 10); |
| 729 | out_be32(&uccup->dump_ptr, 0x4000); |
| 730 | out_8(&uccup->rx_temp_dlst_qe, 0); |
| 731 | out_be32(&uccup->rx_frame_rem, 0); |
| 732 | out_8(&uccup->rx_frame_rem_size, 0); |
| 733 | /* Soft-UART requires TX to be 1X */ |
| 734 | out_8(&uccup->tx_mode, |
| 735 | UCC_UART_TX_STATE_UART | UCC_UART_TX_STATE_X1); |
| 736 | out_be16(&uccup->tx_state, 0); |
| 737 | out_8(&uccup->resD4, 0); |
| 738 | out_be16(&uccup->resD5, 0); |
| 739 | |
| 740 | /* Set UART mode. |
| 741 | * Enable receive and transmit. |
| 742 | */ |
| 743 | |
| 744 | /* From the microcode errata: |
| 745 | * 1.GUMR_L register, set mode=0010 (QMC). |
| 746 | * 2.Set GUMR_H[17] bit. (UART/AHDLC mode). |
| 747 | * 3.Set GUMR_H[19:20] (Transparent mode) |
| 748 | * 4.Clear GUMR_H[26] (RFW) |
| 749 | * ... |
| 750 | * 6.Receiver must use 16x over sampling |
| 751 | */ |
| 752 | clrsetbits_be32(&uccp->gumr_l, |
| 753 | UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | |
| 754 | UCC_SLOW_GUMR_L_RDCR_MASK, |
| 755 | UCC_SLOW_GUMR_L_MODE_QMC | UCC_SLOW_GUMR_L_TDCR_16 | |
| 756 | UCC_SLOW_GUMR_L_RDCR_16); |
| 757 | |
| 758 | clrsetbits_be32(&uccp->gumr_h, |
| 759 | UCC_SLOW_GUMR_H_RFW | UCC_SLOW_GUMR_H_RSYN, |
| 760 | UCC_SLOW_GUMR_H_SUART | UCC_SLOW_GUMR_H_TRX | |
| 761 | UCC_SLOW_GUMR_H_TTX | UCC_SLOW_GUMR_H_TFL); |
| 762 | |
| 763 | #ifdef LOOPBACK |
| 764 | clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK, |
| 765 | UCC_SLOW_GUMR_L_DIAG_LOOP); |
| 766 | clrbits32(&uccp->gumr_h, UCC_SLOW_GUMR_H_CTSP | |
| 767 | UCC_SLOW_GUMR_H_CDS); |
| 768 | #endif |
| 769 | |
| 770 | cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num); |
| 771 | qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock, |
| 772 | QE_CR_PROTOCOL_UNSPECIFIED, 0); |
Dave Liu | b45cc9e | 2009-06-08 22:24:36 +0800 | [diff] [blame] | 773 | } else { |
| 774 | cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num); |
| 775 | qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock, |
| 776 | QE_CR_PROTOCOL_UART, 0); |
Timur Tabi | d7584ed | 2008-01-15 09:56:13 -0600 | [diff] [blame] | 777 | } |
| 778 | } |
| 779 | |
| 780 | /* |
| 781 | * Initialize the port. |
| 782 | */ |
| 783 | static int qe_uart_startup(struct uart_port *port) |
| 784 | { |
| 785 | struct uart_qe_port *qe_port = |
| 786 | container_of(port, struct uart_qe_port, port); |
| 787 | int ret; |
| 788 | |
| 789 | /* |
| 790 | * If we're using Soft-UART mode, then we need to make sure the |
| 791 | * firmware has been uploaded first. |
| 792 | */ |
| 793 | if (soft_uart && !firmware_loaded) { |
| 794 | dev_err(port->dev, "Soft-UART firmware not uploaded\n"); |
| 795 | return -ENODEV; |
| 796 | } |
| 797 | |
| 798 | qe_uart_initbd(qe_port); |
| 799 | qe_uart_init_ucc(qe_port); |
| 800 | |
| 801 | /* Install interrupt handler. */ |
| 802 | ret = request_irq(port->irq, qe_uart_int, IRQF_SHARED, "ucc-uart", |
| 803 | qe_port); |
| 804 | if (ret) { |
| 805 | dev_err(port->dev, "could not claim IRQ %u\n", port->irq); |
| 806 | return ret; |
| 807 | } |
| 808 | |
| 809 | /* Startup rx-int */ |
| 810 | setbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX); |
| 811 | ucc_slow_enable(qe_port->us_private, COMM_DIR_RX_AND_TX); |
| 812 | |
| 813 | return 0; |
| 814 | } |
| 815 | |
| 816 | /* |
| 817 | * Shutdown the port. |
| 818 | */ |
| 819 | static void qe_uart_shutdown(struct uart_port *port) |
| 820 | { |
| 821 | struct uart_qe_port *qe_port = |
| 822 | container_of(port, struct uart_qe_port, port); |
| 823 | struct ucc_slow __iomem *uccp = qe_port->uccp; |
| 824 | unsigned int timeout = 20; |
| 825 | |
| 826 | /* Disable RX and TX */ |
| 827 | |
| 828 | /* Wait for all the BDs marked sent */ |
| 829 | while (!qe_uart_tx_empty(port)) { |
| 830 | if (!--timeout) { |
| 831 | dev_warn(port->dev, "shutdown timeout\n"); |
| 832 | break; |
| 833 | } |
| 834 | set_current_state(TASK_UNINTERRUPTIBLE); |
| 835 | schedule_timeout(2); |
| 836 | } |
| 837 | |
| 838 | if (qe_port->wait_closing) { |
| 839 | /* Wait a bit longer */ |
| 840 | set_current_state(TASK_UNINTERRUPTIBLE); |
| 841 | schedule_timeout(qe_port->wait_closing); |
| 842 | } |
| 843 | |
| 844 | /* Stop uarts */ |
| 845 | ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX); |
| 846 | clrbits16(&uccp->uccm, UCC_UART_UCCE_TX | UCC_UART_UCCE_RX); |
| 847 | |
| 848 | /* Shut them really down and reinit buffer descriptors */ |
| 849 | ucc_slow_graceful_stop_tx(qe_port->us_private); |
| 850 | qe_uart_initbd(qe_port); |
| 851 | |
| 852 | free_irq(port->irq, qe_port); |
| 853 | } |
| 854 | |
| 855 | /* |
| 856 | * Set the serial port parameters. |
| 857 | */ |
| 858 | static void qe_uart_set_termios(struct uart_port *port, |
| 859 | struct ktermios *termios, struct ktermios *old) |
| 860 | { |
| 861 | struct uart_qe_port *qe_port = |
| 862 | container_of(port, struct uart_qe_port, port); |
| 863 | struct ucc_slow __iomem *uccp = qe_port->uccp; |
| 864 | unsigned int baud; |
| 865 | unsigned long flags; |
| 866 | u16 upsmr = in_be16(&uccp->upsmr); |
| 867 | struct ucc_uart_pram __iomem *uccup = qe_port->uccup; |
| 868 | u16 supsmr = in_be16(&uccup->supsmr); |
| 869 | u8 char_length = 2; /* 1 + CL + PEN + 1 + SL */ |
| 870 | |
| 871 | /* Character length programmed into the mode register is the |
| 872 | * sum of: 1 start bit, number of data bits, 0 or 1 parity bit, |
| 873 | * 1 or 2 stop bits, minus 1. |
| 874 | * The value 'bits' counts this for us. |
| 875 | */ |
| 876 | |
| 877 | /* byte size */ |
| 878 | upsmr &= UCC_UART_UPSMR_CL_MASK; |
| 879 | supsmr &= UCC_UART_SUPSMR_CL_MASK; |
| 880 | |
| 881 | switch (termios->c_cflag & CSIZE) { |
| 882 | case CS5: |
| 883 | upsmr |= UCC_UART_UPSMR_CL_5; |
| 884 | supsmr |= UCC_UART_SUPSMR_CL_5; |
| 885 | char_length += 5; |
| 886 | break; |
| 887 | case CS6: |
| 888 | upsmr |= UCC_UART_UPSMR_CL_6; |
| 889 | supsmr |= UCC_UART_SUPSMR_CL_6; |
| 890 | char_length += 6; |
| 891 | break; |
| 892 | case CS7: |
| 893 | upsmr |= UCC_UART_UPSMR_CL_7; |
| 894 | supsmr |= UCC_UART_SUPSMR_CL_7; |
| 895 | char_length += 7; |
| 896 | break; |
| 897 | default: /* case CS8 */ |
| 898 | upsmr |= UCC_UART_UPSMR_CL_8; |
| 899 | supsmr |= UCC_UART_SUPSMR_CL_8; |
| 900 | char_length += 8; |
| 901 | break; |
| 902 | } |
| 903 | |
| 904 | /* If CSTOPB is set, we want two stop bits */ |
| 905 | if (termios->c_cflag & CSTOPB) { |
| 906 | upsmr |= UCC_UART_UPSMR_SL; |
| 907 | supsmr |= UCC_UART_SUPSMR_SL; |
| 908 | char_length++; /* + SL */ |
| 909 | } |
| 910 | |
| 911 | if (termios->c_cflag & PARENB) { |
| 912 | upsmr |= UCC_UART_UPSMR_PEN; |
| 913 | supsmr |= UCC_UART_SUPSMR_PEN; |
| 914 | char_length++; /* + PEN */ |
| 915 | |
| 916 | if (!(termios->c_cflag & PARODD)) { |
| 917 | upsmr &= ~(UCC_UART_UPSMR_RPM_MASK | |
| 918 | UCC_UART_UPSMR_TPM_MASK); |
| 919 | upsmr |= UCC_UART_UPSMR_RPM_EVEN | |
| 920 | UCC_UART_UPSMR_TPM_EVEN; |
| 921 | supsmr &= ~(UCC_UART_SUPSMR_RPM_MASK | |
| 922 | UCC_UART_SUPSMR_TPM_MASK); |
| 923 | supsmr |= UCC_UART_SUPSMR_RPM_EVEN | |
| 924 | UCC_UART_SUPSMR_TPM_EVEN; |
| 925 | } |
| 926 | } |
| 927 | |
| 928 | /* |
| 929 | * Set up parity check flag |
| 930 | */ |
| 931 | port->read_status_mask = BD_SC_EMPTY | BD_SC_OV; |
| 932 | if (termios->c_iflag & INPCK) |
| 933 | port->read_status_mask |= BD_SC_FR | BD_SC_PR; |
| 934 | if (termios->c_iflag & (BRKINT | PARMRK)) |
| 935 | port->read_status_mask |= BD_SC_BR; |
| 936 | |
| 937 | /* |
| 938 | * Characters to ignore |
| 939 | */ |
| 940 | port->ignore_status_mask = 0; |
| 941 | if (termios->c_iflag & IGNPAR) |
| 942 | port->ignore_status_mask |= BD_SC_PR | BD_SC_FR; |
| 943 | if (termios->c_iflag & IGNBRK) { |
| 944 | port->ignore_status_mask |= BD_SC_BR; |
| 945 | /* |
| 946 | * If we're ignore parity and break indicators, ignore |
| 947 | * overruns too. (For real raw support). |
| 948 | */ |
| 949 | if (termios->c_iflag & IGNPAR) |
| 950 | port->ignore_status_mask |= BD_SC_OV; |
| 951 | } |
| 952 | /* |
| 953 | * !!! ignore all characters if CREAD is not set |
| 954 | */ |
| 955 | if ((termios->c_cflag & CREAD) == 0) |
| 956 | port->read_status_mask &= ~BD_SC_EMPTY; |
| 957 | |
| 958 | baud = uart_get_baud_rate(port, termios, old, 0, 115200); |
| 959 | |
| 960 | /* Do we really need a spinlock here? */ |
| 961 | spin_lock_irqsave(&port->lock, flags); |
| 962 | |
| 963 | out_be16(&uccp->upsmr, upsmr); |
| 964 | if (soft_uart) { |
| 965 | out_be16(&uccup->supsmr, supsmr); |
| 966 | out_8(&uccup->rx_length, char_length); |
| 967 | |
| 968 | /* Soft-UART requires a 1X multiplier for TX */ |
| 969 | qe_setbrg(qe_port->us_info.rx_clock, baud, 16); |
| 970 | qe_setbrg(qe_port->us_info.tx_clock, baud, 1); |
| 971 | } else { |
| 972 | qe_setbrg(qe_port->us_info.rx_clock, baud, 16); |
| 973 | qe_setbrg(qe_port->us_info.tx_clock, baud, 16); |
| 974 | } |
| 975 | |
| 976 | spin_unlock_irqrestore(&port->lock, flags); |
| 977 | } |
| 978 | |
| 979 | /* |
| 980 | * Return a pointer to a string that describes what kind of port this is. |
| 981 | */ |
| 982 | static const char *qe_uart_type(struct uart_port *port) |
| 983 | { |
| 984 | return "QE"; |
| 985 | } |
| 986 | |
| 987 | /* |
| 988 | * Allocate any memory and I/O resources required by the port. |
| 989 | */ |
| 990 | static int qe_uart_request_port(struct uart_port *port) |
| 991 | { |
| 992 | int ret; |
| 993 | struct uart_qe_port *qe_port = |
| 994 | container_of(port, struct uart_qe_port, port); |
| 995 | struct ucc_slow_info *us_info = &qe_port->us_info; |
| 996 | struct ucc_slow_private *uccs; |
| 997 | unsigned int rx_size, tx_size; |
| 998 | void *bd_virt; |
| 999 | dma_addr_t bd_dma_addr = 0; |
| 1000 | |
| 1001 | ret = ucc_slow_init(us_info, &uccs); |
| 1002 | if (ret) { |
| 1003 | dev_err(port->dev, "could not initialize UCC%u\n", |
| 1004 | qe_port->ucc_num); |
| 1005 | return ret; |
| 1006 | } |
| 1007 | |
| 1008 | qe_port->us_private = uccs; |
| 1009 | qe_port->uccp = uccs->us_regs; |
| 1010 | qe_port->uccup = (struct ucc_uart_pram *) uccs->us_pram; |
| 1011 | qe_port->rx_bd_base = uccs->rx_bd; |
| 1012 | qe_port->tx_bd_base = uccs->tx_bd; |
| 1013 | |
| 1014 | /* |
| 1015 | * Allocate the transmit and receive data buffers. |
| 1016 | */ |
| 1017 | |
| 1018 | rx_size = L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize); |
| 1019 | tx_size = L1_CACHE_ALIGN(qe_port->tx_nrfifos * qe_port->tx_fifosize); |
| 1020 | |
Becky Bruce | 8b05cef | 2008-09-12 10:42:56 -0500 | [diff] [blame] | 1021 | bd_virt = dma_alloc_coherent(port->dev, rx_size + tx_size, &bd_dma_addr, |
Timur Tabi | d7584ed | 2008-01-15 09:56:13 -0600 | [diff] [blame] | 1022 | GFP_KERNEL); |
| 1023 | if (!bd_virt) { |
| 1024 | dev_err(port->dev, "could not allocate buffer descriptors\n"); |
| 1025 | return -ENOMEM; |
| 1026 | } |
| 1027 | |
| 1028 | qe_port->bd_virt = bd_virt; |
| 1029 | qe_port->bd_dma_addr = bd_dma_addr; |
| 1030 | qe_port->bd_size = rx_size + tx_size; |
| 1031 | |
| 1032 | qe_port->rx_buf = bd_virt; |
| 1033 | qe_port->tx_buf = qe_port->rx_buf + rx_size; |
| 1034 | |
| 1035 | return 0; |
| 1036 | } |
| 1037 | |
| 1038 | /* |
| 1039 | * Configure the port. |
| 1040 | * |
| 1041 | * We say we're a CPM-type port because that's mostly true. Once the device |
| 1042 | * is configured, this driver operates almost identically to the CPM serial |
| 1043 | * driver. |
| 1044 | */ |
| 1045 | static void qe_uart_config_port(struct uart_port *port, int flags) |
| 1046 | { |
| 1047 | if (flags & UART_CONFIG_TYPE) { |
| 1048 | port->type = PORT_CPM; |
| 1049 | qe_uart_request_port(port); |
| 1050 | } |
| 1051 | } |
| 1052 | |
| 1053 | /* |
| 1054 | * Release any memory and I/O resources that were allocated in |
| 1055 | * qe_uart_request_port(). |
| 1056 | */ |
| 1057 | static void qe_uart_release_port(struct uart_port *port) |
| 1058 | { |
| 1059 | struct uart_qe_port *qe_port = |
| 1060 | container_of(port, struct uart_qe_port, port); |
| 1061 | struct ucc_slow_private *uccs = qe_port->us_private; |
| 1062 | |
Becky Bruce | 8b05cef | 2008-09-12 10:42:56 -0500 | [diff] [blame] | 1063 | dma_free_coherent(port->dev, qe_port->bd_size, qe_port->bd_virt, |
Timur Tabi | d7584ed | 2008-01-15 09:56:13 -0600 | [diff] [blame] | 1064 | qe_port->bd_dma_addr); |
| 1065 | |
| 1066 | ucc_slow_free(uccs); |
| 1067 | } |
| 1068 | |
| 1069 | /* |
| 1070 | * Verify that the data in serial_struct is suitable for this device. |
| 1071 | */ |
| 1072 | static int qe_uart_verify_port(struct uart_port *port, |
| 1073 | struct serial_struct *ser) |
| 1074 | { |
| 1075 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_CPM) |
| 1076 | return -EINVAL; |
| 1077 | |
Yinghai Lu | a62c413 | 2008-08-19 20:49:55 -0700 | [diff] [blame] | 1078 | if (ser->irq < 0 || ser->irq >= nr_irqs) |
Timur Tabi | d7584ed | 2008-01-15 09:56:13 -0600 | [diff] [blame] | 1079 | return -EINVAL; |
| 1080 | |
| 1081 | if (ser->baud_base < 9600) |
| 1082 | return -EINVAL; |
| 1083 | |
| 1084 | return 0; |
| 1085 | } |
| 1086 | /* UART operations |
| 1087 | * |
| 1088 | * Details on these functions can be found in Documentation/serial/driver |
| 1089 | */ |
| 1090 | static struct uart_ops qe_uart_pops = { |
| 1091 | .tx_empty = qe_uart_tx_empty, |
| 1092 | .set_mctrl = qe_uart_set_mctrl, |
| 1093 | .get_mctrl = qe_uart_get_mctrl, |
| 1094 | .stop_tx = qe_uart_stop_tx, |
| 1095 | .start_tx = qe_uart_start_tx, |
| 1096 | .stop_rx = qe_uart_stop_rx, |
| 1097 | .enable_ms = qe_uart_enable_ms, |
| 1098 | .break_ctl = qe_uart_break_ctl, |
| 1099 | .startup = qe_uart_startup, |
| 1100 | .shutdown = qe_uart_shutdown, |
| 1101 | .set_termios = qe_uart_set_termios, |
| 1102 | .type = qe_uart_type, |
| 1103 | .release_port = qe_uart_release_port, |
| 1104 | .request_port = qe_uart_request_port, |
| 1105 | .config_port = qe_uart_config_port, |
| 1106 | .verify_port = qe_uart_verify_port, |
| 1107 | }; |
| 1108 | |
| 1109 | /* |
| 1110 | * Obtain the SOC model number and revision level |
| 1111 | * |
| 1112 | * This function parses the device tree to obtain the SOC model. It then |
| 1113 | * reads the SVR register to the revision. |
| 1114 | * |
| 1115 | * The device tree stores the SOC model two different ways. |
| 1116 | * |
| 1117 | * The new way is: |
| 1118 | * |
| 1119 | * cpu@0 { |
| 1120 | * compatible = "PowerPC,8323"; |
| 1121 | * device_type = "cpu"; |
| 1122 | * ... |
| 1123 | * |
| 1124 | * |
| 1125 | * The old way is: |
| 1126 | * PowerPC,8323@0 { |
| 1127 | * device_type = "cpu"; |
| 1128 | * ... |
| 1129 | * |
| 1130 | * This code first checks the new way, and then the old way. |
| 1131 | */ |
| 1132 | static unsigned int soc_info(unsigned int *rev_h, unsigned int *rev_l) |
| 1133 | { |
| 1134 | struct device_node *np; |
| 1135 | const char *soc_string; |
| 1136 | unsigned int svr; |
| 1137 | unsigned int soc; |
| 1138 | |
| 1139 | /* Find the CPU node */ |
| 1140 | np = of_find_node_by_type(NULL, "cpu"); |
| 1141 | if (!np) |
| 1142 | return 0; |
| 1143 | /* Find the compatible property */ |
| 1144 | soc_string = of_get_property(np, "compatible", NULL); |
| 1145 | if (!soc_string) |
| 1146 | /* No compatible property, so try the name. */ |
| 1147 | soc_string = np->name; |
| 1148 | |
| 1149 | /* Extract the SOC number from the "PowerPC," string */ |
| 1150 | if ((sscanf(soc_string, "PowerPC,%u", &soc) != 1) || !soc) |
| 1151 | return 0; |
| 1152 | |
| 1153 | /* Get the revision from the SVR */ |
| 1154 | svr = mfspr(SPRN_SVR); |
| 1155 | *rev_h = (svr >> 4) & 0xf; |
| 1156 | *rev_l = svr & 0xf; |
| 1157 | |
| 1158 | return soc; |
| 1159 | } |
| 1160 | |
| 1161 | /* |
| 1162 | * requst_firmware_nowait() callback function |
| 1163 | * |
| 1164 | * This function is called by the kernel when a firmware is made available, |
| 1165 | * or if it times out waiting for the firmware. |
| 1166 | */ |
| 1167 | static void uart_firmware_cont(const struct firmware *fw, void *context) |
| 1168 | { |
| 1169 | struct qe_firmware *firmware; |
| 1170 | struct device *dev = context; |
| 1171 | int ret; |
| 1172 | |
| 1173 | if (!fw) { |
| 1174 | dev_err(dev, "firmware not found\n"); |
| 1175 | return; |
| 1176 | } |
| 1177 | |
| 1178 | firmware = (struct qe_firmware *) fw->data; |
| 1179 | |
| 1180 | if (firmware->header.length != fw->size) { |
| 1181 | dev_err(dev, "invalid firmware\n"); |
| 1182 | return; |
| 1183 | } |
| 1184 | |
| 1185 | ret = qe_upload_firmware(firmware); |
| 1186 | if (ret) { |
| 1187 | dev_err(dev, "could not load firmware\n"); |
| 1188 | return; |
| 1189 | } |
| 1190 | |
| 1191 | firmware_loaded = 1; |
| 1192 | } |
| 1193 | |
| 1194 | static int ucc_uart_probe(struct of_device *ofdev, |
| 1195 | const struct of_device_id *match) |
| 1196 | { |
| 1197 | struct device_node *np = ofdev->node; |
| 1198 | const unsigned int *iprop; /* Integer OF properties */ |
| 1199 | const char *sprop; /* String OF properties */ |
| 1200 | struct uart_qe_port *qe_port = NULL; |
| 1201 | struct resource res; |
| 1202 | int ret; |
| 1203 | |
| 1204 | /* |
| 1205 | * Determine if we need Soft-UART mode |
| 1206 | */ |
| 1207 | if (of_find_property(np, "soft-uart", NULL)) { |
| 1208 | dev_dbg(&ofdev->dev, "using Soft-UART mode\n"); |
| 1209 | soft_uart = 1; |
| 1210 | } |
| 1211 | |
| 1212 | /* |
| 1213 | * If we are using Soft-UART, determine if we need to upload the |
| 1214 | * firmware, too. |
| 1215 | */ |
| 1216 | if (soft_uart) { |
| 1217 | struct qe_firmware_info *qe_fw_info; |
| 1218 | |
| 1219 | qe_fw_info = qe_get_firmware_info(); |
| 1220 | |
| 1221 | /* Check if the firmware has been uploaded. */ |
| 1222 | if (qe_fw_info && strstr(qe_fw_info->id, "Soft-UART")) { |
| 1223 | firmware_loaded = 1; |
| 1224 | } else { |
| 1225 | char filename[32]; |
| 1226 | unsigned int soc; |
| 1227 | unsigned int rev_h; |
| 1228 | unsigned int rev_l; |
| 1229 | |
| 1230 | soc = soc_info(&rev_h, &rev_l); |
| 1231 | if (!soc) { |
| 1232 | dev_err(&ofdev->dev, "unknown CPU model\n"); |
| 1233 | return -ENXIO; |
| 1234 | } |
| 1235 | sprintf(filename, "fsl_qe_ucode_uart_%u_%u%u.bin", |
| 1236 | soc, rev_h, rev_l); |
| 1237 | |
| 1238 | dev_info(&ofdev->dev, "waiting for firmware %s\n", |
| 1239 | filename); |
| 1240 | |
| 1241 | /* |
| 1242 | * We call request_firmware_nowait instead of |
| 1243 | * request_firmware so that the driver can load and |
| 1244 | * initialize the ports without holding up the rest of |
| 1245 | * the kernel. If hotplug support is enabled in the |
| 1246 | * kernel, then we use it. |
| 1247 | */ |
| 1248 | ret = request_firmware_nowait(THIS_MODULE, |
| 1249 | FW_ACTION_HOTPLUG, filename, &ofdev->dev, |
| 1250 | &ofdev->dev, uart_firmware_cont); |
| 1251 | if (ret) { |
| 1252 | dev_err(&ofdev->dev, |
| 1253 | "could not load firmware %s\n", |
| 1254 | filename); |
| 1255 | return ret; |
| 1256 | } |
| 1257 | } |
| 1258 | } |
| 1259 | |
| 1260 | qe_port = kzalloc(sizeof(struct uart_qe_port), GFP_KERNEL); |
| 1261 | if (!qe_port) { |
| 1262 | dev_err(&ofdev->dev, "can't allocate QE port structure\n"); |
| 1263 | return -ENOMEM; |
| 1264 | } |
| 1265 | |
| 1266 | /* Search for IRQ and mapbase */ |
| 1267 | ret = of_address_to_resource(np, 0, &res); |
| 1268 | if (ret) { |
| 1269 | dev_err(&ofdev->dev, "missing 'reg' property in device tree\n"); |
| 1270 | kfree(qe_port); |
| 1271 | return ret; |
| 1272 | } |
| 1273 | if (!res.start) { |
| 1274 | dev_err(&ofdev->dev, "invalid 'reg' property in device tree\n"); |
| 1275 | kfree(qe_port); |
| 1276 | return -EINVAL; |
| 1277 | } |
| 1278 | qe_port->port.mapbase = res.start; |
| 1279 | |
| 1280 | /* Get the UCC number (device ID) */ |
| 1281 | /* UCCs are numbered 1-7 */ |
Anton Vorontsov | 56626f3 | 2008-04-11 20:06:54 +0400 | [diff] [blame] | 1282 | iprop = of_get_property(np, "cell-index", NULL); |
| 1283 | if (!iprop) { |
| 1284 | iprop = of_get_property(np, "device-id", NULL); |
| 1285 | if (!iprop) { |
Alan Cox | 8d5a05d | 2009-04-06 17:33:48 +0100 | [diff] [blame] | 1286 | kfree(qe_port); |
Anton Vorontsov | 56626f3 | 2008-04-11 20:06:54 +0400 | [diff] [blame] | 1287 | dev_err(&ofdev->dev, "UCC is unspecified in " |
| 1288 | "device tree\n"); |
| 1289 | return -EINVAL; |
| 1290 | } |
| 1291 | } |
| 1292 | |
| 1293 | if ((*iprop < 1) || (*iprop > UCC_MAX_NUM)) { |
| 1294 | dev_err(&ofdev->dev, "no support for UCC%u\n", *iprop); |
Timur Tabi | d7584ed | 2008-01-15 09:56:13 -0600 | [diff] [blame] | 1295 | kfree(qe_port); |
| 1296 | return -ENODEV; |
| 1297 | } |
| 1298 | qe_port->ucc_num = *iprop - 1; |
| 1299 | |
| 1300 | /* |
| 1301 | * In the future, we should not require the BRG to be specified in the |
| 1302 | * device tree. If no clock-source is specified, then just pick a BRG |
| 1303 | * to use. This requires a new QE library function that manages BRG |
| 1304 | * assignments. |
| 1305 | */ |
| 1306 | |
| 1307 | sprop = of_get_property(np, "rx-clock-name", NULL); |
| 1308 | if (!sprop) { |
| 1309 | dev_err(&ofdev->dev, "missing rx-clock-name in device tree\n"); |
| 1310 | kfree(qe_port); |
| 1311 | return -ENODEV; |
| 1312 | } |
| 1313 | |
| 1314 | qe_port->us_info.rx_clock = qe_clock_source(sprop); |
| 1315 | if ((qe_port->us_info.rx_clock < QE_BRG1) || |
| 1316 | (qe_port->us_info.rx_clock > QE_BRG16)) { |
| 1317 | dev_err(&ofdev->dev, "rx-clock-name must be a BRG for UART\n"); |
| 1318 | kfree(qe_port); |
| 1319 | return -ENODEV; |
| 1320 | } |
| 1321 | |
| 1322 | #ifdef LOOPBACK |
| 1323 | /* In internal loopback mode, TX and RX must use the same clock */ |
| 1324 | qe_port->us_info.tx_clock = qe_port->us_info.rx_clock; |
| 1325 | #else |
| 1326 | sprop = of_get_property(np, "tx-clock-name", NULL); |
| 1327 | if (!sprop) { |
| 1328 | dev_err(&ofdev->dev, "missing tx-clock-name in device tree\n"); |
| 1329 | kfree(qe_port); |
| 1330 | return -ENODEV; |
| 1331 | } |
| 1332 | qe_port->us_info.tx_clock = qe_clock_source(sprop); |
| 1333 | #endif |
| 1334 | if ((qe_port->us_info.tx_clock < QE_BRG1) || |
| 1335 | (qe_port->us_info.tx_clock > QE_BRG16)) { |
| 1336 | dev_err(&ofdev->dev, "tx-clock-name must be a BRG for UART\n"); |
| 1337 | kfree(qe_port); |
| 1338 | return -ENODEV; |
| 1339 | } |
| 1340 | |
| 1341 | /* Get the port number, numbered 0-3 */ |
| 1342 | iprop = of_get_property(np, "port-number", NULL); |
| 1343 | if (!iprop) { |
| 1344 | dev_err(&ofdev->dev, "missing port-number in device tree\n"); |
| 1345 | kfree(qe_port); |
| 1346 | return -EINVAL; |
| 1347 | } |
| 1348 | qe_port->port.line = *iprop; |
| 1349 | if (qe_port->port.line >= UCC_MAX_UART) { |
| 1350 | dev_err(&ofdev->dev, "port-number must be 0-%u\n", |
| 1351 | UCC_MAX_UART - 1); |
| 1352 | kfree(qe_port); |
| 1353 | return -EINVAL; |
| 1354 | } |
| 1355 | |
| 1356 | qe_port->port.irq = irq_of_parse_and_map(np, 0); |
| 1357 | if (qe_port->port.irq == NO_IRQ) { |
| 1358 | dev_err(&ofdev->dev, "could not map IRQ for UCC%u\n", |
| 1359 | qe_port->ucc_num + 1); |
| 1360 | kfree(qe_port); |
| 1361 | return -EINVAL; |
| 1362 | } |
| 1363 | |
| 1364 | /* |
| 1365 | * Newer device trees have an "fsl,qe" compatible property for the QE |
| 1366 | * node, but we still need to support older device trees. |
| 1367 | */ |
| 1368 | np = of_find_compatible_node(NULL, NULL, "fsl,qe"); |
| 1369 | if (!np) { |
| 1370 | np = of_find_node_by_type(NULL, "qe"); |
| 1371 | if (!np) { |
| 1372 | dev_err(&ofdev->dev, "could not find 'qe' node\n"); |
| 1373 | kfree(qe_port); |
| 1374 | return -EINVAL; |
| 1375 | } |
| 1376 | } |
| 1377 | |
| 1378 | iprop = of_get_property(np, "brg-frequency", NULL); |
| 1379 | if (!iprop) { |
| 1380 | dev_err(&ofdev->dev, |
| 1381 | "missing brg-frequency in device tree\n"); |
| 1382 | kfree(qe_port); |
| 1383 | return -EINVAL; |
| 1384 | } |
| 1385 | |
| 1386 | if (*iprop) |
| 1387 | qe_port->port.uartclk = *iprop; |
| 1388 | else { |
| 1389 | /* |
| 1390 | * Older versions of U-Boot do not initialize the brg-frequency |
| 1391 | * property, so in this case we assume the BRG frequency is |
| 1392 | * half the QE bus frequency. |
| 1393 | */ |
| 1394 | iprop = of_get_property(np, "bus-frequency", NULL); |
| 1395 | if (!iprop) { |
| 1396 | dev_err(&ofdev->dev, |
| 1397 | "missing QE bus-frequency in device tree\n"); |
| 1398 | kfree(qe_port); |
| 1399 | return -EINVAL; |
| 1400 | } |
| 1401 | if (*iprop) |
| 1402 | qe_port->port.uartclk = *iprop / 2; |
| 1403 | else { |
| 1404 | dev_err(&ofdev->dev, |
| 1405 | "invalid QE bus-frequency in device tree\n"); |
| 1406 | kfree(qe_port); |
| 1407 | return -EINVAL; |
| 1408 | } |
| 1409 | } |
| 1410 | |
| 1411 | spin_lock_init(&qe_port->port.lock); |
| 1412 | qe_port->np = np; |
| 1413 | qe_port->port.dev = &ofdev->dev; |
| 1414 | qe_port->port.ops = &qe_uart_pops; |
| 1415 | qe_port->port.iotype = UPIO_MEM; |
| 1416 | |
| 1417 | qe_port->tx_nrfifos = TX_NUM_FIFO; |
| 1418 | qe_port->tx_fifosize = TX_BUF_SIZE; |
| 1419 | qe_port->rx_nrfifos = RX_NUM_FIFO; |
| 1420 | qe_port->rx_fifosize = RX_BUF_SIZE; |
| 1421 | |
| 1422 | qe_port->wait_closing = UCC_WAIT_CLOSING; |
| 1423 | qe_port->port.fifosize = 512; |
| 1424 | qe_port->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP; |
| 1425 | |
| 1426 | qe_port->us_info.ucc_num = qe_port->ucc_num; |
| 1427 | qe_port->us_info.regs = (phys_addr_t) res.start; |
| 1428 | qe_port->us_info.irq = qe_port->port.irq; |
| 1429 | |
| 1430 | qe_port->us_info.rx_bd_ring_len = qe_port->rx_nrfifos; |
| 1431 | qe_port->us_info.tx_bd_ring_len = qe_port->tx_nrfifos; |
| 1432 | |
| 1433 | /* Make sure ucc_slow_init() initializes both TX and RX */ |
| 1434 | qe_port->us_info.init_tx = 1; |
| 1435 | qe_port->us_info.init_rx = 1; |
| 1436 | |
| 1437 | /* Add the port to the uart sub-system. This will cause |
| 1438 | * qe_uart_config_port() to be called, so the us_info structure must |
| 1439 | * be initialized. |
| 1440 | */ |
| 1441 | ret = uart_add_one_port(&ucc_uart_driver, &qe_port->port); |
| 1442 | if (ret) { |
| 1443 | dev_err(&ofdev->dev, "could not add /dev/ttyQE%u\n", |
| 1444 | qe_port->port.line); |
| 1445 | kfree(qe_port); |
| 1446 | return ret; |
| 1447 | } |
| 1448 | |
| 1449 | dev_set_drvdata(&ofdev->dev, qe_port); |
| 1450 | |
| 1451 | dev_info(&ofdev->dev, "UCC%u assigned to /dev/ttyQE%u\n", |
| 1452 | qe_port->ucc_num + 1, qe_port->port.line); |
| 1453 | |
| 1454 | /* Display the mknod command for this device */ |
| 1455 | dev_dbg(&ofdev->dev, "mknod command is 'mknod /dev/ttyQE%u c %u %u'\n", |
| 1456 | qe_port->port.line, SERIAL_QE_MAJOR, |
| 1457 | SERIAL_QE_MINOR + qe_port->port.line); |
| 1458 | |
| 1459 | return 0; |
| 1460 | } |
| 1461 | |
| 1462 | static int ucc_uart_remove(struct of_device *ofdev) |
| 1463 | { |
| 1464 | struct uart_qe_port *qe_port = dev_get_drvdata(&ofdev->dev); |
| 1465 | |
| 1466 | dev_info(&ofdev->dev, "removing /dev/ttyQE%u\n", qe_port->port.line); |
| 1467 | |
| 1468 | uart_remove_one_port(&ucc_uart_driver, &qe_port->port); |
| 1469 | |
| 1470 | dev_set_drvdata(&ofdev->dev, NULL); |
| 1471 | kfree(qe_port); |
| 1472 | |
| 1473 | return 0; |
| 1474 | } |
| 1475 | |
| 1476 | static struct of_device_id ucc_uart_match[] = { |
| 1477 | { |
| 1478 | .type = "serial", |
| 1479 | .compatible = "ucc_uart", |
| 1480 | }, |
| 1481 | {}, |
| 1482 | }; |
| 1483 | MODULE_DEVICE_TABLE(of, ucc_uart_match); |
| 1484 | |
| 1485 | static struct of_platform_driver ucc_uart_of_driver = { |
| 1486 | .owner = THIS_MODULE, |
| 1487 | .name = "ucc_uart", |
| 1488 | .match_table = ucc_uart_match, |
| 1489 | .probe = ucc_uart_probe, |
| 1490 | .remove = ucc_uart_remove, |
| 1491 | }; |
| 1492 | |
| 1493 | static int __init ucc_uart_init(void) |
| 1494 | { |
| 1495 | int ret; |
| 1496 | |
| 1497 | printk(KERN_INFO "Freescale QUICC Engine UART device driver\n"); |
| 1498 | #ifdef LOOPBACK |
| 1499 | printk(KERN_INFO "ucc-uart: Using loopback mode\n"); |
| 1500 | #endif |
| 1501 | |
| 1502 | ret = uart_register_driver(&ucc_uart_driver); |
| 1503 | if (ret) { |
| 1504 | printk(KERN_ERR "ucc-uart: could not register UART driver\n"); |
| 1505 | return ret; |
| 1506 | } |
| 1507 | |
| 1508 | ret = of_register_platform_driver(&ucc_uart_of_driver); |
| 1509 | if (ret) |
| 1510 | printk(KERN_ERR |
| 1511 | "ucc-uart: could not register platform driver\n"); |
| 1512 | |
| 1513 | return ret; |
| 1514 | } |
| 1515 | |
| 1516 | static void __exit ucc_uart_exit(void) |
| 1517 | { |
| 1518 | printk(KERN_INFO |
| 1519 | "Freescale QUICC Engine UART device driver unloading\n"); |
| 1520 | |
| 1521 | of_unregister_platform_driver(&ucc_uart_of_driver); |
| 1522 | uart_unregister_driver(&ucc_uart_driver); |
| 1523 | } |
| 1524 | |
| 1525 | module_init(ucc_uart_init); |
| 1526 | module_exit(ucc_uart_exit); |
| 1527 | |
| 1528 | MODULE_DESCRIPTION("Freescale QUICC Engine (QE) UART"); |
| 1529 | MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); |
| 1530 | MODULE_LICENSE("GPL v2"); |
| 1531 | MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_QE_MAJOR); |
| 1532 | |