Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the "Software"), |
| 7 | * to deal in the Software without restriction, including without limitation |
| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
| 10 | * Software is furnished to do so, subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice shall be included in |
| 13 | * all copies or substantial portions of the Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 21 | * OTHER DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: Dave Airlie |
| 24 | * Alex Deucher |
| 25 | */ |
| 26 | #include <drm/drmP.h> |
| 27 | #include <drm/drm_crtc_helper.h> |
| 28 | #include <drm/radeon_drm.h> |
| 29 | #include "radeon_fixed.h" |
| 30 | #include "radeon.h" |
| 31 | #include "atom.h" |
| 32 | #include "atom-bits.h" |
| 33 | |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 34 | static void atombios_overscan_setup(struct drm_crtc *crtc, |
| 35 | struct drm_display_mode *mode, |
| 36 | struct drm_display_mode *adjusted_mode) |
| 37 | { |
| 38 | struct drm_device *dev = crtc->dev; |
| 39 | struct radeon_device *rdev = dev->dev_private; |
| 40 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 41 | SET_CRTC_OVERSCAN_PS_ALLOCATION args; |
| 42 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan); |
| 43 | int a1, a2; |
| 44 | |
| 45 | memset(&args, 0, sizeof(args)); |
| 46 | |
| 47 | args.usOverscanRight = 0; |
| 48 | args.usOverscanLeft = 0; |
| 49 | args.usOverscanBottom = 0; |
| 50 | args.usOverscanTop = 0; |
| 51 | args.ucCRTC = radeon_crtc->crtc_id; |
| 52 | |
| 53 | switch (radeon_crtc->rmx_type) { |
| 54 | case RMX_CENTER: |
| 55 | args.usOverscanTop = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2; |
| 56 | args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2; |
| 57 | args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2; |
| 58 | args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2; |
| 59 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 60 | break; |
| 61 | case RMX_ASPECT: |
| 62 | a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; |
| 63 | a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; |
| 64 | |
| 65 | if (a1 > a2) { |
| 66 | args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2; |
| 67 | args.usOverscanRight = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2; |
| 68 | } else if (a2 > a1) { |
| 69 | args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2; |
| 70 | args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2; |
| 71 | } |
| 72 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 73 | break; |
| 74 | case RMX_FULL: |
| 75 | default: |
| 76 | args.usOverscanRight = 0; |
| 77 | args.usOverscanLeft = 0; |
| 78 | args.usOverscanBottom = 0; |
| 79 | args.usOverscanTop = 0; |
| 80 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 81 | break; |
| 82 | } |
| 83 | } |
| 84 | |
| 85 | static void atombios_scaler_setup(struct drm_crtc *crtc) |
| 86 | { |
| 87 | struct drm_device *dev = crtc->dev; |
| 88 | struct radeon_device *rdev = dev->dev_private; |
| 89 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 90 | ENABLE_SCALER_PS_ALLOCATION args; |
| 91 | int index = GetIndexIntoMasterTable(COMMAND, EnableScaler); |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 92 | |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 93 | /* fixme - fill in enc_priv for atom dac */ |
| 94 | enum radeon_tv_std tv_std = TV_STD_NTSC; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 95 | bool is_tv = false, is_cv = false; |
| 96 | struct drm_encoder *encoder; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 97 | |
| 98 | if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) |
| 99 | return; |
| 100 | |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 101 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 102 | /* find tv std */ |
| 103 | if (encoder->crtc == crtc) { |
| 104 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 105 | if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { |
| 106 | struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; |
| 107 | tv_std = tv_dac->tv_std; |
| 108 | is_tv = true; |
| 109 | } |
| 110 | } |
| 111 | } |
| 112 | |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 113 | memset(&args, 0, sizeof(args)); |
| 114 | |
| 115 | args.ucScaler = radeon_crtc->crtc_id; |
| 116 | |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 117 | if (is_tv) { |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 118 | switch (tv_std) { |
| 119 | case TV_STD_NTSC: |
| 120 | default: |
| 121 | args.ucTVStandard = ATOM_TV_NTSC; |
| 122 | break; |
| 123 | case TV_STD_PAL: |
| 124 | args.ucTVStandard = ATOM_TV_PAL; |
| 125 | break; |
| 126 | case TV_STD_PAL_M: |
| 127 | args.ucTVStandard = ATOM_TV_PALM; |
| 128 | break; |
| 129 | case TV_STD_PAL_60: |
| 130 | args.ucTVStandard = ATOM_TV_PAL60; |
| 131 | break; |
| 132 | case TV_STD_NTSC_J: |
| 133 | args.ucTVStandard = ATOM_TV_NTSCJ; |
| 134 | break; |
| 135 | case TV_STD_SCART_PAL: |
| 136 | args.ucTVStandard = ATOM_TV_PAL; /* ??? */ |
| 137 | break; |
| 138 | case TV_STD_SECAM: |
| 139 | args.ucTVStandard = ATOM_TV_SECAM; |
| 140 | break; |
| 141 | case TV_STD_PAL_CN: |
| 142 | args.ucTVStandard = ATOM_TV_PALCN; |
| 143 | break; |
| 144 | } |
| 145 | args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 146 | } else if (is_cv) { |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 147 | args.ucTVStandard = ATOM_TV_CV; |
| 148 | args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; |
| 149 | } else { |
| 150 | switch (radeon_crtc->rmx_type) { |
| 151 | case RMX_FULL: |
| 152 | args.ucEnable = ATOM_SCALER_EXPANSION; |
| 153 | break; |
| 154 | case RMX_CENTER: |
| 155 | args.ucEnable = ATOM_SCALER_CENTER; |
| 156 | break; |
| 157 | case RMX_ASPECT: |
| 158 | args.ucEnable = ATOM_SCALER_EXPANSION; |
| 159 | break; |
| 160 | default: |
| 161 | if (ASIC_IS_AVIVO(rdev)) |
| 162 | args.ucEnable = ATOM_SCALER_DISABLE; |
| 163 | else |
| 164 | args.ucEnable = ATOM_SCALER_CENTER; |
| 165 | break; |
| 166 | } |
| 167 | } |
| 168 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 169 | if ((is_tv || is_cv) |
| 170 | && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) { |
| 171 | atom_rv515_force_tv_scaler(rdev, radeon_crtc); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 172 | } |
| 173 | } |
| 174 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 175 | static void atombios_lock_crtc(struct drm_crtc *crtc, int lock) |
| 176 | { |
| 177 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 178 | struct drm_device *dev = crtc->dev; |
| 179 | struct radeon_device *rdev = dev->dev_private; |
| 180 | int index = |
| 181 | GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters); |
| 182 | ENABLE_CRTC_PS_ALLOCATION args; |
| 183 | |
| 184 | memset(&args, 0, sizeof(args)); |
| 185 | |
| 186 | args.ucCRTC = radeon_crtc->crtc_id; |
| 187 | args.ucEnable = lock; |
| 188 | |
| 189 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 190 | } |
| 191 | |
| 192 | static void atombios_enable_crtc(struct drm_crtc *crtc, int state) |
| 193 | { |
| 194 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 195 | struct drm_device *dev = crtc->dev; |
| 196 | struct radeon_device *rdev = dev->dev_private; |
| 197 | int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC); |
| 198 | ENABLE_CRTC_PS_ALLOCATION args; |
| 199 | |
| 200 | memset(&args, 0, sizeof(args)); |
| 201 | |
| 202 | args.ucCRTC = radeon_crtc->crtc_id; |
| 203 | args.ucEnable = state; |
| 204 | |
| 205 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 206 | } |
| 207 | |
| 208 | static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state) |
| 209 | { |
| 210 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 211 | struct drm_device *dev = crtc->dev; |
| 212 | struct radeon_device *rdev = dev->dev_private; |
| 213 | int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq); |
| 214 | ENABLE_CRTC_PS_ALLOCATION args; |
| 215 | |
| 216 | memset(&args, 0, sizeof(args)); |
| 217 | |
| 218 | args.ucCRTC = radeon_crtc->crtc_id; |
| 219 | args.ucEnable = state; |
| 220 | |
| 221 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 222 | } |
| 223 | |
| 224 | static void atombios_blank_crtc(struct drm_crtc *crtc, int state) |
| 225 | { |
| 226 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 227 | struct drm_device *dev = crtc->dev; |
| 228 | struct radeon_device *rdev = dev->dev_private; |
| 229 | int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC); |
| 230 | BLANK_CRTC_PS_ALLOCATION args; |
| 231 | |
| 232 | memset(&args, 0, sizeof(args)); |
| 233 | |
| 234 | args.ucCRTC = radeon_crtc->crtc_id; |
| 235 | args.ucBlanking = state; |
| 236 | |
| 237 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 238 | } |
| 239 | |
| 240 | void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) |
| 241 | { |
| 242 | struct drm_device *dev = crtc->dev; |
| 243 | struct radeon_device *rdev = dev->dev_private; |
Alex Deucher | 500b758 | 2009-12-02 11:46:52 -0500 | [diff] [blame] | 244 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 245 | |
| 246 | switch (mode) { |
| 247 | case DRM_MODE_DPMS_ON: |
Alex Deucher | 37b4390 | 2010-02-09 12:04:43 -0500 | [diff] [blame] | 248 | atombios_enable_crtc(crtc, ATOM_ENABLE); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 249 | if (ASIC_IS_DCE3(rdev)) |
Alex Deucher | 37b4390 | 2010-02-09 12:04:43 -0500 | [diff] [blame] | 250 | atombios_enable_crtc_memreq(crtc, ATOM_ENABLE); |
| 251 | atombios_blank_crtc(crtc, ATOM_DISABLE); |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 252 | /* XXX re-enable when interrupt support is added */ |
| 253 | if (!ASIC_IS_DCE4(rdev)) |
| 254 | drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); |
Alex Deucher | 500b758 | 2009-12-02 11:46:52 -0500 | [diff] [blame] | 255 | radeon_crtc_load_lut(crtc); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 256 | break; |
| 257 | case DRM_MODE_DPMS_STANDBY: |
| 258 | case DRM_MODE_DPMS_SUSPEND: |
| 259 | case DRM_MODE_DPMS_OFF: |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 260 | /* XXX re-enable when interrupt support is added */ |
| 261 | if (!ASIC_IS_DCE4(rdev)) |
| 262 | drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); |
Alex Deucher | 37b4390 | 2010-02-09 12:04:43 -0500 | [diff] [blame] | 263 | atombios_blank_crtc(crtc, ATOM_ENABLE); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 264 | if (ASIC_IS_DCE3(rdev)) |
Alex Deucher | 37b4390 | 2010-02-09 12:04:43 -0500 | [diff] [blame] | 265 | atombios_enable_crtc_memreq(crtc, ATOM_DISABLE); |
| 266 | atombios_enable_crtc(crtc, ATOM_DISABLE); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 267 | break; |
| 268 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 269 | } |
| 270 | |
| 271 | static void |
| 272 | atombios_set_crtc_dtd_timing(struct drm_crtc *crtc, |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 273 | struct drm_display_mode *mode) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 274 | { |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 275 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 276 | struct drm_device *dev = crtc->dev; |
| 277 | struct radeon_device *rdev = dev->dev_private; |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 278 | SET_CRTC_USING_DTD_TIMING_PARAMETERS args; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 279 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming); |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 280 | u16 misc = 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 281 | |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 282 | memset(&args, 0, sizeof(args)); |
| 283 | args.usH_Size = cpu_to_le16(mode->crtc_hdisplay); |
| 284 | args.usH_Blanking_Time = |
| 285 | cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay); |
| 286 | args.usV_Size = cpu_to_le16(mode->crtc_vdisplay); |
| 287 | args.usV_Blanking_Time = |
| 288 | cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay); |
| 289 | args.usH_SyncOffset = |
| 290 | cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay); |
| 291 | args.usH_SyncWidth = |
| 292 | cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); |
| 293 | args.usV_SyncOffset = |
| 294 | cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay); |
| 295 | args.usV_SyncWidth = |
| 296 | cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); |
| 297 | /*args.ucH_Border = mode->hborder;*/ |
| 298 | /*args.ucV_Border = mode->vborder;*/ |
| 299 | |
| 300 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
| 301 | misc |= ATOM_VSYNC_POLARITY; |
| 302 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) |
| 303 | misc |= ATOM_HSYNC_POLARITY; |
| 304 | if (mode->flags & DRM_MODE_FLAG_CSYNC) |
| 305 | misc |= ATOM_COMPOSITESYNC; |
| 306 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
| 307 | misc |= ATOM_INTERLACE; |
| 308 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
| 309 | misc |= ATOM_DOUBLE_CLOCK_MODE; |
| 310 | |
| 311 | args.susModeMiscInfo.usAccess = cpu_to_le16(misc); |
| 312 | args.ucCRTC = radeon_crtc->crtc_id; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 313 | |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 314 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 315 | } |
| 316 | |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 317 | static void atombios_crtc_set_timing(struct drm_crtc *crtc, |
| 318 | struct drm_display_mode *mode) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 319 | { |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 320 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 321 | struct drm_device *dev = crtc->dev; |
| 322 | struct radeon_device *rdev = dev->dev_private; |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 323 | SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 324 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing); |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 325 | u16 misc = 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 326 | |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 327 | memset(&args, 0, sizeof(args)); |
| 328 | args.usH_Total = cpu_to_le16(mode->crtc_htotal); |
| 329 | args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay); |
| 330 | args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start); |
| 331 | args.usH_SyncWidth = |
| 332 | cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); |
| 333 | args.usV_Total = cpu_to_le16(mode->crtc_vtotal); |
| 334 | args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay); |
| 335 | args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start); |
| 336 | args.usV_SyncWidth = |
| 337 | cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); |
| 338 | |
| 339 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
| 340 | misc |= ATOM_VSYNC_POLARITY; |
| 341 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) |
| 342 | misc |= ATOM_HSYNC_POLARITY; |
| 343 | if (mode->flags & DRM_MODE_FLAG_CSYNC) |
| 344 | misc |= ATOM_COMPOSITESYNC; |
| 345 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
| 346 | misc |= ATOM_INTERLACE; |
| 347 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
| 348 | misc |= ATOM_DOUBLE_CLOCK_MODE; |
| 349 | |
| 350 | args.susModeMiscInfo.usAccess = cpu_to_le16(misc); |
| 351 | args.ucCRTC = radeon_crtc->crtc_id; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 352 | |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 353 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 354 | } |
| 355 | |
Alex Deucher | b792210 | 2010-03-06 10:57:30 -0500 | [diff] [blame] | 356 | static void atombios_disable_ss(struct drm_crtc *crtc) |
| 357 | { |
| 358 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 359 | struct drm_device *dev = crtc->dev; |
| 360 | struct radeon_device *rdev = dev->dev_private; |
| 361 | u32 ss_cntl; |
| 362 | |
| 363 | if (ASIC_IS_DCE4(rdev)) { |
| 364 | switch (radeon_crtc->pll_id) { |
| 365 | case ATOM_PPLL1: |
| 366 | ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL); |
| 367 | ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; |
| 368 | WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl); |
| 369 | break; |
| 370 | case ATOM_PPLL2: |
| 371 | ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL); |
| 372 | ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; |
| 373 | WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl); |
| 374 | break; |
| 375 | case ATOM_DCPLL: |
| 376 | case ATOM_PPLL_INVALID: |
| 377 | return; |
| 378 | } |
| 379 | } else if (ASIC_IS_AVIVO(rdev)) { |
| 380 | switch (radeon_crtc->pll_id) { |
| 381 | case ATOM_PPLL1: |
| 382 | ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL); |
| 383 | ss_cntl &= ~1; |
| 384 | WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl); |
| 385 | break; |
| 386 | case ATOM_PPLL2: |
| 387 | ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL); |
| 388 | ss_cntl &= ~1; |
| 389 | WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl); |
| 390 | break; |
| 391 | case ATOM_DCPLL: |
| 392 | case ATOM_PPLL_INVALID: |
| 393 | return; |
| 394 | } |
| 395 | } |
| 396 | } |
| 397 | |
| 398 | |
Alex Deucher | 26b9fc3 | 2010-02-01 16:39:11 -0500 | [diff] [blame] | 399 | union atom_enable_ss { |
| 400 | ENABLE_LVDS_SS_PARAMETERS legacy; |
| 401 | ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1; |
| 402 | }; |
| 403 | |
Alex Deucher | b792210 | 2010-03-06 10:57:30 -0500 | [diff] [blame] | 404 | static void atombios_enable_ss(struct drm_crtc *crtc) |
Alex Deucher | ebbe1cb | 2009-10-16 11:15:25 -0400 | [diff] [blame] | 405 | { |
| 406 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 407 | struct drm_device *dev = crtc->dev; |
| 408 | struct radeon_device *rdev = dev->dev_private; |
| 409 | struct drm_encoder *encoder = NULL; |
| 410 | struct radeon_encoder *radeon_encoder = NULL; |
| 411 | struct radeon_encoder_atom_dig *dig = NULL; |
| 412 | int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL); |
Alex Deucher | 26b9fc3 | 2010-02-01 16:39:11 -0500 | [diff] [blame] | 413 | union atom_enable_ss args; |
Alex Deucher | ebbe1cb | 2009-10-16 11:15:25 -0400 | [diff] [blame] | 414 | uint16_t percentage = 0; |
| 415 | uint8_t type = 0, step = 0, delay = 0, range = 0; |
| 416 | |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 417 | /* XXX add ss support for DCE4 */ |
| 418 | if (ASIC_IS_DCE4(rdev)) |
| 419 | return; |
| 420 | |
Alex Deucher | ebbe1cb | 2009-10-16 11:15:25 -0400 | [diff] [blame] | 421 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 422 | if (encoder->crtc == crtc) { |
| 423 | radeon_encoder = to_radeon_encoder(encoder); |
Alex Deucher | ebbe1cb | 2009-10-16 11:15:25 -0400 | [diff] [blame] | 424 | /* only enable spread spectrum on LVDS */ |
Alex Deucher | d11aa88 | 2009-10-28 00:51:20 -0400 | [diff] [blame] | 425 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
| 426 | dig = radeon_encoder->enc_priv; |
| 427 | if (dig && dig->ss) { |
| 428 | percentage = dig->ss->percentage; |
| 429 | type = dig->ss->type; |
| 430 | step = dig->ss->step; |
| 431 | delay = dig->ss->delay; |
| 432 | range = dig->ss->range; |
Alex Deucher | b792210 | 2010-03-06 10:57:30 -0500 | [diff] [blame] | 433 | } else |
Alex Deucher | d11aa88 | 2009-10-28 00:51:20 -0400 | [diff] [blame] | 434 | return; |
Alex Deucher | b792210 | 2010-03-06 10:57:30 -0500 | [diff] [blame] | 435 | } else |
Alex Deucher | ebbe1cb | 2009-10-16 11:15:25 -0400 | [diff] [blame] | 436 | return; |
| 437 | break; |
| 438 | } |
| 439 | } |
| 440 | |
| 441 | if (!radeon_encoder) |
| 442 | return; |
| 443 | |
Alex Deucher | 26b9fc3 | 2010-02-01 16:39:11 -0500 | [diff] [blame] | 444 | memset(&args, 0, sizeof(args)); |
Alex Deucher | ebbe1cb | 2009-10-16 11:15:25 -0400 | [diff] [blame] | 445 | if (ASIC_IS_AVIVO(rdev)) { |
Alex Deucher | 26b9fc3 | 2010-02-01 16:39:11 -0500 | [diff] [blame] | 446 | args.v1.usSpreadSpectrumPercentage = cpu_to_le16(percentage); |
| 447 | args.v1.ucSpreadSpectrumType = type; |
| 448 | args.v1.ucSpreadSpectrumStep = step; |
| 449 | args.v1.ucSpreadSpectrumDelay = delay; |
| 450 | args.v1.ucSpreadSpectrumRange = range; |
| 451 | args.v1.ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; |
Alex Deucher | b792210 | 2010-03-06 10:57:30 -0500 | [diff] [blame] | 452 | args.v1.ucEnable = ATOM_ENABLE; |
Alex Deucher | ebbe1cb | 2009-10-16 11:15:25 -0400 | [diff] [blame] | 453 | } else { |
Alex Deucher | 26b9fc3 | 2010-02-01 16:39:11 -0500 | [diff] [blame] | 454 | args.legacy.usSpreadSpectrumPercentage = cpu_to_le16(percentage); |
| 455 | args.legacy.ucSpreadSpectrumType = type; |
| 456 | args.legacy.ucSpreadSpectrumStepSize_Delay = (step & 3) << 2; |
| 457 | args.legacy.ucSpreadSpectrumStepSize_Delay |= (delay & 7) << 4; |
Alex Deucher | b792210 | 2010-03-06 10:57:30 -0500 | [diff] [blame] | 458 | args.legacy.ucEnable = ATOM_ENABLE; |
Alex Deucher | ebbe1cb | 2009-10-16 11:15:25 -0400 | [diff] [blame] | 459 | } |
Alex Deucher | 26b9fc3 | 2010-02-01 16:39:11 -0500 | [diff] [blame] | 460 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
Alex Deucher | ebbe1cb | 2009-10-16 11:15:25 -0400 | [diff] [blame] | 461 | } |
| 462 | |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 463 | union adjust_pixel_clock { |
| 464 | ADJUST_DISPLAY_PLL_PS_ALLOCATION v1; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 465 | ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3; |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 466 | }; |
| 467 | |
| 468 | static u32 atombios_adjust_pll(struct drm_crtc *crtc, |
| 469 | struct drm_display_mode *mode, |
| 470 | struct radeon_pll *pll) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 471 | { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 472 | struct drm_device *dev = crtc->dev; |
| 473 | struct radeon_device *rdev = dev->dev_private; |
| 474 | struct drm_encoder *encoder = NULL; |
| 475 | struct radeon_encoder *radeon_encoder = NULL; |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 476 | u32 adjusted_clock = mode->clock; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 477 | int encoder_mode = 0; |
Alex Deucher | fc10332 | 2010-01-19 17:16:10 -0500 | [diff] [blame] | 478 | |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 479 | /* reset the pll flags */ |
| 480 | pll->flags = 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 481 | |
Alex Deucher | 7c27f87 | 2010-02-02 12:05:01 -0500 | [diff] [blame] | 482 | /* select the PLL algo */ |
| 483 | if (ASIC_IS_AVIVO(rdev)) { |
Alex Deucher | 383be5d | 2010-02-23 03:24:38 -0500 | [diff] [blame] | 484 | if (radeon_new_pll == 0) |
| 485 | pll->algo = PLL_ALGO_LEGACY; |
| 486 | else |
| 487 | pll->algo = PLL_ALGO_NEW; |
| 488 | } else { |
| 489 | if (radeon_new_pll == 1) |
| 490 | pll->algo = PLL_ALGO_NEW; |
Alex Deucher | 7c27f87 | 2010-02-02 12:05:01 -0500 | [diff] [blame] | 491 | else |
| 492 | pll->algo = PLL_ALGO_LEGACY; |
Alex Deucher | 383be5d | 2010-02-23 03:24:38 -0500 | [diff] [blame] | 493 | } |
Alex Deucher | 7c27f87 | 2010-02-02 12:05:01 -0500 | [diff] [blame] | 494 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 495 | if (ASIC_IS_AVIVO(rdev)) { |
Alex Deucher | eb1300b | 2009-07-13 11:09:56 -0400 | [diff] [blame] | 496 | if ((rdev->family == CHIP_RS600) || |
| 497 | (rdev->family == CHIP_RS690) || |
| 498 | (rdev->family == CHIP_RS740)) |
Alex Deucher | fc10332 | 2010-01-19 17:16:10 -0500 | [diff] [blame] | 499 | pll->flags |= (RADEON_PLL_USE_FRAC_FB_DIV | |
| 500 | RADEON_PLL_PREFER_CLOSEST_LOWER); |
Alex Deucher | eb1300b | 2009-07-13 11:09:56 -0400 | [diff] [blame] | 501 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 502 | if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */ |
Alex Deucher | fc10332 | 2010-01-19 17:16:10 -0500 | [diff] [blame] | 503 | pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 504 | else |
Alex Deucher | fc10332 | 2010-01-19 17:16:10 -0500 | [diff] [blame] | 505 | pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 506 | } else { |
Alex Deucher | fc10332 | 2010-01-19 17:16:10 -0500 | [diff] [blame] | 507 | pll->flags |= RADEON_PLL_LEGACY; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 508 | |
| 509 | if (mode->clock > 200000) /* range limits??? */ |
Alex Deucher | fc10332 | 2010-01-19 17:16:10 -0500 | [diff] [blame] | 510 | pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 511 | else |
Alex Deucher | fc10332 | 2010-01-19 17:16:10 -0500 | [diff] [blame] | 512 | pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 513 | |
| 514 | } |
| 515 | |
| 516 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 517 | if (encoder->crtc == crtc) { |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 518 | radeon_encoder = to_radeon_encoder(encoder); |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 519 | encoder_mode = atombios_get_encoder_mode(encoder); |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 520 | if (ASIC_IS_AVIVO(rdev)) { |
| 521 | /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ |
| 522 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) |
| 523 | adjusted_clock = mode->clock * 2; |
| 524 | } else { |
| 525 | if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) |
Alex Deucher | fc10332 | 2010-01-19 17:16:10 -0500 | [diff] [blame] | 526 | pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 527 | if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) |
Alex Deucher | fc10332 | 2010-01-19 17:16:10 -0500 | [diff] [blame] | 528 | pll->flags |= RADEON_PLL_USE_REF_DIV; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 529 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 530 | break; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 531 | } |
| 532 | } |
| 533 | |
Alex Deucher | 2606c88 | 2009-10-08 13:36:21 -0400 | [diff] [blame] | 534 | /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock |
| 535 | * accordingly based on the encoder/transmitter to work around |
| 536 | * special hw requirements. |
| 537 | */ |
| 538 | if (ASIC_IS_DCE3(rdev)) { |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 539 | union adjust_pixel_clock args; |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 540 | u8 frev, crev; |
| 541 | int index; |
Alex Deucher | 2606c88 | 2009-10-08 13:36:21 -0400 | [diff] [blame] | 542 | |
Alex Deucher | 2606c88 | 2009-10-08 13:36:21 -0400 | [diff] [blame] | 543 | index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll); |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame^] | 544 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, |
| 545 | &crev)) |
| 546 | return adjusted_clock; |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 547 | |
| 548 | memset(&args, 0, sizeof(args)); |
| 549 | |
| 550 | switch (frev) { |
| 551 | case 1: |
| 552 | switch (crev) { |
| 553 | case 1: |
| 554 | case 2: |
| 555 | args.v1.usPixelClock = cpu_to_le16(mode->clock / 10); |
| 556 | args.v1.ucTransmitterID = radeon_encoder->encoder_id; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 557 | args.v1.ucEncodeMode = encoder_mode; |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 558 | |
| 559 | atom_execute_table(rdev->mode_info.atom_context, |
| 560 | index, (uint32_t *)&args); |
| 561 | adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10; |
| 562 | break; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 563 | case 3: |
| 564 | args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10); |
| 565 | args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id; |
| 566 | args.v3.sInput.ucEncodeMode = encoder_mode; |
| 567 | args.v3.sInput.ucDispPllConfig = 0; |
| 568 | if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
| 569 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| 570 | |
| 571 | if (encoder_mode == ATOM_ENCODER_MODE_DP) |
| 572 | args.v3.sInput.ucDispPllConfig |= |
| 573 | DISPPLL_CONFIG_COHERENT_MODE; |
| 574 | else { |
| 575 | if (dig->coherent_mode) |
| 576 | args.v3.sInput.ucDispPllConfig |= |
| 577 | DISPPLL_CONFIG_COHERENT_MODE; |
| 578 | if (mode->clock > 165000) |
| 579 | args.v3.sInput.ucDispPllConfig |= |
| 580 | DISPPLL_CONFIG_DUAL_LINK; |
| 581 | } |
| 582 | } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
| 583 | /* may want to enable SS on DP/eDP eventually */ |
| 584 | args.v3.sInput.ucDispPllConfig |= |
| 585 | DISPPLL_CONFIG_SS_ENABLE; |
| 586 | if (mode->clock > 165000) |
| 587 | args.v3.sInput.ucDispPllConfig |= |
| 588 | DISPPLL_CONFIG_DUAL_LINK; |
| 589 | } |
| 590 | atom_execute_table(rdev->mode_info.atom_context, |
| 591 | index, (uint32_t *)&args); |
| 592 | adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10; |
| 593 | if (args.v3.sOutput.ucRefDiv) { |
| 594 | pll->flags |= RADEON_PLL_USE_REF_DIV; |
| 595 | pll->reference_div = args.v3.sOutput.ucRefDiv; |
| 596 | } |
| 597 | if (args.v3.sOutput.ucPostDiv) { |
| 598 | pll->flags |= RADEON_PLL_USE_POST_DIV; |
| 599 | pll->post_div = args.v3.sOutput.ucPostDiv; |
| 600 | } |
| 601 | break; |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 602 | default: |
| 603 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
| 604 | return adjusted_clock; |
| 605 | } |
| 606 | break; |
| 607 | default: |
| 608 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
| 609 | return adjusted_clock; |
| 610 | } |
Alex Deucher | d56ef9c | 2009-10-27 12:11:09 -0400 | [diff] [blame] | 611 | } |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 612 | return adjusted_clock; |
| 613 | } |
| 614 | |
| 615 | union set_pixel_clock { |
| 616 | SET_PIXEL_CLOCK_PS_ALLOCATION base; |
| 617 | PIXEL_CLOCK_PARAMETERS v1; |
| 618 | PIXEL_CLOCK_PARAMETERS_V2 v2; |
| 619 | PIXEL_CLOCK_PARAMETERS_V3 v3; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 620 | PIXEL_CLOCK_PARAMETERS_V5 v5; |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 621 | }; |
| 622 | |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 623 | static void atombios_crtc_set_dcpll(struct drm_crtc *crtc) |
| 624 | { |
| 625 | struct drm_device *dev = crtc->dev; |
| 626 | struct radeon_device *rdev = dev->dev_private; |
| 627 | u8 frev, crev; |
| 628 | int index; |
| 629 | union set_pixel_clock args; |
| 630 | |
| 631 | memset(&args, 0, sizeof(args)); |
| 632 | |
| 633 | index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame^] | 634 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, |
| 635 | &crev)) |
| 636 | return; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 637 | |
| 638 | switch (frev) { |
| 639 | case 1: |
| 640 | switch (crev) { |
| 641 | case 5: |
| 642 | /* if the default dcpll clock is specified, |
| 643 | * SetPixelClock provides the dividers |
| 644 | */ |
| 645 | args.v5.ucCRTC = ATOM_CRTC_INVALID; |
| 646 | args.v5.usPixelClock = rdev->clock.default_dispclk; |
| 647 | args.v5.ucPpll = ATOM_DCPLL; |
| 648 | break; |
| 649 | default: |
| 650 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
| 651 | return; |
| 652 | } |
| 653 | break; |
| 654 | default: |
| 655 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
| 656 | return; |
| 657 | } |
| 658 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 659 | } |
| 660 | |
| 661 | static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 662 | { |
| 663 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 664 | struct drm_device *dev = crtc->dev; |
| 665 | struct radeon_device *rdev = dev->dev_private; |
| 666 | struct drm_encoder *encoder = NULL; |
| 667 | struct radeon_encoder *radeon_encoder = NULL; |
| 668 | u8 frev, crev; |
| 669 | int index; |
| 670 | union set_pixel_clock args; |
| 671 | u32 pll_clock = mode->clock; |
| 672 | u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; |
| 673 | struct radeon_pll *pll; |
| 674 | u32 adjusted_clock; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 675 | int encoder_mode = 0; |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 676 | |
| 677 | memset(&args, 0, sizeof(args)); |
| 678 | |
| 679 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 680 | if (encoder->crtc == crtc) { |
| 681 | radeon_encoder = to_radeon_encoder(encoder); |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 682 | encoder_mode = atombios_get_encoder_mode(encoder); |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 683 | break; |
| 684 | } |
| 685 | } |
| 686 | |
| 687 | if (!radeon_encoder) |
| 688 | return; |
| 689 | |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 690 | switch (radeon_crtc->pll_id) { |
| 691 | case ATOM_PPLL1: |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 692 | pll = &rdev->clock.p1pll; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 693 | break; |
| 694 | case ATOM_PPLL2: |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 695 | pll = &rdev->clock.p2pll; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 696 | break; |
| 697 | case ATOM_DCPLL: |
| 698 | case ATOM_PPLL_INVALID: |
| 699 | pll = &rdev->clock.dcpll; |
| 700 | break; |
| 701 | } |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 702 | |
| 703 | /* adjust pixel clock as needed */ |
| 704 | adjusted_clock = atombios_adjust_pll(crtc, mode, pll); |
Alex Deucher | 2606c88 | 2009-10-08 13:36:21 -0400 | [diff] [blame] | 705 | |
Alex Deucher | 7c27f87 | 2010-02-02 12:05:01 -0500 | [diff] [blame] | 706 | radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div, |
| 707 | &ref_div, &post_div); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 708 | |
Dave Airlie | 39deb2d | 2009-10-12 14:21:19 +1000 | [diff] [blame] | 709 | index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame^] | 710 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, |
| 711 | &crev)) |
| 712 | return; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 713 | |
| 714 | switch (frev) { |
| 715 | case 1: |
| 716 | switch (crev) { |
| 717 | case 1: |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 718 | args.v1.usPixelClock = cpu_to_le16(mode->clock / 10); |
| 719 | args.v1.usRefDiv = cpu_to_le16(ref_div); |
| 720 | args.v1.usFbDiv = cpu_to_le16(fb_div); |
| 721 | args.v1.ucFracFbDiv = frac_fb_div; |
| 722 | args.v1.ucPostDiv = post_div; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 723 | args.v1.ucPpll = radeon_crtc->pll_id; |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 724 | args.v1.ucCRTC = radeon_crtc->crtc_id; |
| 725 | args.v1.ucRefDivSrc = 1; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 726 | break; |
| 727 | case 2: |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 728 | args.v2.usPixelClock = cpu_to_le16(mode->clock / 10); |
| 729 | args.v2.usRefDiv = cpu_to_le16(ref_div); |
| 730 | args.v2.usFbDiv = cpu_to_le16(fb_div); |
| 731 | args.v2.ucFracFbDiv = frac_fb_div; |
| 732 | args.v2.ucPostDiv = post_div; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 733 | args.v2.ucPpll = radeon_crtc->pll_id; |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 734 | args.v2.ucCRTC = radeon_crtc->crtc_id; |
| 735 | args.v2.ucRefDivSrc = 1; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 736 | break; |
| 737 | case 3: |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 738 | args.v3.usPixelClock = cpu_to_le16(mode->clock / 10); |
| 739 | args.v3.usRefDiv = cpu_to_le16(ref_div); |
| 740 | args.v3.usFbDiv = cpu_to_le16(fb_div); |
| 741 | args.v3.ucFracFbDiv = frac_fb_div; |
| 742 | args.v3.ucPostDiv = post_div; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 743 | args.v3.ucPpll = radeon_crtc->pll_id; |
| 744 | args.v3.ucMiscInfo = (radeon_crtc->pll_id << 2); |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 745 | args.v3.ucTransmitterId = radeon_encoder->encoder_id; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 746 | args.v3.ucEncoderMode = encoder_mode; |
| 747 | break; |
| 748 | case 5: |
| 749 | args.v5.ucCRTC = radeon_crtc->crtc_id; |
| 750 | args.v5.usPixelClock = cpu_to_le16(mode->clock / 10); |
| 751 | args.v5.ucRefDiv = ref_div; |
| 752 | args.v5.usFbDiv = cpu_to_le16(fb_div); |
| 753 | args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); |
| 754 | args.v5.ucPostDiv = post_div; |
| 755 | args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */ |
| 756 | args.v5.ucTransmitterID = radeon_encoder->encoder_id; |
| 757 | args.v5.ucEncoderMode = encoder_mode; |
| 758 | args.v5.ucPpll = radeon_crtc->pll_id; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 759 | break; |
| 760 | default: |
| 761 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
| 762 | return; |
| 763 | } |
| 764 | break; |
| 765 | default: |
| 766 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
| 767 | return; |
| 768 | } |
| 769 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 770 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 771 | } |
| 772 | |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 773 | static int evergreen_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
| 774 | struct drm_framebuffer *old_fb) |
| 775 | { |
| 776 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 777 | struct drm_device *dev = crtc->dev; |
| 778 | struct radeon_device *rdev = dev->dev_private; |
| 779 | struct radeon_framebuffer *radeon_fb; |
| 780 | struct drm_gem_object *obj; |
| 781 | struct radeon_bo *rbo; |
| 782 | uint64_t fb_location; |
| 783 | uint32_t fb_format, fb_pitch_pixels, tiling_flags; |
| 784 | int r; |
| 785 | |
| 786 | /* no fb bound */ |
| 787 | if (!crtc->fb) { |
| 788 | DRM_DEBUG("No FB bound\n"); |
| 789 | return 0; |
| 790 | } |
| 791 | |
| 792 | radeon_fb = to_radeon_framebuffer(crtc->fb); |
| 793 | |
| 794 | /* Pin framebuffer & get tilling informations */ |
| 795 | obj = radeon_fb->obj; |
| 796 | rbo = obj->driver_private; |
| 797 | r = radeon_bo_reserve(rbo, false); |
| 798 | if (unlikely(r != 0)) |
| 799 | return r; |
| 800 | r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); |
| 801 | if (unlikely(r != 0)) { |
| 802 | radeon_bo_unreserve(rbo); |
| 803 | return -EINVAL; |
| 804 | } |
| 805 | radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); |
| 806 | radeon_bo_unreserve(rbo); |
| 807 | |
| 808 | switch (crtc->fb->bits_per_pixel) { |
| 809 | case 8: |
| 810 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) | |
| 811 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED)); |
| 812 | break; |
| 813 | case 15: |
| 814 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | |
| 815 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555)); |
| 816 | break; |
| 817 | case 16: |
| 818 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | |
| 819 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565)); |
| 820 | break; |
| 821 | case 24: |
| 822 | case 32: |
| 823 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | |
| 824 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); |
| 825 | break; |
| 826 | default: |
| 827 | DRM_ERROR("Unsupported screen depth %d\n", |
| 828 | crtc->fb->bits_per_pixel); |
| 829 | return -EINVAL; |
| 830 | } |
| 831 | |
| 832 | switch (radeon_crtc->crtc_id) { |
| 833 | case 0: |
| 834 | WREG32(AVIVO_D1VGA_CONTROL, 0); |
| 835 | break; |
| 836 | case 1: |
| 837 | WREG32(AVIVO_D2VGA_CONTROL, 0); |
| 838 | break; |
| 839 | case 2: |
| 840 | WREG32(EVERGREEN_D3VGA_CONTROL, 0); |
| 841 | break; |
| 842 | case 3: |
| 843 | WREG32(EVERGREEN_D4VGA_CONTROL, 0); |
| 844 | break; |
| 845 | case 4: |
| 846 | WREG32(EVERGREEN_D5VGA_CONTROL, 0); |
| 847 | break; |
| 848 | case 5: |
| 849 | WREG32(EVERGREEN_D6VGA_CONTROL, 0); |
| 850 | break; |
| 851 | default: |
| 852 | break; |
| 853 | } |
| 854 | |
| 855 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, |
| 856 | upper_32_bits(fb_location)); |
| 857 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, |
| 858 | upper_32_bits(fb_location)); |
| 859 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
| 860 | (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); |
| 861 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
| 862 | (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); |
| 863 | WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); |
| 864 | |
| 865 | WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); |
| 866 | WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); |
| 867 | WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0); |
| 868 | WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0); |
| 869 | WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width); |
| 870 | WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height); |
| 871 | |
| 872 | fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8); |
| 873 | WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); |
| 874 | WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1); |
| 875 | |
| 876 | WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, |
| 877 | crtc->mode.vdisplay); |
| 878 | x &= ~3; |
| 879 | y &= ~1; |
| 880 | WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, |
| 881 | (x << 16) | y); |
| 882 | WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, |
| 883 | (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay); |
| 884 | |
| 885 | if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) |
| 886 | WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, |
| 887 | EVERGREEN_INTERLEAVE_EN); |
| 888 | else |
| 889 | WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); |
| 890 | |
| 891 | if (old_fb && old_fb != crtc->fb) { |
| 892 | radeon_fb = to_radeon_framebuffer(old_fb); |
| 893 | rbo = radeon_fb->obj->driver_private; |
| 894 | r = radeon_bo_reserve(rbo, false); |
| 895 | if (unlikely(r != 0)) |
| 896 | return r; |
| 897 | radeon_bo_unpin(rbo); |
| 898 | radeon_bo_unreserve(rbo); |
| 899 | } |
| 900 | |
| 901 | /* Bytes per pixel may have changed */ |
| 902 | radeon_bandwidth_update(rdev); |
| 903 | |
| 904 | return 0; |
| 905 | } |
| 906 | |
Alex Deucher | 54f088a | 2010-01-19 16:34:01 -0500 | [diff] [blame] | 907 | static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
| 908 | struct drm_framebuffer *old_fb) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 909 | { |
| 910 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 911 | struct drm_device *dev = crtc->dev; |
| 912 | struct radeon_device *rdev = dev->dev_private; |
| 913 | struct radeon_framebuffer *radeon_fb; |
| 914 | struct drm_gem_object *obj; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 915 | struct radeon_bo *rbo; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 916 | uint64_t fb_location; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 917 | uint32_t fb_format, fb_pitch_pixels, tiling_flags; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 918 | int r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 919 | |
Jerome Glisse | 2de3b48 | 2009-11-17 14:08:55 -0800 | [diff] [blame] | 920 | /* no fb bound */ |
| 921 | if (!crtc->fb) { |
| 922 | DRM_DEBUG("No FB bound\n"); |
| 923 | return 0; |
| 924 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 925 | |
| 926 | radeon_fb = to_radeon_framebuffer(crtc->fb); |
| 927 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 928 | /* Pin framebuffer & get tilling informations */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 929 | obj = radeon_fb->obj; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 930 | rbo = obj->driver_private; |
| 931 | r = radeon_bo_reserve(rbo, false); |
| 932 | if (unlikely(r != 0)) |
| 933 | return r; |
| 934 | r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); |
| 935 | if (unlikely(r != 0)) { |
| 936 | radeon_bo_unreserve(rbo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 937 | return -EINVAL; |
| 938 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 939 | radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); |
| 940 | radeon_bo_unreserve(rbo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 941 | |
| 942 | switch (crtc->fb->bits_per_pixel) { |
Dave Airlie | 41456df | 2009-09-16 10:15:21 +1000 | [diff] [blame] | 943 | case 8: |
| 944 | fb_format = |
| 945 | AVIVO_D1GRPH_CONTROL_DEPTH_8BPP | |
| 946 | AVIVO_D1GRPH_CONTROL_8BPP_INDEXED; |
| 947 | break; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 948 | case 15: |
| 949 | fb_format = |
| 950 | AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | |
| 951 | AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; |
| 952 | break; |
| 953 | case 16: |
| 954 | fb_format = |
| 955 | AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | |
| 956 | AVIVO_D1GRPH_CONTROL_16BPP_RGB565; |
| 957 | break; |
| 958 | case 24: |
| 959 | case 32: |
| 960 | fb_format = |
| 961 | AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | |
| 962 | AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; |
| 963 | break; |
| 964 | default: |
| 965 | DRM_ERROR("Unsupported screen depth %d\n", |
| 966 | crtc->fb->bits_per_pixel); |
| 967 | return -EINVAL; |
| 968 | } |
| 969 | |
Dave Airlie | cf2f05d | 2009-12-08 15:45:13 +1000 | [diff] [blame] | 970 | if (tiling_flags & RADEON_TILING_MACRO) |
| 971 | fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE; |
| 972 | |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 973 | if (tiling_flags & RADEON_TILING_MICRO) |
| 974 | fb_format |= AVIVO_D1GRPH_TILED; |
| 975 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 976 | if (radeon_crtc->crtc_id == 0) |
| 977 | WREG32(AVIVO_D1VGA_CONTROL, 0); |
| 978 | else |
| 979 | WREG32(AVIVO_D2VGA_CONTROL, 0); |
Alex Deucher | c290dad | 2009-10-22 16:12:34 -0400 | [diff] [blame] | 980 | |
| 981 | if (rdev->family >= CHIP_RV770) { |
| 982 | if (radeon_crtc->crtc_id) { |
| 983 | WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0); |
| 984 | WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0); |
| 985 | } else { |
| 986 | WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0); |
| 987 | WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0); |
| 988 | } |
| 989 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 990 | WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
| 991 | (u32) fb_location); |
| 992 | WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + |
| 993 | radeon_crtc->crtc_offset, (u32) fb_location); |
| 994 | WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); |
| 995 | |
| 996 | WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); |
| 997 | WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); |
| 998 | WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); |
| 999 | WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); |
| 1000 | WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width); |
| 1001 | WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height); |
| 1002 | |
| 1003 | fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8); |
| 1004 | WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); |
| 1005 | WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); |
| 1006 | |
| 1007 | WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, |
| 1008 | crtc->mode.vdisplay); |
| 1009 | x &= ~3; |
| 1010 | y &= ~1; |
| 1011 | WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, |
| 1012 | (x << 16) | y); |
| 1013 | WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, |
| 1014 | (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay); |
| 1015 | |
| 1016 | if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) |
| 1017 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, |
| 1018 | AVIVO_D1MODE_INTERLEAVE_EN); |
| 1019 | else |
| 1020 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); |
| 1021 | |
| 1022 | if (old_fb && old_fb != crtc->fb) { |
| 1023 | radeon_fb = to_radeon_framebuffer(old_fb); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1024 | rbo = radeon_fb->obj->driver_private; |
| 1025 | r = radeon_bo_reserve(rbo, false); |
| 1026 | if (unlikely(r != 0)) |
| 1027 | return r; |
| 1028 | radeon_bo_unpin(rbo); |
| 1029 | radeon_bo_unreserve(rbo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1030 | } |
Michel Dänzer | f30f37d | 2009-10-08 10:44:09 +0200 | [diff] [blame] | 1031 | |
| 1032 | /* Bytes per pixel may have changed */ |
| 1033 | radeon_bandwidth_update(rdev); |
| 1034 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1035 | return 0; |
| 1036 | } |
| 1037 | |
Alex Deucher | 54f088a | 2010-01-19 16:34:01 -0500 | [diff] [blame] | 1038 | int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
| 1039 | struct drm_framebuffer *old_fb) |
| 1040 | { |
| 1041 | struct drm_device *dev = crtc->dev; |
| 1042 | struct radeon_device *rdev = dev->dev_private; |
| 1043 | |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1044 | if (ASIC_IS_DCE4(rdev)) |
| 1045 | return evergreen_crtc_set_base(crtc, x, y, old_fb); |
| 1046 | else if (ASIC_IS_AVIVO(rdev)) |
Alex Deucher | 54f088a | 2010-01-19 16:34:01 -0500 | [diff] [blame] | 1047 | return avivo_crtc_set_base(crtc, x, y, old_fb); |
| 1048 | else |
| 1049 | return radeon_crtc_set_base(crtc, x, y, old_fb); |
| 1050 | } |
| 1051 | |
Alex Deucher | 615e0cb | 2010-01-20 16:22:53 -0500 | [diff] [blame] | 1052 | /* properly set additional regs when using atombios */ |
| 1053 | static void radeon_legacy_atom_fixup(struct drm_crtc *crtc) |
| 1054 | { |
| 1055 | struct drm_device *dev = crtc->dev; |
| 1056 | struct radeon_device *rdev = dev->dev_private; |
| 1057 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 1058 | u32 disp_merge_cntl; |
| 1059 | |
| 1060 | switch (radeon_crtc->crtc_id) { |
| 1061 | case 0: |
| 1062 | disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); |
| 1063 | disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; |
| 1064 | WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); |
| 1065 | break; |
| 1066 | case 1: |
| 1067 | disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); |
| 1068 | disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; |
| 1069 | WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl); |
| 1070 | WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID)); |
| 1071 | WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID)); |
| 1072 | break; |
| 1073 | } |
| 1074 | } |
| 1075 | |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1076 | static int radeon_atom_pick_pll(struct drm_crtc *crtc) |
| 1077 | { |
| 1078 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 1079 | struct drm_device *dev = crtc->dev; |
| 1080 | struct radeon_device *rdev = dev->dev_private; |
| 1081 | struct drm_encoder *test_encoder; |
| 1082 | struct drm_crtc *test_crtc; |
| 1083 | uint32_t pll_in_use = 0; |
| 1084 | |
| 1085 | if (ASIC_IS_DCE4(rdev)) { |
| 1086 | /* if crtc is driving DP and we have an ext clock, use that */ |
| 1087 | list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { |
| 1088 | if (test_encoder->crtc && (test_encoder->crtc == crtc)) { |
| 1089 | if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) { |
| 1090 | if (rdev->clock.dp_extclk) |
| 1091 | return ATOM_PPLL_INVALID; |
| 1092 | } |
| 1093 | } |
| 1094 | } |
| 1095 | |
| 1096 | /* otherwise, pick one of the plls */ |
| 1097 | list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { |
| 1098 | struct radeon_crtc *radeon_test_crtc; |
| 1099 | |
| 1100 | if (crtc == test_crtc) |
| 1101 | continue; |
| 1102 | |
| 1103 | radeon_test_crtc = to_radeon_crtc(test_crtc); |
| 1104 | if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) && |
| 1105 | (radeon_test_crtc->pll_id <= ATOM_PPLL2)) |
| 1106 | pll_in_use |= (1 << radeon_test_crtc->pll_id); |
| 1107 | } |
| 1108 | if (!(pll_in_use & 1)) |
| 1109 | return ATOM_PPLL1; |
| 1110 | return ATOM_PPLL2; |
| 1111 | } else |
| 1112 | return radeon_crtc->crtc_id; |
| 1113 | |
| 1114 | } |
| 1115 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1116 | int atombios_crtc_mode_set(struct drm_crtc *crtc, |
| 1117 | struct drm_display_mode *mode, |
| 1118 | struct drm_display_mode *adjusted_mode, |
| 1119 | int x, int y, struct drm_framebuffer *old_fb) |
| 1120 | { |
| 1121 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 1122 | struct drm_device *dev = crtc->dev; |
| 1123 | struct radeon_device *rdev = dev->dev_private; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1124 | |
| 1125 | /* TODO color tiling */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1126 | |
Alex Deucher | b792210 | 2010-03-06 10:57:30 -0500 | [diff] [blame] | 1127 | atombios_disable_ss(crtc); |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1128 | /* always set DCPLL */ |
| 1129 | if (ASIC_IS_DCE4(rdev)) |
| 1130 | atombios_crtc_set_dcpll(crtc); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1131 | atombios_crtc_set_pll(crtc, adjusted_mode); |
Alex Deucher | b792210 | 2010-03-06 10:57:30 -0500 | [diff] [blame] | 1132 | atombios_enable_ss(crtc); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1133 | |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1134 | if (ASIC_IS_DCE4(rdev)) |
| 1135 | atombios_set_crtc_dtd_timing(crtc, adjusted_mode); |
| 1136 | else if (ASIC_IS_AVIVO(rdev)) |
| 1137 | atombios_crtc_set_timing(crtc, adjusted_mode); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1138 | else { |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1139 | atombios_crtc_set_timing(crtc, adjusted_mode); |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 1140 | if (radeon_crtc->crtc_id == 0) |
| 1141 | atombios_set_crtc_dtd_timing(crtc, adjusted_mode); |
Alex Deucher | 615e0cb | 2010-01-20 16:22:53 -0500 | [diff] [blame] | 1142 | radeon_legacy_atom_fixup(crtc); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1143 | } |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1144 | atombios_crtc_set_base(crtc, x, y, old_fb); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1145 | atombios_overscan_setup(crtc, mode, adjusted_mode); |
| 1146 | atombios_scaler_setup(crtc); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1147 | return 0; |
| 1148 | } |
| 1149 | |
| 1150 | static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc, |
| 1151 | struct drm_display_mode *mode, |
| 1152 | struct drm_display_mode *adjusted_mode) |
| 1153 | { |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1154 | if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) |
| 1155 | return false; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1156 | return true; |
| 1157 | } |
| 1158 | |
| 1159 | static void atombios_crtc_prepare(struct drm_crtc *crtc) |
| 1160 | { |
Alex Deucher | 267364a | 2010-03-08 17:10:41 -0500 | [diff] [blame] | 1161 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 1162 | |
| 1163 | /* pick pll */ |
| 1164 | radeon_crtc->pll_id = radeon_atom_pick_pll(crtc); |
| 1165 | |
Alex Deucher | 37b4390 | 2010-02-09 12:04:43 -0500 | [diff] [blame] | 1166 | atombios_lock_crtc(crtc, ATOM_ENABLE); |
Alex Deucher | a348c84 | 2010-01-21 16:50:30 -0500 | [diff] [blame] | 1167 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1168 | } |
| 1169 | |
| 1170 | static void atombios_crtc_commit(struct drm_crtc *crtc) |
| 1171 | { |
| 1172 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON); |
Alex Deucher | 37b4390 | 2010-02-09 12:04:43 -0500 | [diff] [blame] | 1173 | atombios_lock_crtc(crtc, ATOM_DISABLE); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1174 | } |
| 1175 | |
| 1176 | static const struct drm_crtc_helper_funcs atombios_helper_funcs = { |
| 1177 | .dpms = atombios_crtc_dpms, |
| 1178 | .mode_fixup = atombios_crtc_mode_fixup, |
| 1179 | .mode_set = atombios_crtc_mode_set, |
| 1180 | .mode_set_base = atombios_crtc_set_base, |
| 1181 | .prepare = atombios_crtc_prepare, |
| 1182 | .commit = atombios_crtc_commit, |
Dave Airlie | 068143d | 2009-10-05 09:58:02 +1000 | [diff] [blame] | 1183 | .load_lut = radeon_crtc_load_lut, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1184 | }; |
| 1185 | |
| 1186 | void radeon_atombios_init_crtc(struct drm_device *dev, |
| 1187 | struct radeon_crtc *radeon_crtc) |
| 1188 | { |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1189 | struct radeon_device *rdev = dev->dev_private; |
| 1190 | |
| 1191 | if (ASIC_IS_DCE4(rdev)) { |
| 1192 | switch (radeon_crtc->crtc_id) { |
| 1193 | case 0: |
| 1194 | default: |
Alex Deucher | 12d7798 | 2010-02-09 17:18:48 -0500 | [diff] [blame] | 1195 | radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1196 | break; |
| 1197 | case 1: |
Alex Deucher | 12d7798 | 2010-02-09 17:18:48 -0500 | [diff] [blame] | 1198 | radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1199 | break; |
| 1200 | case 2: |
Alex Deucher | 12d7798 | 2010-02-09 17:18:48 -0500 | [diff] [blame] | 1201 | radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1202 | break; |
| 1203 | case 3: |
Alex Deucher | 12d7798 | 2010-02-09 17:18:48 -0500 | [diff] [blame] | 1204 | radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1205 | break; |
| 1206 | case 4: |
Alex Deucher | 12d7798 | 2010-02-09 17:18:48 -0500 | [diff] [blame] | 1207 | radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1208 | break; |
| 1209 | case 5: |
Alex Deucher | 12d7798 | 2010-02-09 17:18:48 -0500 | [diff] [blame] | 1210 | radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1211 | break; |
| 1212 | } |
| 1213 | } else { |
| 1214 | if (radeon_crtc->crtc_id == 1) |
| 1215 | radeon_crtc->crtc_offset = |
| 1216 | AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; |
| 1217 | else |
| 1218 | radeon_crtc->crtc_offset = 0; |
| 1219 | } |
| 1220 | radeon_crtc->pll_id = -1; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1221 | drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); |
| 1222 | } |