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Russell Kinga09e64f2008-08-05 16:14:15 +01001/*
2 * arch/arm/mach-at91/include/mach/at91_rstc.h
3 *
4 * Reset Controller (RSTC) - System peripherals regsters.
5 * Based on AT91SAM9261 datasheet revision D.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#ifndef AT91_RSTC_H
14#define AT91_RSTC_H
15
16#define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */
17#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */
18#define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */
19#define AT91_RSTC_EXTRST (1 << 3) /* External Reset */
20#define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */
21
22#define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */
23#define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */
24#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */
25#define AT91_RSTC_RSTTYP_GENERAL (0 << 8)
26#define AT91_RSTC_RSTTYP_WAKEUP (1 << 8)
27#define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8)
28#define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8)
29#define AT91_RSTC_RSTTYP_USER (4 << 8)
30#define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */
31#define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */
32
33#define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */
34#define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */
35#define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */
36#define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */
37
38#endif