blob: 9f2b1ea8fb209f27ce6058f4d005fef1db14d983 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/arch/arm/mach-integrator/pci_v3.c
3 *
4 * PCI functions for V3 host PCI bridge
5 *
6 * Copyright (C) 1999 ARM Limited
7 * Copyright (C) 2000-2001 Deep Blue Solutions Ltd
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070023#include <linux/kernel.h>
24#include <linux/pci.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070025#include <linux/slab.h>
26#include <linux/ioport.h>
27#include <linux/interrupt.h>
28#include <linux/spinlock.h>
29#include <linux/init.h>
30
Russell Kinga09e64f2008-08-05 16:14:15 +010031#include <mach/hardware.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070032#include <asm/io.h>
33#include <asm/irq.h>
34#include <asm/system.h>
35#include <asm/mach/pci.h>
Russell Kingc6af66b2007-05-17 10:16:55 +010036#include <asm/irq_regs.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070037
38#include <asm/hardware/pci_v3.h>
39
40/*
41 * The V3 PCI interface chip in Integrator provides several windows from
42 * local bus memory into the PCI memory areas. Unfortunately, there
43 * are not really enough windows for our usage, therefore we reuse
44 * one of the windows for access to PCI configuration space. The
45 * memory map is as follows:
46 *
47 * Local Bus Memory Usage
48 *
49 * 40000000 - 4FFFFFFF PCI memory. 256M non-prefetchable
50 * 50000000 - 5FFFFFFF PCI memory. 256M prefetchable
51 * 60000000 - 60FFFFFF PCI IO. 16M
52 * 61000000 - 61FFFFFF PCI Configuration. 16M
53 *
54 * There are three V3 windows, each described by a pair of V3 registers.
55 * These are LB_BASE0/LB_MAP0, LB_BASE1/LB_MAP1 and LB_BASE2/LB_MAP2.
56 * Base0 and Base1 can be used for any type of PCI memory access. Base2
57 * can be used either for PCI I/O or for I20 accesses. By default, uHAL
58 * uses this only for PCI IO space.
59 *
60 * Normally these spaces are mapped using the following base registers:
61 *
62 * Usage Local Bus Memory Base/Map registers used
63 *
64 * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0
65 * Mem 50000000 - 5FFFFFFF LB_BASE1/LB_MAP1
66 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2
67 * Cfg 61000000 - 61FFFFFF
68 *
69 * This means that I20 and PCI configuration space accesses will fail.
70 * When PCI configuration accesses are needed (via the uHAL PCI
71 * configuration space primitives) we must remap the spaces as follows:
72 *
73 * Usage Local Bus Memory Base/Map registers used
74 *
75 * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0
76 * Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0
77 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2
78 * Cfg 61000000 - 61FFFFFF LB_BASE1/LB_MAP1
79 *
80 * To make this work, the code depends on overlapping windows working.
81 * The V3 chip translates an address by checking its range within
82 * each of the BASE/MAP pairs in turn (in ascending register number
83 * order). It will use the first matching pair. So, for example,
84 * if the same address is mapped by both LB_BASE0/LB_MAP0 and
85 * LB_BASE1/LB_MAP1, the V3 will use the translation from
86 * LB_BASE0/LB_MAP0.
87 *
88 * To allow PCI Configuration space access, the code enlarges the
89 * window mapped by LB_BASE0/LB_MAP0 from 256M to 512M. This occludes
90 * the windows currently mapped by LB_BASE1/LB_MAP1 so that it can
91 * be remapped for use by configuration cycles.
92 *
93 * At the end of the PCI Configuration space accesses,
94 * LB_BASE1/LB_MAP1 is reset to map PCI Memory. Finally the window
95 * mapped by LB_BASE0/LB_MAP0 is reduced in size from 512M to 256M to
96 * reveal the now restored LB_BASE1/LB_MAP1 window.
97 *
98 * NOTE: We do not set up I2O mapping. I suspect that this is only
99 * for an intelligent (target) device. Using I2O disables most of
100 * the mappings into PCI memory.
101 */
102
103// V3 access routines
104#define v3_writeb(o,v) __raw_writeb(v, PCI_V3_VADDR + (unsigned int)(o))
105#define v3_readb(o) (__raw_readb(PCI_V3_VADDR + (unsigned int)(o)))
106
107#define v3_writew(o,v) __raw_writew(v, PCI_V3_VADDR + (unsigned int)(o))
108#define v3_readw(o) (__raw_readw(PCI_V3_VADDR + (unsigned int)(o)))
109
110#define v3_writel(o,v) __raw_writel(v, PCI_V3_VADDR + (unsigned int)(o))
111#define v3_readl(o) (__raw_readl(PCI_V3_VADDR + (unsigned int)(o)))
112
113/*============================================================================
114 *
115 * routine: uHALir_PCIMakeConfigAddress()
116 *
117 * parameters: bus = which bus
118 * device = which device
119 * function = which function
120 * offset = configuration space register we are interested in
121 *
122 * description: this routine will generate a platform dependent config
123 * address.
124 *
125 * calls: none
126 *
127 * returns: configuration address to play on the PCI bus
128 *
129 * To generate the appropriate PCI configuration cycles in the PCI
130 * configuration address space, you present the V3 with the following pattern
131 * (which is very nearly a type 1 (except that the lower two bits are 00 and
132 * not 01). In order for this mapping to work you need to set up one of
133 * the local to PCI aperatures to 16Mbytes in length translating to
134 * PCI configuration space starting at 0x0000.0000.
135 *
136 * PCI configuration cycles look like this:
137 *
138 * Type 0:
139 *
140 * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
141 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
142 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
143 * | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0|
144 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
145 *
146 * 31:11 Device select bit.
147 * 10:8 Function number
148 * 7:2 Register number
149 *
150 * Type 1:
151 *
152 * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
153 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
154 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
155 * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
156 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
157 *
158 * 31:24 reserved
159 * 23:16 bus number (8 bits = 128 possible buses)
160 * 15:11 Device number (5 bits)
161 * 10:8 function number
162 * 7:2 register number
163 *
164 */
165static DEFINE_SPINLOCK(v3_lock);
166
167#define PCI_BUS_NONMEM_START 0x00000000
168#define PCI_BUS_NONMEM_SIZE SZ_256M
169
170#define PCI_BUS_PREMEM_START PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE
171#define PCI_BUS_PREMEM_SIZE SZ_256M
172
173#if PCI_BUS_NONMEM_START & 0x000fffff
174#error PCI_BUS_NONMEM_START must be megabyte aligned
175#endif
176#if PCI_BUS_PREMEM_START & 0x000fffff
177#error PCI_BUS_PREMEM_START must be megabyte aligned
178#endif
179
180#undef V3_LB_BASE_PREFETCH
181#define V3_LB_BASE_PREFETCH 0
182
183static unsigned long v3_open_config_window(struct pci_bus *bus,
184 unsigned int devfn, int offset)
185{
186 unsigned int address, mapaddress, busnr;
187
188 busnr = bus->number;
189
190 /*
191 * Trap out illegal values
192 */
193 if (offset > 255)
194 BUG();
195 if (busnr > 255)
196 BUG();
197 if (devfn > 255)
198 BUG();
199
200 if (busnr == 0) {
201 int slot = PCI_SLOT(devfn);
202
203 /*
204 * local bus segment so need a type 0 config cycle
205 *
206 * build the PCI configuration "address" with one-hot in
207 * A31-A11
208 *
209 * mapaddress:
210 * 3:1 = config cycle (101)
211 * 0 = PCI A1 & A0 are 0 (0)
212 */
213 address = PCI_FUNC(devfn) << 8;
214 mapaddress = V3_LB_MAP_TYPE_CONFIG;
215
216 if (slot > 12)
217 /*
218 * high order bits are handled by the MAP register
219 */
220 mapaddress |= 1 << (slot - 5);
221 else
222 /*
223 * low order bits handled directly in the address
224 */
225 address |= 1 << (slot + 11);
226 } else {
227 /*
228 * not the local bus segment so need a type 1 config cycle
229 *
230 * address:
231 * 23:16 = bus number
232 * 15:11 = slot number (7:3 of devfn)
233 * 10:8 = func number (2:0 of devfn)
234 *
235 * mapaddress:
236 * 3:1 = config cycle (101)
237 * 0 = PCI A1 & A0 from host bus (1)
238 */
239 mapaddress = V3_LB_MAP_TYPE_CONFIG | V3_LB_MAP_AD_LOW_EN;
240 address = (busnr << 16) | (devfn << 8);
241 }
242
243 /*
244 * Set up base0 to see all 512Mbytes of memory space (not
245 * prefetchable), this frees up base1 for re-use by
246 * configuration memory
247 */
248 v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
249 V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE);
250
251 /*
252 * Set up base1/map1 to point into configuration space.
253 */
254 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_CONFIG_BASE) |
255 V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE);
256 v3_writew(V3_LB_MAP1, mapaddress);
257
258 return PCI_CONFIG_VADDR + address + offset;
259}
260
261static void v3_close_config_window(void)
262{
263 /*
264 * Reassign base1 for use by prefetchable PCI memory
265 */
266 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) |
267 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
268 V3_LB_BASE_ENABLE);
269 v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) |
270 V3_LB_MAP_TYPE_MEM_MULTIPLE);
271
272 /*
273 * And shrink base0 back to a 256M window (NOTE: MAP0 already correct)
274 */
275 v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
276 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
277}
278
279static int v3_read_config(struct pci_bus *bus, unsigned int devfn, int where,
280 int size, u32 *val)
281{
282 unsigned long addr;
283 unsigned long flags;
284 u32 v;
285
286 spin_lock_irqsave(&v3_lock, flags);
287 addr = v3_open_config_window(bus, devfn, where);
288
289 switch (size) {
290 case 1:
291 v = __raw_readb(addr);
292 break;
293
294 case 2:
295 v = __raw_readw(addr);
296 break;
297
298 default:
299 v = __raw_readl(addr);
300 break;
301 }
302
303 v3_close_config_window();
304 spin_unlock_irqrestore(&v3_lock, flags);
305
306 *val = v;
307 return PCIBIOS_SUCCESSFUL;
308}
309
310static int v3_write_config(struct pci_bus *bus, unsigned int devfn, int where,
311 int size, u32 val)
312{
313 unsigned long addr;
314 unsigned long flags;
315
316 spin_lock_irqsave(&v3_lock, flags);
317 addr = v3_open_config_window(bus, devfn, where);
318
319 switch (size) {
320 case 1:
321 __raw_writeb((u8)val, addr);
322 __raw_readb(addr);
323 break;
324
325 case 2:
326 __raw_writew((u16)val, addr);
327 __raw_readw(addr);
328 break;
329
330 case 4:
331 __raw_writel(val, addr);
332 __raw_readl(addr);
333 break;
334 }
335
336 v3_close_config_window();
337 spin_unlock_irqrestore(&v3_lock, flags);
338
339 return PCIBIOS_SUCCESSFUL;
340}
341
342static struct pci_ops pci_v3_ops = {
343 .read = v3_read_config,
344 .write = v3_write_config,
345};
346
347static struct resource non_mem = {
348 .name = "PCI non-prefetchable",
349 .start = PHYS_PCI_MEM_BASE + PCI_BUS_NONMEM_START,
350 .end = PHYS_PCI_MEM_BASE + PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE - 1,
351 .flags = IORESOURCE_MEM,
352};
353
354static struct resource pre_mem = {
355 .name = "PCI prefetchable",
356 .start = PHYS_PCI_MEM_BASE + PCI_BUS_PREMEM_START,
357 .end = PHYS_PCI_MEM_BASE + PCI_BUS_PREMEM_START + PCI_BUS_PREMEM_SIZE - 1,
358 .flags = IORESOURCE_MEM | IORESOURCE_PREFETCH,
359};
360
361static int __init pci_v3_setup_resources(struct resource **resource)
362{
363 if (request_resource(&iomem_resource, &non_mem)) {
364 printk(KERN_ERR "PCI: unable to allocate non-prefetchable "
365 "memory region\n");
366 return -EBUSY;
367 }
368 if (request_resource(&iomem_resource, &pre_mem)) {
369 release_resource(&non_mem);
370 printk(KERN_ERR "PCI: unable to allocate prefetchable "
371 "memory region\n");
372 return -EBUSY;
373 }
374
375 /*
376 * bus->resource[0] is the IO resource for this bus
377 * bus->resource[1] is the mem resource for this bus
378 * bus->resource[2] is the prefetch mem resource for this bus
379 */
380 resource[0] = &ioport_resource;
381 resource[1] = &non_mem;
382 resource[2] = &pre_mem;
383
384 return 1;
385}
386
387/*
388 * These don't seem to be implemented on the Integrator I have, which
389 * means I can't get additional information on the reason for the pm2fb
390 * problems. I suppose I'll just have to mind-meld with the machine. ;)
391 */
392#define SC_PCI (IO_ADDRESS(INTEGRATOR_SC_BASE) + INTEGRATOR_SC_PCIENABLE_OFFSET)
393#define SC_LBFADDR (IO_ADDRESS(INTEGRATOR_SC_BASE) + 0x20)
394#define SC_LBFCODE (IO_ADDRESS(INTEGRATOR_SC_BASE) + 0x24)
395
396static int
397v3_pci_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
398{
399 unsigned long pc = instruction_pointer(regs);
400 unsigned long instr = *(unsigned long *)pc;
401#if 0
402 char buf[128];
403
404 sprintf(buf, "V3 fault: addr 0x%08lx, FSR 0x%03x, PC 0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x ISTAT=%02x\n",
405 addr, fsr, pc, instr, __raw_readl(SC_LBFADDR), __raw_readl(SC_LBFCODE) & 255,
406 v3_readb(V3_LB_ISTAT));
407 printk(KERN_DEBUG "%s", buf);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700408#endif
409
410 v3_writeb(V3_LB_ISTAT, 0);
411 __raw_writel(3, SC_PCI);
412
413 /*
414 * If the instruction being executed was a read,
415 * make it look like it read all-ones.
416 */
417 if ((instr & 0x0c100000) == 0x04100000) {
418 int reg = (instr >> 12) & 15;
419 unsigned long val;
420
421 if (instr & 0x00400000)
422 val = 255;
423 else
424 val = -1;
425
426 regs->uregs[reg] = val;
427 regs->ARM_pc += 4;
428 return 0;
429 }
430
431 if ((instr & 0x0e100090) == 0x00100090) {
432 int reg = (instr >> 12) & 15;
433
434 regs->uregs[reg] = -1;
435 regs->ARM_pc += 4;
436 return 0;
437 }
438
439 return 1;
440}
441
Jeff Garzike8f2af12007-10-26 05:40:25 -0400442static irqreturn_t v3_irq(int dummy, void *devid)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700443{
444#ifdef CONFIG_DEBUG_LL
Linus Torvalds0cd61b62006-10-06 10:53:39 -0700445 struct pt_regs *regs = get_irq_regs();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700446 unsigned long pc = instruction_pointer(regs);
447 unsigned long instr = *(unsigned long *)pc;
448 char buf[128];
Russell King7c284722008-05-23 19:35:52 +0100449 extern void printascii(const char *);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700450
Jeff Garzike8f2af12007-10-26 05:40:25 -0400451 sprintf(buf, "V3 int %d: pc=0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x "
452 "ISTAT=%02x\n", IRQ_AP_V3INT, pc, instr,
453 __raw_readl(SC_LBFADDR),
454 __raw_readl(SC_LBFCODE) & 255,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700455 v3_readb(V3_LB_ISTAT));
456 printascii(buf);
457#endif
458
459 v3_writew(V3_PCI_STAT, 0xf000);
460 v3_writeb(V3_LB_ISTAT, 0);
461 __raw_writel(3, SC_PCI);
462
463#ifdef CONFIG_DEBUG_LL
464 /*
465 * If the instruction being executed was a read,
466 * make it look like it read all-ones.
467 */
468 if ((instr & 0x0c100000) == 0x04100000) {
469 int reg = (instr >> 16) & 15;
470 sprintf(buf, " reg%d = %08lx\n", reg, regs->uregs[reg]);
471 printascii(buf);
472 }
473#endif
474 return IRQ_HANDLED;
475}
476
477int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
478{
479 int ret = 0;
480
481 if (nr == 0) {
482 sys->mem_offset = PHYS_PCI_MEM_BASE;
483 ret = pci_v3_setup_resources(sys->resource);
484 }
485
486 return ret;
487}
488
489struct pci_bus *pci_v3_scan_bus(int nr, struct pci_sys_data *sys)
490{
491 return pci_scan_bus(sys->busnr, &pci_v3_ops, sys);
492}
493
494/*
495 * V3_LB_BASE? - local bus address
496 * V3_LB_MAP? - pci bus address
497 */
498void __init pci_v3_preinit(void)
499{
500 unsigned long flags;
501 unsigned int temp;
502 int ret;
503
504 /*
505 * Hook in our fault handler for PCI errors
506 */
507 hook_fault_code(4, v3_pci_fault, SIGBUS, "external abort on linefetch");
508 hook_fault_code(6, v3_pci_fault, SIGBUS, "external abort on linefetch");
509 hook_fault_code(8, v3_pci_fault, SIGBUS, "external abort on non-linefetch");
510 hook_fault_code(10, v3_pci_fault, SIGBUS, "external abort on non-linefetch");
511
512 spin_lock_irqsave(&v3_lock, flags);
513
514 /*
515 * Unlock V3 registers, but only if they were previously locked.
516 */
517 if (v3_readw(V3_SYSTEM) & V3_SYSTEM_M_LOCK)
518 v3_writew(V3_SYSTEM, 0xa05f);
519
520 /*
521 * Setup window 0 - PCI non-prefetchable memory
522 * Local: 0x40000000 Bus: 0x00000000 Size: 256MB
523 */
524 v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
525 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
526 v3_writew(V3_LB_MAP0, v3_addr_to_lb_map(PCI_BUS_NONMEM_START) |
527 V3_LB_MAP_TYPE_MEM);
528
529 /*
530 * Setup window 1 - PCI prefetchable memory
531 * Local: 0x50000000 Bus: 0x10000000 Size: 256MB
532 */
533 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) |
534 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
535 V3_LB_BASE_ENABLE);
536 v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) |
537 V3_LB_MAP_TYPE_MEM_MULTIPLE);
538
539 /*
540 * Setup window 2 - PCI IO
541 */
542 v3_writel(V3_LB_BASE2, v3_addr_to_lb_base2(PHYS_PCI_IO_BASE) |
543 V3_LB_BASE_ENABLE);
544 v3_writew(V3_LB_MAP2, v3_addr_to_lb_map2(0));
545
546 /*
547 * Disable PCI to host IO cycles
548 */
549 temp = v3_readw(V3_PCI_CFG) & ~V3_PCI_CFG_M_I2O_EN;
550 temp |= V3_PCI_CFG_M_IO_REG_DIS | V3_PCI_CFG_M_IO_DIS;
551 v3_writew(V3_PCI_CFG, temp);
552
553 printk(KERN_DEBUG "FIFO_CFG: %04x FIFO_PRIO: %04x\n",
554 v3_readw(V3_FIFO_CFG), v3_readw(V3_FIFO_PRIORITY));
555
556 /*
557 * Set the V3 FIFO such that writes have higher priority than
558 * reads, and local bus write causes local bus read fifo flush.
559 * Same for PCI.
560 */
561 v3_writew(V3_FIFO_PRIORITY, 0x0a0a);
562
563 /*
564 * Re-lock the system register.
565 */
566 temp = v3_readw(V3_SYSTEM) | V3_SYSTEM_M_LOCK;
567 v3_writew(V3_SYSTEM, temp);
568
569 /*
570 * Clear any error conditions, and enable write errors.
571 */
572 v3_writeb(V3_LB_ISTAT, 0);
573 v3_writew(V3_LB_CFG, v3_readw(V3_LB_CFG) | (1 << 10));
574 v3_writeb(V3_LB_IMASK, 0x28);
575 __raw_writel(3, SC_PCI);
576
577 /*
578 * Grab the PCI error interrupt.
579 */
580 ret = request_irq(IRQ_AP_V3INT, v3_irq, 0, "V3", NULL);
581 if (ret)
582 printk(KERN_ERR "PCI: unable to grab PCI error "
583 "interrupt: %d\n", ret);
584
585 spin_unlock_irqrestore(&v3_lock, flags);
586}
587
588void __init pci_v3_postinit(void)
589{
590 unsigned int pci_cmd;
591
592 pci_cmd = PCI_COMMAND_MEMORY |
593 PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
594
595 v3_writew(V3_PCI_CMD, pci_cmd);
596
597 v3_writeb(V3_LB_ISTAT, ~0x40);
598 v3_writeb(V3_LB_IMASK, 0x68);
599
600#if 0
601 ret = request_irq(IRQ_AP_LBUSTIMEOUT, lb_timeout, 0, "bus timeout", NULL);
602 if (ret)
603 printk(KERN_ERR "PCI: unable to grab local bus timeout "
604 "interrupt: %d\n", ret);
605#endif
Russell King863dab42006-08-28 12:47:05 +0100606
607 register_isa_ports(PHYS_PCI_MEM_BASE, PHYS_PCI_IO_BASE, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700608}