| Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * arch/arm/mach-ixp4xx/include/mach/ixdp425.h |
| 3 | * |
| 4 | * IXDP425 platform specific definitions |
| 5 | * |
| 6 | * Author: Deepak Saxena <dsaxena@plexity.net> |
| 7 | * |
| 8 | * Copyright 2004 (c) MontaVista, Software, Inc. |
| 9 | * |
| 10 | * This file is licensed under the terms of the GNU General Public |
| 11 | * License version 2. This program is licensed "as is" without any |
| 12 | * warranty of any kind, whether express or implied. |
| 13 | */ |
| 14 | |
| 15 | #ifndef __ASM_ARCH_HARDWARE_H__ |
| 16 | #error "Do not include this directly, instead #include <mach/hardware.h>" |
| 17 | #endif |
| 18 | |
| 19 | #define IXDP425_SDA_PIN 7 |
| 20 | #define IXDP425_SCL_PIN 6 |
| 21 | |
| 22 | /* |
| 23 | * IXDP425 PCI IRQs |
| 24 | */ |
| 25 | #define IXDP425_PCI_MAX_DEV 4 |
| 26 | #define IXDP425_PCI_IRQ_LINES 4 |
| 27 | |
| 28 | |
| 29 | /* PCI controller GPIO to IRQ pin mappings */ |
| 30 | #define IXDP425_PCI_INTA_PIN 11 |
| 31 | #define IXDP425_PCI_INTB_PIN 10 |
| 32 | #define IXDP425_PCI_INTC_PIN 9 |
| 33 | #define IXDP425_PCI_INTD_PIN 8 |
| 34 | |
| 35 | /* NAND Flash pins */ |
| 36 | #define IXDP425_NAND_NCE_PIN 12 |
| 37 | |
| 38 | #define IXDP425_NAND_CMD_BYTE 0x01 |
| 39 | #define IXDP425_NAND_ADDR_BYTE 0x02 |