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Ben Dooks3a38e4b2008-01-28 13:01:34 +01001/* linux/arch/arm/plat-s3c24xx/s3c24xx-clock.c
2 *
3 * Copyright (c) 2004-2005,2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C2440/S3C2442 Common clock support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*/
23
24#include <linux/init.h>
25#include <linux/module.h>
26#include <linux/kernel.h>
27#include <linux/list.h>
28#include <linux/errno.h>
29#include <linux/err.h>
30#include <linux/device.h>
31#include <linux/sysdev.h>
32#include <linux/interrupt.h>
33#include <linux/ioport.h>
34#include <linux/mutex.h>
35#include <linux/clk.h>
36
Russell Kinga09e64f2008-08-05 16:14:15 +010037#include <mach/hardware.h>
Ben Dooks3a38e4b2008-01-28 13:01:34 +010038#include <asm/atomic.h>
39#include <asm/irq.h>
40#include <asm/io.h>
41
Russell Kinga09e64f2008-08-05 16:14:15 +010042#include <mach/regs-clock.h>
Ben Dooks3a38e4b2008-01-28 13:01:34 +010043
44#include <asm/plat-s3c24xx/clock.h>
45#include <asm/plat-s3c24xx/cpu.h>
46
Ben Dooks06dbbd62008-01-28 13:01:35 +010047static int s3c2440_setparent_armclk(struct clk *clk, struct clk *parent)
48{
49 unsigned long camdivn;
50 unsigned long dvs;
51
52 if (parent == &clk_f)
53 dvs = 0;
54 else if (parent == &clk_h)
55 dvs = S3C2440_CAMDIVN_DVSEN;
56 else
57 return -EINVAL;
58
59 clk->parent = parent;
60
61 camdivn = __raw_readl(S3C2440_CAMDIVN);
62 camdivn &= ~S3C2440_CAMDIVN_DVSEN;
63 camdivn |= dvs;
64 __raw_writel(camdivn, S3C2440_CAMDIVN);
65
66 return 0;
67}
68
69static struct clk clk_arm = {
70 .name = "armclk",
71 .id = -1,
72 .set_parent = s3c2440_setparent_armclk,
73};
74
Ben Dooks3a38e4b2008-01-28 13:01:34 +010075static int s3c244x_clk_add(struct sys_device *sysdev)
76{
77 unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
78 unsigned long clkdivn;
79 struct clk *clock_upll;
Ben Dooks06dbbd62008-01-28 13:01:35 +010080 int ret;
Ben Dooks3a38e4b2008-01-28 13:01:34 +010081
82 printk("S3C244X: Clock Support, DVS %s\n",
83 (camdivn & S3C2440_CAMDIVN_DVSEN) ? "on" : "off");
84
Ben Dooks06dbbd62008-01-28 13:01:35 +010085 clk_arm.parent = (camdivn & S3C2440_CAMDIVN_DVSEN) ? &clk_h : &clk_f;
86
87 ret = s3c24xx_register_clock(&clk_arm);
88 if (ret < 0) {
89 printk(KERN_ERR "S3C24XX: Failed to add armclk (%d)\n", ret);
90 return ret;
91 }
92
Ben Dooks3a38e4b2008-01-28 13:01:34 +010093 clock_upll = clk_get(NULL, "upll");
94 if (IS_ERR(clock_upll)) {
95 printk(KERN_ERR "S3C244X: Failed to get upll clock\n");
96 return -ENOENT;
97 }
98
99 /* check rate of UPLL, and if it is near 96MHz, then change
100 * to using half the UPLL rate for the system */
101
102 if (clk_get_rate(clock_upll) > (94 * MHZ)) {
103 clk_usb_bus.rate = clk_get_rate(clock_upll) / 2;
104
105 mutex_lock(&clocks_mutex);
106
107 clkdivn = __raw_readl(S3C2410_CLKDIVN);
108 clkdivn |= S3C2440_CLKDIVN_UCLK;
109 __raw_writel(clkdivn, S3C2410_CLKDIVN);
110
111 mutex_unlock(&clocks_mutex);
112 }
113
114 return 0;
115}
116
117static struct sysdev_driver s3c2440_clk_driver = {
118 .add = s3c244x_clk_add,
119};
120
121static int s3c2440_clk_init(void)
122{
123 return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_clk_driver);
124}
125
126arch_initcall(s3c2440_clk_init);
127
128static struct sysdev_driver s3c2442_clk_driver = {
129 .add = s3c244x_clk_add,
130};
131
132static int s3c2442_clk_init(void)
133{
134 return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_clk_driver);
135}
136
137arch_initcall(s3c2442_clk_init);