Lennert Buytenhek | 1d81eed | 2006-06-24 10:33:02 +0100 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/mach-ep93xx/clock.c |
| 3 | * Clock control for Cirrus EP93xx chips. |
| 4 | * |
| 5 | * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or (at |
| 10 | * your option) any later version. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/kernel.h> |
| 14 | #include <linux/clk.h> |
| 15 | #include <linux/err.h> |
Lennert Buytenhek | 51dd249 | 2007-02-04 22:45:33 +0100 | [diff] [blame] | 16 | #include <linux/module.h> |
Lennert Buytenhek | 1d81eed | 2006-06-24 10:33:02 +0100 | [diff] [blame] | 17 | #include <linux/string.h> |
| 18 | #include <asm/div64.h> |
Russell King | be50972 | 2008-08-04 10:41:28 +0100 | [diff] [blame] | 19 | #include <asm/arch/hardware.h> |
Lennert Buytenhek | 1d81eed | 2006-06-24 10:33:02 +0100 | [diff] [blame] | 20 | #include <asm/io.h> |
| 21 | |
| 22 | struct clk { |
| 23 | char *name; |
| 24 | unsigned long rate; |
| 25 | int users; |
| 26 | u32 enable_reg; |
| 27 | u32 enable_mask; |
| 28 | }; |
| 29 | |
Russell King | ed519de | 2007-04-22 12:30:41 +0100 | [diff] [blame] | 30 | static struct clk clk_uart = { |
| 31 | .name = "UARTCLK", |
| 32 | .rate = 14745600, |
| 33 | }; |
Lennert Buytenhek | 1d81eed | 2006-06-24 10:33:02 +0100 | [diff] [blame] | 34 | static struct clk clk_pll1 = { |
| 35 | .name = "pll1", |
| 36 | }; |
| 37 | static struct clk clk_f = { |
| 38 | .name = "fclk", |
| 39 | }; |
| 40 | static struct clk clk_h = { |
| 41 | .name = "hclk", |
| 42 | }; |
| 43 | static struct clk clk_p = { |
| 44 | .name = "pclk", |
| 45 | }; |
| 46 | static struct clk clk_pll2 = { |
| 47 | .name = "pll2", |
| 48 | }; |
| 49 | static struct clk clk_usb_host = { |
| 50 | .name = "usb_host", |
| 51 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, |
| 52 | .enable_mask = EP93XX_SYSCON_CLOCK_USH_EN, |
| 53 | }; |
| 54 | |
| 55 | |
| 56 | static struct clk *clocks[] = { |
Russell King | ed519de | 2007-04-22 12:30:41 +0100 | [diff] [blame] | 57 | &clk_uart, |
Lennert Buytenhek | 1d81eed | 2006-06-24 10:33:02 +0100 | [diff] [blame] | 58 | &clk_pll1, |
| 59 | &clk_f, |
| 60 | &clk_h, |
| 61 | &clk_p, |
| 62 | &clk_pll2, |
| 63 | &clk_usb_host, |
| 64 | }; |
| 65 | |
| 66 | struct clk *clk_get(struct device *dev, const char *id) |
| 67 | { |
| 68 | int i; |
| 69 | |
| 70 | for (i = 0; i < ARRAY_SIZE(clocks); i++) { |
| 71 | if (!strcmp(clocks[i]->name, id)) |
| 72 | return clocks[i]; |
| 73 | } |
| 74 | |
| 75 | return ERR_PTR(-ENOENT); |
| 76 | } |
Dmitry Baryshkov | 0c5d5b7 | 2008-07-10 14:44:23 +0100 | [diff] [blame] | 77 | EXPORT_SYMBOL(clk_get); |
Lennert Buytenhek | 1d81eed | 2006-06-24 10:33:02 +0100 | [diff] [blame] | 78 | |
| 79 | int clk_enable(struct clk *clk) |
| 80 | { |
| 81 | if (!clk->users++ && clk->enable_reg) { |
| 82 | u32 value; |
| 83 | |
| 84 | value = __raw_readl(clk->enable_reg); |
| 85 | __raw_writel(value | clk->enable_mask, clk->enable_reg); |
| 86 | } |
| 87 | |
| 88 | return 0; |
| 89 | } |
Dmitry Baryshkov | 0c5d5b7 | 2008-07-10 14:44:23 +0100 | [diff] [blame] | 90 | EXPORT_SYMBOL(clk_enable); |
Lennert Buytenhek | 1d81eed | 2006-06-24 10:33:02 +0100 | [diff] [blame] | 91 | |
| 92 | void clk_disable(struct clk *clk) |
| 93 | { |
| 94 | if (!--clk->users && clk->enable_reg) { |
| 95 | u32 value; |
| 96 | |
| 97 | value = __raw_readl(clk->enable_reg); |
| 98 | __raw_writel(value & ~clk->enable_mask, clk->enable_reg); |
| 99 | } |
| 100 | } |
Dmitry Baryshkov | 0c5d5b7 | 2008-07-10 14:44:23 +0100 | [diff] [blame] | 101 | EXPORT_SYMBOL(clk_disable); |
Lennert Buytenhek | 1d81eed | 2006-06-24 10:33:02 +0100 | [diff] [blame] | 102 | |
| 103 | unsigned long clk_get_rate(struct clk *clk) |
| 104 | { |
| 105 | return clk->rate; |
| 106 | } |
Dmitry Baryshkov | 0c5d5b7 | 2008-07-10 14:44:23 +0100 | [diff] [blame] | 107 | EXPORT_SYMBOL(clk_get_rate); |
Lennert Buytenhek | 1d81eed | 2006-06-24 10:33:02 +0100 | [diff] [blame] | 108 | |
| 109 | void clk_put(struct clk *clk) |
| 110 | { |
| 111 | } |
Dmitry Baryshkov | 0c5d5b7 | 2008-07-10 14:44:23 +0100 | [diff] [blame] | 112 | EXPORT_SYMBOL(clk_put); |
Lennert Buytenhek | 1d81eed | 2006-06-24 10:33:02 +0100 | [diff] [blame] | 113 | |
| 114 | |
| 115 | |
| 116 | static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 }; |
| 117 | static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 }; |
| 118 | static char pclk_divisors[] = { 1, 2, 4, 8 }; |
| 119 | |
| 120 | /* |
| 121 | * PLL rate = 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^PS |
| 122 | */ |
| 123 | static unsigned long calc_pll_rate(u32 config_word) |
| 124 | { |
| 125 | unsigned long long rate; |
| 126 | int i; |
| 127 | |
| 128 | rate = 14745600; |
| 129 | rate *= ((config_word >> 11) & 0x1f) + 1; /* X1FBD */ |
| 130 | rate *= ((config_word >> 5) & 0x3f) + 1; /* X2FBD */ |
| 131 | do_div(rate, (config_word & 0x1f) + 1); /* X2IPD */ |
| 132 | for (i = 0; i < ((config_word >> 16) & 3); i++) /* PS */ |
| 133 | rate >>= 1; |
| 134 | |
| 135 | return (unsigned long)rate; |
| 136 | } |
| 137 | |
Lennert Buytenhek | 51dd249 | 2007-02-04 22:45:33 +0100 | [diff] [blame] | 138 | static int __init ep93xx_clock_init(void) |
Lennert Buytenhek | 1d81eed | 2006-06-24 10:33:02 +0100 | [diff] [blame] | 139 | { |
| 140 | u32 value; |
| 141 | |
| 142 | value = __raw_readl(EP93XX_SYSCON_CLOCK_SET1); |
| 143 | if (!(value & 0x00800000)) { /* PLL1 bypassed? */ |
| 144 | clk_pll1.rate = 14745600; |
| 145 | } else { |
| 146 | clk_pll1.rate = calc_pll_rate(value); |
| 147 | } |
| 148 | clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7]; |
| 149 | clk_h.rate = clk_pll1.rate / hclk_divisors[(value >> 20) & 0x7]; |
| 150 | clk_p.rate = clk_h.rate / pclk_divisors[(value >> 18) & 0x3]; |
| 151 | |
| 152 | value = __raw_readl(EP93XX_SYSCON_CLOCK_SET2); |
| 153 | if (!(value & 0x00080000)) { /* PLL2 bypassed? */ |
| 154 | clk_pll2.rate = 14745600; |
| 155 | } else if (value & 0x00040000) { /* PLL2 enabled? */ |
| 156 | clk_pll2.rate = calc_pll_rate(value); |
| 157 | } else { |
| 158 | clk_pll2.rate = 0; |
| 159 | } |
| 160 | clk_usb_host.rate = clk_pll2.rate / (((value >> 28) & 0xf) + 1); |
| 161 | |
| 162 | printk(KERN_INFO "ep93xx: PLL1 running at %ld MHz, PLL2 at %ld MHz\n", |
| 163 | clk_pll1.rate / 1000000, clk_pll2.rate / 1000000); |
| 164 | printk(KERN_INFO "ep93xx: FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n", |
| 165 | clk_f.rate / 1000000, clk_h.rate / 1000000, |
| 166 | clk_p.rate / 1000000); |
Lennert Buytenhek | 51dd249 | 2007-02-04 22:45:33 +0100 | [diff] [blame] | 167 | |
| 168 | return 0; |
Lennert Buytenhek | 1d81eed | 2006-06-24 10:33:02 +0100 | [diff] [blame] | 169 | } |
Lennert Buytenhek | 51dd249 | 2007-02-04 22:45:33 +0100 | [diff] [blame] | 170 | arch_initcall(ep93xx_clock_init); |