| Andrew Victor | 6171de8 | 2006-11-30 14:34:53 +0100 | [diff] [blame] | 1 | /* |
| Andrew Victor | 9d04126 | 2007-02-05 11:42:07 +0100 | [diff] [blame] | 2 | * include/asm-arm/arch-at91/at91_aic.h |
| Andrew Victor | 6171de8 | 2006-11-30 14:34:53 +0100 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2005 Ivan Kokshaysky |
| 5 | * Copyright (C) SAN People |
| 6 | * |
| 7 | * Advanced Interrupt Controller (AIC) - System peripherals registers. |
| 8 | * Based on AT91RM9200 datasheet revision E. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; either version 2 of the License, or |
| 13 | * (at your option) any later version. |
| 14 | */ |
| 15 | |
| 16 | #ifndef AT91_AIC_H |
| 17 | #define AT91_AIC_H |
| 18 | |
| 19 | #define AT91_AIC_SMR(n) (AT91_AIC + ((n) * 4)) /* Source Mode Registers 0-31 */ |
| 20 | #define AT91_AIC_PRIOR (7 << 0) /* Priority Level */ |
| 21 | #define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */ |
| 22 | #define AT91_AIC_SRCTYPE_LOW (0 << 5) |
| 23 | #define AT91_AIC_SRCTYPE_FALLING (1 << 5) |
| 24 | #define AT91_AIC_SRCTYPE_HIGH (2 << 5) |
| 25 | #define AT91_AIC_SRCTYPE_RISING (3 << 5) |
| 26 | |
| 27 | #define AT91_AIC_SVR(n) (AT91_AIC + 0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */ |
| 28 | #define AT91_AIC_IVR (AT91_AIC + 0x100) /* Interrupt Vector Register */ |
| 29 | #define AT91_AIC_FVR (AT91_AIC + 0x104) /* Fast Interrupt Vector Register */ |
| 30 | #define AT91_AIC_ISR (AT91_AIC + 0x108) /* Interrupt Status Register */ |
| 31 | #define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */ |
| 32 | |
| 33 | #define AT91_AIC_IPR (AT91_AIC + 0x10c) /* Interrupt Pending Register */ |
| 34 | #define AT91_AIC_IMR (AT91_AIC + 0x110) /* Interrupt Mask Register */ |
| 35 | #define AT91_AIC_CISR (AT91_AIC + 0x114) /* Core Interrupt Status Register */ |
| 36 | #define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */ |
| 37 | #define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */ |
| 38 | |
| 39 | #define AT91_AIC_IECR (AT91_AIC + 0x120) /* Interrupt Enable Command Register */ |
| 40 | #define AT91_AIC_IDCR (AT91_AIC + 0x124) /* Interrupt Disable Command Register */ |
| 41 | #define AT91_AIC_ICCR (AT91_AIC + 0x128) /* Interrupt Clear Command Register */ |
| 42 | #define AT91_AIC_ISCR (AT91_AIC + 0x12c) /* Interrupt Set Command Register */ |
| 43 | #define AT91_AIC_EOICR (AT91_AIC + 0x130) /* End of Interrupt Command Register */ |
| 44 | #define AT91_AIC_SPU (AT91_AIC + 0x134) /* Spurious Interrupt Vector Register */ |
| 45 | #define AT91_AIC_DCR (AT91_AIC + 0x138) /* Debug Control Register */ |
| 46 | #define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */ |
| 47 | #define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */ |
| 48 | |
| 49 | #define AT91_AIC_FFER (AT91_AIC + 0x140) /* Fast Forcing Enable Register [SAM9 only] */ |
| 50 | #define AT91_AIC_FFDR (AT91_AIC + 0x144) /* Fast Forcing Disable Register [SAM9 only] */ |
| 51 | #define AT91_AIC_FFSR (AT91_AIC + 0x148) /* Fast Forcing Status Register [SAM9 only] */ |
| 52 | |
| 53 | #endif |