| SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 1 | /* |
| Andrew Victor | 9d04126 | 2007-02-05 11:42:07 +0100 | [diff] [blame] | 2 | * include/asm-arm/arch-at91/debug-macro.S |
| SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2003-2005 SAN People |
| 5 | * |
| 6 | * Debugging macro include header |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | * |
| 12 | */ |
| 13 | |
| Russell King | be50972 | 2008-08-04 10:41:28 +0100 | [diff] [blame] | 14 | #include <asm/arch/hardware.h> |
| Andrew Victor | 55d8bae | 2006-11-30 17:16:43 +0100 | [diff] [blame] | 15 | #include <asm/arch/at91_dbgu.h> |
| SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 16 | |
| 17 | .macro addruart,rx |
| 18 | mrc p15, 0, \rx, c1, c0 |
| Andrew Victor | d0760b3 | 2007-02-08 09:00:39 +0100 | [diff] [blame] | 19 | tst \rx, #1 @ MMU enabled? |
| 20 | ldreq \rx, =(AT91_BASE_SYS + AT91_DBGU) @ System peripherals (phys address) |
| 21 | ldrne \rx, =(AT91_VA_BASE_SYS + AT91_DBGU) @ System peripherals (virt address) |
| SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 22 | .endm |
| 23 | |
| 24 | .macro senduart,rd,rx |
| Andrew Victor | d0760b3 | 2007-02-08 09:00:39 +0100 | [diff] [blame] | 25 | strb \rd, [\rx, #(AT91_DBGU_THR - AT91_DBGU)] @ Write to Transmitter Holding Register |
| SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 26 | .endm |
| 27 | |
| 28 | .macro waituart,rd,rx |
| Andrew Victor | d0760b3 | 2007-02-08 09:00:39 +0100 | [diff] [blame] | 29 | 1001: ldr \rd, [\rx, #(AT91_DBGU_SR - AT91_DBGU)] @ Read Status Register |
| 30 | tst \rd, #AT91_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmit |
| SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 31 | beq 1001b |
| 32 | .endm |
| 33 | |
| 34 | .macro busyuart,rd,rx |
| Andrew Victor | d0760b3 | 2007-02-08 09:00:39 +0100 | [diff] [blame] | 35 | 1001: ldr \rd, [\rx, #(AT91_DBGU_SR - AT91_DBGU)] @ Read Status Register |
| 36 | tst \rd, #AT91_DBGU_TXEMPTY @ DBGU_TXEMPTY = 1 when transmission complete |
| SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 37 | beq 1001b |
| 38 | .endm |
| 39 | |