| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * include/asm-arm/arch-h720x/entry-macro.S |
| 3 | * |
| 4 | * Low-level IRQ helper macros for Hynix HMS720x based platforms |
| 5 | * |
| 6 | * This file is licensed under the terms of the GNU General Public |
| 7 | * License version 2. This program is licensed "as is" without any |
| 8 | * warranty of any kind, whether express or implied. |
| 9 | */ |
| 10 | |
| 11 | .macro disable_fiq |
| 12 | .endm |
| 13 | |
| Dan Williams | f80dff9 | 2007-02-16 22:16:32 +0100 | [diff] [blame] | 14 | .macro get_irqnr_preamble, base, tmp |
| 15 | .endm |
| 16 | |
| 17 | .macro arch_ret_to_user, tmp1, tmp2 |
| 18 | .endm |
| 19 | |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 20 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp |
| 21 | #if defined (CONFIG_CPU_H7201) || defined (CONFIG_CPU_H7202) |
| 22 | @ we could use the id register on H7202, but this is not |
| 23 | @ properly updated when we come back from asm_do_irq |
| 24 | @ without a previous return from interrupt |
| 25 | @ (see loops below in irq_svc, irq_usr) |
| 26 | @ We see unmasked pending ints only, as the masked pending ints |
| 27 | @ are not visible here |
| 28 | |
| 29 | mov \base, #0xf0000000 @ base register |
| 30 | orr \base, \base, #0x24000 @ irqbase |
| 31 | ldr \irqstat, [\base, #0x04] @ get interrupt status |
| 32 | #if defined (CONFIG_CPU_H7201) |
| 33 | ldr \tmp, =0x001fffff |
| 34 | #else |
| 35 | mvn \tmp, #0xc0000000 |
| 36 | #endif |
| 37 | and \irqstat, \irqstat, \tmp @ mask out unused ints |
| 38 | mov \irqnr, #0 |
| 39 | |
| 40 | mov \tmp, #0xff00 |
| 41 | orr \tmp, \tmp, #0xff |
| 42 | tst \irqstat, \tmp |
| 43 | addeq \irqnr, \irqnr, #16 |
| 44 | moveq \irqstat, \irqstat, lsr #16 |
| 45 | tst \irqstat, #255 |
| 46 | addeq \irqnr, \irqnr, #8 |
| 47 | moveq \irqstat, \irqstat, lsr #8 |
| 48 | tst \irqstat, #15 |
| 49 | addeq \irqnr, \irqnr, #4 |
| 50 | moveq \irqstat, \irqstat, lsr #4 |
| 51 | tst \irqstat, #3 |
| 52 | addeq \irqnr, \irqnr, #2 |
| 53 | moveq \irqstat, \irqstat, lsr #2 |
| 54 | tst \irqstat, #1 |
| 55 | addeq \irqnr, \irqnr, #1 |
| 56 | moveq \irqstat, \irqstat, lsr #1 |
| 57 | tst \irqstat, #1 @ bit 0 should be set |
| 58 | .endm |
| 59 | |
| 60 | .macro irq_prio_table |
| 61 | .endm |
| 62 | |
| 63 | #else |
| 64 | #error hynix processor selection missmatch |
| 65 | #endif |
| 66 | |