| Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 1 | /* |
| 2 | * include/asm-arm/arch-realview/entry-macro.S |
| 3 | * |
| 4 | * Low-level IRQ helper macros for RealView platforms |
| 5 | * |
| 6 | * This file is licensed under the terms of the GNU General Public |
| 7 | * License version 2. This program is licensed "as is" without any |
| 8 | * warranty of any kind, whether express or implied. |
| 9 | */ |
| Russell King | be50972 | 2008-08-04 10:41:28 +0100 | [diff] [blame] | 10 | #include <asm/arch/hardware.h> |
| Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 11 | #include <asm/hardware/gic.h> |
| 12 | |
| 13 | .macro disable_fiq |
| 14 | .endm |
| 15 | |
| Dan Williams | f80dff9 | 2007-02-16 22:16:32 +0100 | [diff] [blame] | 16 | .macro get_irqnr_preamble, base, tmp |
| Catalin Marinas | c4057f5 | 2008-02-04 17:41:01 +0100 | [diff] [blame] | 17 | ldr \base, =gic_cpu_base_addr |
| 18 | ldr \base, [\base] |
| Dan Williams | f80dff9 | 2007-02-16 22:16:32 +0100 | [diff] [blame] | 19 | .endm |
| 20 | |
| 21 | .macro arch_ret_to_user, tmp1, tmp2 |
| 22 | .endm |
| 23 | |
| Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 24 | /* |
| 25 | * The interrupt numbering scheme is defined in the |
| 26 | * interrupt controller spec. To wit: |
| 27 | * |
| 28 | * Interrupts 0-15 are IPI |
| 29 | * 16-28 are reserved |
| 30 | * 29-31 are local. We allow 30 to be used for the watchdog. |
| 31 | * 32-1020 are global |
| 32 | * 1021-1022 are reserved |
| 33 | * 1023 is "spurious" (no interrupt) |
| 34 | * |
| 35 | * For now, we ignore all local interrupts so only return an interrupt if it's |
| 36 | * between 30 and 1020. The test_for_ipi routine below will pick up on IPIs. |
| 37 | * |
| 38 | * A simple read from the controller will tell us the number of the highest |
| 39 | * priority enabled interrupt. We then just need to check whether it is in the |
| 40 | * valid range for an IRQ (30-1020 inclusive). |
| 41 | */ |
| 42 | |
| 43 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp |
| 44 | |
| Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 45 | ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */ |
| 46 | |
| 47 | ldr \tmp, =1021 |
| 48 | |
| 49 | bic \irqnr, \irqstat, #0x1c00 |
| 50 | |
| 51 | cmp \irqnr, #29 |
| 52 | cmpcc \irqnr, \irqnr |
| 53 | cmpne \irqnr, \tmp |
| 54 | cmpcs \irqnr, \irqnr |
| 55 | |
| 56 | .endm |
| Russell King | 862184f | 2005-11-07 21:05:42 +0000 | [diff] [blame] | 57 | |
| 58 | /* We assume that irqstat (the raw value of the IRQ acknowledge |
| 59 | * register) is preserved from the macro above. |
| 60 | * If there is an IPI, we immediately signal end of interrupt on the |
| 61 | * controller, since this requires the original irqstat value which |
| 62 | * we won't easily be able to recreate later. |
| 63 | */ |
| 64 | |
| 65 | .macro test_for_ipi, irqnr, irqstat, base, tmp |
| 66 | bic \irqnr, \irqstat, #0x1c00 |
| 67 | cmp \irqnr, #16 |
| 68 | strcc \irqstat, [\base, #GIC_CPU_EOI] |
| 69 | cmpcs \irqnr, \irqnr |
| 70 | .endm |
| Russell King | 2a98beb | 2005-11-09 10:50:29 +0000 | [diff] [blame] | 71 | |
| 72 | /* As above, this assumes that irqstat and base are preserved.. */ |
| 73 | |
| 74 | .macro test_for_ltirq, irqnr, irqstat, base, tmp |
| 75 | bic \irqnr, \irqstat, #0x1c00 |
| 76 | mov \tmp, #0 |
| 77 | cmp \irqnr, #29 |
| 78 | moveq \tmp, #1 |
| 79 | streq \irqstat, [\base, #GIC_CPU_EOI] |
| 80 | cmp \tmp, #0 |
| 81 | .endm |