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Catalin Marinasbbe88882007-05-08 22:27:46 +01001/*
2 * linux/arch/arm/mm/cache-v7.S
3 *
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 * Copyright (C) 2005 ARM Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This is the "shell" of the ARMv7 processor support.
12 */
13#include <linux/linkage.h>
14#include <linux/init.h>
15#include <asm/assembler.h>
Catalin Marinas32cfb1b2009-10-06 17:57:09 +010016#include <asm/unwind.h>
Catalin Marinasbbe88882007-05-08 22:27:46 +010017
18#include "proc-macros.S"
19
20/*
Tony Lindgren81d11952010-09-21 17:16:40 +010021 * v7_flush_icache_all()
22 *
23 * Flush the whole I-cache.
24 *
25 * Registers:
26 * r0 - set to 0
27 */
28ENTRY(v7_flush_icache_all)
29 mov r0, #0
30 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable
31 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate
32 mov pc, lr
33ENDPROC(v7_flush_icache_all)
34
35/*
Catalin Marinasbbe88882007-05-08 22:27:46 +010036 * v7_flush_dcache_all()
37 *
38 * Flush the whole D-cache.
39 *
Catalin Marinas347c8b72009-07-24 12:32:56 +010040 * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
Catalin Marinasbbe88882007-05-08 22:27:46 +010041 *
42 * - mm - mm_struct describing address space
43 */
44ENTRY(v7_flush_dcache_all)
Catalin Marinasc30c2f92008-11-06 13:23:07 +000045 dmb @ ensure ordering with previous memory accesses
Catalin Marinasbbe88882007-05-08 22:27:46 +010046 mrc p15, 1, r0, c0, c0, 1 @ read clidr
47 ands r3, r0, #0x7000000 @ extract loc from clidr
48 mov r3, r3, lsr #23 @ left align loc bit field
49 beq finished @ if loc is 0, then no need to clean
50 mov r10, #0 @ start clean at cache level 0
51loop1:
52 add r2, r10, r10, lsr #1 @ work out 3x current cache level
53 mov r1, r0, lsr r2 @ extract cache type bits from clidr
54 and r1, r1, #7 @ mask of the bits for current cache only
55 cmp r1, #2 @ see what cache we have at this level
56 blt skip @ skip if no cache, or just i-cache
57 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
58 isb @ isb to sych the new cssr&csidr
59 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
60 and r2, r1, #7 @ extract the length of the cache lines
61 add r2, r2, #4 @ add 4 (line length offset)
62 ldr r4, =0x3ff
63 ands r4, r4, r1, lsr #3 @ find maximum number on the way size
64 clz r5, r4 @ find bit position of way size increment
65 ldr r7, =0x7fff
66 ands r7, r7, r1, lsr #13 @ extract max number of the index size
67loop2:
68 mov r9, r4 @ create working copy of max way size
69loop3:
Catalin Marinas347c8b72009-07-24 12:32:56 +010070 ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11
71 THUMB( lsl r6, r9, r5 )
72 THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
73 ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11
74 THUMB( lsl r6, r7, r2 )
75 THUMB( orr r11, r11, r6 ) @ factor index number into r11
Catalin Marinasbbe88882007-05-08 22:27:46 +010076 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
77 subs r9, r9, #1 @ decrement the way
78 bge loop3
79 subs r7, r7, #1 @ decrement the index
80 bge loop2
81skip:
82 add r10, r10, #2 @ increment cache number
83 cmp r3, r10
84 bgt loop1
85finished:
86 mov r10, #0 @ swith back to cache level 0
87 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
Catalin Marinasc30c2f92008-11-06 13:23:07 +000088 dsb
Catalin Marinasbbe88882007-05-08 22:27:46 +010089 isb
90 mov pc, lr
Catalin Marinas93ed3972008-08-28 11:22:32 +010091ENDPROC(v7_flush_dcache_all)
Catalin Marinasbbe88882007-05-08 22:27:46 +010092
93/*
94 * v7_flush_cache_all()
95 *
96 * Flush the entire cache system.
97 * The data cache flush is now achieved using atomic clean / invalidates
98 * working outwards from L1 cache. This is done using Set/Way based cache
Lucas De Marchi25985ed2011-03-30 22:57:33 -030099 * maintenance instructions.
Catalin Marinasbbe88882007-05-08 22:27:46 +0100100 * The instruction cache can still be invalidated back to the point of
101 * unification in a single instruction.
102 *
103 */
104ENTRY(v7_flush_kern_cache_all)
Catalin Marinas347c8b72009-07-24 12:32:56 +0100105 ARM( stmfd sp!, {r4-r5, r7, r9-r11, lr} )
106 THUMB( stmfd sp!, {r4-r7, r9-r11, lr} )
Catalin Marinasbbe88882007-05-08 22:27:46 +0100107 bl v7_flush_dcache_all
108 mov r0, #0
Russell Kingf00ec482010-09-04 10:47:48 +0100109 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable
110 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate
Catalin Marinas347c8b72009-07-24 12:32:56 +0100111 ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} )
112 THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} )
Catalin Marinasbbe88882007-05-08 22:27:46 +0100113 mov pc, lr
Catalin Marinas93ed3972008-08-28 11:22:32 +0100114ENDPROC(v7_flush_kern_cache_all)
Catalin Marinasbbe88882007-05-08 22:27:46 +0100115
116/*
117 * v7_flush_cache_all()
118 *
119 * Flush all TLB entries in a particular address space
120 *
121 * - mm - mm_struct describing address space
122 */
123ENTRY(v7_flush_user_cache_all)
124 /*FALLTHROUGH*/
125
126/*
127 * v7_flush_cache_range(start, end, flags)
128 *
129 * Flush a range of TLB entries in the specified address space.
130 *
131 * - start - start address (may not be aligned)
132 * - end - end address (exclusive, may not be aligned)
133 * - flags - vm_area_struct flags describing address space
134 *
135 * It is assumed that:
136 * - we have a VIPT cache.
137 */
138ENTRY(v7_flush_user_cache_range)
139 mov pc, lr
Catalin Marinas93ed3972008-08-28 11:22:32 +0100140ENDPROC(v7_flush_user_cache_all)
141ENDPROC(v7_flush_user_cache_range)
Catalin Marinasbbe88882007-05-08 22:27:46 +0100142
143/*
144 * v7_coherent_kern_range(start,end)
145 *
146 * Ensure that the I and D caches are coherent within specified
147 * region. This is typically used when code has been written to
148 * a memory region, and will be executed.
149 *
150 * - start - virtual start address of region
151 * - end - virtual end address of region
152 *
153 * It is assumed that:
154 * - the Icache does not read data from the write buffer
155 */
156ENTRY(v7_coherent_kern_range)
157 /* FALLTHROUGH */
158
159/*
160 * v7_coherent_user_range(start,end)
161 *
162 * Ensure that the I and D caches are coherent within specified
163 * region. This is typically used when code has been written to
164 * a memory region, and will be executed.
165 *
166 * - start - virtual start address of region
167 * - end - virtual end address of region
168 *
169 * It is assumed that:
170 * - the Icache does not read data from the write buffer
171 */
172ENTRY(v7_coherent_user_range)
Catalin Marinas32cfb1b2009-10-06 17:57:09 +0100173 UNWIND(.fnstart )
Catalin Marinasbbe88882007-05-08 22:27:46 +0100174 dcache_line_size r2, r3
175 sub r3, r2, #1
Catalin Marinasda30e0a2010-12-07 16:56:29 +0100176 bic r12, r0, r3
Catalin Marinas32cfb1b2009-10-06 17:57:09 +01001771:
Catalin Marinasda30e0a2010-12-07 16:56:29 +0100178 USER( mcr p15, 0, r12, c7, c11, 1 ) @ clean D line to the point of unification
179 add r12, r12, r2
180 cmp r12, r1
Catalin Marinasbbe88882007-05-08 22:27:46 +0100181 blo 1b
Catalin Marinasda30e0a2010-12-07 16:56:29 +0100182 dsb
183 icache_line_size r2, r3
184 sub r3, r2, #1
185 bic r12, r0, r3
1862:
187 USER( mcr p15, 0, r12, c7, c5, 1 ) @ invalidate I line
188 add r12, r12, r2
189 cmp r12, r1
190 blo 2b
1913:
Catalin Marinasbbe88882007-05-08 22:27:46 +0100192 mov r0, #0
Russell Kingf00ec482010-09-04 10:47:48 +0100193 ALT_SMP(mcr p15, 0, r0, c7, c1, 6) @ invalidate BTB Inner Shareable
194 ALT_UP(mcr p15, 0, r0, c7, c5, 6) @ invalidate BTB
Catalin Marinasbbe88882007-05-08 22:27:46 +0100195 dsb
196 isb
197 mov pc, lr
Catalin Marinas32cfb1b2009-10-06 17:57:09 +0100198
199/*
200 * Fault handling for the cache operation above. If the virtual address in r0
201 * isn't mapped, just try the next page.
202 */
2039001:
Catalin Marinasda30e0a2010-12-07 16:56:29 +0100204 mov r12, r12, lsr #12
205 mov r12, r12, lsl #12
206 add r12, r12, #4096
207 b 3b
Catalin Marinas32cfb1b2009-10-06 17:57:09 +0100208 UNWIND(.fnend )
Catalin Marinas93ed3972008-08-28 11:22:32 +0100209ENDPROC(v7_coherent_kern_range)
210ENDPROC(v7_coherent_user_range)
Catalin Marinasbbe88882007-05-08 22:27:46 +0100211
212/*
Russell King2c9b9c82009-11-26 12:56:21 +0000213 * v7_flush_kern_dcache_area(void *addr, size_t size)
Catalin Marinasbbe88882007-05-08 22:27:46 +0100214 *
215 * Ensure that the data held in the page kaddr is written back
216 * to the page in question.
217 *
Russell King2c9b9c82009-11-26 12:56:21 +0000218 * - addr - kernel address
219 * - size - region size
Catalin Marinasbbe88882007-05-08 22:27:46 +0100220 */
Russell King2c9b9c82009-11-26 12:56:21 +0000221ENTRY(v7_flush_kern_dcache_area)
Catalin Marinasbbe88882007-05-08 22:27:46 +0100222 dcache_line_size r2, r3
Russell King2c9b9c82009-11-26 12:56:21 +0000223 add r1, r0, r1
Will Deacona248b132011-05-26 11:20:19 +0100224 sub r3, r2, #1
225 bic r0, r0, r3
Catalin Marinasbbe88882007-05-08 22:27:46 +01002261:
227 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line / unified line
228 add r0, r0, r2
229 cmp r0, r1
230 blo 1b
231 dsb
232 mov pc, lr
Russell King2c9b9c82009-11-26 12:56:21 +0000233ENDPROC(v7_flush_kern_dcache_area)
Catalin Marinasbbe88882007-05-08 22:27:46 +0100234
235/*
236 * v7_dma_inv_range(start,end)
237 *
238 * Invalidate the data cache within the specified region; we will
239 * be performing a DMA operation in this region and we want to
240 * purge old data in the cache.
241 *
242 * - start - virtual start address of region
243 * - end - virtual end address of region
244 */
Russell King702b94b2009-11-26 16:24:19 +0000245v7_dma_inv_range:
Catalin Marinasbbe88882007-05-08 22:27:46 +0100246 dcache_line_size r2, r3
247 sub r3, r2, #1
248 tst r0, r3
249 bic r0, r0, r3
250 mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line
251
252 tst r1, r3
253 bic r1, r1, r3
254 mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D / U line
2551:
256 mcr p15, 0, r0, c7, c6, 1 @ invalidate D / U line
257 add r0, r0, r2
258 cmp r0, r1
259 blo 1b
260 dsb
261 mov pc, lr
Catalin Marinas93ed3972008-08-28 11:22:32 +0100262ENDPROC(v7_dma_inv_range)
Catalin Marinasbbe88882007-05-08 22:27:46 +0100263
264/*
265 * v7_dma_clean_range(start,end)
266 * - start - virtual start address of region
267 * - end - virtual end address of region
268 */
Russell King702b94b2009-11-26 16:24:19 +0000269v7_dma_clean_range:
Catalin Marinasbbe88882007-05-08 22:27:46 +0100270 dcache_line_size r2, r3
271 sub r3, r2, #1
272 bic r0, r0, r3
2731:
274 mcr p15, 0, r0, c7, c10, 1 @ clean D / U line
275 add r0, r0, r2
276 cmp r0, r1
277 blo 1b
278 dsb
279 mov pc, lr
Catalin Marinas93ed3972008-08-28 11:22:32 +0100280ENDPROC(v7_dma_clean_range)
Catalin Marinasbbe88882007-05-08 22:27:46 +0100281
282/*
283 * v7_dma_flush_range(start,end)
284 * - start - virtual start address of region
285 * - end - virtual end address of region
286 */
287ENTRY(v7_dma_flush_range)
288 dcache_line_size r2, r3
289 sub r3, r2, #1
290 bic r0, r0, r3
2911:
292 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line
293 add r0, r0, r2
294 cmp r0, r1
295 blo 1b
296 dsb
297 mov pc, lr
Catalin Marinas93ed3972008-08-28 11:22:32 +0100298ENDPROC(v7_dma_flush_range)
Catalin Marinasbbe88882007-05-08 22:27:46 +0100299
Russell Kinga9c91472009-11-26 16:19:58 +0000300/*
301 * dma_map_area(start, size, dir)
302 * - start - kernel virtual start address
303 * - size - size of region
304 * - dir - DMA direction
305 */
306ENTRY(v7_dma_map_area)
307 add r1, r1, r0
Russell King2ffe2da2009-10-31 16:52:16 +0000308 teq r2, #DMA_FROM_DEVICE
309 beq v7_dma_inv_range
310 b v7_dma_clean_range
Russell Kinga9c91472009-11-26 16:19:58 +0000311ENDPROC(v7_dma_map_area)
312
313/*
314 * dma_unmap_area(start, size, dir)
315 * - start - kernel virtual start address
316 * - size - size of region
317 * - dir - DMA direction
318 */
319ENTRY(v7_dma_unmap_area)
Russell King2ffe2da2009-10-31 16:52:16 +0000320 add r1, r1, r0
321 teq r2, #DMA_TO_DEVICE
322 bne v7_dma_inv_range
Russell Kinga9c91472009-11-26 16:19:58 +0000323 mov pc, lr
324ENDPROC(v7_dma_unmap_area)
325
Catalin Marinasbbe88882007-05-08 22:27:46 +0100326 __INITDATA
327
328 .type v7_cache_fns, #object
329ENTRY(v7_cache_fns)
Tony Lindgren81d11952010-09-21 17:16:40 +0100330 .long v7_flush_icache_all
Catalin Marinasbbe88882007-05-08 22:27:46 +0100331 .long v7_flush_kern_cache_all
332 .long v7_flush_user_cache_all
333 .long v7_flush_user_cache_range
334 .long v7_coherent_kern_range
335 .long v7_coherent_user_range
Russell King2c9b9c82009-11-26 12:56:21 +0000336 .long v7_flush_kern_dcache_area
Russell Kinga9c91472009-11-26 16:19:58 +0000337 .long v7_dma_map_area
338 .long v7_dma_unmap_area
Catalin Marinasbbe88882007-05-08 22:27:46 +0100339 .long v7_dma_flush_range
340 .size v7_cache_fns, . - v7_cache_fns