blob: fb90a3004e985059d56a1ace75ea6bb267934607 [file] [log] [blame]
Kukjin Kima2e0d622010-10-18 18:29:51 +09001/* linux/arch/arm/mach-s5p64x0/cpu.c
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/interrupt.h>
14#include <linux/list.h>
15#include <linux/timer.h>
16#include <linux/init.h>
17#include <linux/clk.h>
18#include <linux/io.h>
19#include <linux/sysdev.h>
20#include <linux/serial_core.h>
21#include <linux/platform_device.h>
22
23#include <asm/mach/arch.h>
24#include <asm/mach/map.h>
25#include <asm/mach/irq.h>
26#include <asm/proc-fns.h>
27#include <asm/irq.h>
28
29#include <mach/hardware.h>
30#include <mach/map.h>
31#include <mach/regs-clock.h>
32
33#include <plat/regs-serial.h>
34#include <plat/cpu.h>
35#include <plat/devs.h>
36#include <plat/clock.h>
37#include <plat/s5p6440.h>
38#include <plat/s5p6450.h>
39#include <plat/adc-core.h>
40
41/* Initial IO mappings */
42
43static struct map_desc s5p64x0_iodesc[] __initdata = {
44 {
45 .virtual = (unsigned long)S5P_VA_GPIO,
46 .pfn = __phys_to_pfn(S5P64X0_PA_GPIO),
47 .length = SZ_4K,
48 .type = MT_DEVICE,
49 }, {
50 .virtual = (unsigned long)VA_VIC0,
51 .pfn = __phys_to_pfn(S5P64X0_PA_VIC0),
52 .length = SZ_16K,
53 .type = MT_DEVICE,
54 }, {
55 .virtual = (unsigned long)VA_VIC1,
56 .pfn = __phys_to_pfn(S5P64X0_PA_VIC1),
57 .length = SZ_16K,
58 .type = MT_DEVICE,
59 },
60};
61
62static struct map_desc s5p6440_iodesc[] __initdata = {
63 {
64 .virtual = (unsigned long)S3C_VA_UART,
65 .pfn = __phys_to_pfn(S5P6440_PA_UART(0)),
66 .length = SZ_4K,
67 .type = MT_DEVICE,
68 },
69};
70
71static struct map_desc s5p6450_iodesc[] __initdata = {
72 {
73 .virtual = (unsigned long)S3C_VA_UART,
74 .pfn = __phys_to_pfn(S5P6450_PA_UART(0)),
75 .length = SZ_512K,
76 .type = MT_DEVICE,
77 }, {
78 .virtual = (unsigned long)S3C_VA_UART + SZ_512K,
79 .pfn = __phys_to_pfn(S5P6450_PA_UART(5)),
80 .length = SZ_4K,
81 .type = MT_DEVICE,
82 },
83};
84
85static void s5p64x0_idle(void)
86{
87 unsigned long val;
88
89 if (!need_resched()) {
90 val = __raw_readl(S5P64X0_PWR_CFG);
91 val &= ~(0x3 << 5);
92 val |= (0x1 << 5);
93 __raw_writel(val, S5P64X0_PWR_CFG);
94
95 cpu_do_idle();
96 }
97 local_irq_enable();
98}
99
100/*
101 * s5p64x0_map_io
102 *
103 * register the standard CPU IO areas
104 */
105
106void __init s5p6440_map_io(void)
107{
108 /* initialize any device information early */
109 s3c_adc_setname("s3c64x0-adc");
110
111 iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
112 iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
113}
114
115void __init s5p6450_map_io(void)
116{
117 /* initialize any device information early */
118 s3c_adc_setname("s3c64x0-adc");
119
120 iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
121 iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6440_iodesc));
122}
123
124/*
125 * s5p64x0_init_clocks
126 *
127 * register and setup the CPU clocks
128 */
129
130void __init s5p6440_init_clocks(int xtal)
131{
132 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
133
134 s3c24xx_register_baseclocks(xtal);
135 s5p_register_clocks(xtal);
136 s5p6440_register_clocks();
137 s5p6440_setup_clocks();
138}
139
140void __init s5p6450_init_clocks(int xtal)
141{
142 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
143
144 s3c24xx_register_baseclocks(xtal);
145 s5p_register_clocks(xtal);
146 s5p6450_register_clocks();
147 s5p6450_setup_clocks();
148}
149
150/*
151 * s5p64x0_init_irq
152 *
153 * register the CPU interrupts
154 */
155
156void __init s5p6440_init_irq(void)
157{
158 /* S5P6440 supports 2 VIC */
159 u32 vic[2];
160
161 /*
162 * VIC0 is missing IRQ_VIC0[3, 4, 8, 10, (12-22)]
163 * VIC1 is missing IRQ VIC1[1, 3, 4, 10, 11, 12, 14, 15, 22]
164 */
165 vic[0] = 0xff800ae7;
166 vic[1] = 0xffbf23e5;
167
168 s5p_init_irq(vic, ARRAY_SIZE(vic));
169}
170
171void __init s5p6450_init_irq(void)
172{
173 /* S5P6450 supports only 2 VIC */
174 u32 vic[2];
175
176 /*
177 * VIC0 is missing IRQ_VIC0[(13-15), (21-22)]
178 * VIC1 is missing IRQ VIC1[12, 14, 23]
179 */
180 vic[0] = 0xff9f1fff;
181 vic[1] = 0xff7fafff;
182
183 s5p_init_irq(vic, ARRAY_SIZE(vic));
184}
185
186struct sysdev_class s5p64x0_sysclass = {
187 .name = "s5p64x0-core",
188};
189
190static struct sys_device s5p64x0_sysdev = {
191 .cls = &s5p64x0_sysclass,
192};
193
194static int __init s5p64x0_core_init(void)
195{
196 return sysdev_class_register(&s5p64x0_sysclass);
197}
198core_initcall(s5p64x0_core_init);
199
200int __init s5p64x0_init(void)
201{
202 printk(KERN_INFO "S5P64X0(S5P6440/S5P6450): Initializing architecture\n");
203
204 /* set idle function */
205 pm_idle = s5p64x0_idle;
206
207 return sysdev_register(&s5p64x0_sysdev);
208}