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Linus Torvalds1da177e2005-04-16 15:20:36 -07001#ifndef __ASM_CPU_SH3_DMA_H
2#define __ASM_CPU_SH3_DMA_H
3
Yoshihiro Shimoda31a49c42007-12-26 11:45:06 +09004#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
Nobuhiro Iwamatsu71b973a2009-03-10 17:26:49 +09005 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
6 defined(CONFIG_CPU_SUBTYPE_SH7710) || \
7 defined(CONFIG_CPU_SUBTYPE_SH7712)
8#define SH_DMAC_BASE0 0xa4010020
9#else /* SH7705/06/07/09 */
10#define SH_DMAC_BASE0 0xa4000020
Steve Glendinningcdf7da82008-05-06 11:36:27 +010011#endif
Markus Brunner3ea6bc32007-08-20 08:59:33 +090012
13#define DMTE0_IRQ 48
Markus Brunner3ea6bc32007-08-20 08:59:33 +090014#define DMTE4_IRQ 76
Linus Torvalds1da177e2005-04-16 15:20:36 -070015
Paul Mundt0d831772006-01-16 22:14:09 -080016/* Definitions for the SuperH DMAC */
17#define TM_BURST 0x00000020
18#define TS_8 0x00000000
19#define TS_16 0x00000008
20#define TS_32 0x00000010
21#define TS_128 0x00000018
Linus Torvalds1da177e2005-04-16 15:20:36 -070022
Paul Mundt0d831772006-01-16 22:14:09 -080023#endif /* __ASM_CPU_SH3_DMA_H */