Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1 | /******************************************************************************* |
| 2 | |
| 3 | Intel PRO/1000 Linux driver |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 4 | Copyright(c) 1999 - 2008 Intel Corporation. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5 | |
| 6 | This program is free software; you can redistribute it and/or modify it |
| 7 | under the terms and conditions of the GNU General Public License, |
| 8 | version 2, as published by the Free Software Foundation. |
| 9 | |
| 10 | This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | more details. |
| 14 | |
| 15 | You should have received a copy of the GNU General Public License along with |
| 16 | this program; if not, write to the Free Software Foundation, Inc., |
| 17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
| 18 | |
| 19 | The full GNU General Public License is included in this distribution in |
| 20 | the file called "COPYING". |
| 21 | |
| 22 | Contact Information: |
| 23 | Linux NICS <linux.nics@intel.com> |
| 24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
| 25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 26 | |
| 27 | *******************************************************************************/ |
| 28 | |
| 29 | #include <linux/netdevice.h> |
| 30 | #include <linux/ethtool.h> |
| 31 | #include <linux/delay.h> |
| 32 | #include <linux/pci.h> |
| 33 | |
| 34 | #include "e1000.h" |
| 35 | |
| 36 | enum e1000_mng_mode { |
| 37 | e1000_mng_mode_none = 0, |
| 38 | e1000_mng_mode_asf, |
| 39 | e1000_mng_mode_pt, |
| 40 | e1000_mng_mode_ipmi, |
| 41 | e1000_mng_mode_host_if_only |
| 42 | }; |
| 43 | |
| 44 | #define E1000_FACTPS_MNGCG 0x20000000 |
| 45 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 46 | /* Intel(R) Active Management Technology signature */ |
| 47 | #define E1000_IAMT_SIGNATURE 0x544D4149 |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 48 | |
| 49 | /** |
| 50 | * e1000e_get_bus_info_pcie - Get PCIe bus information |
| 51 | * @hw: pointer to the HW structure |
| 52 | * |
| 53 | * Determines and stores the system bus information for a particular |
| 54 | * network interface. The following bus information is determined and stored: |
| 55 | * bus speed, bus width, type (PCIe), and PCIe function. |
| 56 | **/ |
| 57 | s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw) |
| 58 | { |
| 59 | struct e1000_bus_info *bus = &hw->bus; |
| 60 | struct e1000_adapter *adapter = hw->adapter; |
| 61 | u32 status; |
| 62 | u16 pcie_link_status, pci_header_type, cap_offset; |
| 63 | |
| 64 | cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP); |
| 65 | if (!cap_offset) { |
| 66 | bus->width = e1000_bus_width_unknown; |
| 67 | } else { |
| 68 | pci_read_config_word(adapter->pdev, |
| 69 | cap_offset + PCIE_LINK_STATUS, |
| 70 | &pcie_link_status); |
| 71 | bus->width = (enum e1000_bus_width)((pcie_link_status & |
| 72 | PCIE_LINK_WIDTH_MASK) >> |
| 73 | PCIE_LINK_WIDTH_SHIFT); |
| 74 | } |
| 75 | |
| 76 | pci_read_config_word(adapter->pdev, PCI_HEADER_TYPE_REGISTER, |
| 77 | &pci_header_type); |
| 78 | if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) { |
| 79 | status = er32(STATUS); |
| 80 | bus->func = (status & E1000_STATUS_FUNC_MASK) |
| 81 | >> E1000_STATUS_FUNC_SHIFT; |
| 82 | } else { |
| 83 | bus->func = 0; |
| 84 | } |
| 85 | |
| 86 | return 0; |
| 87 | } |
| 88 | |
| 89 | /** |
| 90 | * e1000e_write_vfta - Write value to VLAN filter table |
| 91 | * @hw: pointer to the HW structure |
| 92 | * @offset: register offset in VLAN filter table |
| 93 | * @value: register value written to VLAN filter table |
| 94 | * |
| 95 | * Writes value at the given offset in the register array which stores |
| 96 | * the VLAN filter table. |
| 97 | **/ |
| 98 | void e1000e_write_vfta(struct e1000_hw *hw, u32 offset, u32 value) |
| 99 | { |
| 100 | E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); |
| 101 | e1e_flush(); |
| 102 | } |
| 103 | |
| 104 | /** |
| 105 | * e1000e_init_rx_addrs - Initialize receive address's |
| 106 | * @hw: pointer to the HW structure |
| 107 | * @rar_count: receive address registers |
| 108 | * |
| 109 | * Setups the receive address registers by setting the base receive address |
| 110 | * register to the devices MAC address and clearing all the other receive |
| 111 | * address registers to 0. |
| 112 | **/ |
| 113 | void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count) |
| 114 | { |
| 115 | u32 i; |
| 116 | |
| 117 | /* Setup the receive address */ |
| 118 | hw_dbg(hw, "Programming MAC Address into RAR[0]\n"); |
| 119 | |
| 120 | e1000e_rar_set(hw, hw->mac.addr, 0); |
| 121 | |
| 122 | /* Zero out the other (rar_entry_count - 1) receive addresses */ |
| 123 | hw_dbg(hw, "Clearing RAR[1-%u]\n", rar_count-1); |
| 124 | for (i = 1; i < rar_count; i++) { |
| 125 | E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1), 0); |
| 126 | e1e_flush(); |
| 127 | E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((i << 1) + 1), 0); |
| 128 | e1e_flush(); |
| 129 | } |
| 130 | } |
| 131 | |
| 132 | /** |
| 133 | * e1000e_rar_set - Set receive address register |
| 134 | * @hw: pointer to the HW structure |
| 135 | * @addr: pointer to the receive address |
| 136 | * @index: receive address array register |
| 137 | * |
| 138 | * Sets the receive address array register at index to the address passed |
| 139 | * in by addr. |
| 140 | **/ |
| 141 | void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index) |
| 142 | { |
| 143 | u32 rar_low, rar_high; |
| 144 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 145 | /* |
| 146 | * HW expects these in little endian so we reverse the byte order |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 147 | * from network order (big endian) to little endian |
| 148 | */ |
| 149 | rar_low = ((u32) addr[0] | |
| 150 | ((u32) addr[1] << 8) | |
| 151 | ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); |
| 152 | |
| 153 | rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); |
| 154 | |
| 155 | rar_high |= E1000_RAH_AV; |
| 156 | |
| 157 | E1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low); |
| 158 | E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high); |
| 159 | } |
| 160 | |
| 161 | /** |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 162 | * e1000_hash_mc_addr - Generate a multicast hash value |
| 163 | * @hw: pointer to the HW structure |
| 164 | * @mc_addr: pointer to a multicast address |
| 165 | * |
| 166 | * Generates a multicast address hash value which is used to determine |
| 167 | * the multicast filter table array address and new table value. See |
| 168 | * e1000_mta_set_generic() |
| 169 | **/ |
| 170 | static u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) |
| 171 | { |
| 172 | u32 hash_value, hash_mask; |
| 173 | u8 bit_shift = 0; |
| 174 | |
| 175 | /* Register count multiplied by bits per register */ |
| 176 | hash_mask = (hw->mac.mta_reg_count * 32) - 1; |
| 177 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 178 | /* |
| 179 | * For a mc_filter_type of 0, bit_shift is the number of left-shifts |
| 180 | * where 0xFF would still fall within the hash mask. |
| 181 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 182 | while (hash_mask >> bit_shift != 0xFF) |
| 183 | bit_shift++; |
| 184 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 185 | /* |
| 186 | * The portion of the address that is used for the hash table |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 187 | * is determined by the mc_filter_type setting. |
| 188 | * The algorithm is such that there is a total of 8 bits of shifting. |
| 189 | * The bit_shift for a mc_filter_type of 0 represents the number of |
| 190 | * left-shifts where the MSB of mc_addr[5] would still fall within |
| 191 | * the hash_mask. Case 0 does this exactly. Since there are a total |
| 192 | * of 8 bits of shifting, then mc_addr[4] will shift right the |
| 193 | * remaining number of bits. Thus 8 - bit_shift. The rest of the |
| 194 | * cases are a variation of this algorithm...essentially raising the |
| 195 | * number of bits to shift mc_addr[5] left, while still keeping the |
| 196 | * 8-bit shifting total. |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 197 | * |
| 198 | * For example, given the following Destination MAC Address and an |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 199 | * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), |
| 200 | * we can see that the bit_shift for case 0 is 4. These are the hash |
| 201 | * values resulting from each mc_filter_type... |
| 202 | * [0] [1] [2] [3] [4] [5] |
| 203 | * 01 AA 00 12 34 56 |
| 204 | * LSB MSB |
| 205 | * |
| 206 | * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 |
| 207 | * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 |
| 208 | * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 |
| 209 | * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 |
| 210 | */ |
| 211 | switch (hw->mac.mc_filter_type) { |
| 212 | default: |
| 213 | case 0: |
| 214 | break; |
| 215 | case 1: |
| 216 | bit_shift += 1; |
| 217 | break; |
| 218 | case 2: |
| 219 | bit_shift += 2; |
| 220 | break; |
| 221 | case 3: |
| 222 | bit_shift += 4; |
| 223 | break; |
| 224 | } |
| 225 | |
| 226 | hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | |
| 227 | (((u16) mc_addr[5]) << bit_shift))); |
| 228 | |
| 229 | return hash_value; |
| 230 | } |
| 231 | |
| 232 | /** |
Jeff Kirsher | e2de3eb | 2008-03-28 09:15:11 -0700 | [diff] [blame] | 233 | * e1000e_update_mc_addr_list_generic - Update Multicast addresses |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 234 | * @hw: pointer to the HW structure |
| 235 | * @mc_addr_list: array of multicast addresses to program |
| 236 | * @mc_addr_count: number of multicast addresses to program |
| 237 | * @rar_used_count: the first RAR register free to program |
| 238 | * @rar_count: total number of supported Receive Address Registers |
| 239 | * |
| 240 | * Updates the Receive Address Registers and Multicast Table Array. |
| 241 | * The caller must have a packed mc_addr_list of multicast addresses. |
| 242 | * The parameter rar_count will usually be hw->mac.rar_entry_count |
| 243 | * unless there are workarounds that change this. |
| 244 | **/ |
Jeff Kirsher | e2de3eb | 2008-03-28 09:15:11 -0700 | [diff] [blame] | 245 | void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw, |
| 246 | u8 *mc_addr_list, u32 mc_addr_count, |
| 247 | u32 rar_used_count, u32 rar_count) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 248 | { |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 249 | u32 i; |
Jesse Brandeburg | a72d2b2 | 2009-03-25 22:05:21 +0000 | [diff] [blame^] | 250 | u32 *mcarray = kzalloc(hw->mac.mta_reg_count * sizeof(u32), GFP_ATOMIC); |
| 251 | |
| 252 | if (!mcarray) { |
| 253 | printk(KERN_ERR "multicast array memory allocation failed\n"); |
| 254 | return; |
| 255 | } |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 256 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 257 | /* |
| 258 | * Load the first set of multicast addresses into the exact |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 259 | * filters (RAR). If there are not enough to fill the RAR |
| 260 | * array, clear the filters. |
| 261 | */ |
| 262 | for (i = rar_used_count; i < rar_count; i++) { |
| 263 | if (mc_addr_count) { |
| 264 | e1000e_rar_set(hw, mc_addr_list, i); |
| 265 | mc_addr_count--; |
| 266 | mc_addr_list += ETH_ALEN; |
| 267 | } else { |
| 268 | E1000_WRITE_REG_ARRAY(hw, E1000_RA, i << 1, 0); |
| 269 | e1e_flush(); |
| 270 | E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1) + 1, 0); |
| 271 | e1e_flush(); |
| 272 | } |
| 273 | } |
| 274 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 275 | /* Load any remaining multicast addresses into the hash table. */ |
| 276 | for (; mc_addr_count > 0; mc_addr_count--) { |
Jesse Brandeburg | a72d2b2 | 2009-03-25 22:05:21 +0000 | [diff] [blame^] | 277 | u32 hash_value, hash_reg, hash_bit, mta; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 278 | hash_value = e1000_hash_mc_addr(hw, mc_addr_list); |
| 279 | hw_dbg(hw, "Hash value = 0x%03X\n", hash_value); |
Jesse Brandeburg | a72d2b2 | 2009-03-25 22:05:21 +0000 | [diff] [blame^] | 280 | hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); |
| 281 | hash_bit = hash_value & 0x1F; |
| 282 | mta = (1 << hash_bit); |
| 283 | mcarray[hash_reg] |= mta; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 284 | mc_addr_list += ETH_ALEN; |
| 285 | } |
Jesse Brandeburg | a72d2b2 | 2009-03-25 22:05:21 +0000 | [diff] [blame^] | 286 | |
| 287 | /* write the hash table completely */ |
| 288 | for (i = 0; i < hw->mac.mta_reg_count; i++) |
| 289 | E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, mcarray[i]); |
| 290 | |
| 291 | e1e_flush(); |
| 292 | kfree(mcarray); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 293 | } |
| 294 | |
| 295 | /** |
| 296 | * e1000e_clear_hw_cntrs_base - Clear base hardware counters |
| 297 | * @hw: pointer to the HW structure |
| 298 | * |
| 299 | * Clears the base hardware counters by reading the counter registers. |
| 300 | **/ |
| 301 | void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw) |
| 302 | { |
| 303 | u32 temp; |
| 304 | |
| 305 | temp = er32(CRCERRS); |
| 306 | temp = er32(SYMERRS); |
| 307 | temp = er32(MPC); |
| 308 | temp = er32(SCC); |
| 309 | temp = er32(ECOL); |
| 310 | temp = er32(MCC); |
| 311 | temp = er32(LATECOL); |
| 312 | temp = er32(COLC); |
| 313 | temp = er32(DC); |
| 314 | temp = er32(SEC); |
| 315 | temp = er32(RLEC); |
| 316 | temp = er32(XONRXC); |
| 317 | temp = er32(XONTXC); |
| 318 | temp = er32(XOFFRXC); |
| 319 | temp = er32(XOFFTXC); |
| 320 | temp = er32(FCRUC); |
| 321 | temp = er32(GPRC); |
| 322 | temp = er32(BPRC); |
| 323 | temp = er32(MPRC); |
| 324 | temp = er32(GPTC); |
| 325 | temp = er32(GORCL); |
| 326 | temp = er32(GORCH); |
| 327 | temp = er32(GOTCL); |
| 328 | temp = er32(GOTCH); |
| 329 | temp = er32(RNBC); |
| 330 | temp = er32(RUC); |
| 331 | temp = er32(RFC); |
| 332 | temp = er32(ROC); |
| 333 | temp = er32(RJC); |
| 334 | temp = er32(TORL); |
| 335 | temp = er32(TORH); |
| 336 | temp = er32(TOTL); |
| 337 | temp = er32(TOTH); |
| 338 | temp = er32(TPR); |
| 339 | temp = er32(TPT); |
| 340 | temp = er32(MPTC); |
| 341 | temp = er32(BPTC); |
| 342 | } |
| 343 | |
| 344 | /** |
| 345 | * e1000e_check_for_copper_link - Check for link (Copper) |
| 346 | * @hw: pointer to the HW structure |
| 347 | * |
| 348 | * Checks to see of the link status of the hardware has changed. If a |
| 349 | * change in link status has been detected, then we read the PHY registers |
| 350 | * to get the current speed/duplex if link exists. |
| 351 | **/ |
| 352 | s32 e1000e_check_for_copper_link(struct e1000_hw *hw) |
| 353 | { |
| 354 | struct e1000_mac_info *mac = &hw->mac; |
| 355 | s32 ret_val; |
| 356 | bool link; |
| 357 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 358 | /* |
| 359 | * We only want to go out to the PHY registers to see if Auto-Neg |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 360 | * has completed and/or if our link status has changed. The |
| 361 | * get_link_status flag is set upon receiving a Link Status |
| 362 | * Change or Rx Sequence Error interrupt. |
| 363 | */ |
| 364 | if (!mac->get_link_status) |
| 365 | return 0; |
| 366 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 367 | /* |
| 368 | * First we want to see if the MII Status Register reports |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 369 | * link. If so, then we want to get the current speed/duplex |
| 370 | * of the PHY. |
| 371 | */ |
| 372 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); |
| 373 | if (ret_val) |
| 374 | return ret_val; |
| 375 | |
| 376 | if (!link) |
| 377 | return ret_val; /* No link detected */ |
| 378 | |
| 379 | mac->get_link_status = 0; |
| 380 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 381 | /* |
| 382 | * Check if there was DownShift, must be checked |
| 383 | * immediately after link-up |
| 384 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 385 | e1000e_check_downshift(hw); |
| 386 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 387 | /* |
| 388 | * If we are forcing speed/duplex, then we simply return since |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 389 | * we have already determined whether we have link or not. |
| 390 | */ |
| 391 | if (!mac->autoneg) { |
| 392 | ret_val = -E1000_ERR_CONFIG; |
| 393 | return ret_val; |
| 394 | } |
| 395 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 396 | /* |
| 397 | * Auto-Neg is enabled. Auto Speed Detection takes care |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 398 | * of MAC speed/duplex configuration. So we only need to |
| 399 | * configure Collision Distance in the MAC. |
| 400 | */ |
| 401 | e1000e_config_collision_dist(hw); |
| 402 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 403 | /* |
| 404 | * Configure Flow Control now that Auto-Neg has completed. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 405 | * First, we need to restore the desired flow control |
| 406 | * settings because we may have had to re-autoneg with a |
| 407 | * different link partner. |
| 408 | */ |
| 409 | ret_val = e1000e_config_fc_after_link_up(hw); |
| 410 | if (ret_val) { |
| 411 | hw_dbg(hw, "Error configuring flow control\n"); |
| 412 | } |
| 413 | |
| 414 | return ret_val; |
| 415 | } |
| 416 | |
| 417 | /** |
| 418 | * e1000e_check_for_fiber_link - Check for link (Fiber) |
| 419 | * @hw: pointer to the HW structure |
| 420 | * |
| 421 | * Checks for link up on the hardware. If link is not up and we have |
| 422 | * a signal, then we need to force link up. |
| 423 | **/ |
| 424 | s32 e1000e_check_for_fiber_link(struct e1000_hw *hw) |
| 425 | { |
| 426 | struct e1000_mac_info *mac = &hw->mac; |
| 427 | u32 rxcw; |
| 428 | u32 ctrl; |
| 429 | u32 status; |
| 430 | s32 ret_val; |
| 431 | |
| 432 | ctrl = er32(CTRL); |
| 433 | status = er32(STATUS); |
| 434 | rxcw = er32(RXCW); |
| 435 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 436 | /* |
| 437 | * If we don't have link (auto-negotiation failed or link partner |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 438 | * cannot auto-negotiate), the cable is plugged in (we have signal), |
| 439 | * and our link partner is not trying to auto-negotiate with us (we |
| 440 | * are receiving idles or data), we need to force link up. We also |
| 441 | * need to give auto-negotiation time to complete, in case the cable |
| 442 | * was just plugged in. The autoneg_failed flag does this. |
| 443 | */ |
| 444 | /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ |
| 445 | if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) && |
| 446 | (!(rxcw & E1000_RXCW_C))) { |
| 447 | if (mac->autoneg_failed == 0) { |
| 448 | mac->autoneg_failed = 1; |
| 449 | return 0; |
| 450 | } |
| 451 | hw_dbg(hw, "NOT RXing /C/, disable AutoNeg and force link.\n"); |
| 452 | |
| 453 | /* Disable auto-negotiation in the TXCW register */ |
| 454 | ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE)); |
| 455 | |
| 456 | /* Force link-up and also force full-duplex. */ |
| 457 | ctrl = er32(CTRL); |
| 458 | ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); |
| 459 | ew32(CTRL, ctrl); |
| 460 | |
| 461 | /* Configure Flow Control after forcing link up. */ |
| 462 | ret_val = e1000e_config_fc_after_link_up(hw); |
| 463 | if (ret_val) { |
| 464 | hw_dbg(hw, "Error configuring flow control\n"); |
| 465 | return ret_val; |
| 466 | } |
| 467 | } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 468 | /* |
| 469 | * If we are forcing link and we are receiving /C/ ordered |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 470 | * sets, re-enable auto-negotiation in the TXCW register |
| 471 | * and disable forced link in the Device Control register |
| 472 | * in an attempt to auto-negotiate with our link partner. |
| 473 | */ |
| 474 | hw_dbg(hw, "RXing /C/, enable AutoNeg and stop forcing link.\n"); |
| 475 | ew32(TXCW, mac->txcw); |
| 476 | ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); |
| 477 | |
Alex Chiang | 612e244 | 2009-02-05 23:55:45 -0800 | [diff] [blame] | 478 | mac->serdes_has_link = true; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 479 | } |
| 480 | |
| 481 | return 0; |
| 482 | } |
| 483 | |
| 484 | /** |
| 485 | * e1000e_check_for_serdes_link - Check for link (Serdes) |
| 486 | * @hw: pointer to the HW structure |
| 487 | * |
| 488 | * Checks for link up on the hardware. If link is not up and we have |
| 489 | * a signal, then we need to force link up. |
| 490 | **/ |
| 491 | s32 e1000e_check_for_serdes_link(struct e1000_hw *hw) |
| 492 | { |
| 493 | struct e1000_mac_info *mac = &hw->mac; |
| 494 | u32 rxcw; |
| 495 | u32 ctrl; |
| 496 | u32 status; |
| 497 | s32 ret_val; |
| 498 | |
| 499 | ctrl = er32(CTRL); |
| 500 | status = er32(STATUS); |
| 501 | rxcw = er32(RXCW); |
| 502 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 503 | /* |
| 504 | * If we don't have link (auto-negotiation failed or link partner |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 505 | * cannot auto-negotiate), and our link partner is not trying to |
| 506 | * auto-negotiate with us (we are receiving idles or data), |
| 507 | * we need to force link up. We also need to give auto-negotiation |
| 508 | * time to complete. |
| 509 | */ |
| 510 | /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ |
| 511 | if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { |
| 512 | if (mac->autoneg_failed == 0) { |
| 513 | mac->autoneg_failed = 1; |
| 514 | return 0; |
| 515 | } |
| 516 | hw_dbg(hw, "NOT RXing /C/, disable AutoNeg and force link.\n"); |
| 517 | |
| 518 | /* Disable auto-negotiation in the TXCW register */ |
| 519 | ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE)); |
| 520 | |
| 521 | /* Force link-up and also force full-duplex. */ |
| 522 | ctrl = er32(CTRL); |
| 523 | ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); |
| 524 | ew32(CTRL, ctrl); |
| 525 | |
| 526 | /* Configure Flow Control after forcing link up. */ |
| 527 | ret_val = e1000e_config_fc_after_link_up(hw); |
| 528 | if (ret_val) { |
| 529 | hw_dbg(hw, "Error configuring flow control\n"); |
| 530 | return ret_val; |
| 531 | } |
| 532 | } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 533 | /* |
| 534 | * If we are forcing link and we are receiving /C/ ordered |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 535 | * sets, re-enable auto-negotiation in the TXCW register |
| 536 | * and disable forced link in the Device Control register |
| 537 | * in an attempt to auto-negotiate with our link partner. |
| 538 | */ |
| 539 | hw_dbg(hw, "RXing /C/, enable AutoNeg and stop forcing link.\n"); |
| 540 | ew32(TXCW, mac->txcw); |
| 541 | ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); |
| 542 | |
Alex Chiang | 612e244 | 2009-02-05 23:55:45 -0800 | [diff] [blame] | 543 | mac->serdes_has_link = true; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 544 | } else if (!(E1000_TXCW_ANE & er32(TXCW))) { |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 545 | /* |
| 546 | * If we force link for non-auto-negotiation switch, check |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 547 | * link status based on MAC synchronization for internal |
| 548 | * serdes media type. |
| 549 | */ |
| 550 | /* SYNCH bit and IV bit are sticky. */ |
| 551 | udelay(10); |
Bruce Allan | 63dcf3d | 2008-11-21 16:50:34 -0800 | [diff] [blame] | 552 | rxcw = er32(RXCW); |
| 553 | if (rxcw & E1000_RXCW_SYNCH) { |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 554 | if (!(rxcw & E1000_RXCW_IV)) { |
Bruce Allan | 63dcf3d | 2008-11-21 16:50:34 -0800 | [diff] [blame] | 555 | mac->serdes_has_link = true; |
| 556 | hw_dbg(hw, "SERDES: Link up - forced.\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 557 | } |
| 558 | } else { |
Bruce Allan | 63dcf3d | 2008-11-21 16:50:34 -0800 | [diff] [blame] | 559 | mac->serdes_has_link = false; |
| 560 | hw_dbg(hw, "SERDES: Link down - force failed.\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 561 | } |
| 562 | } |
| 563 | |
| 564 | if (E1000_TXCW_ANE & er32(TXCW)) { |
| 565 | status = er32(STATUS); |
Bruce Allan | 63dcf3d | 2008-11-21 16:50:34 -0800 | [diff] [blame] | 566 | if (status & E1000_STATUS_LU) { |
| 567 | /* SYNCH bit and IV bit are sticky, so reread rxcw. */ |
| 568 | udelay(10); |
| 569 | rxcw = er32(RXCW); |
| 570 | if (rxcw & E1000_RXCW_SYNCH) { |
| 571 | if (!(rxcw & E1000_RXCW_IV)) { |
| 572 | mac->serdes_has_link = true; |
| 573 | hw_dbg(hw, "SERDES: Link up - autoneg " |
| 574 | "completed sucessfully.\n"); |
| 575 | } else { |
| 576 | mac->serdes_has_link = false; |
| 577 | hw_dbg(hw, "SERDES: Link down - invalid" |
| 578 | "codewords detected in autoneg.\n"); |
| 579 | } |
| 580 | } else { |
| 581 | mac->serdes_has_link = false; |
| 582 | hw_dbg(hw, "SERDES: Link down - no sync.\n"); |
| 583 | } |
| 584 | } else { |
| 585 | mac->serdes_has_link = false; |
| 586 | hw_dbg(hw, "SERDES: Link down - autoneg failed\n"); |
| 587 | } |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 588 | } |
| 589 | |
| 590 | return 0; |
| 591 | } |
| 592 | |
| 593 | /** |
| 594 | * e1000_set_default_fc_generic - Set flow control default values |
| 595 | * @hw: pointer to the HW structure |
| 596 | * |
| 597 | * Read the EEPROM for the default values for flow control and store the |
| 598 | * values. |
| 599 | **/ |
| 600 | static s32 e1000_set_default_fc_generic(struct e1000_hw *hw) |
| 601 | { |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 602 | s32 ret_val; |
| 603 | u16 nvm_data; |
| 604 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 605 | /* |
| 606 | * Read and store word 0x0F of the EEPROM. This word contains bits |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 607 | * that determine the hardware's default PAUSE (flow control) mode, |
| 608 | * a bit that determines whether the HW defaults to enabling or |
| 609 | * disabling auto-negotiation, and the direction of the |
| 610 | * SW defined pins. If there is no SW over-ride of the flow |
| 611 | * control setting, then the variable hw->fc will |
| 612 | * be initialized based on a value in the EEPROM. |
| 613 | */ |
| 614 | ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); |
| 615 | |
| 616 | if (ret_val) { |
| 617 | hw_dbg(hw, "NVM Read Error\n"); |
| 618 | return ret_val; |
| 619 | } |
| 620 | |
| 621 | if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0) |
Bruce Allan | 5c48ef3e2 | 2008-11-21 16:57:36 -0800 | [diff] [blame] | 622 | hw->fc.requested_mode = e1000_fc_none; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 623 | else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == |
| 624 | NVM_WORD0F_ASM_DIR) |
Bruce Allan | 5c48ef3e2 | 2008-11-21 16:57:36 -0800 | [diff] [blame] | 625 | hw->fc.requested_mode = e1000_fc_tx_pause; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 626 | else |
Bruce Allan | 5c48ef3e2 | 2008-11-21 16:57:36 -0800 | [diff] [blame] | 627 | hw->fc.requested_mode = e1000_fc_full; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 628 | |
| 629 | return 0; |
| 630 | } |
| 631 | |
| 632 | /** |
| 633 | * e1000e_setup_link - Setup flow control and link settings |
| 634 | * @hw: pointer to the HW structure |
| 635 | * |
| 636 | * Determines which flow control settings to use, then configures flow |
| 637 | * control. Calls the appropriate media-specific link configuration |
| 638 | * function. Assuming the adapter has a valid link partner, a valid link |
| 639 | * should be established. Assumes the hardware has previously been reset |
| 640 | * and the transmitter and receiver are not enabled. |
| 641 | **/ |
| 642 | s32 e1000e_setup_link(struct e1000_hw *hw) |
| 643 | { |
| 644 | struct e1000_mac_info *mac = &hw->mac; |
| 645 | s32 ret_val; |
| 646 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 647 | /* |
| 648 | * In the case of the phy reset being blocked, we already have a link. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 649 | * We do not need to set it up again. |
| 650 | */ |
| 651 | if (e1000_check_reset_block(hw)) |
| 652 | return 0; |
| 653 | |
Auke Kok | 309af40 | 2007-10-05 15:22:02 -0700 | [diff] [blame] | 654 | /* |
Bruce Allan | 5c48ef3e2 | 2008-11-21 16:57:36 -0800 | [diff] [blame] | 655 | * If requested flow control is set to default, set flow control |
| 656 | * based on the EEPROM flow control settings. |
Auke Kok | 309af40 | 2007-10-05 15:22:02 -0700 | [diff] [blame] | 657 | */ |
Bruce Allan | 5c48ef3e2 | 2008-11-21 16:57:36 -0800 | [diff] [blame] | 658 | if (hw->fc.requested_mode == e1000_fc_default) { |
Auke Kok | 309af40 | 2007-10-05 15:22:02 -0700 | [diff] [blame] | 659 | ret_val = e1000_set_default_fc_generic(hw); |
| 660 | if (ret_val) |
| 661 | return ret_val; |
| 662 | } |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 663 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 664 | /* |
Bruce Allan | 5c48ef3e2 | 2008-11-21 16:57:36 -0800 | [diff] [blame] | 665 | * Save off the requested flow control mode for use later. Depending |
| 666 | * on the link partner's capabilities, we may or may not use this mode. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 667 | */ |
Bruce Allan | 5c48ef3e2 | 2008-11-21 16:57:36 -0800 | [diff] [blame] | 668 | hw->fc.current_mode = hw->fc.requested_mode; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 669 | |
Bruce Allan | 5c48ef3e2 | 2008-11-21 16:57:36 -0800 | [diff] [blame] | 670 | hw_dbg(hw, "After fix-ups FlowControl is now = %x\n", |
| 671 | hw->fc.current_mode); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 672 | |
| 673 | /* Call the necessary media_type subroutine to configure the link. */ |
| 674 | ret_val = mac->ops.setup_physical_interface(hw); |
| 675 | if (ret_val) |
| 676 | return ret_val; |
| 677 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 678 | /* |
| 679 | * Initialize the flow control address, type, and PAUSE timer |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 680 | * registers to their default values. This is done even if flow |
| 681 | * control is disabled, because it does not hurt anything to |
| 682 | * initialize these registers. |
| 683 | */ |
| 684 | hw_dbg(hw, "Initializing the Flow Control address, type and timer regs\n"); |
| 685 | ew32(FCT, FLOW_CONTROL_TYPE); |
| 686 | ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH); |
| 687 | ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW); |
| 688 | |
Jeff Kirsher | 318a94d | 2008-03-28 09:15:16 -0700 | [diff] [blame] | 689 | ew32(FCTTV, hw->fc.pause_time); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 690 | |
| 691 | return e1000e_set_fc_watermarks(hw); |
| 692 | } |
| 693 | |
| 694 | /** |
| 695 | * e1000_commit_fc_settings_generic - Configure flow control |
| 696 | * @hw: pointer to the HW structure |
| 697 | * |
| 698 | * Write the flow control settings to the Transmit Config Word Register (TXCW) |
| 699 | * base on the flow control settings in e1000_mac_info. |
| 700 | **/ |
| 701 | static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) |
| 702 | { |
| 703 | struct e1000_mac_info *mac = &hw->mac; |
| 704 | u32 txcw; |
| 705 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 706 | /* |
| 707 | * Check for a software override of the flow control settings, and |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 708 | * setup the device accordingly. If auto-negotiation is enabled, then |
| 709 | * software will have to set the "PAUSE" bits to the correct value in |
| 710 | * the Transmit Config Word Register (TXCW) and re-start auto- |
| 711 | * negotiation. However, if auto-negotiation is disabled, then |
| 712 | * software will have to manually configure the two flow control enable |
| 713 | * bits in the CTRL register. |
| 714 | * |
| 715 | * The possible values of the "fc" parameter are: |
| 716 | * 0: Flow control is completely disabled |
| 717 | * 1: Rx flow control is enabled (we can receive pause frames, |
| 718 | * but not send pause frames). |
| 719 | * 2: Tx flow control is enabled (we can send pause frames but we |
| 720 | * do not support receiving pause frames). |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 721 | * 3: Both Rx and Tx flow control (symmetric) are enabled. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 722 | */ |
Bruce Allan | 5c48ef3e2 | 2008-11-21 16:57:36 -0800 | [diff] [blame] | 723 | switch (hw->fc.current_mode) { |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 724 | case e1000_fc_none: |
| 725 | /* Flow control completely disabled by a software over-ride. */ |
| 726 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); |
| 727 | break; |
| 728 | case e1000_fc_rx_pause: |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 729 | /* |
| 730 | * Rx Flow control is enabled and Tx Flow control is disabled |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 731 | * by a software over-ride. Since there really isn't a way to |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 732 | * advertise that we are capable of Rx Pause ONLY, we will |
| 733 | * advertise that we support both symmetric and asymmetric Rx |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 734 | * PAUSE. Later, we will disable the adapter's ability to send |
| 735 | * PAUSE frames. |
| 736 | */ |
| 737 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); |
| 738 | break; |
| 739 | case e1000_fc_tx_pause: |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 740 | /* |
| 741 | * Tx Flow control is enabled, and Rx Flow control is disabled, |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 742 | * by a software over-ride. |
| 743 | */ |
| 744 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); |
| 745 | break; |
| 746 | case e1000_fc_full: |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 747 | /* |
| 748 | * Flow control (both Rx and Tx) is enabled by a software |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 749 | * over-ride. |
| 750 | */ |
| 751 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); |
| 752 | break; |
| 753 | default: |
| 754 | hw_dbg(hw, "Flow control param set incorrectly\n"); |
| 755 | return -E1000_ERR_CONFIG; |
| 756 | break; |
| 757 | } |
| 758 | |
| 759 | ew32(TXCW, txcw); |
| 760 | mac->txcw = txcw; |
| 761 | |
| 762 | return 0; |
| 763 | } |
| 764 | |
| 765 | /** |
| 766 | * e1000_poll_fiber_serdes_link_generic - Poll for link up |
| 767 | * @hw: pointer to the HW structure |
| 768 | * |
| 769 | * Polls for link up by reading the status register, if link fails to come |
| 770 | * up with auto-negotiation, then the link is forced if a signal is detected. |
| 771 | **/ |
| 772 | static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) |
| 773 | { |
| 774 | struct e1000_mac_info *mac = &hw->mac; |
| 775 | u32 i, status; |
| 776 | s32 ret_val; |
| 777 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 778 | /* |
| 779 | * If we have a signal (the cable is plugged in, or assumed true for |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 780 | * serdes media) then poll for a "Link-Up" indication in the Device |
| 781 | * Status Register. Time-out if a link isn't seen in 500 milliseconds |
| 782 | * seconds (Auto-negotiation should complete in less than 500 |
| 783 | * milliseconds even if the other end is doing it in SW). |
| 784 | */ |
| 785 | for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { |
| 786 | msleep(10); |
| 787 | status = er32(STATUS); |
| 788 | if (status & E1000_STATUS_LU) |
| 789 | break; |
| 790 | } |
| 791 | if (i == FIBER_LINK_UP_LIMIT) { |
| 792 | hw_dbg(hw, "Never got a valid link from auto-neg!!!\n"); |
| 793 | mac->autoneg_failed = 1; |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 794 | /* |
| 795 | * AutoNeg failed to achieve a link, so we'll call |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 796 | * mac->check_for_link. This routine will force the |
| 797 | * link up if we detect a signal. This will allow us to |
| 798 | * communicate with non-autonegotiating link partners. |
| 799 | */ |
| 800 | ret_val = mac->ops.check_for_link(hw); |
| 801 | if (ret_val) { |
| 802 | hw_dbg(hw, "Error while checking for link\n"); |
| 803 | return ret_val; |
| 804 | } |
| 805 | mac->autoneg_failed = 0; |
| 806 | } else { |
| 807 | mac->autoneg_failed = 0; |
| 808 | hw_dbg(hw, "Valid Link Found\n"); |
| 809 | } |
| 810 | |
| 811 | return 0; |
| 812 | } |
| 813 | |
| 814 | /** |
| 815 | * e1000e_setup_fiber_serdes_link - Setup link for fiber/serdes |
| 816 | * @hw: pointer to the HW structure |
| 817 | * |
| 818 | * Configures collision distance and flow control for fiber and serdes |
| 819 | * links. Upon successful setup, poll for link. |
| 820 | **/ |
| 821 | s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw) |
| 822 | { |
| 823 | u32 ctrl; |
| 824 | s32 ret_val; |
| 825 | |
| 826 | ctrl = er32(CTRL); |
| 827 | |
| 828 | /* Take the link out of reset */ |
| 829 | ctrl &= ~E1000_CTRL_LRST; |
| 830 | |
| 831 | e1000e_config_collision_dist(hw); |
| 832 | |
| 833 | ret_val = e1000_commit_fc_settings_generic(hw); |
| 834 | if (ret_val) |
| 835 | return ret_val; |
| 836 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 837 | /* |
| 838 | * Since auto-negotiation is enabled, take the link out of reset (the |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 839 | * link will be in reset, because we previously reset the chip). This |
| 840 | * will restart auto-negotiation. If auto-negotiation is successful |
| 841 | * then the link-up status bit will be set and the flow control enable |
| 842 | * bits (RFCE and TFCE) will be set according to their negotiated value. |
| 843 | */ |
| 844 | hw_dbg(hw, "Auto-negotiation enabled\n"); |
| 845 | |
| 846 | ew32(CTRL, ctrl); |
| 847 | e1e_flush(); |
| 848 | msleep(1); |
| 849 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 850 | /* |
| 851 | * For these adapters, the SW definable pin 1 is set when the optics |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 852 | * detect a signal. If we have a signal, then poll for a "Link-Up" |
| 853 | * indication. |
| 854 | */ |
Jeff Kirsher | 318a94d | 2008-03-28 09:15:16 -0700 | [diff] [blame] | 855 | if (hw->phy.media_type == e1000_media_type_internal_serdes || |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 856 | (er32(CTRL) & E1000_CTRL_SWDPIN1)) { |
| 857 | ret_val = e1000_poll_fiber_serdes_link_generic(hw); |
| 858 | } else { |
| 859 | hw_dbg(hw, "No signal detected\n"); |
| 860 | } |
| 861 | |
| 862 | return 0; |
| 863 | } |
| 864 | |
| 865 | /** |
| 866 | * e1000e_config_collision_dist - Configure collision distance |
| 867 | * @hw: pointer to the HW structure |
| 868 | * |
| 869 | * Configures the collision distance to the default value and is used |
| 870 | * during link setup. Currently no func pointer exists and all |
| 871 | * implementations are handled in the generic version of this function. |
| 872 | **/ |
| 873 | void e1000e_config_collision_dist(struct e1000_hw *hw) |
| 874 | { |
| 875 | u32 tctl; |
| 876 | |
| 877 | tctl = er32(TCTL); |
| 878 | |
| 879 | tctl &= ~E1000_TCTL_COLD; |
| 880 | tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; |
| 881 | |
| 882 | ew32(TCTL, tctl); |
| 883 | e1e_flush(); |
| 884 | } |
| 885 | |
| 886 | /** |
| 887 | * e1000e_set_fc_watermarks - Set flow control high/low watermarks |
| 888 | * @hw: pointer to the HW structure |
| 889 | * |
| 890 | * Sets the flow control high/low threshold (watermark) registers. If |
| 891 | * flow control XON frame transmission is enabled, then set XON frame |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 892 | * transmission as well. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 893 | **/ |
| 894 | s32 e1000e_set_fc_watermarks(struct e1000_hw *hw) |
| 895 | { |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 896 | u32 fcrtl = 0, fcrth = 0; |
| 897 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 898 | /* |
| 899 | * Set the flow control receive threshold registers. Normally, |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 900 | * these registers will be set to a default threshold that may be |
| 901 | * adjusted later by the driver's runtime code. However, if the |
| 902 | * ability to transmit pause frames is not enabled, then these |
| 903 | * registers will be set to 0. |
| 904 | */ |
Bruce Allan | 5c48ef3e2 | 2008-11-21 16:57:36 -0800 | [diff] [blame] | 905 | if (hw->fc.current_mode & e1000_fc_tx_pause) { |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 906 | /* |
| 907 | * We need to set up the Receive Threshold high and low water |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 908 | * marks as well as (optionally) enabling the transmission of |
| 909 | * XON frames. |
| 910 | */ |
Jeff Kirsher | 318a94d | 2008-03-28 09:15:16 -0700 | [diff] [blame] | 911 | fcrtl = hw->fc.low_water; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 912 | fcrtl |= E1000_FCRTL_XONE; |
Jeff Kirsher | 318a94d | 2008-03-28 09:15:16 -0700 | [diff] [blame] | 913 | fcrth = hw->fc.high_water; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 914 | } |
| 915 | ew32(FCRTL, fcrtl); |
| 916 | ew32(FCRTH, fcrth); |
| 917 | |
| 918 | return 0; |
| 919 | } |
| 920 | |
| 921 | /** |
| 922 | * e1000e_force_mac_fc - Force the MAC's flow control settings |
| 923 | * @hw: pointer to the HW structure |
| 924 | * |
| 925 | * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the |
| 926 | * device control register to reflect the adapter settings. TFCE and RFCE |
| 927 | * need to be explicitly set by software when a copper PHY is used because |
| 928 | * autonegotiation is managed by the PHY rather than the MAC. Software must |
| 929 | * also configure these bits when link is forced on a fiber connection. |
| 930 | **/ |
| 931 | s32 e1000e_force_mac_fc(struct e1000_hw *hw) |
| 932 | { |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 933 | u32 ctrl; |
| 934 | |
| 935 | ctrl = er32(CTRL); |
| 936 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 937 | /* |
| 938 | * Because we didn't get link via the internal auto-negotiation |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 939 | * mechanism (we either forced link or we got link via PHY |
| 940 | * auto-neg), we have to manually enable/disable transmit an |
| 941 | * receive flow control. |
| 942 | * |
| 943 | * The "Case" statement below enables/disable flow control |
Bruce Allan | 5c48ef3e2 | 2008-11-21 16:57:36 -0800 | [diff] [blame] | 944 | * according to the "hw->fc.current_mode" parameter. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 945 | * |
| 946 | * The possible values of the "fc" parameter are: |
| 947 | * 0: Flow control is completely disabled |
| 948 | * 1: Rx flow control is enabled (we can receive pause |
| 949 | * frames but not send pause frames). |
| 950 | * 2: Tx flow control is enabled (we can send pause frames |
| 951 | * frames but we do not receive pause frames). |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 952 | * 3: Both Rx and Tx flow control (symmetric) is enabled. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 953 | * other: No other values should be possible at this point. |
| 954 | */ |
Bruce Allan | 5c48ef3e2 | 2008-11-21 16:57:36 -0800 | [diff] [blame] | 955 | hw_dbg(hw, "hw->fc.current_mode = %u\n", hw->fc.current_mode); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 956 | |
Bruce Allan | 5c48ef3e2 | 2008-11-21 16:57:36 -0800 | [diff] [blame] | 957 | switch (hw->fc.current_mode) { |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 958 | case e1000_fc_none: |
| 959 | ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); |
| 960 | break; |
| 961 | case e1000_fc_rx_pause: |
| 962 | ctrl &= (~E1000_CTRL_TFCE); |
| 963 | ctrl |= E1000_CTRL_RFCE; |
| 964 | break; |
| 965 | case e1000_fc_tx_pause: |
| 966 | ctrl &= (~E1000_CTRL_RFCE); |
| 967 | ctrl |= E1000_CTRL_TFCE; |
| 968 | break; |
| 969 | case e1000_fc_full: |
| 970 | ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); |
| 971 | break; |
| 972 | default: |
| 973 | hw_dbg(hw, "Flow control param set incorrectly\n"); |
| 974 | return -E1000_ERR_CONFIG; |
| 975 | } |
| 976 | |
| 977 | ew32(CTRL, ctrl); |
| 978 | |
| 979 | return 0; |
| 980 | } |
| 981 | |
| 982 | /** |
| 983 | * e1000e_config_fc_after_link_up - Configures flow control after link |
| 984 | * @hw: pointer to the HW structure |
| 985 | * |
| 986 | * Checks the status of auto-negotiation after link up to ensure that the |
| 987 | * speed and duplex were not forced. If the link needed to be forced, then |
| 988 | * flow control needs to be forced also. If auto-negotiation is enabled |
| 989 | * and did not fail, then we configure flow control based on our link |
| 990 | * partner. |
| 991 | **/ |
| 992 | s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw) |
| 993 | { |
| 994 | struct e1000_mac_info *mac = &hw->mac; |
| 995 | s32 ret_val = 0; |
| 996 | u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; |
| 997 | u16 speed, duplex; |
| 998 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 999 | /* |
| 1000 | * Check for the case where we have fiber media and auto-neg failed |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1001 | * so we had to force link. In this case, we need to force the |
| 1002 | * configuration of the MAC to match the "fc" parameter. |
| 1003 | */ |
| 1004 | if (mac->autoneg_failed) { |
Jeff Kirsher | 318a94d | 2008-03-28 09:15:16 -0700 | [diff] [blame] | 1005 | if (hw->phy.media_type == e1000_media_type_fiber || |
| 1006 | hw->phy.media_type == e1000_media_type_internal_serdes) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1007 | ret_val = e1000e_force_mac_fc(hw); |
| 1008 | } else { |
Jeff Kirsher | 318a94d | 2008-03-28 09:15:16 -0700 | [diff] [blame] | 1009 | if (hw->phy.media_type == e1000_media_type_copper) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1010 | ret_val = e1000e_force_mac_fc(hw); |
| 1011 | } |
| 1012 | |
| 1013 | if (ret_val) { |
| 1014 | hw_dbg(hw, "Error forcing flow control settings\n"); |
| 1015 | return ret_val; |
| 1016 | } |
| 1017 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1018 | /* |
| 1019 | * Check for the case where we have copper media and auto-neg is |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1020 | * enabled. In this case, we need to check and see if Auto-Neg |
| 1021 | * has completed, and if so, how the PHY and link partner has |
| 1022 | * flow control configured. |
| 1023 | */ |
Jeff Kirsher | 318a94d | 2008-03-28 09:15:16 -0700 | [diff] [blame] | 1024 | if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1025 | /* |
| 1026 | * Read the MII Status Register and check to see if AutoNeg |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1027 | * has completed. We read this twice because this reg has |
| 1028 | * some "sticky" (latched) bits. |
| 1029 | */ |
| 1030 | ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg); |
| 1031 | if (ret_val) |
| 1032 | return ret_val; |
| 1033 | ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg); |
| 1034 | if (ret_val) |
| 1035 | return ret_val; |
| 1036 | |
| 1037 | if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { |
| 1038 | hw_dbg(hw, "Copper PHY and Auto Neg " |
| 1039 | "has not completed.\n"); |
| 1040 | return ret_val; |
| 1041 | } |
| 1042 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1043 | /* |
| 1044 | * The AutoNeg process has completed, so we now need to |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1045 | * read both the Auto Negotiation Advertisement |
| 1046 | * Register (Address 4) and the Auto_Negotiation Base |
| 1047 | * Page Ability Register (Address 5) to determine how |
| 1048 | * flow control was negotiated. |
| 1049 | */ |
| 1050 | ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg); |
| 1051 | if (ret_val) |
| 1052 | return ret_val; |
| 1053 | ret_val = e1e_rphy(hw, PHY_LP_ABILITY, &mii_nway_lp_ability_reg); |
| 1054 | if (ret_val) |
| 1055 | return ret_val; |
| 1056 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1057 | /* |
| 1058 | * Two bits in the Auto Negotiation Advertisement Register |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1059 | * (Address 4) and two bits in the Auto Negotiation Base |
| 1060 | * Page Ability Register (Address 5) determine flow control |
| 1061 | * for both the PHY and the link partner. The following |
| 1062 | * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, |
| 1063 | * 1999, describes these PAUSE resolution bits and how flow |
| 1064 | * control is determined based upon these settings. |
| 1065 | * NOTE: DC = Don't Care |
| 1066 | * |
| 1067 | * LOCAL DEVICE | LINK PARTNER |
| 1068 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution |
| 1069 | *-------|---------|-------|---------|-------------------- |
| 1070 | * 0 | 0 | DC | DC | e1000_fc_none |
| 1071 | * 0 | 1 | 0 | DC | e1000_fc_none |
| 1072 | * 0 | 1 | 1 | 0 | e1000_fc_none |
| 1073 | * 0 | 1 | 1 | 1 | e1000_fc_tx_pause |
| 1074 | * 1 | 0 | 0 | DC | e1000_fc_none |
| 1075 | * 1 | DC | 1 | DC | e1000_fc_full |
| 1076 | * 1 | 1 | 0 | 0 | e1000_fc_none |
| 1077 | * 1 | 1 | 0 | 1 | e1000_fc_rx_pause |
| 1078 | * |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1079 | * |
| 1080 | * Are both PAUSE bits set to 1? If so, this implies |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1081 | * Symmetric Flow Control is enabled at both ends. The |
| 1082 | * ASM_DIR bits are irrelevant per the spec. |
| 1083 | * |
| 1084 | * For Symmetric Flow Control: |
| 1085 | * |
| 1086 | * LOCAL DEVICE | LINK PARTNER |
| 1087 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
| 1088 | *-------|---------|-------|---------|-------------------- |
| 1089 | * 1 | DC | 1 | DC | E1000_fc_full |
| 1090 | * |
| 1091 | */ |
| 1092 | if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && |
| 1093 | (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1094 | /* |
| 1095 | * Now we need to check if the user selected Rx ONLY |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1096 | * of pause frames. In this case, we had to advertise |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1097 | * FULL flow control because we could not advertise Rx |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1098 | * ONLY. Hence, we must now check to see if we need to |
| 1099 | * turn OFF the TRANSMISSION of PAUSE frames. |
| 1100 | */ |
Bruce Allan | 5c48ef3e2 | 2008-11-21 16:57:36 -0800 | [diff] [blame] | 1101 | if (hw->fc.requested_mode == e1000_fc_full) { |
| 1102 | hw->fc.current_mode = e1000_fc_full; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1103 | hw_dbg(hw, "Flow Control = FULL.\r\n"); |
| 1104 | } else { |
Bruce Allan | 5c48ef3e2 | 2008-11-21 16:57:36 -0800 | [diff] [blame] | 1105 | hw->fc.current_mode = e1000_fc_rx_pause; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1106 | hw_dbg(hw, "Flow Control = " |
| 1107 | "RX PAUSE frames only.\r\n"); |
| 1108 | } |
| 1109 | } |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1110 | /* |
| 1111 | * For receiving PAUSE frames ONLY. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1112 | * |
| 1113 | * LOCAL DEVICE | LINK PARTNER |
| 1114 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
| 1115 | *-------|---------|-------|---------|-------------------- |
| 1116 | * 0 | 1 | 1 | 1 | e1000_fc_tx_pause |
| 1117 | * |
| 1118 | */ |
| 1119 | else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && |
| 1120 | (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && |
| 1121 | (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && |
| 1122 | (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { |
Bruce Allan | 5c48ef3e2 | 2008-11-21 16:57:36 -0800 | [diff] [blame] | 1123 | hw->fc.current_mode = e1000_fc_tx_pause; |
Jeff Kirsher | 318a94d | 2008-03-28 09:15:16 -0700 | [diff] [blame] | 1124 | hw_dbg(hw, "Flow Control = Tx PAUSE frames only.\r\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1125 | } |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1126 | /* |
| 1127 | * For transmitting PAUSE frames ONLY. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1128 | * |
| 1129 | * LOCAL DEVICE | LINK PARTNER |
| 1130 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
| 1131 | *-------|---------|-------|---------|-------------------- |
| 1132 | * 1 | 1 | 0 | 1 | e1000_fc_rx_pause |
| 1133 | * |
| 1134 | */ |
| 1135 | else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && |
| 1136 | (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && |
| 1137 | !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && |
| 1138 | (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { |
Bruce Allan | 5c48ef3e2 | 2008-11-21 16:57:36 -0800 | [diff] [blame] | 1139 | hw->fc.current_mode = e1000_fc_rx_pause; |
Jeff Kirsher | 318a94d | 2008-03-28 09:15:16 -0700 | [diff] [blame] | 1140 | hw_dbg(hw, "Flow Control = Rx PAUSE frames only.\r\n"); |
Jesse Brandeburg | de92d84 | 2008-02-21 15:11:02 -0800 | [diff] [blame] | 1141 | } else { |
| 1142 | /* |
| 1143 | * Per the IEEE spec, at this point flow control |
| 1144 | * should be disabled. |
| 1145 | */ |
Bruce Allan | 5c48ef3e2 | 2008-11-21 16:57:36 -0800 | [diff] [blame] | 1146 | hw->fc.current_mode = e1000_fc_none; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1147 | hw_dbg(hw, "Flow Control = NONE.\r\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1148 | } |
| 1149 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1150 | /* |
| 1151 | * Now we need to do one last check... If we auto- |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1152 | * negotiated to HALF DUPLEX, flow control should not be |
| 1153 | * enabled per IEEE 802.3 spec. |
| 1154 | */ |
| 1155 | ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); |
| 1156 | if (ret_val) { |
| 1157 | hw_dbg(hw, "Error getting link speed and duplex\n"); |
| 1158 | return ret_val; |
| 1159 | } |
| 1160 | |
| 1161 | if (duplex == HALF_DUPLEX) |
Bruce Allan | 5c48ef3e2 | 2008-11-21 16:57:36 -0800 | [diff] [blame] | 1162 | hw->fc.current_mode = e1000_fc_none; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1163 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1164 | /* |
| 1165 | * Now we call a subroutine to actually force the MAC |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1166 | * controller to use the correct flow control settings. |
| 1167 | */ |
| 1168 | ret_val = e1000e_force_mac_fc(hw); |
| 1169 | if (ret_val) { |
| 1170 | hw_dbg(hw, "Error forcing flow control settings\n"); |
| 1171 | return ret_val; |
| 1172 | } |
| 1173 | } |
| 1174 | |
| 1175 | return 0; |
| 1176 | } |
| 1177 | |
| 1178 | /** |
Auke Kok | 489815c | 2008-02-21 15:11:07 -0800 | [diff] [blame] | 1179 | * e1000e_get_speed_and_duplex_copper - Retrieve current speed/duplex |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1180 | * @hw: pointer to the HW structure |
| 1181 | * @speed: stores the current speed |
| 1182 | * @duplex: stores the current duplex |
| 1183 | * |
| 1184 | * Read the status register for the current speed/duplex and store the current |
| 1185 | * speed and duplex for copper connections. |
| 1186 | **/ |
| 1187 | s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex) |
| 1188 | { |
| 1189 | u32 status; |
| 1190 | |
| 1191 | status = er32(STATUS); |
| 1192 | if (status & E1000_STATUS_SPEED_1000) { |
| 1193 | *speed = SPEED_1000; |
| 1194 | hw_dbg(hw, "1000 Mbs, "); |
| 1195 | } else if (status & E1000_STATUS_SPEED_100) { |
| 1196 | *speed = SPEED_100; |
| 1197 | hw_dbg(hw, "100 Mbs, "); |
| 1198 | } else { |
| 1199 | *speed = SPEED_10; |
| 1200 | hw_dbg(hw, "10 Mbs, "); |
| 1201 | } |
| 1202 | |
| 1203 | if (status & E1000_STATUS_FD) { |
| 1204 | *duplex = FULL_DUPLEX; |
| 1205 | hw_dbg(hw, "Full Duplex\n"); |
| 1206 | } else { |
| 1207 | *duplex = HALF_DUPLEX; |
| 1208 | hw_dbg(hw, "Half Duplex\n"); |
| 1209 | } |
| 1210 | |
| 1211 | return 0; |
| 1212 | } |
| 1213 | |
| 1214 | /** |
Auke Kok | 489815c | 2008-02-21 15:11:07 -0800 | [diff] [blame] | 1215 | * e1000e_get_speed_and_duplex_fiber_serdes - Retrieve current speed/duplex |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1216 | * @hw: pointer to the HW structure |
| 1217 | * @speed: stores the current speed |
| 1218 | * @duplex: stores the current duplex |
| 1219 | * |
| 1220 | * Sets the speed and duplex to gigabit full duplex (the only possible option) |
| 1221 | * for fiber/serdes links. |
| 1222 | **/ |
| 1223 | s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex) |
| 1224 | { |
| 1225 | *speed = SPEED_1000; |
| 1226 | *duplex = FULL_DUPLEX; |
| 1227 | |
| 1228 | return 0; |
| 1229 | } |
| 1230 | |
| 1231 | /** |
| 1232 | * e1000e_get_hw_semaphore - Acquire hardware semaphore |
| 1233 | * @hw: pointer to the HW structure |
| 1234 | * |
| 1235 | * Acquire the HW semaphore to access the PHY or NVM |
| 1236 | **/ |
| 1237 | s32 e1000e_get_hw_semaphore(struct e1000_hw *hw) |
| 1238 | { |
| 1239 | u32 swsm; |
| 1240 | s32 timeout = hw->nvm.word_size + 1; |
| 1241 | s32 i = 0; |
| 1242 | |
| 1243 | /* Get the SW semaphore */ |
| 1244 | while (i < timeout) { |
| 1245 | swsm = er32(SWSM); |
| 1246 | if (!(swsm & E1000_SWSM_SMBI)) |
| 1247 | break; |
| 1248 | |
| 1249 | udelay(50); |
| 1250 | i++; |
| 1251 | } |
| 1252 | |
| 1253 | if (i == timeout) { |
| 1254 | hw_dbg(hw, "Driver can't access device - SMBI bit is set.\n"); |
| 1255 | return -E1000_ERR_NVM; |
| 1256 | } |
| 1257 | |
| 1258 | /* Get the FW semaphore. */ |
| 1259 | for (i = 0; i < timeout; i++) { |
| 1260 | swsm = er32(SWSM); |
| 1261 | ew32(SWSM, swsm | E1000_SWSM_SWESMBI); |
| 1262 | |
| 1263 | /* Semaphore acquired if bit latched */ |
| 1264 | if (er32(SWSM) & E1000_SWSM_SWESMBI) |
| 1265 | break; |
| 1266 | |
| 1267 | udelay(50); |
| 1268 | } |
| 1269 | |
| 1270 | if (i == timeout) { |
| 1271 | /* Release semaphores */ |
| 1272 | e1000e_put_hw_semaphore(hw); |
| 1273 | hw_dbg(hw, "Driver can't access the NVM\n"); |
| 1274 | return -E1000_ERR_NVM; |
| 1275 | } |
| 1276 | |
| 1277 | return 0; |
| 1278 | } |
| 1279 | |
| 1280 | /** |
| 1281 | * e1000e_put_hw_semaphore - Release hardware semaphore |
| 1282 | * @hw: pointer to the HW structure |
| 1283 | * |
| 1284 | * Release hardware semaphore used to access the PHY or NVM |
| 1285 | **/ |
| 1286 | void e1000e_put_hw_semaphore(struct e1000_hw *hw) |
| 1287 | { |
| 1288 | u32 swsm; |
| 1289 | |
| 1290 | swsm = er32(SWSM); |
| 1291 | swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); |
| 1292 | ew32(SWSM, swsm); |
| 1293 | } |
| 1294 | |
| 1295 | /** |
| 1296 | * e1000e_get_auto_rd_done - Check for auto read completion |
| 1297 | * @hw: pointer to the HW structure |
| 1298 | * |
| 1299 | * Check EEPROM for Auto Read done bit. |
| 1300 | **/ |
| 1301 | s32 e1000e_get_auto_rd_done(struct e1000_hw *hw) |
| 1302 | { |
| 1303 | s32 i = 0; |
| 1304 | |
| 1305 | while (i < AUTO_READ_DONE_TIMEOUT) { |
| 1306 | if (er32(EECD) & E1000_EECD_AUTO_RD) |
| 1307 | break; |
| 1308 | msleep(1); |
| 1309 | i++; |
| 1310 | } |
| 1311 | |
| 1312 | if (i == AUTO_READ_DONE_TIMEOUT) { |
| 1313 | hw_dbg(hw, "Auto read by HW from NVM has not completed.\n"); |
| 1314 | return -E1000_ERR_RESET; |
| 1315 | } |
| 1316 | |
| 1317 | return 0; |
| 1318 | } |
| 1319 | |
| 1320 | /** |
| 1321 | * e1000e_valid_led_default - Verify a valid default LED config |
| 1322 | * @hw: pointer to the HW structure |
| 1323 | * @data: pointer to the NVM (EEPROM) |
| 1324 | * |
| 1325 | * Read the EEPROM for the current default LED configuration. If the |
| 1326 | * LED configuration is not valid, set to a valid LED configuration. |
| 1327 | **/ |
| 1328 | s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data) |
| 1329 | { |
| 1330 | s32 ret_val; |
| 1331 | |
| 1332 | ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); |
| 1333 | if (ret_val) { |
| 1334 | hw_dbg(hw, "NVM Read Error\n"); |
| 1335 | return ret_val; |
| 1336 | } |
| 1337 | |
| 1338 | if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) |
| 1339 | *data = ID_LED_DEFAULT; |
| 1340 | |
| 1341 | return 0; |
| 1342 | } |
| 1343 | |
| 1344 | /** |
| 1345 | * e1000e_id_led_init - |
| 1346 | * @hw: pointer to the HW structure |
| 1347 | * |
| 1348 | **/ |
| 1349 | s32 e1000e_id_led_init(struct e1000_hw *hw) |
| 1350 | { |
| 1351 | struct e1000_mac_info *mac = &hw->mac; |
| 1352 | s32 ret_val; |
| 1353 | const u32 ledctl_mask = 0x000000FF; |
| 1354 | const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; |
| 1355 | const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; |
| 1356 | u16 data, i, temp; |
| 1357 | const u16 led_mask = 0x0F; |
| 1358 | |
| 1359 | ret_val = hw->nvm.ops.valid_led_default(hw, &data); |
| 1360 | if (ret_val) |
| 1361 | return ret_val; |
| 1362 | |
| 1363 | mac->ledctl_default = er32(LEDCTL); |
| 1364 | mac->ledctl_mode1 = mac->ledctl_default; |
| 1365 | mac->ledctl_mode2 = mac->ledctl_default; |
| 1366 | |
| 1367 | for (i = 0; i < 4; i++) { |
| 1368 | temp = (data >> (i << 2)) & led_mask; |
| 1369 | switch (temp) { |
| 1370 | case ID_LED_ON1_DEF2: |
| 1371 | case ID_LED_ON1_ON2: |
| 1372 | case ID_LED_ON1_OFF2: |
| 1373 | mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); |
| 1374 | mac->ledctl_mode1 |= ledctl_on << (i << 3); |
| 1375 | break; |
| 1376 | case ID_LED_OFF1_DEF2: |
| 1377 | case ID_LED_OFF1_ON2: |
| 1378 | case ID_LED_OFF1_OFF2: |
| 1379 | mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); |
| 1380 | mac->ledctl_mode1 |= ledctl_off << (i << 3); |
| 1381 | break; |
| 1382 | default: |
| 1383 | /* Do nothing */ |
| 1384 | break; |
| 1385 | } |
| 1386 | switch (temp) { |
| 1387 | case ID_LED_DEF1_ON2: |
| 1388 | case ID_LED_ON1_ON2: |
| 1389 | case ID_LED_OFF1_ON2: |
| 1390 | mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); |
| 1391 | mac->ledctl_mode2 |= ledctl_on << (i << 3); |
| 1392 | break; |
| 1393 | case ID_LED_DEF1_OFF2: |
| 1394 | case ID_LED_ON1_OFF2: |
| 1395 | case ID_LED_OFF1_OFF2: |
| 1396 | mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); |
| 1397 | mac->ledctl_mode2 |= ledctl_off << (i << 3); |
| 1398 | break; |
| 1399 | default: |
| 1400 | /* Do nothing */ |
| 1401 | break; |
| 1402 | } |
| 1403 | } |
| 1404 | |
| 1405 | return 0; |
| 1406 | } |
| 1407 | |
| 1408 | /** |
| 1409 | * e1000e_cleanup_led_generic - Set LED config to default operation |
| 1410 | * @hw: pointer to the HW structure |
| 1411 | * |
| 1412 | * Remove the current LED configuration and set the LED configuration |
| 1413 | * to the default value, saved from the EEPROM. |
| 1414 | **/ |
| 1415 | s32 e1000e_cleanup_led_generic(struct e1000_hw *hw) |
| 1416 | { |
| 1417 | ew32(LEDCTL, hw->mac.ledctl_default); |
| 1418 | return 0; |
| 1419 | } |
| 1420 | |
| 1421 | /** |
| 1422 | * e1000e_blink_led - Blink LED |
| 1423 | * @hw: pointer to the HW structure |
| 1424 | * |
Auke Kok | 489815c | 2008-02-21 15:11:07 -0800 | [diff] [blame] | 1425 | * Blink the LEDs which are set to be on. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1426 | **/ |
| 1427 | s32 e1000e_blink_led(struct e1000_hw *hw) |
| 1428 | { |
| 1429 | u32 ledctl_blink = 0; |
| 1430 | u32 i; |
| 1431 | |
Jeff Kirsher | 318a94d | 2008-03-28 09:15:16 -0700 | [diff] [blame] | 1432 | if (hw->phy.media_type == e1000_media_type_fiber) { |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1433 | /* always blink LED0 for PCI-E fiber */ |
| 1434 | ledctl_blink = E1000_LEDCTL_LED0_BLINK | |
| 1435 | (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); |
| 1436 | } else { |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1437 | /* |
| 1438 | * set the blink bit for each LED that's "on" (0x0E) |
| 1439 | * in ledctl_mode2 |
| 1440 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1441 | ledctl_blink = hw->mac.ledctl_mode2; |
| 1442 | for (i = 0; i < 4; i++) |
| 1443 | if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == |
| 1444 | E1000_LEDCTL_MODE_LED_ON) |
| 1445 | ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << |
| 1446 | (i * 8)); |
| 1447 | } |
| 1448 | |
| 1449 | ew32(LEDCTL, ledctl_blink); |
| 1450 | |
| 1451 | return 0; |
| 1452 | } |
| 1453 | |
| 1454 | /** |
| 1455 | * e1000e_led_on_generic - Turn LED on |
| 1456 | * @hw: pointer to the HW structure |
| 1457 | * |
| 1458 | * Turn LED on. |
| 1459 | **/ |
| 1460 | s32 e1000e_led_on_generic(struct e1000_hw *hw) |
| 1461 | { |
| 1462 | u32 ctrl; |
| 1463 | |
Jeff Kirsher | 318a94d | 2008-03-28 09:15:16 -0700 | [diff] [blame] | 1464 | switch (hw->phy.media_type) { |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1465 | case e1000_media_type_fiber: |
| 1466 | ctrl = er32(CTRL); |
| 1467 | ctrl &= ~E1000_CTRL_SWDPIN0; |
| 1468 | ctrl |= E1000_CTRL_SWDPIO0; |
| 1469 | ew32(CTRL, ctrl); |
| 1470 | break; |
| 1471 | case e1000_media_type_copper: |
| 1472 | ew32(LEDCTL, hw->mac.ledctl_mode2); |
| 1473 | break; |
| 1474 | default: |
| 1475 | break; |
| 1476 | } |
| 1477 | |
| 1478 | return 0; |
| 1479 | } |
| 1480 | |
| 1481 | /** |
| 1482 | * e1000e_led_off_generic - Turn LED off |
| 1483 | * @hw: pointer to the HW structure |
| 1484 | * |
| 1485 | * Turn LED off. |
| 1486 | **/ |
| 1487 | s32 e1000e_led_off_generic(struct e1000_hw *hw) |
| 1488 | { |
| 1489 | u32 ctrl; |
| 1490 | |
Jeff Kirsher | 318a94d | 2008-03-28 09:15:16 -0700 | [diff] [blame] | 1491 | switch (hw->phy.media_type) { |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1492 | case e1000_media_type_fiber: |
| 1493 | ctrl = er32(CTRL); |
| 1494 | ctrl |= E1000_CTRL_SWDPIN0; |
| 1495 | ctrl |= E1000_CTRL_SWDPIO0; |
| 1496 | ew32(CTRL, ctrl); |
| 1497 | break; |
| 1498 | case e1000_media_type_copper: |
| 1499 | ew32(LEDCTL, hw->mac.ledctl_mode1); |
| 1500 | break; |
| 1501 | default: |
| 1502 | break; |
| 1503 | } |
| 1504 | |
| 1505 | return 0; |
| 1506 | } |
| 1507 | |
| 1508 | /** |
| 1509 | * e1000e_set_pcie_no_snoop - Set PCI-express capabilities |
| 1510 | * @hw: pointer to the HW structure |
| 1511 | * @no_snoop: bitmap of snoop events |
| 1512 | * |
| 1513 | * Set the PCI-express register to snoop for events enabled in 'no_snoop'. |
| 1514 | **/ |
| 1515 | void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop) |
| 1516 | { |
| 1517 | u32 gcr; |
| 1518 | |
| 1519 | if (no_snoop) { |
| 1520 | gcr = er32(GCR); |
| 1521 | gcr &= ~(PCIE_NO_SNOOP_ALL); |
| 1522 | gcr |= no_snoop; |
| 1523 | ew32(GCR, gcr); |
| 1524 | } |
| 1525 | } |
| 1526 | |
| 1527 | /** |
| 1528 | * e1000e_disable_pcie_master - Disables PCI-express master access |
| 1529 | * @hw: pointer to the HW structure |
| 1530 | * |
| 1531 | * Returns 0 if successful, else returns -10 |
Auke Kok | 489815c | 2008-02-21 15:11:07 -0800 | [diff] [blame] | 1532 | * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1533 | * the master requests to be disabled. |
| 1534 | * |
| 1535 | * Disables PCI-Express master access and verifies there are no pending |
| 1536 | * requests. |
| 1537 | **/ |
| 1538 | s32 e1000e_disable_pcie_master(struct e1000_hw *hw) |
| 1539 | { |
| 1540 | u32 ctrl; |
| 1541 | s32 timeout = MASTER_DISABLE_TIMEOUT; |
| 1542 | |
| 1543 | ctrl = er32(CTRL); |
| 1544 | ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; |
| 1545 | ew32(CTRL, ctrl); |
| 1546 | |
| 1547 | while (timeout) { |
| 1548 | if (!(er32(STATUS) & |
| 1549 | E1000_STATUS_GIO_MASTER_ENABLE)) |
| 1550 | break; |
| 1551 | udelay(100); |
| 1552 | timeout--; |
| 1553 | } |
| 1554 | |
| 1555 | if (!timeout) { |
| 1556 | hw_dbg(hw, "Master requests are pending.\n"); |
| 1557 | return -E1000_ERR_MASTER_REQUESTS_PENDING; |
| 1558 | } |
| 1559 | |
| 1560 | return 0; |
| 1561 | } |
| 1562 | |
| 1563 | /** |
| 1564 | * e1000e_reset_adaptive - Reset Adaptive Interframe Spacing |
| 1565 | * @hw: pointer to the HW structure |
| 1566 | * |
| 1567 | * Reset the Adaptive Interframe Spacing throttle to default values. |
| 1568 | **/ |
| 1569 | void e1000e_reset_adaptive(struct e1000_hw *hw) |
| 1570 | { |
| 1571 | struct e1000_mac_info *mac = &hw->mac; |
| 1572 | |
| 1573 | mac->current_ifs_val = 0; |
| 1574 | mac->ifs_min_val = IFS_MIN; |
| 1575 | mac->ifs_max_val = IFS_MAX; |
| 1576 | mac->ifs_step_size = IFS_STEP; |
| 1577 | mac->ifs_ratio = IFS_RATIO; |
| 1578 | |
| 1579 | mac->in_ifs_mode = 0; |
| 1580 | ew32(AIT, 0); |
| 1581 | } |
| 1582 | |
| 1583 | /** |
| 1584 | * e1000e_update_adaptive - Update Adaptive Interframe Spacing |
| 1585 | * @hw: pointer to the HW structure |
| 1586 | * |
| 1587 | * Update the Adaptive Interframe Spacing Throttle value based on the |
| 1588 | * time between transmitted packets and time between collisions. |
| 1589 | **/ |
| 1590 | void e1000e_update_adaptive(struct e1000_hw *hw) |
| 1591 | { |
| 1592 | struct e1000_mac_info *mac = &hw->mac; |
| 1593 | |
| 1594 | if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { |
| 1595 | if (mac->tx_packet_delta > MIN_NUM_XMITS) { |
| 1596 | mac->in_ifs_mode = 1; |
| 1597 | if (mac->current_ifs_val < mac->ifs_max_val) { |
| 1598 | if (!mac->current_ifs_val) |
| 1599 | mac->current_ifs_val = mac->ifs_min_val; |
| 1600 | else |
| 1601 | mac->current_ifs_val += |
| 1602 | mac->ifs_step_size; |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1603 | ew32(AIT, mac->current_ifs_val); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1604 | } |
| 1605 | } |
| 1606 | } else { |
| 1607 | if (mac->in_ifs_mode && |
| 1608 | (mac->tx_packet_delta <= MIN_NUM_XMITS)) { |
| 1609 | mac->current_ifs_val = 0; |
| 1610 | mac->in_ifs_mode = 0; |
| 1611 | ew32(AIT, 0); |
| 1612 | } |
| 1613 | } |
| 1614 | } |
| 1615 | |
| 1616 | /** |
| 1617 | * e1000_raise_eec_clk - Raise EEPROM clock |
| 1618 | * @hw: pointer to the HW structure |
| 1619 | * @eecd: pointer to the EEPROM |
| 1620 | * |
| 1621 | * Enable/Raise the EEPROM clock bit. |
| 1622 | **/ |
| 1623 | static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd) |
| 1624 | { |
| 1625 | *eecd = *eecd | E1000_EECD_SK; |
| 1626 | ew32(EECD, *eecd); |
| 1627 | e1e_flush(); |
| 1628 | udelay(hw->nvm.delay_usec); |
| 1629 | } |
| 1630 | |
| 1631 | /** |
| 1632 | * e1000_lower_eec_clk - Lower EEPROM clock |
| 1633 | * @hw: pointer to the HW structure |
| 1634 | * @eecd: pointer to the EEPROM |
| 1635 | * |
| 1636 | * Clear/Lower the EEPROM clock bit. |
| 1637 | **/ |
| 1638 | static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd) |
| 1639 | { |
| 1640 | *eecd = *eecd & ~E1000_EECD_SK; |
| 1641 | ew32(EECD, *eecd); |
| 1642 | e1e_flush(); |
| 1643 | udelay(hw->nvm.delay_usec); |
| 1644 | } |
| 1645 | |
| 1646 | /** |
| 1647 | * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM |
| 1648 | * @hw: pointer to the HW structure |
| 1649 | * @data: data to send to the EEPROM |
| 1650 | * @count: number of bits to shift out |
| 1651 | * |
| 1652 | * We need to shift 'count' bits out to the EEPROM. So, the value in the |
| 1653 | * "data" parameter will be shifted out to the EEPROM one bit at a time. |
| 1654 | * In order to do this, "data" must be broken down into bits. |
| 1655 | **/ |
| 1656 | static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count) |
| 1657 | { |
| 1658 | struct e1000_nvm_info *nvm = &hw->nvm; |
| 1659 | u32 eecd = er32(EECD); |
| 1660 | u32 mask; |
| 1661 | |
| 1662 | mask = 0x01 << (count - 1); |
| 1663 | if (nvm->type == e1000_nvm_eeprom_spi) |
| 1664 | eecd |= E1000_EECD_DO; |
| 1665 | |
| 1666 | do { |
| 1667 | eecd &= ~E1000_EECD_DI; |
| 1668 | |
| 1669 | if (data & mask) |
| 1670 | eecd |= E1000_EECD_DI; |
| 1671 | |
| 1672 | ew32(EECD, eecd); |
| 1673 | e1e_flush(); |
| 1674 | |
| 1675 | udelay(nvm->delay_usec); |
| 1676 | |
| 1677 | e1000_raise_eec_clk(hw, &eecd); |
| 1678 | e1000_lower_eec_clk(hw, &eecd); |
| 1679 | |
| 1680 | mask >>= 1; |
| 1681 | } while (mask); |
| 1682 | |
| 1683 | eecd &= ~E1000_EECD_DI; |
| 1684 | ew32(EECD, eecd); |
| 1685 | } |
| 1686 | |
| 1687 | /** |
| 1688 | * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM |
| 1689 | * @hw: pointer to the HW structure |
| 1690 | * @count: number of bits to shift in |
| 1691 | * |
| 1692 | * In order to read a register from the EEPROM, we need to shift 'count' bits |
| 1693 | * in from the EEPROM. Bits are "shifted in" by raising the clock input to |
| 1694 | * the EEPROM (setting the SK bit), and then reading the value of the data out |
| 1695 | * "DO" bit. During this "shifting in" process the data in "DI" bit should |
| 1696 | * always be clear. |
| 1697 | **/ |
| 1698 | static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count) |
| 1699 | { |
| 1700 | u32 eecd; |
| 1701 | u32 i; |
| 1702 | u16 data; |
| 1703 | |
| 1704 | eecd = er32(EECD); |
| 1705 | |
| 1706 | eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); |
| 1707 | data = 0; |
| 1708 | |
| 1709 | for (i = 0; i < count; i++) { |
| 1710 | data <<= 1; |
| 1711 | e1000_raise_eec_clk(hw, &eecd); |
| 1712 | |
| 1713 | eecd = er32(EECD); |
| 1714 | |
| 1715 | eecd &= ~E1000_EECD_DI; |
| 1716 | if (eecd & E1000_EECD_DO) |
| 1717 | data |= 1; |
| 1718 | |
| 1719 | e1000_lower_eec_clk(hw, &eecd); |
| 1720 | } |
| 1721 | |
| 1722 | return data; |
| 1723 | } |
| 1724 | |
| 1725 | /** |
| 1726 | * e1000e_poll_eerd_eewr_done - Poll for EEPROM read/write completion |
| 1727 | * @hw: pointer to the HW structure |
| 1728 | * @ee_reg: EEPROM flag for polling |
| 1729 | * |
| 1730 | * Polls the EEPROM status bit for either read or write completion based |
| 1731 | * upon the value of 'ee_reg'. |
| 1732 | **/ |
| 1733 | s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg) |
| 1734 | { |
| 1735 | u32 attempts = 100000; |
| 1736 | u32 i, reg = 0; |
| 1737 | |
| 1738 | for (i = 0; i < attempts; i++) { |
| 1739 | if (ee_reg == E1000_NVM_POLL_READ) |
| 1740 | reg = er32(EERD); |
| 1741 | else |
| 1742 | reg = er32(EEWR); |
| 1743 | |
| 1744 | if (reg & E1000_NVM_RW_REG_DONE) |
| 1745 | return 0; |
| 1746 | |
| 1747 | udelay(5); |
| 1748 | } |
| 1749 | |
| 1750 | return -E1000_ERR_NVM; |
| 1751 | } |
| 1752 | |
| 1753 | /** |
| 1754 | * e1000e_acquire_nvm - Generic request for access to EEPROM |
| 1755 | * @hw: pointer to the HW structure |
| 1756 | * |
| 1757 | * Set the EEPROM access request bit and wait for EEPROM access grant bit. |
| 1758 | * Return successful if access grant bit set, else clear the request for |
| 1759 | * EEPROM access and return -E1000_ERR_NVM (-1). |
| 1760 | **/ |
| 1761 | s32 e1000e_acquire_nvm(struct e1000_hw *hw) |
| 1762 | { |
| 1763 | u32 eecd = er32(EECD); |
| 1764 | s32 timeout = E1000_NVM_GRANT_ATTEMPTS; |
| 1765 | |
| 1766 | ew32(EECD, eecd | E1000_EECD_REQ); |
| 1767 | eecd = er32(EECD); |
| 1768 | |
| 1769 | while (timeout) { |
| 1770 | if (eecd & E1000_EECD_GNT) |
| 1771 | break; |
| 1772 | udelay(5); |
| 1773 | eecd = er32(EECD); |
| 1774 | timeout--; |
| 1775 | } |
| 1776 | |
| 1777 | if (!timeout) { |
| 1778 | eecd &= ~E1000_EECD_REQ; |
| 1779 | ew32(EECD, eecd); |
| 1780 | hw_dbg(hw, "Could not acquire NVM grant\n"); |
| 1781 | return -E1000_ERR_NVM; |
| 1782 | } |
| 1783 | |
| 1784 | return 0; |
| 1785 | } |
| 1786 | |
| 1787 | /** |
| 1788 | * e1000_standby_nvm - Return EEPROM to standby state |
| 1789 | * @hw: pointer to the HW structure |
| 1790 | * |
| 1791 | * Return the EEPROM to a standby state. |
| 1792 | **/ |
| 1793 | static void e1000_standby_nvm(struct e1000_hw *hw) |
| 1794 | { |
| 1795 | struct e1000_nvm_info *nvm = &hw->nvm; |
| 1796 | u32 eecd = er32(EECD); |
| 1797 | |
| 1798 | if (nvm->type == e1000_nvm_eeprom_spi) { |
| 1799 | /* Toggle CS to flush commands */ |
| 1800 | eecd |= E1000_EECD_CS; |
| 1801 | ew32(EECD, eecd); |
| 1802 | e1e_flush(); |
| 1803 | udelay(nvm->delay_usec); |
| 1804 | eecd &= ~E1000_EECD_CS; |
| 1805 | ew32(EECD, eecd); |
| 1806 | e1e_flush(); |
| 1807 | udelay(nvm->delay_usec); |
| 1808 | } |
| 1809 | } |
| 1810 | |
| 1811 | /** |
| 1812 | * e1000_stop_nvm - Terminate EEPROM command |
| 1813 | * @hw: pointer to the HW structure |
| 1814 | * |
| 1815 | * Terminates the current command by inverting the EEPROM's chip select pin. |
| 1816 | **/ |
| 1817 | static void e1000_stop_nvm(struct e1000_hw *hw) |
| 1818 | { |
| 1819 | u32 eecd; |
| 1820 | |
| 1821 | eecd = er32(EECD); |
| 1822 | if (hw->nvm.type == e1000_nvm_eeprom_spi) { |
| 1823 | /* Pull CS high */ |
| 1824 | eecd |= E1000_EECD_CS; |
| 1825 | e1000_lower_eec_clk(hw, &eecd); |
| 1826 | } |
| 1827 | } |
| 1828 | |
| 1829 | /** |
| 1830 | * e1000e_release_nvm - Release exclusive access to EEPROM |
| 1831 | * @hw: pointer to the HW structure |
| 1832 | * |
| 1833 | * Stop any current commands to the EEPROM and clear the EEPROM request bit. |
| 1834 | **/ |
| 1835 | void e1000e_release_nvm(struct e1000_hw *hw) |
| 1836 | { |
| 1837 | u32 eecd; |
| 1838 | |
| 1839 | e1000_stop_nvm(hw); |
| 1840 | |
| 1841 | eecd = er32(EECD); |
| 1842 | eecd &= ~E1000_EECD_REQ; |
| 1843 | ew32(EECD, eecd); |
| 1844 | } |
| 1845 | |
| 1846 | /** |
| 1847 | * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write |
| 1848 | * @hw: pointer to the HW structure |
| 1849 | * |
| 1850 | * Setups the EEPROM for reading and writing. |
| 1851 | **/ |
| 1852 | static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw) |
| 1853 | { |
| 1854 | struct e1000_nvm_info *nvm = &hw->nvm; |
| 1855 | u32 eecd = er32(EECD); |
| 1856 | u16 timeout = 0; |
| 1857 | u8 spi_stat_reg; |
| 1858 | |
| 1859 | if (nvm->type == e1000_nvm_eeprom_spi) { |
| 1860 | /* Clear SK and CS */ |
| 1861 | eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); |
| 1862 | ew32(EECD, eecd); |
| 1863 | udelay(1); |
| 1864 | timeout = NVM_MAX_RETRY_SPI; |
| 1865 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1866 | /* |
| 1867 | * Read "Status Register" repeatedly until the LSB is cleared. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1868 | * The EEPROM will signal that the command has been completed |
| 1869 | * by clearing bit 0 of the internal status register. If it's |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1870 | * not cleared within 'timeout', then error out. |
| 1871 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1872 | while (timeout) { |
| 1873 | e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI, |
| 1874 | hw->nvm.opcode_bits); |
| 1875 | spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8); |
| 1876 | if (!(spi_stat_reg & NVM_STATUS_RDY_SPI)) |
| 1877 | break; |
| 1878 | |
| 1879 | udelay(5); |
| 1880 | e1000_standby_nvm(hw); |
| 1881 | timeout--; |
| 1882 | } |
| 1883 | |
| 1884 | if (!timeout) { |
| 1885 | hw_dbg(hw, "SPI NVM Status error\n"); |
| 1886 | return -E1000_ERR_NVM; |
| 1887 | } |
| 1888 | } |
| 1889 | |
| 1890 | return 0; |
| 1891 | } |
| 1892 | |
| 1893 | /** |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1894 | * e1000e_read_nvm_eerd - Reads EEPROM using EERD register |
| 1895 | * @hw: pointer to the HW structure |
| 1896 | * @offset: offset of word in the EEPROM to read |
| 1897 | * @words: number of words to read |
| 1898 | * @data: word read from the EEPROM |
| 1899 | * |
| 1900 | * Reads a 16 bit word from the EEPROM using the EERD register. |
| 1901 | **/ |
| 1902 | s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) |
| 1903 | { |
| 1904 | struct e1000_nvm_info *nvm = &hw->nvm; |
| 1905 | u32 i, eerd = 0; |
| 1906 | s32 ret_val = 0; |
| 1907 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1908 | /* |
| 1909 | * A check for invalid values: offset too large, too many words, |
| 1910 | * too many words for the offset, and not enough words. |
| 1911 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1912 | if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || |
| 1913 | (words == 0)) { |
| 1914 | hw_dbg(hw, "nvm parameter(s) out of bounds\n"); |
| 1915 | return -E1000_ERR_NVM; |
| 1916 | } |
| 1917 | |
| 1918 | for (i = 0; i < words; i++) { |
| 1919 | eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) + |
| 1920 | E1000_NVM_RW_REG_START; |
| 1921 | |
| 1922 | ew32(EERD, eerd); |
| 1923 | ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ); |
| 1924 | if (ret_val) |
| 1925 | break; |
| 1926 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1927 | data[i] = (er32(EERD) >> E1000_NVM_RW_REG_DATA); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1928 | } |
| 1929 | |
| 1930 | return ret_val; |
| 1931 | } |
| 1932 | |
| 1933 | /** |
| 1934 | * e1000e_write_nvm_spi - Write to EEPROM using SPI |
| 1935 | * @hw: pointer to the HW structure |
| 1936 | * @offset: offset within the EEPROM to be written to |
| 1937 | * @words: number of words to write |
| 1938 | * @data: 16 bit word(s) to be written to the EEPROM |
| 1939 | * |
| 1940 | * Writes data to EEPROM at offset using SPI interface. |
| 1941 | * |
| 1942 | * If e1000e_update_nvm_checksum is not called after this function , the |
Auke Kok | 489815c | 2008-02-21 15:11:07 -0800 | [diff] [blame] | 1943 | * EEPROM will most likely contain an invalid checksum. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1944 | **/ |
| 1945 | s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) |
| 1946 | { |
| 1947 | struct e1000_nvm_info *nvm = &hw->nvm; |
| 1948 | s32 ret_val; |
| 1949 | u16 widx = 0; |
| 1950 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1951 | /* |
| 1952 | * A check for invalid values: offset too large, too many words, |
| 1953 | * and not enough words. |
| 1954 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1955 | if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || |
| 1956 | (words == 0)) { |
| 1957 | hw_dbg(hw, "nvm parameter(s) out of bounds\n"); |
| 1958 | return -E1000_ERR_NVM; |
| 1959 | } |
| 1960 | |
| 1961 | ret_val = nvm->ops.acquire_nvm(hw); |
| 1962 | if (ret_val) |
| 1963 | return ret_val; |
| 1964 | |
| 1965 | msleep(10); |
| 1966 | |
| 1967 | while (widx < words) { |
| 1968 | u8 write_opcode = NVM_WRITE_OPCODE_SPI; |
| 1969 | |
| 1970 | ret_val = e1000_ready_nvm_eeprom(hw); |
| 1971 | if (ret_val) { |
| 1972 | nvm->ops.release_nvm(hw); |
| 1973 | return ret_val; |
| 1974 | } |
| 1975 | |
| 1976 | e1000_standby_nvm(hw); |
| 1977 | |
| 1978 | /* Send the WRITE ENABLE command (8 bit opcode) */ |
| 1979 | e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI, |
| 1980 | nvm->opcode_bits); |
| 1981 | |
| 1982 | e1000_standby_nvm(hw); |
| 1983 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1984 | /* |
| 1985 | * Some SPI eeproms use the 8th address bit embedded in the |
| 1986 | * opcode |
| 1987 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1988 | if ((nvm->address_bits == 8) && (offset >= 128)) |
| 1989 | write_opcode |= NVM_A8_OPCODE_SPI; |
| 1990 | |
| 1991 | /* Send the Write command (8-bit opcode + addr) */ |
| 1992 | e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits); |
| 1993 | e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2), |
| 1994 | nvm->address_bits); |
| 1995 | |
| 1996 | /* Loop to allow for up to whole page write of eeprom */ |
| 1997 | while (widx < words) { |
| 1998 | u16 word_out = data[widx]; |
| 1999 | word_out = (word_out >> 8) | (word_out << 8); |
| 2000 | e1000_shift_out_eec_bits(hw, word_out, 16); |
| 2001 | widx++; |
| 2002 | |
| 2003 | if ((((offset + widx) * 2) % nvm->page_size) == 0) { |
| 2004 | e1000_standby_nvm(hw); |
| 2005 | break; |
| 2006 | } |
| 2007 | } |
| 2008 | } |
| 2009 | |
| 2010 | msleep(10); |
Arthur Jones | 1694f25 | 2008-09-29 11:51:09 +0000 | [diff] [blame] | 2011 | nvm->ops.release_nvm(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2012 | return 0; |
| 2013 | } |
| 2014 | |
| 2015 | /** |
| 2016 | * e1000e_read_mac_addr - Read device MAC address |
| 2017 | * @hw: pointer to the HW structure |
| 2018 | * |
| 2019 | * Reads the device MAC address from the EEPROM and stores the value. |
| 2020 | * Since devices with two ports use the same EEPROM, we increment the |
| 2021 | * last bit in the MAC address for the second port. |
| 2022 | **/ |
| 2023 | s32 e1000e_read_mac_addr(struct e1000_hw *hw) |
| 2024 | { |
| 2025 | s32 ret_val; |
| 2026 | u16 offset, nvm_data, i; |
Bill Hayes | 93ca161 | 2007-10-31 15:21:52 -0700 | [diff] [blame] | 2027 | u16 mac_addr_offset = 0; |
| 2028 | |
| 2029 | if (hw->mac.type == e1000_82571) { |
| 2030 | /* Check for an alternate MAC address. An alternate MAC |
| 2031 | * address can be setup by pre-boot software and must be |
| 2032 | * treated like a permanent address and must override the |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2033 | * actual permanent MAC address.*/ |
Bill Hayes | 93ca161 | 2007-10-31 15:21:52 -0700 | [diff] [blame] | 2034 | ret_val = e1000_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1, |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2035 | &mac_addr_offset); |
Bill Hayes | 93ca161 | 2007-10-31 15:21:52 -0700 | [diff] [blame] | 2036 | if (ret_val) { |
| 2037 | hw_dbg(hw, "NVM Read Error\n"); |
| 2038 | return ret_val; |
| 2039 | } |
| 2040 | if (mac_addr_offset == 0xFFFF) |
| 2041 | mac_addr_offset = 0; |
| 2042 | |
| 2043 | if (mac_addr_offset) { |
| 2044 | if (hw->bus.func == E1000_FUNC_1) |
| 2045 | mac_addr_offset += ETH_ALEN/sizeof(u16); |
| 2046 | |
| 2047 | /* make sure we have a valid mac address here |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2048 | * before using it */ |
Bill Hayes | 93ca161 | 2007-10-31 15:21:52 -0700 | [diff] [blame] | 2049 | ret_val = e1000_read_nvm(hw, mac_addr_offset, 1, |
| 2050 | &nvm_data); |
| 2051 | if (ret_val) { |
| 2052 | hw_dbg(hw, "NVM Read Error\n"); |
| 2053 | return ret_val; |
| 2054 | } |
| 2055 | if (nvm_data & 0x0001) |
| 2056 | mac_addr_offset = 0; |
| 2057 | } |
| 2058 | |
| 2059 | if (mac_addr_offset) |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2060 | hw->dev_spec.e82571.alt_mac_addr_is_present = 1; |
Bill Hayes | 93ca161 | 2007-10-31 15:21:52 -0700 | [diff] [blame] | 2061 | } |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2062 | |
| 2063 | for (i = 0; i < ETH_ALEN; i += 2) { |
Bill Hayes | 93ca161 | 2007-10-31 15:21:52 -0700 | [diff] [blame] | 2064 | offset = mac_addr_offset + (i >> 1); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2065 | ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data); |
| 2066 | if (ret_val) { |
| 2067 | hw_dbg(hw, "NVM Read Error\n"); |
| 2068 | return ret_val; |
| 2069 | } |
| 2070 | hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF); |
| 2071 | hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8); |
| 2072 | } |
| 2073 | |
| 2074 | /* Flip last bit of mac address if we're on second port */ |
Bill Hayes | 93ca161 | 2007-10-31 15:21:52 -0700 | [diff] [blame] | 2075 | if (!mac_addr_offset && hw->bus.func == E1000_FUNC_1) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2076 | hw->mac.perm_addr[5] ^= 1; |
| 2077 | |
| 2078 | for (i = 0; i < ETH_ALEN; i++) |
| 2079 | hw->mac.addr[i] = hw->mac.perm_addr[i]; |
| 2080 | |
| 2081 | return 0; |
| 2082 | } |
| 2083 | |
| 2084 | /** |
| 2085 | * e1000e_validate_nvm_checksum_generic - Validate EEPROM checksum |
| 2086 | * @hw: pointer to the HW structure |
| 2087 | * |
| 2088 | * Calculates the EEPROM checksum by reading/adding each word of the EEPROM |
| 2089 | * and then verifies that the sum of the EEPROM is equal to 0xBABA. |
| 2090 | **/ |
| 2091 | s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw) |
| 2092 | { |
| 2093 | s32 ret_val; |
| 2094 | u16 checksum = 0; |
| 2095 | u16 i, nvm_data; |
| 2096 | |
| 2097 | for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) { |
| 2098 | ret_val = e1000_read_nvm(hw, i, 1, &nvm_data); |
| 2099 | if (ret_val) { |
| 2100 | hw_dbg(hw, "NVM Read Error\n"); |
| 2101 | return ret_val; |
| 2102 | } |
| 2103 | checksum += nvm_data; |
| 2104 | } |
| 2105 | |
| 2106 | if (checksum != (u16) NVM_SUM) { |
| 2107 | hw_dbg(hw, "NVM Checksum Invalid\n"); |
| 2108 | return -E1000_ERR_NVM; |
| 2109 | } |
| 2110 | |
| 2111 | return 0; |
| 2112 | } |
| 2113 | |
| 2114 | /** |
| 2115 | * e1000e_update_nvm_checksum_generic - Update EEPROM checksum |
| 2116 | * @hw: pointer to the HW structure |
| 2117 | * |
| 2118 | * Updates the EEPROM checksum by reading/adding each word of the EEPROM |
| 2119 | * up to the checksum. Then calculates the EEPROM checksum and writes the |
| 2120 | * value to the EEPROM. |
| 2121 | **/ |
| 2122 | s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw) |
| 2123 | { |
| 2124 | s32 ret_val; |
| 2125 | u16 checksum = 0; |
| 2126 | u16 i, nvm_data; |
| 2127 | |
| 2128 | for (i = 0; i < NVM_CHECKSUM_REG; i++) { |
| 2129 | ret_val = e1000_read_nvm(hw, i, 1, &nvm_data); |
| 2130 | if (ret_val) { |
| 2131 | hw_dbg(hw, "NVM Read Error while updating checksum.\n"); |
| 2132 | return ret_val; |
| 2133 | } |
| 2134 | checksum += nvm_data; |
| 2135 | } |
| 2136 | checksum = (u16) NVM_SUM - checksum; |
| 2137 | ret_val = e1000_write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum); |
| 2138 | if (ret_val) |
| 2139 | hw_dbg(hw, "NVM Write Error while updating checksum.\n"); |
| 2140 | |
| 2141 | return ret_val; |
| 2142 | } |
| 2143 | |
| 2144 | /** |
| 2145 | * e1000e_reload_nvm - Reloads EEPROM |
| 2146 | * @hw: pointer to the HW structure |
| 2147 | * |
| 2148 | * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the |
| 2149 | * extended control register. |
| 2150 | **/ |
| 2151 | void e1000e_reload_nvm(struct e1000_hw *hw) |
| 2152 | { |
| 2153 | u32 ctrl_ext; |
| 2154 | |
| 2155 | udelay(10); |
| 2156 | ctrl_ext = er32(CTRL_EXT); |
| 2157 | ctrl_ext |= E1000_CTRL_EXT_EE_RST; |
| 2158 | ew32(CTRL_EXT, ctrl_ext); |
| 2159 | e1e_flush(); |
| 2160 | } |
| 2161 | |
| 2162 | /** |
| 2163 | * e1000_calculate_checksum - Calculate checksum for buffer |
| 2164 | * @buffer: pointer to EEPROM |
| 2165 | * @length: size of EEPROM to calculate a checksum for |
| 2166 | * |
| 2167 | * Calculates the checksum for some buffer on a specified length. The |
| 2168 | * checksum calculated is returned. |
| 2169 | **/ |
| 2170 | static u8 e1000_calculate_checksum(u8 *buffer, u32 length) |
| 2171 | { |
| 2172 | u32 i; |
| 2173 | u8 sum = 0; |
| 2174 | |
| 2175 | if (!buffer) |
| 2176 | return 0; |
| 2177 | |
| 2178 | for (i = 0; i < length; i++) |
| 2179 | sum += buffer[i]; |
| 2180 | |
| 2181 | return (u8) (0 - sum); |
| 2182 | } |
| 2183 | |
| 2184 | /** |
| 2185 | * e1000_mng_enable_host_if - Checks host interface is enabled |
| 2186 | * @hw: pointer to the HW structure |
| 2187 | * |
| 2188 | * Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND |
| 2189 | * |
Auke Kok | 489815c | 2008-02-21 15:11:07 -0800 | [diff] [blame] | 2190 | * This function checks whether the HOST IF is enabled for command operation |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2191 | * and also checks whether the previous command is completed. It busy waits |
| 2192 | * in case of previous command is not completed. |
| 2193 | **/ |
| 2194 | static s32 e1000_mng_enable_host_if(struct e1000_hw *hw) |
| 2195 | { |
| 2196 | u32 hicr; |
| 2197 | u8 i; |
| 2198 | |
| 2199 | /* Check that the host interface is enabled. */ |
| 2200 | hicr = er32(HICR); |
| 2201 | if ((hicr & E1000_HICR_EN) == 0) { |
| 2202 | hw_dbg(hw, "E1000_HOST_EN bit disabled.\n"); |
| 2203 | return -E1000_ERR_HOST_INTERFACE_COMMAND; |
| 2204 | } |
| 2205 | /* check the previous command is completed */ |
| 2206 | for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) { |
| 2207 | hicr = er32(HICR); |
| 2208 | if (!(hicr & E1000_HICR_C)) |
| 2209 | break; |
| 2210 | mdelay(1); |
| 2211 | } |
| 2212 | |
| 2213 | if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) { |
| 2214 | hw_dbg(hw, "Previous command timeout failed .\n"); |
| 2215 | return -E1000_ERR_HOST_INTERFACE_COMMAND; |
| 2216 | } |
| 2217 | |
| 2218 | return 0; |
| 2219 | } |
| 2220 | |
| 2221 | /** |
Bruce Allan | 4662e82 | 2008-08-26 18:37:06 -0700 | [diff] [blame] | 2222 | * e1000e_check_mng_mode_generic - check management mode |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2223 | * @hw: pointer to the HW structure |
| 2224 | * |
| 2225 | * Reads the firmware semaphore register and returns true (>0) if |
| 2226 | * manageability is enabled, else false (0). |
| 2227 | **/ |
Bruce Allan | 4662e82 | 2008-08-26 18:37:06 -0700 | [diff] [blame] | 2228 | bool e1000e_check_mng_mode_generic(struct e1000_hw *hw) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2229 | { |
| 2230 | u32 fwsm = er32(FWSM); |
| 2231 | |
Bruce Allan | 4662e82 | 2008-08-26 18:37:06 -0700 | [diff] [blame] | 2232 | return (fwsm & E1000_FWSM_MODE_MASK) == |
| 2233 | (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2234 | } |
| 2235 | |
| 2236 | /** |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2237 | * e1000e_enable_tx_pkt_filtering - Enable packet filtering on Tx |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2238 | * @hw: pointer to the HW structure |
| 2239 | * |
| 2240 | * Enables packet filtering on transmit packets if manageability is enabled |
| 2241 | * and host interface is enabled. |
| 2242 | **/ |
| 2243 | bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw) |
| 2244 | { |
| 2245 | struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie; |
| 2246 | u32 *buffer = (u32 *)&hw->mng_cookie; |
| 2247 | u32 offset; |
| 2248 | s32 ret_val, hdr_csum, csum; |
| 2249 | u8 i, len; |
| 2250 | |
| 2251 | /* No manageability, no filtering */ |
| 2252 | if (!e1000e_check_mng_mode(hw)) { |
| 2253 | hw->mac.tx_pkt_filtering = 0; |
| 2254 | return 0; |
| 2255 | } |
| 2256 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2257 | /* |
| 2258 | * If we can't read from the host interface for whatever |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2259 | * reason, disable filtering. |
| 2260 | */ |
| 2261 | ret_val = e1000_mng_enable_host_if(hw); |
| 2262 | if (ret_val != 0) { |
| 2263 | hw->mac.tx_pkt_filtering = 0; |
| 2264 | return ret_val; |
| 2265 | } |
| 2266 | |
| 2267 | /* Read in the header. Length and offset are in dwords. */ |
| 2268 | len = E1000_MNG_DHCP_COOKIE_LENGTH >> 2; |
| 2269 | offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2; |
| 2270 | for (i = 0; i < len; i++) |
| 2271 | *(buffer + i) = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset + i); |
| 2272 | hdr_csum = hdr->checksum; |
| 2273 | hdr->checksum = 0; |
| 2274 | csum = e1000_calculate_checksum((u8 *)hdr, |
| 2275 | E1000_MNG_DHCP_COOKIE_LENGTH); |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2276 | /* |
| 2277 | * If either the checksums or signature don't match, then |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2278 | * the cookie area isn't considered valid, in which case we |
| 2279 | * take the safe route of assuming Tx filtering is enabled. |
| 2280 | */ |
| 2281 | if ((hdr_csum != csum) || (hdr->signature != E1000_IAMT_SIGNATURE)) { |
| 2282 | hw->mac.tx_pkt_filtering = 1; |
| 2283 | return 1; |
| 2284 | } |
| 2285 | |
| 2286 | /* Cookie area is valid, make the final check for filtering. */ |
| 2287 | if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING)) { |
| 2288 | hw->mac.tx_pkt_filtering = 0; |
| 2289 | return 0; |
| 2290 | } |
| 2291 | |
| 2292 | hw->mac.tx_pkt_filtering = 1; |
| 2293 | return 1; |
| 2294 | } |
| 2295 | |
| 2296 | /** |
| 2297 | * e1000_mng_write_cmd_header - Writes manageability command header |
| 2298 | * @hw: pointer to the HW structure |
| 2299 | * @hdr: pointer to the host interface command header |
| 2300 | * |
| 2301 | * Writes the command header after does the checksum calculation. |
| 2302 | **/ |
| 2303 | static s32 e1000_mng_write_cmd_header(struct e1000_hw *hw, |
| 2304 | struct e1000_host_mng_command_header *hdr) |
| 2305 | { |
| 2306 | u16 i, length = sizeof(struct e1000_host_mng_command_header); |
| 2307 | |
| 2308 | /* Write the whole command header structure with new checksum. */ |
| 2309 | |
| 2310 | hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length); |
| 2311 | |
| 2312 | length >>= 2; |
| 2313 | /* Write the relevant command block into the ram area. */ |
| 2314 | for (i = 0; i < length; i++) { |
| 2315 | E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, i, |
| 2316 | *((u32 *) hdr + i)); |
| 2317 | e1e_flush(); |
| 2318 | } |
| 2319 | |
| 2320 | return 0; |
| 2321 | } |
| 2322 | |
| 2323 | /** |
| 2324 | * e1000_mng_host_if_write - Writes to the manageability host interface |
| 2325 | * @hw: pointer to the HW structure |
| 2326 | * @buffer: pointer to the host interface buffer |
| 2327 | * @length: size of the buffer |
| 2328 | * @offset: location in the buffer to write to |
| 2329 | * @sum: sum of the data (not checksum) |
| 2330 | * |
| 2331 | * This function writes the buffer content at the offset given on the host if. |
| 2332 | * It also does alignment considerations to do the writes in most efficient |
| 2333 | * way. Also fills up the sum of the buffer in *buffer parameter. |
| 2334 | **/ |
| 2335 | static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, |
| 2336 | u16 length, u16 offset, u8 *sum) |
| 2337 | { |
| 2338 | u8 *tmp; |
| 2339 | u8 *bufptr = buffer; |
| 2340 | u32 data = 0; |
| 2341 | u16 remaining, i, j, prev_bytes; |
| 2342 | |
| 2343 | /* sum = only sum of the data and it is not checksum */ |
| 2344 | |
| 2345 | if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) |
| 2346 | return -E1000_ERR_PARAM; |
| 2347 | |
| 2348 | tmp = (u8 *)&data; |
| 2349 | prev_bytes = offset & 0x3; |
| 2350 | offset >>= 2; |
| 2351 | |
| 2352 | if (prev_bytes) { |
| 2353 | data = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset); |
| 2354 | for (j = prev_bytes; j < sizeof(u32); j++) { |
| 2355 | *(tmp + j) = *bufptr++; |
| 2356 | *sum += *(tmp + j); |
| 2357 | } |
| 2358 | E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset, data); |
| 2359 | length -= j - prev_bytes; |
| 2360 | offset++; |
| 2361 | } |
| 2362 | |
| 2363 | remaining = length & 0x3; |
| 2364 | length -= remaining; |
| 2365 | |
| 2366 | /* Calculate length in DWORDs */ |
| 2367 | length >>= 2; |
| 2368 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2369 | /* |
| 2370 | * The device driver writes the relevant command block into the |
| 2371 | * ram area. |
| 2372 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2373 | for (i = 0; i < length; i++) { |
| 2374 | for (j = 0; j < sizeof(u32); j++) { |
| 2375 | *(tmp + j) = *bufptr++; |
| 2376 | *sum += *(tmp + j); |
| 2377 | } |
| 2378 | |
| 2379 | E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data); |
| 2380 | } |
| 2381 | if (remaining) { |
| 2382 | for (j = 0; j < sizeof(u32); j++) { |
| 2383 | if (j < remaining) |
| 2384 | *(tmp + j) = *bufptr++; |
| 2385 | else |
| 2386 | *(tmp + j) = 0; |
| 2387 | |
| 2388 | *sum += *(tmp + j); |
| 2389 | } |
| 2390 | E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data); |
| 2391 | } |
| 2392 | |
| 2393 | return 0; |
| 2394 | } |
| 2395 | |
| 2396 | /** |
| 2397 | * e1000e_mng_write_dhcp_info - Writes DHCP info to host interface |
| 2398 | * @hw: pointer to the HW structure |
| 2399 | * @buffer: pointer to the host interface |
| 2400 | * @length: size of the buffer |
| 2401 | * |
| 2402 | * Writes the DHCP information to the host interface. |
| 2403 | **/ |
| 2404 | s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length) |
| 2405 | { |
| 2406 | struct e1000_host_mng_command_header hdr; |
| 2407 | s32 ret_val; |
| 2408 | u32 hicr; |
| 2409 | |
| 2410 | hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD; |
| 2411 | hdr.command_length = length; |
| 2412 | hdr.reserved1 = 0; |
| 2413 | hdr.reserved2 = 0; |
| 2414 | hdr.checksum = 0; |
| 2415 | |
| 2416 | /* Enable the host interface */ |
| 2417 | ret_val = e1000_mng_enable_host_if(hw); |
| 2418 | if (ret_val) |
| 2419 | return ret_val; |
| 2420 | |
| 2421 | /* Populate the host interface with the contents of "buffer". */ |
| 2422 | ret_val = e1000_mng_host_if_write(hw, buffer, length, |
| 2423 | sizeof(hdr), &(hdr.checksum)); |
| 2424 | if (ret_val) |
| 2425 | return ret_val; |
| 2426 | |
| 2427 | /* Write the manageability command header */ |
| 2428 | ret_val = e1000_mng_write_cmd_header(hw, &hdr); |
| 2429 | if (ret_val) |
| 2430 | return ret_val; |
| 2431 | |
| 2432 | /* Tell the ARC a new command is pending. */ |
| 2433 | hicr = er32(HICR); |
| 2434 | ew32(HICR, hicr | E1000_HICR_C); |
| 2435 | |
| 2436 | return 0; |
| 2437 | } |
| 2438 | |
| 2439 | /** |
| 2440 | * e1000e_enable_mng_pass_thru - Enable processing of ARP's |
| 2441 | * @hw: pointer to the HW structure |
| 2442 | * |
| 2443 | * Verifies the hardware needs to allow ARPs to be processed by the host. |
| 2444 | **/ |
| 2445 | bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw) |
| 2446 | { |
| 2447 | u32 manc; |
| 2448 | u32 fwsm, factps; |
| 2449 | bool ret_val = 0; |
| 2450 | |
| 2451 | manc = er32(MANC); |
| 2452 | |
| 2453 | if (!(manc & E1000_MANC_RCV_TCO_EN) || |
| 2454 | !(manc & E1000_MANC_EN_MAC_ADDR_FILTER)) |
| 2455 | return ret_val; |
| 2456 | |
| 2457 | if (hw->mac.arc_subsystem_valid) { |
| 2458 | fwsm = er32(FWSM); |
| 2459 | factps = er32(FACTPS); |
| 2460 | |
| 2461 | if (!(factps & E1000_FACTPS_MNGCG) && |
| 2462 | ((fwsm & E1000_FWSM_MODE_MASK) == |
| 2463 | (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) { |
| 2464 | ret_val = 1; |
| 2465 | return ret_val; |
| 2466 | } |
| 2467 | } else { |
| 2468 | if ((manc & E1000_MANC_SMBUS_EN) && |
| 2469 | !(manc & E1000_MANC_ASF_EN)) { |
| 2470 | ret_val = 1; |
| 2471 | return ret_val; |
| 2472 | } |
| 2473 | } |
| 2474 | |
| 2475 | return ret_val; |
| 2476 | } |
| 2477 | |
Jeff Kirsher | 69e3fd8 | 2008-04-02 13:48:18 -0700 | [diff] [blame] | 2478 | s32 e1000e_read_pba_num(struct e1000_hw *hw, u32 *pba_num) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2479 | { |
| 2480 | s32 ret_val; |
| 2481 | u16 nvm_data; |
| 2482 | |
| 2483 | ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); |
| 2484 | if (ret_val) { |
| 2485 | hw_dbg(hw, "NVM Read Error\n"); |
| 2486 | return ret_val; |
| 2487 | } |
Jeff Kirsher | 69e3fd8 | 2008-04-02 13:48:18 -0700 | [diff] [blame] | 2488 | *pba_num = (u32)(nvm_data << 16); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2489 | |
| 2490 | ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_1, 1, &nvm_data); |
| 2491 | if (ret_val) { |
| 2492 | hw_dbg(hw, "NVM Read Error\n"); |
| 2493 | return ret_val; |
| 2494 | } |
Jeff Kirsher | 69e3fd8 | 2008-04-02 13:48:18 -0700 | [diff] [blame] | 2495 | *pba_num |= nvm_data; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2496 | |
| 2497 | return 0; |
| 2498 | } |