Ian Molton | ec43b81 | 2008-07-15 16:04:22 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Toshiba TMIO NAND flash controller driver |
| 3 | * |
| 4 | * Slightly murky pre-git history of the driver: |
| 5 | * |
| 6 | * Copyright (c) Ian Molton 2004, 2005, 2008 |
| 7 | * Original work, independant of sharps code. Included hardware ECC support. |
| 8 | * Hard ECC did not work for writes in the early revisions. |
| 9 | * Copyright (c) Dirk Opfer 2005. |
| 10 | * Modifications developed from sharps code but |
| 11 | * NOT containing any, ported onto Ians base. |
| 12 | * Copyright (c) Chris Humbert 2005 |
| 13 | * Copyright (c) Dmitry Baryshkov 2008 |
| 14 | * Minor fixes |
| 15 | * |
| 16 | * Parts copyright Sebastian Carlier |
| 17 | * |
| 18 | * This file is licensed under |
| 19 | * the terms of the GNU General Public License version 2. This program |
| 20 | * is licensed "as is" without any warranty of any kind, whether express |
| 21 | * or implied. |
| 22 | * |
| 23 | */ |
| 24 | |
| 25 | |
| 26 | #include <linux/kernel.h> |
| 27 | #include <linux/module.h> |
| 28 | #include <linux/platform_device.h> |
| 29 | #include <linux/mfd/core.h> |
| 30 | #include <linux/mfd/tmio.h> |
| 31 | #include <linux/delay.h> |
| 32 | #include <linux/io.h> |
| 33 | #include <linux/irq.h> |
| 34 | #include <linux/interrupt.h> |
| 35 | #include <linux/ioport.h> |
| 36 | #include <linux/mtd/mtd.h> |
| 37 | #include <linux/mtd/nand.h> |
| 38 | #include <linux/mtd/nand_ecc.h> |
| 39 | #include <linux/mtd/partitions.h> |
| 40 | |
| 41 | /*--------------------------------------------------------------------------*/ |
| 42 | |
| 43 | /* |
| 44 | * NAND Flash Host Controller Configuration Register |
| 45 | */ |
| 46 | #define CCR_COMMAND 0x04 /* w Command */ |
| 47 | #define CCR_BASE 0x10 /* l NAND Flash Control Reg Base Addr */ |
| 48 | #define CCR_INTP 0x3d /* b Interrupt Pin */ |
| 49 | #define CCR_INTE 0x48 /* b Interrupt Enable */ |
| 50 | #define CCR_EC 0x4a /* b Event Control */ |
| 51 | #define CCR_ICC 0x4c /* b Internal Clock Control */ |
| 52 | #define CCR_ECCC 0x5b /* b ECC Control */ |
| 53 | #define CCR_NFTC 0x60 /* b NAND Flash Transaction Control */ |
| 54 | #define CCR_NFM 0x61 /* b NAND Flash Monitor */ |
| 55 | #define CCR_NFPSC 0x62 /* b NAND Flash Power Supply Control */ |
| 56 | #define CCR_NFDC 0x63 /* b NAND Flash Detect Control */ |
| 57 | |
| 58 | /* |
| 59 | * NAND Flash Control Register |
| 60 | */ |
| 61 | #define FCR_DATA 0x00 /* bwl Data Register */ |
| 62 | #define FCR_MODE 0x04 /* b Mode Register */ |
| 63 | #define FCR_STATUS 0x05 /* b Status Register */ |
| 64 | #define FCR_ISR 0x06 /* b Interrupt Status Register */ |
| 65 | #define FCR_IMR 0x07 /* b Interrupt Mask Register */ |
| 66 | |
| 67 | /* FCR_MODE Register Command List */ |
| 68 | #define FCR_MODE_DATA 0x94 /* Data Data_Mode */ |
| 69 | #define FCR_MODE_COMMAND 0x95 /* Data Command_Mode */ |
| 70 | #define FCR_MODE_ADDRESS 0x96 /* Data Address_Mode */ |
| 71 | |
| 72 | #define FCR_MODE_HWECC_CALC 0xB4 /* HW-ECC Data */ |
| 73 | #define FCR_MODE_HWECC_RESULT 0xD4 /* HW-ECC Calc result Read_Mode */ |
| 74 | #define FCR_MODE_HWECC_RESET 0xF4 /* HW-ECC Reset */ |
| 75 | |
| 76 | #define FCR_MODE_POWER_ON 0x0C /* Power Supply ON to SSFDC card */ |
| 77 | #define FCR_MODE_POWER_OFF 0x08 /* Power Supply OFF to SSFDC card */ |
| 78 | |
| 79 | #define FCR_MODE_LED_OFF 0x00 /* LED OFF */ |
| 80 | #define FCR_MODE_LED_ON 0x04 /* LED ON */ |
| 81 | |
| 82 | #define FCR_MODE_EJECT_ON 0x68 /* Ejection events active */ |
| 83 | #define FCR_MODE_EJECT_OFF 0x08 /* Ejection events ignored */ |
| 84 | |
| 85 | #define FCR_MODE_LOCK 0x6C /* Lock_Mode. Eject Switch Invalid */ |
| 86 | #define FCR_MODE_UNLOCK 0x0C /* UnLock_Mode. Eject Switch is valid */ |
| 87 | |
| 88 | #define FCR_MODE_CONTROLLER_ID 0x40 /* Controller ID Read */ |
| 89 | #define FCR_MODE_STANDBY 0x00 /* SSFDC card Changes Standby State */ |
| 90 | |
| 91 | #define FCR_MODE_WE 0x80 |
| 92 | #define FCR_MODE_ECC1 0x40 |
| 93 | #define FCR_MODE_ECC0 0x20 |
| 94 | #define FCR_MODE_CE 0x10 |
| 95 | #define FCR_MODE_PCNT1 0x08 |
| 96 | #define FCR_MODE_PCNT0 0x04 |
| 97 | #define FCR_MODE_ALE 0x02 |
| 98 | #define FCR_MODE_CLE 0x01 |
| 99 | |
| 100 | #define FCR_STATUS_BUSY 0x80 |
| 101 | |
| 102 | /*--------------------------------------------------------------------------*/ |
| 103 | |
| 104 | struct tmio_nand { |
| 105 | struct mtd_info mtd; |
| 106 | struct nand_chip chip; |
| 107 | |
| 108 | struct platform_device *dev; |
| 109 | |
| 110 | void __iomem *ccr; |
| 111 | void __iomem *fcr; |
Dmitry Baryshkov | 076c7f4 | 2008-09-04 13:28:33 +0400 | [diff] [blame] | 112 | unsigned long fcr_base; |
Ian Molton | ec43b81 | 2008-07-15 16:04:22 +0100 | [diff] [blame] | 113 | |
| 114 | unsigned int irq; |
| 115 | |
| 116 | /* for tmio_nand_read_byte */ |
| 117 | u8 read; |
| 118 | unsigned read_good:1; |
| 119 | }; |
| 120 | |
| 121 | #define mtd_to_tmio(m) container_of(m, struct tmio_nand, mtd) |
| 122 | |
| 123 | #ifdef CONFIG_MTD_CMDLINE_PARTS |
| 124 | static const char *part_probes[] = { "cmdlinepart", NULL }; |
| 125 | #endif |
| 126 | |
| 127 | /*--------------------------------------------------------------------------*/ |
| 128 | |
| 129 | static void tmio_nand_hwcontrol(struct mtd_info *mtd, int cmd, |
| 130 | unsigned int ctrl) |
| 131 | { |
| 132 | struct tmio_nand *tmio = mtd_to_tmio(mtd); |
| 133 | struct nand_chip *chip = mtd->priv; |
| 134 | |
| 135 | if (ctrl & NAND_CTRL_CHANGE) { |
| 136 | u8 mode; |
| 137 | |
| 138 | if (ctrl & NAND_NCE) { |
| 139 | mode = FCR_MODE_DATA; |
| 140 | |
| 141 | if (ctrl & NAND_CLE) |
| 142 | mode |= FCR_MODE_CLE; |
| 143 | else |
| 144 | mode &= ~FCR_MODE_CLE; |
| 145 | |
| 146 | if (ctrl & NAND_ALE) |
| 147 | mode |= FCR_MODE_ALE; |
| 148 | else |
| 149 | mode &= ~FCR_MODE_ALE; |
| 150 | } else { |
| 151 | mode = FCR_MODE_STANDBY; |
| 152 | } |
| 153 | |
| 154 | tmio_iowrite8(mode, tmio->fcr + FCR_MODE); |
| 155 | tmio->read_good = 0; |
| 156 | } |
| 157 | |
| 158 | if (cmd != NAND_CMD_NONE) |
| 159 | tmio_iowrite8(cmd, chip->IO_ADDR_W); |
| 160 | } |
| 161 | |
| 162 | static int tmio_nand_dev_ready(struct mtd_info *mtd) |
| 163 | { |
| 164 | struct tmio_nand *tmio = mtd_to_tmio(mtd); |
| 165 | |
| 166 | return !(tmio_ioread8(tmio->fcr + FCR_STATUS) & FCR_STATUS_BUSY); |
| 167 | } |
| 168 | |
| 169 | static irqreturn_t tmio_irq(int irq, void *__tmio) |
| 170 | { |
| 171 | struct tmio_nand *tmio = __tmio; |
| 172 | struct nand_chip *nand_chip = &tmio->chip; |
| 173 | |
| 174 | /* disable RDYREQ interrupt */ |
| 175 | tmio_iowrite8(0x00, tmio->fcr + FCR_IMR); |
| 176 | |
| 177 | if (unlikely(!waitqueue_active(&nand_chip->controller->wq))) |
| 178 | dev_warn(&tmio->dev->dev, "spurious interrupt\n"); |
| 179 | |
| 180 | wake_up(&nand_chip->controller->wq); |
| 181 | return IRQ_HANDLED; |
| 182 | } |
| 183 | |
| 184 | /* |
| 185 | *The TMIO core has a RDYREQ interrupt on the posedge of #SMRB. |
| 186 | *This interrupt is normally disabled, but for long operations like |
| 187 | *erase and write, we enable it to wake us up. The irq handler |
| 188 | *disables the interrupt. |
| 189 | */ |
| 190 | static int |
| 191 | tmio_nand_wait(struct mtd_info *mtd, struct nand_chip *nand_chip) |
| 192 | { |
| 193 | struct tmio_nand *tmio = mtd_to_tmio(mtd); |
| 194 | long timeout; |
| 195 | |
| 196 | /* enable RDYREQ interrupt */ |
| 197 | tmio_iowrite8(0x0f, tmio->fcr + FCR_ISR); |
| 198 | tmio_iowrite8(0x81, tmio->fcr + FCR_IMR); |
| 199 | |
| 200 | timeout = wait_event_timeout(nand_chip->controller->wq, |
| 201 | tmio_nand_dev_ready(mtd), |
| 202 | msecs_to_jiffies(nand_chip->state == FL_ERASING ? 400 : 20)); |
| 203 | |
| 204 | if (unlikely(!tmio_nand_dev_ready(mtd))) { |
| 205 | tmio_iowrite8(0x00, tmio->fcr + FCR_IMR); |
| 206 | dev_warn(&tmio->dev->dev, "still busy with %s after %d ms\n", |
| 207 | nand_chip->state == FL_ERASING ? "erase" : "program", |
| 208 | nand_chip->state == FL_ERASING ? 400 : 20); |
| 209 | |
| 210 | } else if (unlikely(!timeout)) { |
| 211 | tmio_iowrite8(0x00, tmio->fcr + FCR_IMR); |
| 212 | dev_warn(&tmio->dev->dev, "timeout waiting for interrupt\n"); |
| 213 | } |
| 214 | |
| 215 | nand_chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
| 216 | return nand_chip->read_byte(mtd); |
| 217 | } |
| 218 | |
| 219 | /* |
| 220 | *The TMIO controller combines two 8-bit data bytes into one 16-bit |
| 221 | *word. This function separates them so nand_base.c works as expected, |
| 222 | *especially its NAND_CMD_READID routines. |
| 223 | * |
| 224 | *To prevent stale data from being read, tmio_nand_hwcontrol() clears |
| 225 | *tmio->read_good. |
| 226 | */ |
| 227 | static u_char tmio_nand_read_byte(struct mtd_info *mtd) |
| 228 | { |
| 229 | struct tmio_nand *tmio = mtd_to_tmio(mtd); |
| 230 | unsigned int data; |
| 231 | |
| 232 | if (tmio->read_good--) |
| 233 | return tmio->read; |
| 234 | |
| 235 | data = tmio_ioread16(tmio->fcr + FCR_DATA); |
| 236 | tmio->read = data >> 8; |
| 237 | return data; |
| 238 | } |
| 239 | |
| 240 | /* |
| 241 | *The TMIO controller converts an 8-bit NAND interface to a 16-bit |
| 242 | *bus interface, so all data reads and writes must be 16-bit wide. |
| 243 | *Thus, we implement 16-bit versions of the read, write, and verify |
| 244 | *buffer functions. |
| 245 | */ |
| 246 | static void |
| 247 | tmio_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) |
| 248 | { |
| 249 | struct tmio_nand *tmio = mtd_to_tmio(mtd); |
| 250 | |
| 251 | tmio_iowrite16_rep(tmio->fcr + FCR_DATA, buf, len >> 1); |
| 252 | } |
| 253 | |
| 254 | static void tmio_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) |
| 255 | { |
| 256 | struct tmio_nand *tmio = mtd_to_tmio(mtd); |
| 257 | |
| 258 | tmio_ioread16_rep(tmio->fcr + FCR_DATA, buf, len >> 1); |
| 259 | } |
| 260 | |
| 261 | static int |
| 262 | tmio_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) |
| 263 | { |
| 264 | struct tmio_nand *tmio = mtd_to_tmio(mtd); |
| 265 | u16 *p = (u16 *) buf; |
| 266 | |
| 267 | for (len >>= 1; len; len--) |
| 268 | if (*(p++) != tmio_ioread16(tmio->fcr + FCR_DATA)) |
| 269 | return -EFAULT; |
| 270 | return 0; |
| 271 | } |
| 272 | |
| 273 | static void tmio_nand_enable_hwecc(struct mtd_info *mtd, int mode) |
| 274 | { |
| 275 | struct tmio_nand *tmio = mtd_to_tmio(mtd); |
| 276 | |
| 277 | tmio_iowrite8(FCR_MODE_HWECC_RESET, tmio->fcr + FCR_MODE); |
| 278 | tmio_ioread8(tmio->fcr + FCR_DATA); /* dummy read */ |
| 279 | tmio_iowrite8(FCR_MODE_HWECC_CALC, tmio->fcr + FCR_MODE); |
| 280 | } |
| 281 | |
| 282 | static int tmio_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, |
| 283 | u_char *ecc_code) |
| 284 | { |
| 285 | struct tmio_nand *tmio = mtd_to_tmio(mtd); |
| 286 | unsigned int ecc; |
| 287 | |
| 288 | tmio_iowrite8(FCR_MODE_HWECC_RESULT, tmio->fcr + FCR_MODE); |
| 289 | |
| 290 | ecc = tmio_ioread16(tmio->fcr + FCR_DATA); |
| 291 | ecc_code[1] = ecc; /* 000-255 LP7-0 */ |
| 292 | ecc_code[0] = ecc >> 8; /* 000-255 LP15-8 */ |
| 293 | ecc = tmio_ioread16(tmio->fcr + FCR_DATA); |
| 294 | ecc_code[2] = ecc; /* 000-255 CP5-0,11b */ |
| 295 | ecc_code[4] = ecc >> 8; /* 256-511 LP7-0 */ |
| 296 | ecc = tmio_ioread16(tmio->fcr + FCR_DATA); |
| 297 | ecc_code[3] = ecc; /* 256-511 LP15-8 */ |
| 298 | ecc_code[5] = ecc >> 8; /* 256-511 CP5-0,11b */ |
| 299 | |
| 300 | tmio_iowrite8(FCR_MODE_DATA, tmio->fcr + FCR_MODE); |
| 301 | return 0; |
| 302 | } |
| 303 | |
Atsushi Nemoto | 0f777fb | 2009-09-05 01:20:44 +0900 | [diff] [blame] | 304 | static int tmio_nand_correct_data(struct mtd_info *mtd, unsigned char *buf, |
| 305 | unsigned char *read_ecc, unsigned char *calc_ecc) |
| 306 | { |
| 307 | int r0, r1; |
| 308 | |
| 309 | /* assume ecc.size = 512 and ecc.bytes = 6 */ |
| 310 | r0 = __nand_correct_data(buf, read_ecc, calc_ecc, 256); |
| 311 | if (r0 < 0) |
| 312 | return r0; |
| 313 | r1 = __nand_correct_data(buf + 256, read_ecc + 3, calc_ecc + 3, 256); |
| 314 | if (r1 < 0) |
| 315 | return r1; |
| 316 | return r0 + r1; |
| 317 | } |
| 318 | |
Ian Molton | ec43b81 | 2008-07-15 16:04:22 +0100 | [diff] [blame] | 319 | static int tmio_hw_init(struct platform_device *dev, struct tmio_nand *tmio) |
| 320 | { |
| 321 | struct mfd_cell *cell = (struct mfd_cell *)dev->dev.platform_data; |
| 322 | int ret; |
| 323 | |
| 324 | if (cell->enable) { |
| 325 | ret = cell->enable(dev); |
| 326 | if (ret) |
| 327 | return ret; |
| 328 | } |
| 329 | |
| 330 | /* (4Ch) CLKRUN Enable 1st spcrunc */ |
| 331 | tmio_iowrite8(0x81, tmio->ccr + CCR_ICC); |
| 332 | |
| 333 | /* (10h)BaseAddress 0x1000 spba.spba2 */ |
Dmitry Baryshkov | 076c7f4 | 2008-09-04 13:28:33 +0400 | [diff] [blame] | 334 | tmio_iowrite16(tmio->fcr_base, tmio->ccr + CCR_BASE); |
| 335 | tmio_iowrite16(tmio->fcr_base >> 16, tmio->ccr + CCR_BASE + 2); |
Ian Molton | ec43b81 | 2008-07-15 16:04:22 +0100 | [diff] [blame] | 336 | |
| 337 | /* (04h)Command Register I/O spcmd */ |
| 338 | tmio_iowrite8(0x02, tmio->ccr + CCR_COMMAND); |
| 339 | |
| 340 | /* (62h) Power Supply Control ssmpwc */ |
| 341 | /* HardPowerOFF - SuspendOFF - PowerSupplyWait_4MS */ |
| 342 | tmio_iowrite8(0x02, tmio->ccr + CCR_NFPSC); |
| 343 | |
| 344 | /* (63h) Detect Control ssmdtc */ |
| 345 | tmio_iowrite8(0x02, tmio->ccr + CCR_NFDC); |
| 346 | |
| 347 | /* Interrupt status register clear sintst */ |
| 348 | tmio_iowrite8(0x0f, tmio->fcr + FCR_ISR); |
| 349 | |
| 350 | /* After power supply, Media are reset smode */ |
| 351 | tmio_iowrite8(FCR_MODE_POWER_ON, tmio->fcr + FCR_MODE); |
| 352 | tmio_iowrite8(FCR_MODE_COMMAND, tmio->fcr + FCR_MODE); |
| 353 | tmio_iowrite8(NAND_CMD_RESET, tmio->fcr + FCR_DATA); |
| 354 | |
| 355 | /* Standby Mode smode */ |
| 356 | tmio_iowrite8(FCR_MODE_STANDBY, tmio->fcr + FCR_MODE); |
| 357 | |
| 358 | mdelay(5); |
| 359 | |
| 360 | return 0; |
| 361 | } |
| 362 | |
| 363 | static void tmio_hw_stop(struct platform_device *dev, struct tmio_nand *tmio) |
| 364 | { |
| 365 | struct mfd_cell *cell = (struct mfd_cell *)dev->dev.platform_data; |
| 366 | |
| 367 | tmio_iowrite8(FCR_MODE_POWER_OFF, tmio->fcr + FCR_MODE); |
| 368 | if (cell->disable) |
| 369 | cell->disable(dev); |
| 370 | } |
| 371 | |
| 372 | static int tmio_probe(struct platform_device *dev) |
| 373 | { |
| 374 | struct mfd_cell *cell = (struct mfd_cell *)dev->dev.platform_data; |
| 375 | struct tmio_nand_data *data = cell->driver_data; |
| 376 | struct resource *fcr = platform_get_resource(dev, |
| 377 | IORESOURCE_MEM, 0); |
| 378 | struct resource *ccr = platform_get_resource(dev, |
| 379 | IORESOURCE_MEM, 1); |
| 380 | int irq = platform_get_irq(dev, 0); |
| 381 | struct tmio_nand *tmio; |
| 382 | struct mtd_info *mtd; |
| 383 | struct nand_chip *nand_chip; |
| 384 | #ifdef CONFIG_MTD_PARTITIONS |
| 385 | struct mtd_partition *parts; |
| 386 | int nbparts = 0; |
| 387 | #endif |
| 388 | int retval; |
| 389 | |
| 390 | if (data == NULL) |
| 391 | dev_warn(&dev->dev, "NULL platform data!\n"); |
| 392 | |
| 393 | tmio = kzalloc(sizeof *tmio, GFP_KERNEL); |
| 394 | if (!tmio) { |
| 395 | retval = -ENOMEM; |
| 396 | goto err_kzalloc; |
| 397 | } |
| 398 | |
| 399 | tmio->dev = dev; |
| 400 | |
| 401 | platform_set_drvdata(dev, tmio); |
| 402 | mtd = &tmio->mtd; |
| 403 | nand_chip = &tmio->chip; |
| 404 | mtd->priv = nand_chip; |
| 405 | mtd->name = "tmio-nand"; |
| 406 | |
| 407 | tmio->ccr = ioremap(ccr->start, ccr->end - ccr->start + 1); |
| 408 | if (!tmio->ccr) { |
| 409 | retval = -EIO; |
| 410 | goto err_iomap_ccr; |
| 411 | } |
| 412 | |
Dmitry Baryshkov | 076c7f4 | 2008-09-04 13:28:33 +0400 | [diff] [blame] | 413 | tmio->fcr_base = fcr->start & 0xfffff; |
Ian Molton | ec43b81 | 2008-07-15 16:04:22 +0100 | [diff] [blame] | 414 | tmio->fcr = ioremap(fcr->start, fcr->end - fcr->start + 1); |
| 415 | if (!tmio->fcr) { |
| 416 | retval = -EIO; |
| 417 | goto err_iomap_fcr; |
| 418 | } |
| 419 | |
| 420 | retval = tmio_hw_init(dev, tmio); |
| 421 | if (retval) |
| 422 | goto err_hwinit; |
| 423 | |
| 424 | /* Set address of NAND IO lines */ |
| 425 | nand_chip->IO_ADDR_R = tmio->fcr; |
| 426 | nand_chip->IO_ADDR_W = tmio->fcr; |
| 427 | |
| 428 | /* Set address of hardware control function */ |
| 429 | nand_chip->cmd_ctrl = tmio_nand_hwcontrol; |
| 430 | nand_chip->dev_ready = tmio_nand_dev_ready; |
| 431 | nand_chip->read_byte = tmio_nand_read_byte; |
| 432 | nand_chip->write_buf = tmio_nand_write_buf; |
| 433 | nand_chip->read_buf = tmio_nand_read_buf; |
| 434 | nand_chip->verify_buf = tmio_nand_verify_buf; |
| 435 | |
| 436 | /* set eccmode using hardware ECC */ |
| 437 | nand_chip->ecc.mode = NAND_ECC_HW; |
| 438 | nand_chip->ecc.size = 512; |
| 439 | nand_chip->ecc.bytes = 6; |
| 440 | nand_chip->ecc.hwctl = tmio_nand_enable_hwecc; |
| 441 | nand_chip->ecc.calculate = tmio_nand_calculate_ecc; |
Atsushi Nemoto | 0f777fb | 2009-09-05 01:20:44 +0900 | [diff] [blame] | 442 | nand_chip->ecc.correct = tmio_nand_correct_data; |
Ian Molton | ec43b81 | 2008-07-15 16:04:22 +0100 | [diff] [blame] | 443 | |
| 444 | if (data) |
| 445 | nand_chip->badblock_pattern = data->badblock_pattern; |
| 446 | |
| 447 | /* 15 us command delay time */ |
| 448 | nand_chip->chip_delay = 15; |
| 449 | |
| 450 | retval = request_irq(irq, &tmio_irq, |
Kay Sievers | 475b44c | 2009-01-06 10:44:38 -0800 | [diff] [blame] | 451 | IRQF_DISABLED, dev_name(&dev->dev), tmio); |
Ian Molton | ec43b81 | 2008-07-15 16:04:22 +0100 | [diff] [blame] | 452 | if (retval) { |
| 453 | dev_err(&dev->dev, "request_irq error %d\n", retval); |
| 454 | goto err_irq; |
| 455 | } |
| 456 | |
| 457 | tmio->irq = irq; |
| 458 | nand_chip->waitfunc = tmio_nand_wait; |
| 459 | |
| 460 | /* Scan to find existence of the device */ |
| 461 | if (nand_scan(mtd, 1)) { |
| 462 | retval = -ENODEV; |
| 463 | goto err_scan; |
| 464 | } |
| 465 | /* Register the partitions */ |
| 466 | #ifdef CONFIG_MTD_PARTITIONS |
| 467 | #ifdef CONFIG_MTD_CMDLINE_PARTS |
| 468 | nbparts = parse_mtd_partitions(mtd, part_probes, &parts, 0); |
| 469 | #endif |
| 470 | if (nbparts <= 0 && data) { |
| 471 | parts = data->partition; |
| 472 | nbparts = data->num_partitions; |
| 473 | } |
| 474 | |
| 475 | if (nbparts) |
| 476 | retval = add_mtd_partitions(mtd, parts, nbparts); |
| 477 | else |
| 478 | #endif |
| 479 | retval = add_mtd_device(mtd); |
| 480 | |
| 481 | if (!retval) |
| 482 | return retval; |
| 483 | |
| 484 | nand_release(mtd); |
| 485 | |
| 486 | err_scan: |
| 487 | if (tmio->irq) |
| 488 | free_irq(tmio->irq, tmio); |
| 489 | err_irq: |
| 490 | tmio_hw_stop(dev, tmio); |
| 491 | err_hwinit: |
| 492 | iounmap(tmio->fcr); |
| 493 | err_iomap_fcr: |
| 494 | iounmap(tmio->ccr); |
| 495 | err_iomap_ccr: |
| 496 | kfree(tmio); |
| 497 | err_kzalloc: |
| 498 | return retval; |
| 499 | } |
| 500 | |
| 501 | static int tmio_remove(struct platform_device *dev) |
| 502 | { |
| 503 | struct tmio_nand *tmio = platform_get_drvdata(dev); |
| 504 | |
| 505 | nand_release(&tmio->mtd); |
| 506 | if (tmio->irq) |
| 507 | free_irq(tmio->irq, tmio); |
| 508 | tmio_hw_stop(dev, tmio); |
| 509 | iounmap(tmio->fcr); |
| 510 | iounmap(tmio->ccr); |
| 511 | kfree(tmio); |
| 512 | return 0; |
| 513 | } |
| 514 | |
| 515 | #ifdef CONFIG_PM |
| 516 | static int tmio_suspend(struct platform_device *dev, pm_message_t state) |
| 517 | { |
| 518 | struct mfd_cell *cell = (struct mfd_cell *)dev->dev.platform_data; |
| 519 | |
| 520 | if (cell->suspend) |
| 521 | cell->suspend(dev); |
| 522 | |
| 523 | tmio_hw_stop(dev, platform_get_drvdata(dev)); |
| 524 | return 0; |
| 525 | } |
| 526 | |
| 527 | static int tmio_resume(struct platform_device *dev) |
| 528 | { |
| 529 | struct mfd_cell *cell = (struct mfd_cell *)dev->dev.platform_data; |
| 530 | |
| 531 | /* FIXME - is this required or merely another attack of the broken |
| 532 | * SHARP platform? Looks suspicious. |
| 533 | */ |
| 534 | tmio_hw_init(dev, platform_get_drvdata(dev)); |
| 535 | |
| 536 | if (cell->resume) |
| 537 | cell->resume(dev); |
| 538 | |
| 539 | return 0; |
| 540 | } |
| 541 | #else |
| 542 | #define tmio_suspend NULL |
| 543 | #define tmio_resume NULL |
| 544 | #endif |
| 545 | |
| 546 | static struct platform_driver tmio_driver = { |
| 547 | .driver.name = "tmio-nand", |
| 548 | .driver.owner = THIS_MODULE, |
| 549 | .probe = tmio_probe, |
| 550 | .remove = tmio_remove, |
| 551 | .suspend = tmio_suspend, |
| 552 | .resume = tmio_resume, |
| 553 | }; |
| 554 | |
| 555 | static int __init tmio_init(void) |
| 556 | { |
| 557 | return platform_driver_register(&tmio_driver); |
| 558 | } |
| 559 | |
| 560 | static void __exit tmio_exit(void) |
| 561 | { |
| 562 | platform_driver_unregister(&tmio_driver); |
| 563 | } |
| 564 | |
| 565 | module_init(tmio_init); |
| 566 | module_exit(tmio_exit); |
| 567 | |
| 568 | MODULE_LICENSE("GPL v2"); |
| 569 | MODULE_AUTHOR("Ian Molton, Dirk Opfer, Chris Humbert, Dmitry Baryshkov"); |
| 570 | MODULE_DESCRIPTION("NAND flash driver on Toshiba Mobile IO controller"); |
| 571 | MODULE_ALIAS("platform:tmio-nand"); |