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Mark Brownf10485e2008-06-05 13:49:33 +01001/*
2 * wm8990.c -- WM8990 ALSA Soc Audio driver
3 *
4 * Copyright 2008 Wolfson Microelectronics PLC.
Liam Girdwood64ca0402009-02-02 22:23:22 +00005 * Author: Liam Girdwood <lrg@slimlogic.co.uk>
Mark Brownf10485e2008-06-05 13:49:33 +01006 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090021#include <linux/slab.h>
Mark Brownf10485e2008-06-05 13:49:33 +010022#include <sound/core.h>
23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
25#include <sound/soc.h>
26#include <sound/soc-dapm.h>
27#include <sound/initval.h>
28#include <sound/tlv.h>
29#include <asm/div64.h>
30
31#include "wm8990.h"
32
Mark Brownf10485e2008-06-05 13:49:33 +010033#define WM8990_VERSION "0.2"
34
Mark Brownf10485e2008-06-05 13:49:33 +010035/* codec private data */
36struct wm8990_priv {
37 unsigned int sysclk;
38 unsigned int pcmclk;
39};
40
41/*
42 * wm8990 register cache. Note that register 0 is not included in the
43 * cache.
44 */
45static const u16 wm8990_reg[] = {
46 0x8990, /* R0 - Reset */
47 0x0000, /* R1 - Power Management (1) */
48 0x6000, /* R2 - Power Management (2) */
49 0x0000, /* R3 - Power Management (3) */
50 0x4050, /* R4 - Audio Interface (1) */
51 0x4000, /* R5 - Audio Interface (2) */
52 0x01C8, /* R6 - Clocking (1) */
53 0x0000, /* R7 - Clocking (2) */
54 0x0040, /* R8 - Audio Interface (3) */
55 0x0040, /* R9 - Audio Interface (4) */
56 0x0004, /* R10 - DAC CTRL */
57 0x00C0, /* R11 - Left DAC Digital Volume */
58 0x00C0, /* R12 - Right DAC Digital Volume */
59 0x0000, /* R13 - Digital Side Tone */
60 0x0100, /* R14 - ADC CTRL */
61 0x00C0, /* R15 - Left ADC Digital Volume */
62 0x00C0, /* R16 - Right ADC Digital Volume */
63 0x0000, /* R17 */
64 0x0000, /* R18 - GPIO CTRL 1 */
65 0x1000, /* R19 - GPIO1 & GPIO2 */
66 0x1010, /* R20 - GPIO3 & GPIO4 */
67 0x1010, /* R21 - GPIO5 & GPIO6 */
68 0x8000, /* R22 - GPIOCTRL 2 */
69 0x0800, /* R23 - GPIO_POL */
70 0x008B, /* R24 - Left Line Input 1&2 Volume */
71 0x008B, /* R25 - Left Line Input 3&4 Volume */
72 0x008B, /* R26 - Right Line Input 1&2 Volume */
73 0x008B, /* R27 - Right Line Input 3&4 Volume */
74 0x0000, /* R28 - Left Output Volume */
75 0x0000, /* R29 - Right Output Volume */
76 0x0066, /* R30 - Line Outputs Volume */
77 0x0022, /* R31 - Out3/4 Volume */
78 0x0079, /* R32 - Left OPGA Volume */
79 0x0079, /* R33 - Right OPGA Volume */
80 0x0003, /* R34 - Speaker Volume */
81 0x0003, /* R35 - ClassD1 */
82 0x0000, /* R36 */
83 0x0100, /* R37 - ClassD3 */
Mark Brown97bb8122008-08-15 16:22:33 +010084 0x0079, /* R38 - ClassD4 */
Mark Brownf10485e2008-06-05 13:49:33 +010085 0x0000, /* R39 - Input Mixer1 */
86 0x0000, /* R40 - Input Mixer2 */
87 0x0000, /* R41 - Input Mixer3 */
88 0x0000, /* R42 - Input Mixer4 */
89 0x0000, /* R43 - Input Mixer5 */
90 0x0000, /* R44 - Input Mixer6 */
91 0x0000, /* R45 - Output Mixer1 */
92 0x0000, /* R46 - Output Mixer2 */
93 0x0000, /* R47 - Output Mixer3 */
94 0x0000, /* R48 - Output Mixer4 */
95 0x0000, /* R49 - Output Mixer5 */
96 0x0000, /* R50 - Output Mixer6 */
97 0x0180, /* R51 - Out3/4 Mixer */
98 0x0000, /* R52 - Line Mixer1 */
99 0x0000, /* R53 - Line Mixer2 */
100 0x0000, /* R54 - Speaker Mixer */
101 0x0000, /* R55 - Additional Control */
102 0x0000, /* R56 - AntiPOP1 */
103 0x0000, /* R57 - AntiPOP2 */
104 0x0000, /* R58 - MICBIAS */
105 0x0000, /* R59 */
106 0x0008, /* R60 - PLL1 */
107 0x0031, /* R61 - PLL2 */
108 0x0026, /* R62 - PLL3 */
Mark Brownba533e92008-11-17 16:59:24 +0000109 0x0000, /* R63 - Driver internal */
Mark Brownf10485e2008-06-05 13:49:33 +0100110};
111
Mark Brown8d50e442009-07-10 23:12:01 +0100112#define wm8990_reset(c) snd_soc_write(c, WM8990_RESET, 0)
Mark Brownf10485e2008-06-05 13:49:33 +0100113
Mark Brownf68596c2010-05-25 10:49:00 -0700114static const DECLARE_TLV_DB_SCALE(rec_mix_tlv, -1500, 600, 0);
Mark Brownf10485e2008-06-05 13:49:33 +0100115
Mark Brownf68596c2010-05-25 10:49:00 -0700116static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1650, 3000, 0);
Mark Brownf10485e2008-06-05 13:49:33 +0100117
Mark Brownf68596c2010-05-25 10:49:00 -0700118static const DECLARE_TLV_DB_SCALE(out_mix_tlv, 0, -2100, 0);
Mark Brownf10485e2008-06-05 13:49:33 +0100119
Mark Brownf68596c2010-05-25 10:49:00 -0700120static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -7300, 600, 0);
Mark Brownf10485e2008-06-05 13:49:33 +0100121
Mark Brownf68596c2010-05-25 10:49:00 -0700122static const DECLARE_TLV_DB_SCALE(out_omix_tlv, -600, 0, 0);
Mark Brownf10485e2008-06-05 13:49:33 +0100123
Mark Brownf68596c2010-05-25 10:49:00 -0700124static const DECLARE_TLV_DB_SCALE(out_dac_tlv, -7163, 0, 0);
Mark Brownf10485e2008-06-05 13:49:33 +0100125
Mark Brownf68596c2010-05-25 10:49:00 -0700126static const DECLARE_TLV_DB_SCALE(in_adc_tlv, -7163, 1763, 0);
Mark Brownf10485e2008-06-05 13:49:33 +0100127
Mark Brownf68596c2010-05-25 10:49:00 -0700128static const DECLARE_TLV_DB_SCALE(out_sidetone_tlv, -3600, 0, 0);
Mark Brownf10485e2008-06-05 13:49:33 +0100129
130static int wm899x_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol,
131 struct snd_ctl_elem_value *ucontrol)
132{
133 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
Jarkko Nikula397d5ae2009-02-06 12:01:05 +0200134 struct soc_mixer_control *mc =
135 (struct soc_mixer_control *)kcontrol->private_value;
136 int reg = mc->reg;
Mark Brownf10485e2008-06-05 13:49:33 +0100137 int ret;
138 u16 val;
139
140 ret = snd_soc_put_volsw(kcontrol, ucontrol);
141 if (ret < 0)
142 return ret;
143
144 /* now hit the volume update bits (always bit 8) */
Mark Brown8d50e442009-07-10 23:12:01 +0100145 val = snd_soc_read(codec, reg);
146 return snd_soc_write(codec, reg, val | 0x0100);
Mark Brownf10485e2008-06-05 13:49:33 +0100147}
148
149#define SOC_WM899X_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert,\
150 tlv_array) {\
151 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
152 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
153 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
154 .tlv.p = (tlv_array), \
155 .info = snd_soc_info_volsw, \
156 .get = snd_soc_get_volsw, .put = wm899x_outpga_put_volsw_vu, \
157 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
158
159
160static const char *wm8990_digital_sidetone[] =
161 {"None", "Left ADC", "Right ADC", "Reserved"};
162
163static const struct soc_enum wm8990_left_digital_sidetone_enum =
164SOC_ENUM_SINGLE(WM8990_DIGITAL_SIDE_TONE,
165 WM8990_ADC_TO_DACL_SHIFT,
166 WM8990_ADC_TO_DACL_MASK,
167 wm8990_digital_sidetone);
168
169static const struct soc_enum wm8990_right_digital_sidetone_enum =
170SOC_ENUM_SINGLE(WM8990_DIGITAL_SIDE_TONE,
171 WM8990_ADC_TO_DACR_SHIFT,
172 WM8990_ADC_TO_DACR_MASK,
173 wm8990_digital_sidetone);
174
175static const char *wm8990_adcmode[] =
176 {"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"};
177
178static const struct soc_enum wm8990_right_adcmode_enum =
179SOC_ENUM_SINGLE(WM8990_ADC_CTRL,
180 WM8990_ADC_HPF_CUT_SHIFT,
181 WM8990_ADC_HPF_CUT_MASK,
182 wm8990_adcmode);
183
184static const struct snd_kcontrol_new wm8990_snd_controls[] = {
185/* INMIXL */
186SOC_SINGLE("LIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L12MNBST_BIT, 1, 0),
187SOC_SINGLE("LIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L34MNBST_BIT, 1, 0),
188/* INMIXR */
189SOC_SINGLE("RIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R12MNBST_BIT, 1, 0),
190SOC_SINGLE("RIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R34MNBST_BIT, 1, 0),
191
192/* LOMIX */
193SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER3,
194 WM8990_LLI3LOVOL_SHIFT, WM8990_LLI3LOVOL_MASK, 1, out_mix_tlv),
195SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3,
196 WM8990_LR12LOVOL_SHIFT, WM8990_LR12LOVOL_MASK, 1, out_mix_tlv),
197SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3,
198 WM8990_LL12LOVOL_SHIFT, WM8990_LL12LOVOL_MASK, 1, out_mix_tlv),
199SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER5,
200 WM8990_LRI3LOVOL_SHIFT, WM8990_LRI3LOVOL_MASK, 1, out_mix_tlv),
201SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER5,
202 WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv),
203SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER5,
204 WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv),
205
206/* ROMIX */
207SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER4,
208 WM8990_RRI3ROVOL_SHIFT, WM8990_RRI3ROVOL_MASK, 1, out_mix_tlv),
209SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4,
210 WM8990_RL12ROVOL_SHIFT, WM8990_RL12ROVOL_MASK, 1, out_mix_tlv),
211SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4,
212 WM8990_RR12ROVOL_SHIFT, WM8990_RR12ROVOL_MASK, 1, out_mix_tlv),
213SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER6,
214 WM8990_RLI3ROVOL_SHIFT, WM8990_RLI3ROVOL_MASK, 1, out_mix_tlv),
215SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER6,
216 WM8990_RLBROVOL_SHIFT, WM8990_RLBROVOL_MASK, 1, out_mix_tlv),
217SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER6,
218 WM8990_RRBROVOL_SHIFT, WM8990_RRBROVOL_MASK, 1, out_mix_tlv),
219
220/* LOUT */
221SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8990_LEFT_OUTPUT_VOLUME,
222 WM8990_LOUTVOL_SHIFT, WM8990_LOUTVOL_MASK, 0, out_pga_tlv),
223SOC_SINGLE("LOUT ZC", WM8990_LEFT_OUTPUT_VOLUME, WM8990_LOZC_BIT, 1, 0),
224
225/* ROUT */
226SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8990_RIGHT_OUTPUT_VOLUME,
227 WM8990_ROUTVOL_SHIFT, WM8990_ROUTVOL_MASK, 0, out_pga_tlv),
228SOC_SINGLE("ROUT ZC", WM8990_RIGHT_OUTPUT_VOLUME, WM8990_ROZC_BIT, 1, 0),
229
230/* LOPGA */
231SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8990_LEFT_OPGA_VOLUME,
232 WM8990_LOPGAVOL_SHIFT, WM8990_LOPGAVOL_MASK, 0, out_pga_tlv),
233SOC_SINGLE("LOPGA ZC Switch", WM8990_LEFT_OPGA_VOLUME,
234 WM8990_LOPGAZC_BIT, 1, 0),
235
236/* ROPGA */
237SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8990_RIGHT_OPGA_VOLUME,
238 WM8990_ROPGAVOL_SHIFT, WM8990_ROPGAVOL_MASK, 0, out_pga_tlv),
239SOC_SINGLE("ROPGA ZC Switch", WM8990_RIGHT_OPGA_VOLUME,
240 WM8990_ROPGAZC_BIT, 1, 0),
241
242SOC_SINGLE("LON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
243 WM8990_LONMUTE_BIT, 1, 0),
244SOC_SINGLE("LOP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
245 WM8990_LOPMUTE_BIT, 1, 0),
246SOC_SINGLE("LOP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME,
247 WM8990_LOATTN_BIT, 1, 0),
248SOC_SINGLE("RON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
249 WM8990_RONMUTE_BIT, 1, 0),
250SOC_SINGLE("ROP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
251 WM8990_ROPMUTE_BIT, 1, 0),
252SOC_SINGLE("ROP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME,
253 WM8990_ROATTN_BIT, 1, 0),
254
255SOC_SINGLE("OUT3 Mute Switch", WM8990_OUT3_4_VOLUME,
256 WM8990_OUT3MUTE_BIT, 1, 0),
257SOC_SINGLE("OUT3 Attenuation Switch", WM8990_OUT3_4_VOLUME,
258 WM8990_OUT3ATTN_BIT, 1, 0),
259
260SOC_SINGLE("OUT4 Mute Switch", WM8990_OUT3_4_VOLUME,
261 WM8990_OUT4MUTE_BIT, 1, 0),
262SOC_SINGLE("OUT4 Attenuation Switch", WM8990_OUT3_4_VOLUME,
263 WM8990_OUT4ATTN_BIT, 1, 0),
264
265SOC_SINGLE("Speaker Mode Switch", WM8990_CLASSD1,
266 WM8990_CDMODE_BIT, 1, 0),
267
268SOC_SINGLE("Speaker Output Attenuation Volume", WM8990_SPEAKER_VOLUME,
Mark Brown97bb8122008-08-15 16:22:33 +0100269 WM8990_SPKATTN_SHIFT, WM8990_SPKATTN_MASK, 0),
Mark Brownf10485e2008-06-05 13:49:33 +0100270SOC_SINGLE("Speaker DC Boost Volume", WM8990_CLASSD3,
271 WM8990_DCGAIN_SHIFT, WM8990_DCGAIN_MASK, 0),
272SOC_SINGLE("Speaker AC Boost Volume", WM8990_CLASSD3,
273 WM8990_ACGAIN_SHIFT, WM8990_ACGAIN_MASK, 0),
Mark Brown97bb8122008-08-15 16:22:33 +0100274SOC_SINGLE_TLV("Speaker Volume", WM8990_CLASSD4,
275 WM8990_SPKVOL_SHIFT, WM8990_SPKVOL_MASK, 0, out_pga_tlv),
276SOC_SINGLE("Speaker ZC Switch", WM8990_CLASSD4,
277 WM8990_SPKZC_SHIFT, WM8990_SPKZC_MASK, 0),
Mark Brownf10485e2008-06-05 13:49:33 +0100278
279SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume",
280 WM8990_LEFT_DAC_DIGITAL_VOLUME,
281 WM8990_DACL_VOL_SHIFT,
282 WM8990_DACL_VOL_MASK,
283 0,
284 out_dac_tlv),
285
286SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume",
287 WM8990_RIGHT_DAC_DIGITAL_VOLUME,
288 WM8990_DACR_VOL_SHIFT,
289 WM8990_DACR_VOL_MASK,
290 0,
291 out_dac_tlv),
292
293SOC_ENUM("Left Digital Sidetone", wm8990_left_digital_sidetone_enum),
294SOC_ENUM("Right Digital Sidetone", wm8990_right_digital_sidetone_enum),
295
296SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE,
297 WM8990_ADCL_DAC_SVOL_SHIFT, WM8990_ADCL_DAC_SVOL_MASK, 0,
298 out_sidetone_tlv),
299SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE,
300 WM8990_ADCR_DAC_SVOL_SHIFT, WM8990_ADCR_DAC_SVOL_MASK, 0,
301 out_sidetone_tlv),
302
303SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8990_ADC_CTRL,
304 WM8990_ADC_HPF_ENA_BIT, 1, 0),
305
306SOC_ENUM("ADC HPF Mode", wm8990_right_adcmode_enum),
307
308SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume",
309 WM8990_LEFT_ADC_DIGITAL_VOLUME,
310 WM8990_ADCL_VOL_SHIFT,
311 WM8990_ADCL_VOL_MASK,
312 0,
313 in_adc_tlv),
314
315SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume",
316 WM8990_RIGHT_ADC_DIGITAL_VOLUME,
317 WM8990_ADCR_VOL_SHIFT,
318 WM8990_ADCR_VOL_MASK,
319 0,
320 in_adc_tlv),
321
322SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN12 Volume",
323 WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
324 WM8990_LIN12VOL_SHIFT,
325 WM8990_LIN12VOL_MASK,
326 0,
327 in_pga_tlv),
328
329SOC_SINGLE("LIN12 ZC Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
330 WM8990_LI12ZC_BIT, 1, 0),
331
332SOC_SINGLE("LIN12 Mute Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
333 WM8990_LI12MUTE_BIT, 1, 0),
334
335SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN34 Volume",
336 WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
337 WM8990_LIN34VOL_SHIFT,
338 WM8990_LIN34VOL_MASK,
339 0,
340 in_pga_tlv),
341
342SOC_SINGLE("LIN34 ZC Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
343 WM8990_LI34ZC_BIT, 1, 0),
344
345SOC_SINGLE("LIN34 Mute Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
346 WM8990_LI34MUTE_BIT, 1, 0),
347
348SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN12 Volume",
349 WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
350 WM8990_RIN12VOL_SHIFT,
351 WM8990_RIN12VOL_MASK,
352 0,
353 in_pga_tlv),
354
355SOC_SINGLE("RIN12 ZC Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
356 WM8990_RI12ZC_BIT, 1, 0),
357
358SOC_SINGLE("RIN12 Mute Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
359 WM8990_RI12MUTE_BIT, 1, 0),
360
361SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN34 Volume",
362 WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
363 WM8990_RIN34VOL_SHIFT,
364 WM8990_RIN34VOL_MASK,
365 0,
366 in_pga_tlv),
367
368SOC_SINGLE("RIN34 ZC Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
369 WM8990_RI34ZC_BIT, 1, 0),
370
371SOC_SINGLE("RIN34 Mute Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
372 WM8990_RI34MUTE_BIT, 1, 0),
373
374};
375
Mark Brownf10485e2008-06-05 13:49:33 +0100376/*
377 * _DAPM_ Controls
378 */
379
380static int inmixer_event(struct snd_soc_dapm_widget *w,
381 struct snd_kcontrol *kcontrol, int event)
382{
383 u16 reg, fakepower;
384
Mark Brown8d50e442009-07-10 23:12:01 +0100385 reg = snd_soc_read(w->codec, WM8990_POWER_MANAGEMENT_2);
386 fakepower = snd_soc_read(w->codec, WM8990_INTDRIVBITS);
Mark Brownf10485e2008-06-05 13:49:33 +0100387
388 if (fakepower & ((1 << WM8990_INMIXL_PWR_BIT) |
389 (1 << WM8990_AINLMUX_PWR_BIT))) {
390 reg |= WM8990_AINL_ENA;
391 } else {
392 reg &= ~WM8990_AINL_ENA;
393 }
394
395 if (fakepower & ((1 << WM8990_INMIXR_PWR_BIT) |
396 (1 << WM8990_AINRMUX_PWR_BIT))) {
397 reg |= WM8990_AINR_ENA;
398 } else {
399 reg &= ~WM8990_AINL_ENA;
400 }
Mark Brown8d50e442009-07-10 23:12:01 +0100401 snd_soc_write(w->codec, WM8990_POWER_MANAGEMENT_2, reg);
Mark Brownf10485e2008-06-05 13:49:33 +0100402
403 return 0;
404}
405
406static int outmixer_event(struct snd_soc_dapm_widget *w,
407 struct snd_kcontrol *kcontrol, int event)
408{
409 u32 reg_shift = kcontrol->private_value & 0xfff;
410 int ret = 0;
411 u16 reg;
412
413 switch (reg_shift) {
414 case WM8990_SPEAKER_MIXER | (WM8990_LDSPK_BIT << 8) :
Mark Brown8d50e442009-07-10 23:12:01 +0100415 reg = snd_soc_read(w->codec, WM8990_OUTPUT_MIXER1);
Mark Brownf10485e2008-06-05 13:49:33 +0100416 if (reg & WM8990_LDLO) {
417 printk(KERN_WARNING
418 "Cannot set as Output Mixer 1 LDLO Set\n");
419 ret = -1;
420 }
421 break;
422 case WM8990_SPEAKER_MIXER | (WM8990_RDSPK_BIT << 8):
Mark Brown8d50e442009-07-10 23:12:01 +0100423 reg = snd_soc_read(w->codec, WM8990_OUTPUT_MIXER2);
Mark Brownf10485e2008-06-05 13:49:33 +0100424 if (reg & WM8990_RDRO) {
425 printk(KERN_WARNING
426 "Cannot set as Output Mixer 2 RDRO Set\n");
427 ret = -1;
428 }
429 break;
430 case WM8990_OUTPUT_MIXER1 | (WM8990_LDLO_BIT << 8):
Mark Brown8d50e442009-07-10 23:12:01 +0100431 reg = snd_soc_read(w->codec, WM8990_SPEAKER_MIXER);
Mark Brownf10485e2008-06-05 13:49:33 +0100432 if (reg & WM8990_LDSPK) {
433 printk(KERN_WARNING
434 "Cannot set as Speaker Mixer LDSPK Set\n");
435 ret = -1;
436 }
437 break;
438 case WM8990_OUTPUT_MIXER2 | (WM8990_RDRO_BIT << 8):
Mark Brown8d50e442009-07-10 23:12:01 +0100439 reg = snd_soc_read(w->codec, WM8990_SPEAKER_MIXER);
Mark Brownf10485e2008-06-05 13:49:33 +0100440 if (reg & WM8990_RDSPK) {
441 printk(KERN_WARNING
442 "Cannot set as Speaker Mixer RDSPK Set\n");
443 ret = -1;
444 }
445 break;
446 }
447
448 return ret;
449}
450
451/* INMIX dB values */
452static const unsigned int in_mix_tlv[] = {
453 TLV_DB_RANGE_HEAD(1),
Mark Brownf68596c2010-05-25 10:49:00 -0700454 0, 7, TLV_DB_SCALE_ITEM(-1200, 600, 0),
Mark Brownf10485e2008-06-05 13:49:33 +0100455};
456
457/* Left In PGA Connections */
458static const struct snd_kcontrol_new wm8990_dapm_lin12_pga_controls[] = {
459SOC_DAPM_SINGLE("LIN1 Switch", WM8990_INPUT_MIXER2, WM8990_LMN1_BIT, 1, 0),
460SOC_DAPM_SINGLE("LIN2 Switch", WM8990_INPUT_MIXER2, WM8990_LMP2_BIT, 1, 0),
461};
462
463static const struct snd_kcontrol_new wm8990_dapm_lin34_pga_controls[] = {
464SOC_DAPM_SINGLE("LIN3 Switch", WM8990_INPUT_MIXER2, WM8990_LMN3_BIT, 1, 0),
465SOC_DAPM_SINGLE("LIN4 Switch", WM8990_INPUT_MIXER2, WM8990_LMP4_BIT, 1, 0),
466};
467
468/* Right In PGA Connections */
469static const struct snd_kcontrol_new wm8990_dapm_rin12_pga_controls[] = {
470SOC_DAPM_SINGLE("RIN1 Switch", WM8990_INPUT_MIXER2, WM8990_RMN1_BIT, 1, 0),
471SOC_DAPM_SINGLE("RIN2 Switch", WM8990_INPUT_MIXER2, WM8990_RMP2_BIT, 1, 0),
472};
473
474static const struct snd_kcontrol_new wm8990_dapm_rin34_pga_controls[] = {
475SOC_DAPM_SINGLE("RIN3 Switch", WM8990_INPUT_MIXER2, WM8990_RMN3_BIT, 1, 0),
476SOC_DAPM_SINGLE("RIN4 Switch", WM8990_INPUT_MIXER2, WM8990_RMP4_BIT, 1, 0),
477};
478
479/* INMIXL */
480static const struct snd_kcontrol_new wm8990_dapm_inmixl_controls[] = {
481SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8990_INPUT_MIXER3,
482 WM8990_LDBVOL_SHIFT, WM8990_LDBVOL_MASK, 0, in_mix_tlv),
483SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8990_INPUT_MIXER5, WM8990_LI2BVOL_SHIFT,
484 7, 0, in_mix_tlv),
485SOC_DAPM_SINGLE("LINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT,
486 1, 0),
487SOC_DAPM_SINGLE("LINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT,
488 1, 0),
489};
490
491/* INMIXR */
492static const struct snd_kcontrol_new wm8990_dapm_inmixr_controls[] = {
493SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8990_INPUT_MIXER4,
494 WM8990_RDBVOL_SHIFT, WM8990_RDBVOL_MASK, 0, in_mix_tlv),
495SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8990_INPUT_MIXER6, WM8990_RI2BVOL_SHIFT,
496 7, 0, in_mix_tlv),
497SOC_DAPM_SINGLE("RINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT,
498 1, 0),
499SOC_DAPM_SINGLE("RINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT,
500 1, 0),
501};
502
503/* AINLMUX */
504static const char *wm8990_ainlmux[] =
505 {"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"};
506
507static const struct soc_enum wm8990_ainlmux_enum =
508SOC_ENUM_SINGLE(WM8990_INPUT_MIXER1, WM8990_AINLMODE_SHIFT,
509 ARRAY_SIZE(wm8990_ainlmux), wm8990_ainlmux);
510
511static const struct snd_kcontrol_new wm8990_dapm_ainlmux_controls =
512SOC_DAPM_ENUM("Route", wm8990_ainlmux_enum);
513
514/* DIFFINL */
515
516/* AINRMUX */
517static const char *wm8990_ainrmux[] =
518 {"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"};
519
520static const struct soc_enum wm8990_ainrmux_enum =
521SOC_ENUM_SINGLE(WM8990_INPUT_MIXER1, WM8990_AINRMODE_SHIFT,
522 ARRAY_SIZE(wm8990_ainrmux), wm8990_ainrmux);
523
524static const struct snd_kcontrol_new wm8990_dapm_ainrmux_controls =
525SOC_DAPM_ENUM("Route", wm8990_ainrmux_enum);
526
527/* RXVOICE */
528static const struct snd_kcontrol_new wm8990_dapm_rxvoice_controls[] = {
529SOC_DAPM_SINGLE_TLV("LIN4/RXN", WM8990_INPUT_MIXER5, WM8990_LR4BVOL_SHIFT,
530 WM8990_LR4BVOL_MASK, 0, in_mix_tlv),
531SOC_DAPM_SINGLE_TLV("RIN4/RXP", WM8990_INPUT_MIXER6, WM8990_RL4BVOL_SHIFT,
532 WM8990_RL4BVOL_MASK, 0, in_mix_tlv),
533};
534
535/* LOMIX */
536static const struct snd_kcontrol_new wm8990_dapm_lomix_controls[] = {
537SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER1,
538 WM8990_LRBLO_BIT, 1, 0),
539SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER1,
540 WM8990_LLBLO_BIT, 1, 0),
541SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER1,
542 WM8990_LRI3LO_BIT, 1, 0),
543SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER1,
544 WM8990_LLI3LO_BIT, 1, 0),
545SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1,
546 WM8990_LR12LO_BIT, 1, 0),
547SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1,
548 WM8990_LL12LO_BIT, 1, 0),
549SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8990_OUTPUT_MIXER1,
550 WM8990_LDLO_BIT, 1, 0),
551};
552
553/* ROMIX */
554static const struct snd_kcontrol_new wm8990_dapm_romix_controls[] = {
555SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER2,
556 WM8990_RLBRO_BIT, 1, 0),
557SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER2,
558 WM8990_RRBRO_BIT, 1, 0),
559SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER2,
560 WM8990_RLI3RO_BIT, 1, 0),
561SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER2,
562 WM8990_RRI3RO_BIT, 1, 0),
563SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2,
564 WM8990_RL12RO_BIT, 1, 0),
565SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2,
566 WM8990_RR12RO_BIT, 1, 0),
567SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8990_OUTPUT_MIXER2,
568 WM8990_RDRO_BIT, 1, 0),
569};
570
571/* LONMIX */
572static const struct snd_kcontrol_new wm8990_dapm_lonmix_controls[] = {
573SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1,
574 WM8990_LLOPGALON_BIT, 1, 0),
575SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER1,
576 WM8990_LROPGALON_BIT, 1, 0),
577SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8990_LINE_MIXER1,
578 WM8990_LOPLON_BIT, 1, 0),
579};
580
581/* LOPMIX */
582static const struct snd_kcontrol_new wm8990_dapm_lopmix_controls[] = {
583SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER1,
584 WM8990_LR12LOP_BIT, 1, 0),
585SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER1,
586 WM8990_LL12LOP_BIT, 1, 0),
587SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1,
588 WM8990_LLOPGALOP_BIT, 1, 0),
589};
590
591/* RONMIX */
592static const struct snd_kcontrol_new wm8990_dapm_ronmix_controls[] = {
593SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2,
594 WM8990_RROPGARON_BIT, 1, 0),
595SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER2,
596 WM8990_RLOPGARON_BIT, 1, 0),
597SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8990_LINE_MIXER2,
598 WM8990_ROPRON_BIT, 1, 0),
599};
600
601/* ROPMIX */
602static const struct snd_kcontrol_new wm8990_dapm_ropmix_controls[] = {
603SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER2,
604 WM8990_RL12ROP_BIT, 1, 0),
605SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER2,
606 WM8990_RR12ROP_BIT, 1, 0),
607SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2,
608 WM8990_RROPGAROP_BIT, 1, 0),
609};
610
611/* OUT3MIX */
612static const struct snd_kcontrol_new wm8990_dapm_out3mix_controls[] = {
613SOC_DAPM_SINGLE("OUT3MIX LIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER,
614 WM8990_LI4O3_BIT, 1, 0),
615SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8990_OUT3_4_MIXER,
616 WM8990_LPGAO3_BIT, 1, 0),
617};
618
619/* OUT4MIX */
620static const struct snd_kcontrol_new wm8990_dapm_out4mix_controls[] = {
621SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8990_OUT3_4_MIXER,
622 WM8990_RPGAO4_BIT, 1, 0),
623SOC_DAPM_SINGLE("OUT4MIX RIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER,
624 WM8990_RI4O4_BIT, 1, 0),
625};
626
627/* SPKMIX */
628static const struct snd_kcontrol_new wm8990_dapm_spkmix_controls[] = {
629SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8990_SPEAKER_MIXER,
630 WM8990_LI2SPK_BIT, 1, 0),
631SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8990_SPEAKER_MIXER,
632 WM8990_LB2SPK_BIT, 1, 0),
633SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8990_SPEAKER_MIXER,
634 WM8990_LOPGASPK_BIT, 1, 0),
635SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8990_SPEAKER_MIXER,
636 WM8990_LDSPK_BIT, 1, 0),
637SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8990_SPEAKER_MIXER,
638 WM8990_RDSPK_BIT, 1, 0),
639SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8990_SPEAKER_MIXER,
640 WM8990_ROPGASPK_BIT, 1, 0),
641SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8990_SPEAKER_MIXER,
642 WM8990_RL12ROP_BIT, 1, 0),
643SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8990_SPEAKER_MIXER,
644 WM8990_RI2SPK_BIT, 1, 0),
645};
646
647static const struct snd_soc_dapm_widget wm8990_dapm_widgets[] = {
648/* Input Side */
649/* Input Lines */
650SND_SOC_DAPM_INPUT("LIN1"),
651SND_SOC_DAPM_INPUT("LIN2"),
652SND_SOC_DAPM_INPUT("LIN3"),
653SND_SOC_DAPM_INPUT("LIN4/RXN"),
654SND_SOC_DAPM_INPUT("RIN3"),
655SND_SOC_DAPM_INPUT("RIN4/RXP"),
656SND_SOC_DAPM_INPUT("RIN1"),
657SND_SOC_DAPM_INPUT("RIN2"),
658SND_SOC_DAPM_INPUT("Internal ADC Source"),
659
660/* DACs */
661SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8990_POWER_MANAGEMENT_2,
662 WM8990_ADCL_ENA_BIT, 0),
663SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8990_POWER_MANAGEMENT_2,
664 WM8990_ADCR_ENA_BIT, 0),
665
666/* Input PGAs */
667SND_SOC_DAPM_MIXER("LIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN12_ENA_BIT,
668 0, &wm8990_dapm_lin12_pga_controls[0],
669 ARRAY_SIZE(wm8990_dapm_lin12_pga_controls)),
670SND_SOC_DAPM_MIXER("LIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN34_ENA_BIT,
671 0, &wm8990_dapm_lin34_pga_controls[0],
672 ARRAY_SIZE(wm8990_dapm_lin34_pga_controls)),
673SND_SOC_DAPM_MIXER("RIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN12_ENA_BIT,
674 0, &wm8990_dapm_rin12_pga_controls[0],
675 ARRAY_SIZE(wm8990_dapm_rin12_pga_controls)),
676SND_SOC_DAPM_MIXER("RIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN34_ENA_BIT,
677 0, &wm8990_dapm_rin34_pga_controls[0],
678 ARRAY_SIZE(wm8990_dapm_rin34_pga_controls)),
679
680/* INMIXL */
681SND_SOC_DAPM_MIXER_E("INMIXL", WM8990_INTDRIVBITS, WM8990_INMIXL_PWR_BIT, 0,
682 &wm8990_dapm_inmixl_controls[0],
683 ARRAY_SIZE(wm8990_dapm_inmixl_controls),
684 inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
685
686/* AINLMUX */
Jinyoung Park97a775c2009-05-01 12:54:31 +0100687SND_SOC_DAPM_MUX_E("AINLMUX", WM8990_INTDRIVBITS, WM8990_AINLMUX_PWR_BIT, 0,
Mark Brownf10485e2008-06-05 13:49:33 +0100688 &wm8990_dapm_ainlmux_controls, inmixer_event,
689 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
690
691/* INMIXR */
692SND_SOC_DAPM_MIXER_E("INMIXR", WM8990_INTDRIVBITS, WM8990_INMIXR_PWR_BIT, 0,
693 &wm8990_dapm_inmixr_controls[0],
694 ARRAY_SIZE(wm8990_dapm_inmixr_controls),
695 inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
696
697/* AINRMUX */
Jinyoung Park97a775c2009-05-01 12:54:31 +0100698SND_SOC_DAPM_MUX_E("AINRMUX", WM8990_INTDRIVBITS, WM8990_AINRMUX_PWR_BIT, 0,
Mark Brownf10485e2008-06-05 13:49:33 +0100699 &wm8990_dapm_ainrmux_controls, inmixer_event,
700 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
701
702/* Output Side */
703/* DACs */
704SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8990_POWER_MANAGEMENT_3,
705 WM8990_DACL_ENA_BIT, 0),
706SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8990_POWER_MANAGEMENT_3,
707 WM8990_DACR_ENA_BIT, 0),
708
709/* LOMIX */
710SND_SOC_DAPM_MIXER_E("LOMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOMIX_ENA_BIT,
711 0, &wm8990_dapm_lomix_controls[0],
712 ARRAY_SIZE(wm8990_dapm_lomix_controls),
713 outmixer_event, SND_SOC_DAPM_PRE_REG),
714
715/* LONMIX */
716SND_SOC_DAPM_MIXER("LONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LON_ENA_BIT, 0,
717 &wm8990_dapm_lonmix_controls[0],
718 ARRAY_SIZE(wm8990_dapm_lonmix_controls)),
719
720/* LOPMIX */
721SND_SOC_DAPM_MIXER("LOPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOP_ENA_BIT, 0,
722 &wm8990_dapm_lopmix_controls[0],
723 ARRAY_SIZE(wm8990_dapm_lopmix_controls)),
724
725/* OUT3MIX */
726SND_SOC_DAPM_MIXER("OUT3MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT3_ENA_BIT, 0,
727 &wm8990_dapm_out3mix_controls[0],
728 ARRAY_SIZE(wm8990_dapm_out3mix_controls)),
729
730/* SPKMIX */
731SND_SOC_DAPM_MIXER_E("SPKMIX", WM8990_POWER_MANAGEMENT_1, WM8990_SPK_ENA_BIT, 0,
732 &wm8990_dapm_spkmix_controls[0],
733 ARRAY_SIZE(wm8990_dapm_spkmix_controls), outmixer_event,
734 SND_SOC_DAPM_PRE_REG),
735
736/* OUT4MIX */
737SND_SOC_DAPM_MIXER("OUT4MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT4_ENA_BIT, 0,
738 &wm8990_dapm_out4mix_controls[0],
739 ARRAY_SIZE(wm8990_dapm_out4mix_controls)),
740
741/* ROPMIX */
742SND_SOC_DAPM_MIXER("ROPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROP_ENA_BIT, 0,
743 &wm8990_dapm_ropmix_controls[0],
744 ARRAY_SIZE(wm8990_dapm_ropmix_controls)),
745
746/* RONMIX */
747SND_SOC_DAPM_MIXER("RONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_RON_ENA_BIT, 0,
748 &wm8990_dapm_ronmix_controls[0],
749 ARRAY_SIZE(wm8990_dapm_ronmix_controls)),
750
751/* ROMIX */
752SND_SOC_DAPM_MIXER_E("ROMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROMIX_ENA_BIT,
753 0, &wm8990_dapm_romix_controls[0],
754 ARRAY_SIZE(wm8990_dapm_romix_controls),
755 outmixer_event, SND_SOC_DAPM_PRE_REG),
756
757/* LOUT PGA */
758SND_SOC_DAPM_PGA("LOUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_LOUT_ENA_BIT, 0,
759 NULL, 0),
760
761/* ROUT PGA */
762SND_SOC_DAPM_PGA("ROUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_ROUT_ENA_BIT, 0,
763 NULL, 0),
764
765/* LOPGA */
766SND_SOC_DAPM_PGA("LOPGA", WM8990_POWER_MANAGEMENT_3, WM8990_LOPGA_ENA_BIT, 0,
767 NULL, 0),
768
769/* ROPGA */
770SND_SOC_DAPM_PGA("ROPGA", WM8990_POWER_MANAGEMENT_3, WM8990_ROPGA_ENA_BIT, 0,
771 NULL, 0),
772
773/* MICBIAS */
774SND_SOC_DAPM_MICBIAS("MICBIAS", WM8990_POWER_MANAGEMENT_1,
775 WM8990_MICBIAS_ENA_BIT, 0),
776
777SND_SOC_DAPM_OUTPUT("LON"),
778SND_SOC_DAPM_OUTPUT("LOP"),
779SND_SOC_DAPM_OUTPUT("OUT3"),
780SND_SOC_DAPM_OUTPUT("LOUT"),
781SND_SOC_DAPM_OUTPUT("SPKN"),
782SND_SOC_DAPM_OUTPUT("SPKP"),
783SND_SOC_DAPM_OUTPUT("ROUT"),
784SND_SOC_DAPM_OUTPUT("OUT4"),
785SND_SOC_DAPM_OUTPUT("ROP"),
786SND_SOC_DAPM_OUTPUT("RON"),
787
788SND_SOC_DAPM_OUTPUT("Internal DAC Sink"),
789};
790
791static const struct snd_soc_dapm_route audio_map[] = {
792 /* Make DACs turn on when playing even if not mixed into any outputs */
793 {"Internal DAC Sink", NULL, "Left DAC"},
794 {"Internal DAC Sink", NULL, "Right DAC"},
795
796 /* Make ADCs turn on when recording even if not mixed from any inputs */
797 {"Left ADC", NULL, "Internal ADC Source"},
798 {"Right ADC", NULL, "Internal ADC Source"},
799
800 /* Input Side */
801 /* LIN12 PGA */
802 {"LIN12 PGA", "LIN1 Switch", "LIN1"},
803 {"LIN12 PGA", "LIN2 Switch", "LIN2"},
804 /* LIN34 PGA */
805 {"LIN34 PGA", "LIN3 Switch", "LIN3"},
Jinyoung Park97a775c2009-05-01 12:54:31 +0100806 {"LIN34 PGA", "LIN4 Switch", "LIN4/RXN"},
Mark Brownf10485e2008-06-05 13:49:33 +0100807 /* INMIXL */
808 {"INMIXL", "Record Left Volume", "LOMIX"},
809 {"INMIXL", "LIN2 Volume", "LIN2"},
810 {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"},
811 {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"},
Jinyoung Park97a775c2009-05-01 12:54:31 +0100812 /* AINLMUX */
813 {"AINLMUX", "INMIXL Mix", "INMIXL"},
814 {"AINLMUX", "DIFFINL Mix", "LIN12 PGA"},
815 {"AINLMUX", "DIFFINL Mix", "LIN34 PGA"},
816 {"AINLMUX", "RXVOICE Mix", "LIN4/RXN"},
817 {"AINLMUX", "RXVOICE Mix", "RIN4/RXP"},
Mark Brownf10485e2008-06-05 13:49:33 +0100818 /* ADC */
Jinyoung Park97a775c2009-05-01 12:54:31 +0100819 {"Left ADC", NULL, "AINLMUX"},
Mark Brownf10485e2008-06-05 13:49:33 +0100820
821 /* RIN12 PGA */
822 {"RIN12 PGA", "RIN1 Switch", "RIN1"},
823 {"RIN12 PGA", "RIN2 Switch", "RIN2"},
824 /* RIN34 PGA */
825 {"RIN34 PGA", "RIN3 Switch", "RIN3"},
Jinyoung Park97a775c2009-05-01 12:54:31 +0100826 {"RIN34 PGA", "RIN4 Switch", "RIN4/RXP"},
Mark Brownf10485e2008-06-05 13:49:33 +0100827 /* INMIXL */
828 {"INMIXR", "Record Right Volume", "ROMIX"},
829 {"INMIXR", "RIN2 Volume", "RIN2"},
830 {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"},
831 {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"},
Jinyoung Park97a775c2009-05-01 12:54:31 +0100832 /* AINRMUX */
833 {"AINRMUX", "INMIXR Mix", "INMIXR"},
834 {"AINRMUX", "DIFFINR Mix", "RIN12 PGA"},
835 {"AINRMUX", "DIFFINR Mix", "RIN34 PGA"},
836 {"AINRMUX", "RXVOICE Mix", "LIN4/RXN"},
837 {"AINRMUX", "RXVOICE Mix", "RIN4/RXP"},
Mark Brownf10485e2008-06-05 13:49:33 +0100838 /* ADC */
Jinyoung Park97a775c2009-05-01 12:54:31 +0100839 {"Right ADC", NULL, "AINRMUX"},
Mark Brownf10485e2008-06-05 13:49:33 +0100840
841 /* LOMIX */
842 {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"},
843 {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"},
844 {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
845 {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
846 {"LOMIX", "LOMIX Right ADC Bypass Switch", "AINRMUX"},
847 {"LOMIX", "LOMIX Left ADC Bypass Switch", "AINLMUX"},
848 {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"},
849
850 /* ROMIX */
851 {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"},
852 {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"},
853 {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
854 {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
855 {"ROMIX", "ROMIX Right ADC Bypass Switch", "AINRMUX"},
856 {"ROMIX", "ROMIX Left ADC Bypass Switch", "AINLMUX"},
857 {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"},
858
859 /* SPKMIX */
860 {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"},
861 {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"},
862 {"SPKMIX", "SPKMIX LADC Bypass Switch", "AINLMUX"},
863 {"SPKMIX", "SPKMIX RADC Bypass Switch", "AINRMUX"},
864 {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"},
865 {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"},
866 {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"},
Mark Brown436a7452008-08-15 16:22:32 +0100867 {"SPKMIX", "SPKMIX Left DAC Switch", "Left DAC"},
Mark Brownf10485e2008-06-05 13:49:33 +0100868
869 /* LONMIX */
870 {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"},
871 {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"},
872 {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"},
873
874 /* LOPMIX */
875 {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"},
876 {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"},
877 {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"},
878
879 /* OUT3MIX */
Jinyoung Park97a775c2009-05-01 12:54:31 +0100880 {"OUT3MIX", "OUT3MIX LIN4/RXP Bypass Switch", "LIN4/RXN"},
Mark Brownf10485e2008-06-05 13:49:33 +0100881 {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"},
882
883 /* OUT4MIX */
884 {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"},
885 {"OUT4MIX", "OUT4MIX RIN4/RXP Bypass Switch", "RIN4/RXP"},
886
887 /* RONMIX */
888 {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"},
889 {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"},
890 {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"},
891
892 /* ROPMIX */
893 {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"},
894 {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"},
895 {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"},
896
897 /* Out Mixer PGAs */
898 {"LOPGA", NULL, "LOMIX"},
899 {"ROPGA", NULL, "ROMIX"},
900
901 {"LOUT PGA", NULL, "LOMIX"},
902 {"ROUT PGA", NULL, "ROMIX"},
903
904 /* Output Pins */
905 {"LON", NULL, "LONMIX"},
906 {"LOP", NULL, "LOPMIX"},
Jinyoung Park97a775c2009-05-01 12:54:31 +0100907 {"OUT3", NULL, "OUT3MIX"},
Mark Brownf10485e2008-06-05 13:49:33 +0100908 {"LOUT", NULL, "LOUT PGA"},
909 {"SPKN", NULL, "SPKMIX"},
910 {"ROUT", NULL, "ROUT PGA"},
911 {"OUT4", NULL, "OUT4MIX"},
912 {"ROP", NULL, "ROPMIX"},
913 {"RON", NULL, "RONMIX"},
914};
915
916static int wm8990_add_widgets(struct snd_soc_codec *codec)
917{
918 snd_soc_dapm_new_controls(codec, wm8990_dapm_widgets,
919 ARRAY_SIZE(wm8990_dapm_widgets));
920
921 /* set up the WM8990 audio map */
922 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
923
Mark Brownf10485e2008-06-05 13:49:33 +0100924 return 0;
925}
926
927/* PLL divisors */
928struct _pll_div {
929 u32 div2;
930 u32 n;
931 u32 k;
932};
933
934/* The size in bits of the pll divide multiplied by 10
935 * to allow rounding later */
936#define FIXED_PLL_SIZE ((1 << 16) * 10)
937
938static void pll_factors(struct _pll_div *pll_div, unsigned int target,
939 unsigned int source)
940{
941 u64 Kpart;
942 unsigned int K, Ndiv, Nmod;
943
944
945 Ndiv = target / source;
946 if (Ndiv < 6) {
947 source >>= 1;
948 pll_div->div2 = 1;
949 Ndiv = target / source;
950 } else
951 pll_div->div2 = 0;
952
953 if ((Ndiv < 6) || (Ndiv > 12))
954 printk(KERN_WARNING
Roel Kluin449bd542009-05-27 17:08:39 -0700955 "WM8990 N value outwith recommended range! N = %u\n", Ndiv);
Mark Brownf10485e2008-06-05 13:49:33 +0100956
957 pll_div->n = Ndiv;
958 Nmod = target % source;
959 Kpart = FIXED_PLL_SIZE * (long long)Nmod;
960
961 do_div(Kpart, source);
962
963 K = Kpart & 0xFFFFFFFF;
964
965 /* Check if we need to round */
966 if ((K % 10) >= 5)
967 K += 5;
968
969 /* Move down to proper range now rounding is done */
970 K /= 10;
971
972 pll_div->k = K;
973}
974
Mark Brown85488032009-09-05 18:52:16 +0100975static int wm8990_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
976 int source, unsigned int freq_in, unsigned int freq_out)
Mark Brownf10485e2008-06-05 13:49:33 +0100977{
978 u16 reg;
979 struct snd_soc_codec *codec = codec_dai->codec;
980 struct _pll_div pll_div;
981
982 if (freq_in && freq_out) {
983 pll_factors(&pll_div, freq_out * 4, freq_in);
984
985 /* Turn on PLL */
Mark Brown8d50e442009-07-10 23:12:01 +0100986 reg = snd_soc_read(codec, WM8990_POWER_MANAGEMENT_2);
Mark Brownf10485e2008-06-05 13:49:33 +0100987 reg |= WM8990_PLL_ENA;
Mark Brown8d50e442009-07-10 23:12:01 +0100988 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_2, reg);
Mark Brownf10485e2008-06-05 13:49:33 +0100989
990 /* sysclk comes from PLL */
Mark Brown8d50e442009-07-10 23:12:01 +0100991 reg = snd_soc_read(codec, WM8990_CLOCKING_2);
992 snd_soc_write(codec, WM8990_CLOCKING_2, reg | WM8990_SYSCLK_SRC);
Mark Brownf10485e2008-06-05 13:49:33 +0100993
Daniel Mack3ad2f3f2010-02-03 08:01:28 +0800994 /* set up N , fractional mode and pre-divisor if necessary */
Mark Brown8d50e442009-07-10 23:12:01 +0100995 snd_soc_write(codec, WM8990_PLL1, pll_div.n | WM8990_SDM |
Mark Brownf10485e2008-06-05 13:49:33 +0100996 (pll_div.div2?WM8990_PRESCALE:0));
Mark Brown8d50e442009-07-10 23:12:01 +0100997 snd_soc_write(codec, WM8990_PLL2, (u8)(pll_div.k>>8));
998 snd_soc_write(codec, WM8990_PLL3, (u8)(pll_div.k & 0xFF));
Mark Brownf10485e2008-06-05 13:49:33 +0100999 } else {
1000 /* Turn on PLL */
Mark Brown8d50e442009-07-10 23:12:01 +01001001 reg = snd_soc_read(codec, WM8990_POWER_MANAGEMENT_2);
Mark Brownf10485e2008-06-05 13:49:33 +01001002 reg &= ~WM8990_PLL_ENA;
Mark Brown8d50e442009-07-10 23:12:01 +01001003 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_2, reg);
Mark Brownf10485e2008-06-05 13:49:33 +01001004 }
1005 return 0;
1006}
1007
1008/*
1009 * Clock after PLL and dividers
1010 */
Liam Girdwoode550e172008-07-07 16:07:52 +01001011static int wm8990_set_dai_sysclk(struct snd_soc_dai *codec_dai,
Mark Brownf10485e2008-06-05 13:49:33 +01001012 int clk_id, unsigned int freq, int dir)
1013{
1014 struct snd_soc_codec *codec = codec_dai->codec;
Mark Brownb2c812e2010-04-14 15:35:19 +09001015 struct wm8990_priv *wm8990 = snd_soc_codec_get_drvdata(codec);
Mark Brownf10485e2008-06-05 13:49:33 +01001016
1017 wm8990->sysclk = freq;
1018 return 0;
1019}
1020
1021/*
1022 * Set's ADC and Voice DAC format.
1023 */
Liam Girdwoode550e172008-07-07 16:07:52 +01001024static int wm8990_set_dai_fmt(struct snd_soc_dai *codec_dai,
Mark Brownf10485e2008-06-05 13:49:33 +01001025 unsigned int fmt)
1026{
1027 struct snd_soc_codec *codec = codec_dai->codec;
1028 u16 audio1, audio3;
1029
Mark Brown8d50e442009-07-10 23:12:01 +01001030 audio1 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_1);
1031 audio3 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_3);
Mark Brownf10485e2008-06-05 13:49:33 +01001032
1033 /* set master/slave audio interface */
1034 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1035 case SND_SOC_DAIFMT_CBS_CFS:
1036 audio3 &= ~WM8990_AIF_MSTR1;
1037 break;
1038 case SND_SOC_DAIFMT_CBM_CFM:
1039 audio3 |= WM8990_AIF_MSTR1;
1040 break;
1041 default:
1042 return -EINVAL;
1043 }
1044
1045 audio1 &= ~WM8990_AIF_FMT_MASK;
1046
1047 /* interface format */
1048 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1049 case SND_SOC_DAIFMT_I2S:
1050 audio1 |= WM8990_AIF_TMF_I2S;
1051 audio1 &= ~WM8990_AIF_LRCLK_INV;
1052 break;
1053 case SND_SOC_DAIFMT_RIGHT_J:
1054 audio1 |= WM8990_AIF_TMF_RIGHTJ;
1055 audio1 &= ~WM8990_AIF_LRCLK_INV;
1056 break;
1057 case SND_SOC_DAIFMT_LEFT_J:
1058 audio1 |= WM8990_AIF_TMF_LEFTJ;
1059 audio1 &= ~WM8990_AIF_LRCLK_INV;
1060 break;
1061 case SND_SOC_DAIFMT_DSP_A:
1062 audio1 |= WM8990_AIF_TMF_DSP;
1063 audio1 &= ~WM8990_AIF_LRCLK_INV;
1064 break;
1065 case SND_SOC_DAIFMT_DSP_B:
1066 audio1 |= WM8990_AIF_TMF_DSP | WM8990_AIF_LRCLK_INV;
1067 break;
1068 default:
1069 return -EINVAL;
1070 }
1071
Mark Brown8d50e442009-07-10 23:12:01 +01001072 snd_soc_write(codec, WM8990_AUDIO_INTERFACE_1, audio1);
1073 snd_soc_write(codec, WM8990_AUDIO_INTERFACE_3, audio3);
Mark Brownf10485e2008-06-05 13:49:33 +01001074 return 0;
1075}
1076
Liam Girdwoode550e172008-07-07 16:07:52 +01001077static int wm8990_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
Mark Brownf10485e2008-06-05 13:49:33 +01001078 int div_id, int div)
1079{
1080 struct snd_soc_codec *codec = codec_dai->codec;
1081 u16 reg;
1082
1083 switch (div_id) {
1084 case WM8990_MCLK_DIV:
Mark Brown8d50e442009-07-10 23:12:01 +01001085 reg = snd_soc_read(codec, WM8990_CLOCKING_2) &
Mark Brownf10485e2008-06-05 13:49:33 +01001086 ~WM8990_MCLK_DIV_MASK;
Mark Brown8d50e442009-07-10 23:12:01 +01001087 snd_soc_write(codec, WM8990_CLOCKING_2, reg | div);
Mark Brownf10485e2008-06-05 13:49:33 +01001088 break;
1089 case WM8990_DACCLK_DIV:
Mark Brown8d50e442009-07-10 23:12:01 +01001090 reg = snd_soc_read(codec, WM8990_CLOCKING_2) &
Mark Brownf10485e2008-06-05 13:49:33 +01001091 ~WM8990_DAC_CLKDIV_MASK;
Mark Brown8d50e442009-07-10 23:12:01 +01001092 snd_soc_write(codec, WM8990_CLOCKING_2, reg | div);
Mark Brownf10485e2008-06-05 13:49:33 +01001093 break;
1094 case WM8990_ADCCLK_DIV:
Mark Brown8d50e442009-07-10 23:12:01 +01001095 reg = snd_soc_read(codec, WM8990_CLOCKING_2) &
Mark Brownf10485e2008-06-05 13:49:33 +01001096 ~WM8990_ADC_CLKDIV_MASK;
Mark Brown8d50e442009-07-10 23:12:01 +01001097 snd_soc_write(codec, WM8990_CLOCKING_2, reg | div);
Mark Brownf10485e2008-06-05 13:49:33 +01001098 break;
1099 case WM8990_BCLK_DIV:
Mark Brown8d50e442009-07-10 23:12:01 +01001100 reg = snd_soc_read(codec, WM8990_CLOCKING_1) &
Mark Brownf10485e2008-06-05 13:49:33 +01001101 ~WM8990_BCLK_DIV_MASK;
Mark Brown8d50e442009-07-10 23:12:01 +01001102 snd_soc_write(codec, WM8990_CLOCKING_1, reg | div);
Mark Brownf10485e2008-06-05 13:49:33 +01001103 break;
1104 default:
1105 return -EINVAL;
1106 }
1107
1108 return 0;
1109}
1110
1111/*
1112 * Set PCM DAI bit size and sample rate.
1113 */
1114static int wm8990_hw_params(struct snd_pcm_substream *substream,
Mark Browndee89c42008-11-18 22:11:38 +00001115 struct snd_pcm_hw_params *params,
1116 struct snd_soc_dai *dai)
Mark Brownf10485e2008-06-05 13:49:33 +01001117{
1118 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1119 struct snd_soc_device *socdev = rtd->socdev;
Mark Brown6627a652009-01-23 22:55:23 +00001120 struct snd_soc_codec *codec = socdev->card->codec;
Mark Brown8d50e442009-07-10 23:12:01 +01001121 u16 audio1 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_1);
Mark Brownf10485e2008-06-05 13:49:33 +01001122
1123 audio1 &= ~WM8990_AIF_WL_MASK;
1124 /* bit size */
1125 switch (params_format(params)) {
1126 case SNDRV_PCM_FORMAT_S16_LE:
1127 break;
1128 case SNDRV_PCM_FORMAT_S20_3LE:
1129 audio1 |= WM8990_AIF_WL_20BITS;
1130 break;
1131 case SNDRV_PCM_FORMAT_S24_LE:
1132 audio1 |= WM8990_AIF_WL_24BITS;
1133 break;
1134 case SNDRV_PCM_FORMAT_S32_LE:
1135 audio1 |= WM8990_AIF_WL_32BITS;
1136 break;
1137 }
1138
Mark Brown8d50e442009-07-10 23:12:01 +01001139 snd_soc_write(codec, WM8990_AUDIO_INTERFACE_1, audio1);
Mark Brownf10485e2008-06-05 13:49:33 +01001140 return 0;
1141}
1142
Liam Girdwoode550e172008-07-07 16:07:52 +01001143static int wm8990_mute(struct snd_soc_dai *dai, int mute)
Mark Brownf10485e2008-06-05 13:49:33 +01001144{
1145 struct snd_soc_codec *codec = dai->codec;
1146 u16 val;
1147
Mark Brown8d50e442009-07-10 23:12:01 +01001148 val = snd_soc_read(codec, WM8990_DAC_CTRL) & ~WM8990_DAC_MUTE;
Mark Brownf10485e2008-06-05 13:49:33 +01001149
1150 if (mute)
Mark Brown8d50e442009-07-10 23:12:01 +01001151 snd_soc_write(codec, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE);
Mark Brownf10485e2008-06-05 13:49:33 +01001152 else
Mark Brown8d50e442009-07-10 23:12:01 +01001153 snd_soc_write(codec, WM8990_DAC_CTRL, val);
Mark Brownf10485e2008-06-05 13:49:33 +01001154
1155 return 0;
1156}
1157
1158static int wm8990_set_bias_level(struct snd_soc_codec *codec,
1159 enum snd_soc_bias_level level)
1160{
1161 u16 val;
1162
1163 switch (level) {
1164 case SND_SOC_BIAS_ON:
1165 break;
Mark Brown2adb9832008-11-17 17:11:14 +00001166
Mark Brownf10485e2008-06-05 13:49:33 +01001167 case SND_SOC_BIAS_PREPARE:
Mark Brown2adb9832008-11-17 17:11:14 +00001168 /* VMID=2*50k */
Mark Brown8d50e442009-07-10 23:12:01 +01001169 val = snd_soc_read(codec, WM8990_POWER_MANAGEMENT_1) &
Mark Brown2adb9832008-11-17 17:11:14 +00001170 ~WM8990_VMID_MODE_MASK;
Mark Brown8d50e442009-07-10 23:12:01 +01001171 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, val | 0x2);
Mark Brownf10485e2008-06-05 13:49:33 +01001172 break;
Mark Brown2adb9832008-11-17 17:11:14 +00001173
Mark Brownf10485e2008-06-05 13:49:33 +01001174 case SND_SOC_BIAS_STANDBY:
1175 if (codec->bias_level == SND_SOC_BIAS_OFF) {
1176 /* Enable all output discharge bits */
Mark Brown8d50e442009-07-10 23:12:01 +01001177 snd_soc_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE |
Mark Brownf10485e2008-06-05 13:49:33 +01001178 WM8990_DIS_RLINE | WM8990_DIS_OUT3 |
1179 WM8990_DIS_OUT4 | WM8990_DIS_LOUT |
1180 WM8990_DIS_ROUT);
1181
1182 /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */
Mark Brown8d50e442009-07-10 23:12:01 +01001183 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
Mark Brownf10485e2008-06-05 13:49:33 +01001184 WM8990_BUFDCOPEN | WM8990_POBCTRL |
1185 WM8990_VMIDTOG);
1186
1187 /* Delay to allow output caps to discharge */
1188 msleep(msecs_to_jiffies(300));
1189
1190 /* Disable VMIDTOG */
Mark Brown8d50e442009-07-10 23:12:01 +01001191 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
Mark Brownf10485e2008-06-05 13:49:33 +01001192 WM8990_BUFDCOPEN | WM8990_POBCTRL);
1193
1194 /* disable all output discharge bits */
Mark Brown8d50e442009-07-10 23:12:01 +01001195 snd_soc_write(codec, WM8990_ANTIPOP1, 0);
Mark Brownf10485e2008-06-05 13:49:33 +01001196
1197 /* Enable outputs */
Mark Brown8d50e442009-07-10 23:12:01 +01001198 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1b00);
Mark Brownf10485e2008-06-05 13:49:33 +01001199
1200 msleep(msecs_to_jiffies(50));
1201
1202 /* Enable VMID at 2x50k */
Mark Brown8d50e442009-07-10 23:12:01 +01001203 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f02);
Mark Brownf10485e2008-06-05 13:49:33 +01001204
1205 msleep(msecs_to_jiffies(100));
1206
1207 /* Enable VREF */
Mark Brown8d50e442009-07-10 23:12:01 +01001208 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03);
Mark Brownf10485e2008-06-05 13:49:33 +01001209
1210 msleep(msecs_to_jiffies(600));
1211
1212 /* Enable BUFIOEN */
Mark Brown8d50e442009-07-10 23:12:01 +01001213 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
Mark Brownf10485e2008-06-05 13:49:33 +01001214 WM8990_BUFDCOPEN | WM8990_POBCTRL |
1215 WM8990_BUFIOEN);
1216
1217 /* Disable outputs */
Mark Brown8d50e442009-07-10 23:12:01 +01001218 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x3);
Mark Brownf10485e2008-06-05 13:49:33 +01001219
1220 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
Mark Brown8d50e442009-07-10 23:12:01 +01001221 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_BUFIOEN);
Mark Brownf10485e2008-06-05 13:49:33 +01001222
Mark Brownbe1b87c2008-11-17 17:09:34 +00001223 /* Enable workaround for ADC clocking issue. */
Mark Brown8d50e442009-07-10 23:12:01 +01001224 snd_soc_write(codec, WM8990_EXT_ACCESS_ENA, 0x2);
1225 snd_soc_write(codec, WM8990_EXT_CTL1, 0xa003);
1226 snd_soc_write(codec, WM8990_EXT_ACCESS_ENA, 0);
Mark Brownf10485e2008-06-05 13:49:33 +01001227 }
Mark Brown2adb9832008-11-17 17:11:14 +00001228
1229 /* VMID=2*250k */
Mark Brown8d50e442009-07-10 23:12:01 +01001230 val = snd_soc_read(codec, WM8990_POWER_MANAGEMENT_1) &
Mark Brown2adb9832008-11-17 17:11:14 +00001231 ~WM8990_VMID_MODE_MASK;
Mark Brown8d50e442009-07-10 23:12:01 +01001232 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, val | 0x4);
Mark Brownf10485e2008-06-05 13:49:33 +01001233 break;
1234
1235 case SND_SOC_BIAS_OFF:
1236 /* Enable POBCTRL and SOFT_ST */
Mark Brown8d50e442009-07-10 23:12:01 +01001237 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
Mark Brownf10485e2008-06-05 13:49:33 +01001238 WM8990_POBCTRL | WM8990_BUFIOEN);
1239
1240 /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */
Mark Brown8d50e442009-07-10 23:12:01 +01001241 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
Mark Brownf10485e2008-06-05 13:49:33 +01001242 WM8990_BUFDCOPEN | WM8990_POBCTRL |
1243 WM8990_BUFIOEN);
1244
1245 /* mute DAC */
Mark Brown8d50e442009-07-10 23:12:01 +01001246 val = snd_soc_read(codec, WM8990_DAC_CTRL);
1247 snd_soc_write(codec, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE);
Mark Brownf10485e2008-06-05 13:49:33 +01001248
1249 /* Enable any disabled outputs */
Mark Brown8d50e442009-07-10 23:12:01 +01001250 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03);
Mark Brownf10485e2008-06-05 13:49:33 +01001251
1252 /* Disable VMID */
Mark Brown8d50e442009-07-10 23:12:01 +01001253 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f01);
Mark Brownf10485e2008-06-05 13:49:33 +01001254
1255 msleep(msecs_to_jiffies(300));
1256
1257 /* Enable all output discharge bits */
Mark Brown8d50e442009-07-10 23:12:01 +01001258 snd_soc_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE |
Mark Brownf10485e2008-06-05 13:49:33 +01001259 WM8990_DIS_RLINE | WM8990_DIS_OUT3 |
1260 WM8990_DIS_OUT4 | WM8990_DIS_LOUT |
1261 WM8990_DIS_ROUT);
1262
1263 /* Disable VREF */
Mark Brown8d50e442009-07-10 23:12:01 +01001264 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x0);
Mark Brownf10485e2008-06-05 13:49:33 +01001265
1266 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
Mark Brown8d50e442009-07-10 23:12:01 +01001267 snd_soc_write(codec, WM8990_ANTIPOP2, 0x0);
Mark Brownf10485e2008-06-05 13:49:33 +01001268 break;
1269 }
1270
1271 codec->bias_level = level;
1272 return 0;
1273}
1274
1275#define WM8990_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
1276 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
1277 SNDRV_PCM_RATE_48000)
1278
1279#define WM8990_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1280 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1281
1282/*
1283 * The WM8990 supports 2 different and mutually exclusive DAI
1284 * configurations.
1285 *
1286 * 1. ADC/DAC on Primary Interface
1287 * 2. ADC on Primary Interface/DAC on secondary
1288 */
Eric Miao6335d052009-03-03 09:41:00 +08001289static struct snd_soc_dai_ops wm8990_dai_ops = {
1290 .hw_params = wm8990_hw_params,
1291 .digital_mute = wm8990_mute,
1292 .set_fmt = wm8990_set_dai_fmt,
1293 .set_clkdiv = wm8990_set_dai_clkdiv,
1294 .set_pll = wm8990_set_dai_pll,
1295 .set_sysclk = wm8990_set_dai_sysclk,
1296};
1297
Liam Girdwoode550e172008-07-07 16:07:52 +01001298struct snd_soc_dai wm8990_dai = {
Mark Brownf10485e2008-06-05 13:49:33 +01001299/* ADC/DAC on primary */
1300 .name = "WM8990 ADC/DAC Primary",
1301 .id = 1,
1302 .playback = {
1303 .stream_name = "Playback",
1304 .channels_min = 1,
1305 .channels_max = 2,
1306 .rates = WM8990_RATES,
1307 .formats = WM8990_FORMATS,},
1308 .capture = {
1309 .stream_name = "Capture",
1310 .channels_min = 1,
1311 .channels_max = 2,
1312 .rates = WM8990_RATES,
1313 .formats = WM8990_FORMATS,},
Eric Miao6335d052009-03-03 09:41:00 +08001314 .ops = &wm8990_dai_ops,
Mark Brownf10485e2008-06-05 13:49:33 +01001315};
1316EXPORT_SYMBOL_GPL(wm8990_dai);
1317
1318static int wm8990_suspend(struct platform_device *pdev, pm_message_t state)
1319{
1320 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
Mark Brown6627a652009-01-23 22:55:23 +00001321 struct snd_soc_codec *codec = socdev->card->codec;
Mark Brownf10485e2008-06-05 13:49:33 +01001322
Mark Brownf10485e2008-06-05 13:49:33 +01001323 wm8990_set_bias_level(codec, SND_SOC_BIAS_OFF);
1324 return 0;
1325}
1326
1327static int wm8990_resume(struct platform_device *pdev)
1328{
1329 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
Mark Brown6627a652009-01-23 22:55:23 +00001330 struct snd_soc_codec *codec = socdev->card->codec;
Mark Brownf10485e2008-06-05 13:49:33 +01001331 int i;
1332 u8 data[2];
1333 u16 *cache = codec->reg_cache;
1334
Mark Brownf10485e2008-06-05 13:49:33 +01001335 /* Sync reg_cache with the hardware */
1336 for (i = 0; i < ARRAY_SIZE(wm8990_reg); i++) {
1337 if (i + 1 == WM8990_RESET)
1338 continue;
1339 data[0] = ((i + 1) << 1) | ((cache[i] >> 8) & 0x0001);
1340 data[1] = cache[i] & 0x00ff;
1341 codec->hw_write(codec->control_data, data, 2);
1342 }
1343
1344 wm8990_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1345 return 0;
1346}
1347
1348/*
1349 * initialise the WM8990 driver
1350 * register the mixer and dsp interfaces with the kernel
1351 */
1352static int wm8990_init(struct snd_soc_device *socdev)
1353{
Mark Brown6627a652009-01-23 22:55:23 +00001354 struct snd_soc_codec *codec = socdev->card->codec;
Mark Brownf10485e2008-06-05 13:49:33 +01001355 u16 reg;
1356 int ret = 0;
1357
1358 codec->name = "WM8990";
1359 codec->owner = THIS_MODULE;
Mark Brownf10485e2008-06-05 13:49:33 +01001360 codec->set_bias_level = wm8990_set_bias_level;
1361 codec->dai = &wm8990_dai;
1362 codec->num_dai = 2;
1363 codec->reg_cache_size = ARRAY_SIZE(wm8990_reg);
1364 codec->reg_cache = kmemdup(wm8990_reg, sizeof(wm8990_reg), GFP_KERNEL);
1365
1366 if (codec->reg_cache == NULL)
1367 return -ENOMEM;
1368
Mark Brown8d50e442009-07-10 23:12:01 +01001369 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1370 if (ret < 0) {
1371 printk(KERN_ERR "wm8990: failed to set cache I/O: %d\n", ret);
1372 goto pcm_err;
1373 }
1374
Mark Brownf10485e2008-06-05 13:49:33 +01001375 wm8990_reset(codec);
1376
1377 /* register pcms */
1378 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1379 if (ret < 0) {
1380 printk(KERN_ERR "wm8990: failed to create pcms\n");
1381 goto pcm_err;
1382 }
1383
1384 /* charge output caps */
1385 codec->bias_level = SND_SOC_BIAS_OFF;
1386 wm8990_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1387
Mark Brown8d50e442009-07-10 23:12:01 +01001388 reg = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_4);
1389 snd_soc_write(codec, WM8990_AUDIO_INTERFACE_4, reg | WM8990_ALRCGPIO1);
Mark Brownf10485e2008-06-05 13:49:33 +01001390
Mark Brown8d50e442009-07-10 23:12:01 +01001391 reg = snd_soc_read(codec, WM8990_GPIO1_GPIO2) &
Mark Brownf10485e2008-06-05 13:49:33 +01001392 ~WM8990_GPIO1_SEL_MASK;
Mark Brown8d50e442009-07-10 23:12:01 +01001393 snd_soc_write(codec, WM8990_GPIO1_GPIO2, reg | 1);
Mark Brownf10485e2008-06-05 13:49:33 +01001394
Mark Brown8d50e442009-07-10 23:12:01 +01001395 reg = snd_soc_read(codec, WM8990_POWER_MANAGEMENT_2);
1396 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_2, reg | WM8990_OPCLK_ENA);
Mark Brownf10485e2008-06-05 13:49:33 +01001397
Mark Brown8d50e442009-07-10 23:12:01 +01001398 snd_soc_write(codec, WM8990_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8));
1399 snd_soc_write(codec, WM8990_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8));
Mark Brownf10485e2008-06-05 13:49:33 +01001400
Ian Molton3e8e1952009-01-09 00:23:21 +00001401 snd_soc_add_controls(codec, wm8990_snd_controls,
1402 ARRAY_SIZE(wm8990_snd_controls));
Mark Brownf10485e2008-06-05 13:49:33 +01001403 wm8990_add_widgets(codec);
Mark Brownfe3e78e2009-11-03 22:13:13 +00001404
Mark Brownf10485e2008-06-05 13:49:33 +01001405 return ret;
1406
Mark Brownf10485e2008-06-05 13:49:33 +01001407pcm_err:
1408 kfree(codec->reg_cache);
1409 return ret;
1410}
1411
1412/* If the i2c layer weren't so broken, we could pass this kind of data
1413 around */
1414static struct snd_soc_device *wm8990_socdev;
1415
1416#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1417
1418/*
1419 * WM891 2 wire address is determined by GPIO5
1420 * state during powerup.
1421 * low = 0x34
1422 * high = 0x36
1423 */
Mark Brownf10485e2008-06-05 13:49:33 +01001424
Jean Delvaree5d3fd32008-09-01 18:47:02 +01001425static int wm8990_i2c_probe(struct i2c_client *i2c,
1426 const struct i2c_device_id *id)
Mark Brownf10485e2008-06-05 13:49:33 +01001427{
1428 struct snd_soc_device *socdev = wm8990_socdev;
Mark Brown6627a652009-01-23 22:55:23 +00001429 struct snd_soc_codec *codec = socdev->card->codec;
Mark Brownf10485e2008-06-05 13:49:33 +01001430 int ret;
1431
Mark Brownf10485e2008-06-05 13:49:33 +01001432 i2c_set_clientdata(i2c, codec);
1433 codec->control_data = i2c;
1434
Mark Brownf10485e2008-06-05 13:49:33 +01001435 ret = wm8990_init(socdev);
Jean Delvaree5d3fd32008-09-01 18:47:02 +01001436 if (ret < 0)
Mark Browna5c95e92008-06-23 14:51:29 +01001437 pr_err("failed to initialise WM8990\n");
Mark Brownf10485e2008-06-05 13:49:33 +01001438
Mark Brownf10485e2008-06-05 13:49:33 +01001439 return ret;
1440}
1441
Jean Delvaree5d3fd32008-09-01 18:47:02 +01001442static int wm8990_i2c_remove(struct i2c_client *client)
Mark Brownf10485e2008-06-05 13:49:33 +01001443{
1444 struct snd_soc_codec *codec = i2c_get_clientdata(client);
Mark Brownf10485e2008-06-05 13:49:33 +01001445 kfree(codec->reg_cache);
Mark Brownf10485e2008-06-05 13:49:33 +01001446 return 0;
1447}
1448
Jean Delvaree5d3fd32008-09-01 18:47:02 +01001449static const struct i2c_device_id wm8990_i2c_id[] = {
1450 { "wm8990", 0 },
1451 { }
1452};
1453MODULE_DEVICE_TABLE(i2c, wm8990_i2c_id);
Mark Brownf10485e2008-06-05 13:49:33 +01001454
1455static struct i2c_driver wm8990_i2c_driver = {
1456 .driver = {
1457 .name = "WM8990 I2C Codec",
1458 .owner = THIS_MODULE,
1459 },
Jean Delvaree5d3fd32008-09-01 18:47:02 +01001460 .probe = wm8990_i2c_probe,
1461 .remove = wm8990_i2c_remove,
1462 .id_table = wm8990_i2c_id,
Mark Brownf10485e2008-06-05 13:49:33 +01001463};
1464
Jean Delvaree5d3fd32008-09-01 18:47:02 +01001465static int wm8990_add_i2c_device(struct platform_device *pdev,
1466 const struct wm8990_setup_data *setup)
1467{
1468 struct i2c_board_info info;
1469 struct i2c_adapter *adapter;
1470 struct i2c_client *client;
1471 int ret;
1472
1473 ret = i2c_add_driver(&wm8990_i2c_driver);
1474 if (ret != 0) {
1475 dev_err(&pdev->dev, "can't add i2c driver\n");
1476 return ret;
1477 }
1478
1479 memset(&info, 0, sizeof(struct i2c_board_info));
1480 info.addr = setup->i2c_address;
1481 strlcpy(info.type, "wm8990", I2C_NAME_SIZE);
1482
1483 adapter = i2c_get_adapter(setup->i2c_bus);
1484 if (!adapter) {
1485 dev_err(&pdev->dev, "can't get i2c adapter %d\n",
1486 setup->i2c_bus);
1487 goto err_driver;
1488 }
1489
1490 client = i2c_new_device(adapter, &info);
1491 i2c_put_adapter(adapter);
1492 if (!client) {
1493 dev_err(&pdev->dev, "can't add i2c device at 0x%x\n",
1494 (unsigned int)info.addr);
1495 goto err_driver;
1496 }
1497
1498 return 0;
1499
1500err_driver:
1501 i2c_del_driver(&wm8990_i2c_driver);
1502 return -ENODEV;
1503}
Mark Brownf10485e2008-06-05 13:49:33 +01001504#endif
1505
1506static int wm8990_probe(struct platform_device *pdev)
1507{
1508 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1509 struct wm8990_setup_data *setup;
1510 struct snd_soc_codec *codec;
1511 struct wm8990_priv *wm8990;
Mark Brownb7c9d852008-09-01 18:47:04 +01001512 int ret;
Mark Brownf10485e2008-06-05 13:49:33 +01001513
Mark Browna5c95e92008-06-23 14:51:29 +01001514 pr_info("WM8990 Audio Codec %s\n", WM8990_VERSION);
Mark Brownf10485e2008-06-05 13:49:33 +01001515
1516 setup = socdev->codec_data;
1517 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
1518 if (codec == NULL)
1519 return -ENOMEM;
1520
1521 wm8990 = kzalloc(sizeof(struct wm8990_priv), GFP_KERNEL);
1522 if (wm8990 == NULL) {
1523 kfree(codec);
1524 return -ENOMEM;
1525 }
1526
Mark Brownb2c812e2010-04-14 15:35:19 +09001527 snd_soc_codec_set_drvdata(codec, wm8990);
Mark Brown6627a652009-01-23 22:55:23 +00001528 socdev->card->codec = codec;
Mark Brownf10485e2008-06-05 13:49:33 +01001529 mutex_init(&codec->mutex);
1530 INIT_LIST_HEAD(&codec->dapm_widgets);
1531 INIT_LIST_HEAD(&codec->dapm_paths);
1532 wm8990_socdev = socdev;
1533
Mark Brownb7c9d852008-09-01 18:47:04 +01001534 ret = -ENODEV;
1535
Mark Brownf10485e2008-06-05 13:49:33 +01001536#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1537 if (setup->i2c_address) {
Mark Brownf10485e2008-06-05 13:49:33 +01001538 codec->hw_write = (hw_write_t)i2c_master_send;
Jean Delvaree5d3fd32008-09-01 18:47:02 +01001539 ret = wm8990_add_i2c_device(pdev, setup);
Mark Brownf10485e2008-06-05 13:49:33 +01001540 }
Mark Brownf10485e2008-06-05 13:49:33 +01001541#endif
Jean Delvare3051e412008-08-25 11:49:20 +01001542
1543 if (ret != 0) {
Mark Brownb2c812e2010-04-14 15:35:19 +09001544 kfree(snd_soc_codec_get_drvdata(codec));
Jean Delvare3051e412008-08-25 11:49:20 +01001545 kfree(codec);
1546 }
Mark Brownf10485e2008-06-05 13:49:33 +01001547 return ret;
1548}
1549
1550/* power down chip */
1551static int wm8990_remove(struct platform_device *pdev)
1552{
1553 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
Mark Brown6627a652009-01-23 22:55:23 +00001554 struct snd_soc_codec *codec = socdev->card->codec;
Mark Brownf10485e2008-06-05 13:49:33 +01001555
1556 if (codec->control_data)
1557 wm8990_set_bias_level(codec, SND_SOC_BIAS_OFF);
1558 snd_soc_free_pcms(socdev);
1559 snd_soc_dapm_free(socdev);
1560#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
Jean Delvaree5d3fd32008-09-01 18:47:02 +01001561 i2c_unregister_device(codec->control_data);
Mark Brownf10485e2008-06-05 13:49:33 +01001562 i2c_del_driver(&wm8990_i2c_driver);
1563#endif
Mark Brownb2c812e2010-04-14 15:35:19 +09001564 kfree(snd_soc_codec_get_drvdata(codec));
Mark Brownf10485e2008-06-05 13:49:33 +01001565 kfree(codec);
1566
1567 return 0;
1568}
1569
1570struct snd_soc_codec_device soc_codec_dev_wm8990 = {
1571 .probe = wm8990_probe,
1572 .remove = wm8990_remove,
1573 .suspend = wm8990_suspend,
1574 .resume = wm8990_resume,
1575};
1576EXPORT_SYMBOL_GPL(soc_codec_dev_wm8990);
1577
Takashi Iwaic9b3a402008-12-10 07:47:22 +01001578static int __init wm8990_modinit(void)
Mark Brown64089b82008-12-08 19:17:58 +00001579{
1580 return snd_soc_register_dai(&wm8990_dai);
1581}
1582module_init(wm8990_modinit);
1583
1584static void __exit wm8990_exit(void)
1585{
1586 snd_soc_unregister_dai(&wm8990_dai);
1587}
1588module_exit(wm8990_exit);
1589
Mark Brownf10485e2008-06-05 13:49:33 +01001590MODULE_DESCRIPTION("ASoC WM8990 driver");
1591MODULE_AUTHOR("Liam Girdwood");
1592MODULE_LICENSE("GPL");