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Russell Kinga09e64f2008-08-05 16:14:15 +01001/*
2 * arch/arm/mach-sa1100/include/mach/irqs.h
3 *
4 * Copyright (C) 1996 Russell King
5 * Copyright (C) 1998 Deborah Wallach (updates for SA1100/Brutus).
6 * Copyright (C) 1999 Nicolas Pitre (full GPIO irq isolation)
7 *
8 * 2001/11/14 RMK Cleaned up and standardised a lot of the IRQs.
9 */
10
11#define IRQ_GPIO0 0
12#define IRQ_GPIO1 1
13#define IRQ_GPIO2 2
14#define IRQ_GPIO3 3
15#define IRQ_GPIO4 4
16#define IRQ_GPIO5 5
17#define IRQ_GPIO6 6
18#define IRQ_GPIO7 7
19#define IRQ_GPIO8 8
20#define IRQ_GPIO9 9
21#define IRQ_GPIO10 10
22#define IRQ_GPIO11_27 11
23#define IRQ_LCD 12 /* LCD controller */
24#define IRQ_Ser0UDC 13 /* Ser. port 0 UDC */
25#define IRQ_Ser1SDLC 14 /* Ser. port 1 SDLC */
26#define IRQ_Ser1UART 15 /* Ser. port 1 UART */
27#define IRQ_Ser2ICP 16 /* Ser. port 2 ICP */
28#define IRQ_Ser3UART 17 /* Ser. port 3 UART */
29#define IRQ_Ser4MCP 18 /* Ser. port 4 MCP */
30#define IRQ_Ser4SSP 19 /* Ser. port 4 SSP */
31#define IRQ_DMA0 20 /* DMA controller channel 0 */
32#define IRQ_DMA1 21 /* DMA controller channel 1 */
33#define IRQ_DMA2 22 /* DMA controller channel 2 */
34#define IRQ_DMA3 23 /* DMA controller channel 3 */
35#define IRQ_DMA4 24 /* DMA controller channel 4 */
36#define IRQ_DMA5 25 /* DMA controller channel 5 */
37#define IRQ_OST0 26 /* OS Timer match 0 */
38#define IRQ_OST1 27 /* OS Timer match 1 */
39#define IRQ_OST2 28 /* OS Timer match 2 */
40#define IRQ_OST3 29 /* OS Timer match 3 */
41#define IRQ_RTC1Hz 30 /* RTC 1 Hz clock */
42#define IRQ_RTCAlrm 31 /* RTC Alarm */
43
44#define IRQ_GPIO11 32
45#define IRQ_GPIO12 33
46#define IRQ_GPIO13 34
47#define IRQ_GPIO14 35
48#define IRQ_GPIO15 36
49#define IRQ_GPIO16 37
50#define IRQ_GPIO17 38
51#define IRQ_GPIO18 39
52#define IRQ_GPIO19 40
53#define IRQ_GPIO20 41
54#define IRQ_GPIO21 42
55#define IRQ_GPIO22 43
56#define IRQ_GPIO23 44
57#define IRQ_GPIO24 45
58#define IRQ_GPIO25 46
59#define IRQ_GPIO26 47
60#define IRQ_GPIO27 48
61
62/*
63 * The next 16 interrupts are for board specific purposes. Since
64 * the kernel can only run on one machine at a time, we can re-use
65 * these. If you need more, increase IRQ_BOARD_END, but keep it
66 * within sensible limits. IRQs 49 to 64 are available.
67 */
68#define IRQ_BOARD_START 49
69#define IRQ_BOARD_END 65
70
71#define IRQ_SA1111_START (IRQ_BOARD_END)
72#define IRQ_GPAIN0 (IRQ_BOARD_END + 0)
73#define IRQ_GPAIN1 (IRQ_BOARD_END + 1)
74#define IRQ_GPAIN2 (IRQ_BOARD_END + 2)
75#define IRQ_GPAIN3 (IRQ_BOARD_END + 3)
76#define IRQ_GPBIN0 (IRQ_BOARD_END + 4)
77#define IRQ_GPBIN1 (IRQ_BOARD_END + 5)
78#define IRQ_GPBIN2 (IRQ_BOARD_END + 6)
79#define IRQ_GPBIN3 (IRQ_BOARD_END + 7)
80#define IRQ_GPBIN4 (IRQ_BOARD_END + 8)
81#define IRQ_GPBIN5 (IRQ_BOARD_END + 9)
82#define IRQ_GPCIN0 (IRQ_BOARD_END + 10)
83#define IRQ_GPCIN1 (IRQ_BOARD_END + 11)
84#define IRQ_GPCIN2 (IRQ_BOARD_END + 12)
85#define IRQ_GPCIN3 (IRQ_BOARD_END + 13)
86#define IRQ_GPCIN4 (IRQ_BOARD_END + 14)
87#define IRQ_GPCIN5 (IRQ_BOARD_END + 15)
88#define IRQ_GPCIN6 (IRQ_BOARD_END + 16)
89#define IRQ_GPCIN7 (IRQ_BOARD_END + 17)
90#define IRQ_MSTXINT (IRQ_BOARD_END + 18)
91#define IRQ_MSRXINT (IRQ_BOARD_END + 19)
92#define IRQ_MSSTOPERRINT (IRQ_BOARD_END + 20)
93#define IRQ_TPTXINT (IRQ_BOARD_END + 21)
94#define IRQ_TPRXINT (IRQ_BOARD_END + 22)
95#define IRQ_TPSTOPERRINT (IRQ_BOARD_END + 23)
96#define SSPXMTINT (IRQ_BOARD_END + 24)
97#define SSPRCVINT (IRQ_BOARD_END + 25)
98#define SSPROR (IRQ_BOARD_END + 26)
99#define AUDXMTDMADONEA (IRQ_BOARD_END + 32)
100#define AUDRCVDMADONEA (IRQ_BOARD_END + 33)
101#define AUDXMTDMADONEB (IRQ_BOARD_END + 34)
102#define AUDRCVDMADONEB (IRQ_BOARD_END + 35)
103#define AUDTFSR (IRQ_BOARD_END + 36)
104#define AUDRFSR (IRQ_BOARD_END + 37)
105#define AUDTUR (IRQ_BOARD_END + 38)
106#define AUDROR (IRQ_BOARD_END + 39)
107#define AUDDTS (IRQ_BOARD_END + 40)
108#define AUDRDD (IRQ_BOARD_END + 41)
109#define AUDSTO (IRQ_BOARD_END + 42)
110#define IRQ_USBPWR (IRQ_BOARD_END + 43)
111#define IRQ_HCIM (IRQ_BOARD_END + 44)
112#define IRQ_HCIBUFFACC (IRQ_BOARD_END + 45)
113#define IRQ_HCIRMTWKP (IRQ_BOARD_END + 46)
114#define IRQ_NHCIMFCIR (IRQ_BOARD_END + 47)
115#define IRQ_USB_PORT_RESUME (IRQ_BOARD_END + 48)
116#define IRQ_S0_READY_NINT (IRQ_BOARD_END + 49)
117#define IRQ_S1_READY_NINT (IRQ_BOARD_END + 50)
118#define IRQ_S0_CD_VALID (IRQ_BOARD_END + 51)
119#define IRQ_S1_CD_VALID (IRQ_BOARD_END + 52)
120#define IRQ_S0_BVD1_STSCHG (IRQ_BOARD_END + 53)
121#define IRQ_S1_BVD1_STSCHG (IRQ_BOARD_END + 54)
122
Russell Kinga09e64f2008-08-05 16:14:15 +0100123/*
124 * Figure out the MAX IRQ number.
125 *
126 * If we have an SA1111, the max IRQ is S1_BVD1_STSCHG+1.
127 * If we have an LoCoMo, the max IRQ is IRQ_LOCOMO_SPI_TEND+1
128 * Otherwise, we have the standard IRQs only.
129 */
130#ifdef CONFIG_SA1111
131#define NR_IRQS (IRQ_S1_BVD1_STSCHG + 1)
Russell Kinga09e64f2008-08-05 16:14:15 +0100132#elif defined(CONFIG_SHARP_LOCOMO)
Eric Miao00dd8022009-12-25 12:18:33 +0800133#define NR_IRQS (IRQ_LOCOMO_SPI + 1)
Russell Kinga09e64f2008-08-05 16:14:15 +0100134#else
135#define NR_IRQS (IRQ_BOARD_START)
136#endif
137
138/*
139 * Board specific IRQs. Define them here.
140 * Do not surround them with ifdefs.
141 */
142#define IRQ_NEPONSET_SMC9196 (IRQ_BOARD_START + 0)
143#define IRQ_NEPONSET_USAR (IRQ_BOARD_START + 1)
144#define IRQ_NEPONSET_SA1111 (IRQ_BOARD_START + 2)
145
146/* LoCoMo Interrupts (CONFIG_SHARP_LOCOMO) */
Eric Miaoda8065a2010-02-04 17:13:55 -0800147#define IRQ_LOCOMO_KEY (IRQ_BOARD_START + 0)
Russell Kinga09e64f2008-08-05 16:14:15 +0100148#define IRQ_LOCOMO_GPIO_BASE (IRQ_BOARD_START + 1)
149#define IRQ_LOCOMO_LT_BASE (IRQ_BOARD_START + 2)
150#define IRQ_LOCOMO_SPI_BASE (IRQ_BOARD_START + 3)
151