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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* -*- mode: c; c-basic-offset: 8 -*- */
2
3/* Driver for 53c700 and 53c700-66 chips from NCR and Symbios
4 *
5 * Copyright (C) 2001 by James.Bottomley@HansenPartnership.com
6 */
7
8#ifndef _53C700_H
9#define _53C700_H
10
11#include <linux/interrupt.h>
12#include <asm/io.h>
13
14#include <scsi/scsi_device.h>
15
16
Linus Torvalds1da177e2005-04-16 15:20:36 -070017/* Turn on for general debugging---too verbose for normal use */
18#undef NCR_700_DEBUG
19/* Debug the tag queues, checking hash queue allocation and deallocation
20 * and search for duplicate tags */
21#undef NCR_700_TAG_DEBUG
22
23#ifdef NCR_700_DEBUG
24#define DEBUG(x) printk x
25#else
26#define DEBUG(x)
27#endif
28
29/* The number of available command slots */
30#define NCR_700_COMMAND_SLOTS_PER_HOST 64
31/* The maximum number of Scatter Gathers we allow */
32#define NCR_700_SG_SEGMENTS 32
33/* The maximum number of luns (make this of the form 2^n) */
34#define NCR_700_MAX_LUNS 32
35#define NCR_700_LUN_MASK (NCR_700_MAX_LUNS - 1)
36/* Maximum number of tags the driver ever allows per device */
37#define NCR_700_MAX_TAGS 16
38/* Tag depth the driver starts out with (can be altered in sysfs) */
39#define NCR_700_DEFAULT_TAGS 4
40/* This is the default number of commands per LUN in the untagged case.
41 * two is a good value because it means we can have one command active and
42 * one command fully prepared and waiting
43 */
44#define NCR_700_CMD_PER_LUN 2
45/* magic byte identifying an internally generated REQUEST_SENSE command */
46#define NCR_700_INTERNAL_SENSE_MAGIC 0x42
47
Linus Torvalds1da177e2005-04-16 15:20:36 -070048struct NCR_700_Host_Parameters;
49
50/* These are the externally used routines */
51struct Scsi_Host *NCR_700_detect(struct scsi_host_template *,
52 struct NCR_700_Host_Parameters *, struct device *);
53int NCR_700_release(struct Scsi_Host *host);
54irqreturn_t NCR_700_intr(int, void *, struct pt_regs *);
55
56
57enum NCR_700_Host_State {
58 NCR_700_HOST_BUSY,
59 NCR_700_HOST_FREE,
60};
61
62struct NCR_700_SG_List {
63 /* The following is a script fragment to move the buffer onto the
64 * bus and then link the next fragment or return */
65 #define SCRIPT_MOVE_DATA_IN 0x09000000
66 #define SCRIPT_MOVE_DATA_OUT 0x08000000
67 __u32 ins;
68 __u32 pAddr;
69 #define SCRIPT_NOP 0x80000000
70 #define SCRIPT_RETURN 0x90080000
71};
72
73/* We use device->hostdata to store negotiated parameters. This is
74 * supposed to be a pointer to a device private area, but we cannot
75 * really use it as such since it will never be freed, so just use the
76 * 32 bits to cram the information. The SYNC negotiation sequence looks
77 * like:
78 *
79 * If DEV_NEGOTIATED_SYNC not set, tack and SDTR message on to the
80 * initial identify for the device and set DEV_BEGIN_SYNC_NEGOTATION
81 * If we get an SDTR reply, work out the SXFER parameters, squirrel
82 * them away here, clear DEV_BEGIN_SYNC_NEGOTIATION and set
83 * DEV_NEGOTIATED_SYNC. If we get a REJECT msg, squirrel
84 *
85 *
86 * 0:7 SXFER_REG negotiated value for this device
87 * 8:15 Current queue depth
88 * 16 negotiated SYNC flag
89 * 17 begin SYNC negotiation flag
90 * 18 device supports tag queueing */
91#define NCR_700_DEV_NEGOTIATED_SYNC (1<<16)
92#define NCR_700_DEV_BEGIN_SYNC_NEGOTIATION (1<<17)
93#define NCR_700_DEV_PRINT_SYNC_NEGOTIATION (1<<19)
94
95static inline void
96NCR_700_set_depth(struct scsi_device *SDp, __u8 depth)
97{
98 long l = (long)SDp->hostdata;
99
100 l &= 0xffff00ff;
101 l |= 0xff00 & (depth << 8);
102 SDp->hostdata = (void *)l;
103}
104static inline __u8
105NCR_700_get_depth(struct scsi_device *SDp)
106{
107 return ((((unsigned long)SDp->hostdata) & 0xff00)>>8);
108}
109static inline int
110NCR_700_is_flag_set(struct scsi_device *SDp, __u32 flag)
111{
112 return (spi_flags(SDp->sdev_target) & flag) == flag;
113}
114static inline int
115NCR_700_is_flag_clear(struct scsi_device *SDp, __u32 flag)
116{
117 return (spi_flags(SDp->sdev_target) & flag) == 0;
118}
119static inline void
120NCR_700_set_flag(struct scsi_device *SDp, __u32 flag)
121{
122 spi_flags(SDp->sdev_target) |= flag;
123}
124static inline void
125NCR_700_clear_flag(struct scsi_device *SDp, __u32 flag)
126{
127 spi_flags(SDp->sdev_target) &= ~flag;
128}
129
130enum NCR_700_tag_neg_state {
131 NCR_700_START_TAG_NEGOTIATION = 0,
132 NCR_700_DURING_TAG_NEGOTIATION = 1,
133 NCR_700_FINISHED_TAG_NEGOTIATION = 2,
134};
135
136static inline enum NCR_700_tag_neg_state
137NCR_700_get_tag_neg_state(struct scsi_device *SDp)
138{
139 return (enum NCR_700_tag_neg_state)((spi_flags(SDp->sdev_target)>>20) & 0x3);
140}
141
142static inline void
143NCR_700_set_tag_neg_state(struct scsi_device *SDp,
144 enum NCR_700_tag_neg_state state)
145{
146 /* clear the slot */
147 spi_flags(SDp->sdev_target) &= ~(0x3 << 20);
148 spi_flags(SDp->sdev_target) |= ((__u32)state) << 20;
149}
150
151struct NCR_700_command_slot {
152 struct NCR_700_SG_List SG[NCR_700_SG_SEGMENTS+1];
153 struct NCR_700_SG_List *pSG;
154 #define NCR_700_SLOT_MASK 0xFC
155 #define NCR_700_SLOT_MAGIC 0xb8
156 #define NCR_700_SLOT_FREE (0|NCR_700_SLOT_MAGIC) /* slot may be used */
157 #define NCR_700_SLOT_BUSY (1|NCR_700_SLOT_MAGIC) /* slot has command active on HA */
158 #define NCR_700_SLOT_QUEUED (2|NCR_700_SLOT_MAGIC) /* slot has command to be made active on HA */
159 __u8 state;
160 int tag;
161 __u32 resume_offset;
162 struct scsi_cmnd *cmnd;
163 /* The pci_mapped address of the actual command in cmnd */
164 dma_addr_t pCmd;
165 __u32 temp;
166 /* if this command is a pci_single mapping, holds the dma address
167 * for later unmapping in the done routine */
168 dma_addr_t dma_handle;
169 /* historical remnant, now used to link free commands */
170 struct NCR_700_command_slot *ITL_forw;
171};
172
173struct NCR_700_Host_Parameters {
174 /* These must be filled in by the calling driver */
175 int clock; /* board clock speed in MHz */
56fece22005-04-03 03:57:48 -0600176 void __iomem *base; /* the base for the port (copied to host) */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700177 struct device *dev;
178 __u32 dmode_extra; /* adjustable bus settings */
179 __u32 differential:1; /* if we are differential */
180#ifdef CONFIG_53C700_LE_ON_BE
181 /* This option is for HP only. Set it if your chip is wired for
182 * little endian on this platform (which is big endian) */
183 __u32 force_le_on_be:1;
184#endif
185 __u32 chip710:1; /* set if really a 710 not 700 */
186 __u32 burst_disable:1; /* set to 1 to disable 710 bursting */
187
188 /* NOTHING BELOW HERE NEEDS ALTERING */
189 __u32 fast:1; /* if we can alter the SCSI bus clock
190 speed (so can negiotiate sync) */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700191 int sync_clock; /* The speed of the SYNC core */
192
193 __u32 *script; /* pointer to script location */
194 __u32 pScript; /* physical mem addr of script */
195
196 enum NCR_700_Host_State state; /* protected by state lock */
197 struct scsi_cmnd *cmd;
198 /* Note: pScript contains the single consistent block of
199 * memory. All the msgin, msgout and status are allocated in
200 * this memory too (at separate cache lines). TOTAL_MEM_SIZE
201 * represents the total size of this area */
202#define MSG_ARRAY_SIZE 8
203#define MSGOUT_OFFSET (L1_CACHE_ALIGN(sizeof(SCRIPT)))
204 __u8 *msgout;
205#define MSGIN_OFFSET (MSGOUT_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
206 __u8 *msgin;
207#define STATUS_OFFSET (MSGIN_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
208 __u8 *status;
209#define SLOTS_OFFSET (STATUS_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
210 struct NCR_700_command_slot *slots;
211#define TOTAL_MEM_SIZE (SLOTS_OFFSET + L1_CACHE_ALIGN(sizeof(struct NCR_700_command_slot) * NCR_700_COMMAND_SLOTS_PER_HOST))
212 int saved_slot_position;
213 int command_slot_count; /* protected by state lock */
214 __u8 tag_negotiated;
215 __u8 rev;
216 __u8 reselection_id;
217 __u8 min_period;
218
219 /* Free list, singly linked by ITL_forw elements */
220 struct NCR_700_command_slot *free_list;
221 /* Completion for waited for ops, like reset, abort or
222 * device reset.
223 *
224 * NOTE: relies on single threading in the error handler to
225 * have only one outstanding at once */
226 struct completion *eh_complete;
227};
228
229/*
230 * 53C700 Register Interface - the offset from the Selected base
231 * I/O address */
232#ifdef CONFIG_53C700_LE_ON_BE
233#define bE (hostdata->force_le_on_be ? 0 : 3)
234#define bSWAP (hostdata->force_le_on_be)
56fece22005-04-03 03:57:48 -0600235/* This is terrible, but there's no raw version of ioread32. That means
236 * that on a be board we swap twice (once in ioread32 and once again to
237 * get the value correct) */
238#define bS_to_io(x) ((hostdata->force_le_on_be) ? (x) : cpu_to_le32(x))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700239#elif defined(__BIG_ENDIAN)
240#define bE 3
241#define bSWAP 0
56fece22005-04-03 03:57:48 -0600242#define bS_to_io(x) (x)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700243#elif defined(__LITTLE_ENDIAN)
244#define bE 0
245#define bSWAP 0
56fece22005-04-03 03:57:48 -0600246#define bS_to_io(x) (x)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700247#else
248#error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined, did you include byteorder.h?"
249#endif
250#define bS_to_cpu(x) (bSWAP ? le32_to_cpu(x) : (x))
251#define bS_to_host(x) (bSWAP ? cpu_to_le32(x) : (x))
252
253/* NOTE: These registers are in the LE register space only, the required byte
254 * swapping is done by the NCR_700_{read|write}[b] functions */
255#define SCNTL0_REG 0x00
256#define FULL_ARBITRATION 0xc0
257#define PARITY 0x08
258#define ENABLE_PARITY 0x04
259#define AUTO_ATN 0x02
260#define SCNTL1_REG 0x01
261#define SLOW_BUS 0x80
262#define ENABLE_SELECT 0x20
263#define ASSERT_RST 0x08
264#define ASSERT_EVEN_PARITY 0x04
265#define SDID_REG 0x02
266#define SIEN_REG 0x03
267#define PHASE_MM_INT 0x80
268#define FUNC_COMP_INT 0x40
269#define SEL_TIMEOUT_INT 0x20
270#define SELECT_INT 0x10
271#define GROSS_ERR_INT 0x08
272#define UX_DISC_INT 0x04
273#define RST_INT 0x02
274#define PAR_ERR_INT 0x01
275#define SCID_REG 0x04
276#define SXFER_REG 0x05
277#define ASYNC_OPERATION 0x00
278#define SODL_REG 0x06
279#define SOCL_REG 0x07
280#define SFBR_REG 0x08
281#define SIDL_REG 0x09
282#define SBDL_REG 0x0A
283#define SBCL_REG 0x0B
284/* read bits */
285#define SBCL_IO 0x01
286/*write bits */
287#define SYNC_DIV_AS_ASYNC 0x00
288#define SYNC_DIV_1_0 0x01
289#define SYNC_DIV_1_5 0x02
290#define SYNC_DIV_2_0 0x03
291#define DSTAT_REG 0x0C
292#define ILGL_INST_DETECTED 0x01
293#define WATCH_DOG_INTERRUPT 0x02
294#define SCRIPT_INT_RECEIVED 0x04
295#define ABORTED 0x10
296#define SSTAT0_REG 0x0D
297#define PARITY_ERROR 0x01
298#define SCSI_RESET_DETECTED 0x02
299#define UNEXPECTED_DISCONNECT 0x04
300#define SCSI_GROSS_ERROR 0x08
301#define SELECTED 0x10
302#define SELECTION_TIMEOUT 0x20
303#define FUNCTION_COMPLETE 0x40
304#define PHASE_MISMATCH 0x80
305#define SSTAT1_REG 0x0E
306#define SIDL_REG_FULL 0x80
307#define SODR_REG_FULL 0x40
308#define SODL_REG_FULL 0x20
309#define SSTAT2_REG 0x0F
310#define CTEST0_REG 0x14
311#define BTB_TIMER_DISABLE 0x40
312#define CTEST1_REG 0x15
313#define CTEST2_REG 0x16
314#define CTEST3_REG 0x17
315#define CTEST4_REG 0x18
316#define DISABLE_FIFO 0x00
317#define SLBE 0x10
318#define SFWR 0x08
319#define BYTE_LANE0 0x04
320#define BYTE_LANE1 0x05
321#define BYTE_LANE2 0x06
322#define BYTE_LANE3 0x07
323#define SCSI_ZMODE 0x20
324#define ZMODE 0x40
325#define CTEST5_REG 0x19
326#define MASTER_CONTROL 0x10
327#define DMA_DIRECTION 0x08
328#define CTEST7_REG 0x1B
329#define BURST_DISABLE 0x80 /* 710 only */
330#define SEL_TIMEOUT_DISABLE 0x10 /* 710 only */
331#define DFP 0x08
332#define EVP 0x04
333#define DIFF 0x01
334#define CTEST6_REG 0x1A
335#define TEMP_REG 0x1C
336#define DFIFO_REG 0x20
337#define FLUSH_DMA_FIFO 0x80
338#define CLR_FIFO 0x40
339#define ISTAT_REG 0x21
340#define ABORT_OPERATION 0x80
341#define SOFTWARE_RESET_710 0x40
342#define DMA_INT_PENDING 0x01
343#define SCSI_INT_PENDING 0x02
344#define CONNECTED 0x08
345#define CTEST8_REG 0x22
346#define LAST_DIS_ENBL 0x01
347#define SHORTEN_FILTERING 0x04
348#define ENABLE_ACTIVE_NEGATION 0x10
349#define GENERATE_RECEIVE_PARITY 0x20
350#define CLR_FIFO_710 0x04
351#define FLUSH_DMA_FIFO_710 0x08
352#define CTEST9_REG 0x23
353#define DBC_REG 0x24
354#define DCMD_REG 0x27
355#define DNAD_REG 0x28
356#define DIEN_REG 0x39
357#define BUS_FAULT 0x20
358#define ABORT_INT 0x10
359#define INT_INST_INT 0x04
360#define WD_INT 0x02
361#define ILGL_INST_INT 0x01
362#define DCNTL_REG 0x3B
363#define SOFTWARE_RESET 0x01
364#define COMPAT_700_MODE 0x01
365#define SCRPTS_16BITS 0x20
366#define ASYNC_DIV_2_0 0x00
367#define ASYNC_DIV_1_5 0x40
368#define ASYNC_DIV_1_0 0x80
369#define ASYNC_DIV_3_0 0xc0
370#define DMODE_710_REG 0x38
371#define DMODE_700_REG 0x34
372#define BURST_LENGTH_1 0x00
373#define BURST_LENGTH_2 0x40
374#define BURST_LENGTH_4 0x80
375#define BURST_LENGTH_8 0xC0
376#define DMODE_FC1 0x10
377#define DMODE_FC2 0x20
378#define BW16 32
379#define MODE_286 16
380#define IO_XFER 8
381#define FIXED_ADDR 4
382
383#define DSP_REG 0x2C
384#define DSPS_REG 0x30
385
386/* Parameters to begin SDTR negotiations. Empirically, I find that
387 * the 53c700-66 cannot handle an offset >8, so don't change this */
388#define NCR_700_MAX_OFFSET 8
389/* Was hoping the max offset would be greater for the 710, but
390 * empirically it seems to be 8 also */
391#define NCR_710_MAX_OFFSET 8
392#define NCR_700_MIN_XFERP 1
393#define NCR_710_MIN_XFERP 0
394#define NCR_700_MIN_PERIOD 25 /* for SDTR message, 100ns */
395
396#define script_patch_32(script, symbol, value) \
397{ \
398 int i; \
399 for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
400 __u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]) + value; \
401 (script)[A_##symbol##_used[i]] = bS_to_host(val); \
402 dma_cache_sync(&(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \
403 DEBUG((" script, patching %s at %d to 0x%lx\n", \
404 #symbol, A_##symbol##_used[i], (value))); \
405 } \
406}
407
408#define script_patch_32_abs(script, symbol, value) \
409{ \
410 int i; \
411 for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
412 (script)[A_##symbol##_used[i]] = bS_to_host(value); \
413 dma_cache_sync(&(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \
414 DEBUG((" script, patching %s at %d to 0x%lx\n", \
415 #symbol, A_##symbol##_used[i], (value))); \
416 } \
417}
418
419/* Used for patching the SCSI ID in the SELECT instruction */
420#define script_patch_ID(script, symbol, value) \
421{ \
422 int i; \
423 for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
424 __u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]); \
425 val &= 0xff00ffff; \
426 val |= ((value) & 0xff) << 16; \
427 (script)[A_##symbol##_used[i]] = bS_to_host(val); \
428 dma_cache_sync(&(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \
429 DEBUG((" script, patching ID field %s at %d to 0x%x\n", \
430 #symbol, A_##symbol##_used[i], val)); \
431 } \
432}
433
434#define script_patch_16(script, symbol, value) \
435{ \
436 int i; \
437 for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
438 __u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]); \
439 val &= 0xffff0000; \
440 val |= ((value) & 0xffff); \
441 (script)[A_##symbol##_used[i]] = bS_to_host(val); \
442 dma_cache_sync(&(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \
443 DEBUG((" script, patching short field %s at %d to 0x%x\n", \
444 #symbol, A_##symbol##_used[i], val)); \
445 } \
446}
447
448
449static inline __u8
Linus Torvalds1da177e2005-04-16 15:20:36 -0700450NCR_700_readb(struct Scsi_Host *host, __u32 reg)
451{
56fece22005-04-03 03:57:48 -0600452 const struct NCR_700_Host_Parameters *hostdata
Linus Torvalds1da177e2005-04-16 15:20:36 -0700453 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
454
56fece22005-04-03 03:57:48 -0600455 return ioread8(hostdata->base + (reg^bE));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700456}
457
458static inline __u32
459NCR_700_readl(struct Scsi_Host *host, __u32 reg)
460{
56fece22005-04-03 03:57:48 -0600461 const struct NCR_700_Host_Parameters *hostdata
Linus Torvalds1da177e2005-04-16 15:20:36 -0700462 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
56fece22005-04-03 03:57:48 -0600463 __u32 value = ioread32(hostdata->base + reg);
464#if 1
465 /* sanity check the register */
466 if((reg & 0x3) != 0)
467 BUG();
468#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700469
56fece22005-04-03 03:57:48 -0600470 return bS_to_io(value);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700471}
472
473static inline void
474NCR_700_writeb(__u8 value, struct Scsi_Host *host, __u32 reg)
475{
56fece22005-04-03 03:57:48 -0600476 const struct NCR_700_Host_Parameters *hostdata
Linus Torvalds1da177e2005-04-16 15:20:36 -0700477 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
478
56fece22005-04-03 03:57:48 -0600479 iowrite8(value, hostdata->base + (reg^bE));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700480}
481
482static inline void
483NCR_700_writel(__u32 value, struct Scsi_Host *host, __u32 reg)
484{
56fece22005-04-03 03:57:48 -0600485 const struct NCR_700_Host_Parameters *hostdata
Linus Torvalds1da177e2005-04-16 15:20:36 -0700486 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
487
56fece22005-04-03 03:57:48 -0600488#if 1
489 /* sanity check the register */
490 if((reg & 0x3) != 0)
491 BUG();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700492#endif
493
56fece22005-04-03 03:57:48 -0600494 iowrite32(bS_to_io(value), hostdata->base + reg);
495}
496
Linus Torvalds1da177e2005-04-16 15:20:36 -0700497#endif