blob: 1e65a5f70dd13813044dd35cba774bed838567db [file] [log] [blame]
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001#ifndef _KGSL_DRM_H_
2#define _KGSL_DRM_H_
3
4#include "drm.h"
5
6#define DRM_KGSL_GEM_CREATE 0x00
7#define DRM_KGSL_GEM_PREP 0x01
8#define DRM_KGSL_GEM_SETMEMTYPE 0x02
9#define DRM_KGSL_GEM_GETMEMTYPE 0x03
10#define DRM_KGSL_GEM_MMAP 0x04
11#define DRM_KGSL_GEM_ALLOC 0x05
12#define DRM_KGSL_GEM_BIND_GPU 0x06
13#define DRM_KGSL_GEM_UNBIND_GPU 0x07
14
15#define DRM_KGSL_GEM_GET_BUFINFO 0x08
16#define DRM_KGSL_GEM_SET_BUFCOUNT 0x09
17#define DRM_KGSL_GEM_SET_ACTIVE 0x0A
18#define DRM_KGSL_GEM_LOCK_HANDLE 0x0B
19#define DRM_KGSL_GEM_UNLOCK_HANDLE 0x0C
20#define DRM_KGSL_GEM_UNLOCK_ON_TS 0x0D
21#define DRM_KGSL_GEM_CREATE_FD 0x0E
Michael Street536af832012-11-08 22:36:04 -080022#define DRM_KGSL_GEM_GET_ION_FD 0x0F
Michael Street8ebe7032013-02-20 16:04:18 -080023#define DRM_KGSL_GEM_CREATE_FROM_ION 0x10
Alex Wong33be4942013-04-05 00:01:57 -070024#define DRM_KGSL_GEM_SET_GLOCK_HANDLES_INFO 0x11
25#define DRM_KGSL_GEM_GET_GLOCK_HANDLES_INFO 0x12
26#define DRM_KGSL_GEM_GET_BUFCOUNT 0x13
27
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070028
29#define DRM_IOCTL_KGSL_GEM_CREATE \
30DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_CREATE, struct drm_kgsl_gem_create)
31
32#define DRM_IOCTL_KGSL_GEM_PREP \
33DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_PREP, struct drm_kgsl_gem_prep)
34
35#define DRM_IOCTL_KGSL_GEM_SETMEMTYPE \
36DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_SETMEMTYPE, \
37struct drm_kgsl_gem_memtype)
38
39#define DRM_IOCTL_KGSL_GEM_GETMEMTYPE \
40DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_GETMEMTYPE, \
41struct drm_kgsl_gem_memtype)
42
43#define DRM_IOCTL_KGSL_GEM_MMAP \
44DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_MMAP, struct drm_kgsl_gem_mmap)
45
46#define DRM_IOCTL_KGSL_GEM_ALLOC \
47DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_ALLOC, struct drm_kgsl_gem_alloc)
48
49#define DRM_IOCTL_KGSL_GEM_BIND_GPU \
50DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_BIND_GPU, struct drm_kgsl_gem_bind_gpu)
51
52#define DRM_IOCTL_KGSL_GEM_UNBIND_GPU \
53DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_UNBIND_GPU, \
54struct drm_kgsl_gem_bind_gpu)
55
56#define DRM_IOCTL_KGSL_GEM_GET_BUFINFO \
57DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_GET_BUFINFO, \
58 struct drm_kgsl_gem_bufinfo)
59
60#define DRM_IOCTL_KGSL_GEM_SET_BUFCOUNT \
61DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_SET_BUFCOUNT, \
62 struct drm_kgsl_gem_bufcount)
63
Alex Wong33be4942013-04-05 00:01:57 -070064#define DRM_IOCTL_KGSL_GEM_GET_BUFCOUNT \
65DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_GET_BUFCOUNT, \
66 struct drm_kgsl_gem_bufcount)
67
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070068#define DRM_IOCTL_KGSL_GEM_SET_ACTIVE \
69DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_SET_ACTIVE, \
70 struct drm_kgsl_gem_active)
71
72#define DRM_IOCTL_KGSL_GEM_LOCK_HANDLE \
73DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_LOCK_HANDLE, \
74struct drm_kgsl_gem_lock_handles)
75
76#define DRM_IOCTL_KGSL_GEM_UNLOCK_HANDLE \
77DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_UNLOCK_HANDLE, \
78struct drm_kgsl_gem_unlock_handles)
79
80#define DRM_IOCTL_KGSL_GEM_UNLOCK_ON_TS \
81DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_UNLOCK_ON_TS, \
82struct drm_kgsl_gem_unlock_on_ts)
83
84#define DRM_IOCTL_KGSL_GEM_CREATE_FD \
85DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_CREATE_FD, \
86struct drm_kgsl_gem_create_fd)
87
Michael Street536af832012-11-08 22:36:04 -080088#define DRM_IOCTL_KGSL_GEM_GET_ION_FD \
89DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_GET_ION_FD, \
90struct drm_kgsl_gem_get_ion_fd)
91
Michael Street8ebe7032013-02-20 16:04:18 -080092#define DRM_IOCTL_KGSL_GEM_CREATE_FROM_ION \
93DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_CREATE_FROM_ION, \
94struct drm_kgsl_gem_create_from_ion)
95
Alex Wong33be4942013-04-05 00:01:57 -070096#define DRM_IOCTL_KGSL_GEM_SET_GLOCK_HANDLES_INFO \
97DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_SET_GLOCK_HANDLES_INFO, \
98struct drm_kgsl_gem_glockinfo)
99
100#define DRM_IOCTL_KGSL_GEM_GET_GLOCK_HANDLES_INFO \
101DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_GET_GLOCK_HANDLES_INFO, \
102struct drm_kgsl_gem_glockinfo)
103
104
105
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700106/* Maximum number of sub buffers per GEM object */
Michael Streetb1489242013-03-22 12:15:25 -0700107#define DRM_KGSL_GEM_MAX_BUFFERS 3
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700108
109/* Memory types - these define the source and caching policies
110 of the GEM memory chunk */
111
112/* Legacy definitions left for compatability */
113
114#define DRM_KGSL_GEM_TYPE_EBI 0
115#define DRM_KGSL_GEM_TYPE_SMI 1
116#define DRM_KGSL_GEM_TYPE_KMEM 2
117#define DRM_KGSL_GEM_TYPE_KMEM_NOCACHE 3
118#define DRM_KGSL_GEM_TYPE_MEM_MASK 0xF
119
120/* Contiguous memory (PMEM) */
121#define DRM_KGSL_GEM_TYPE_PMEM 0x000100
122
123/* PMEM memory types */
124#define DRM_KGSL_GEM_PMEM_EBI 0x001000
125#define DRM_KGSL_GEM_PMEM_SMI 0x002000
126
127/* Standard paged memory */
128#define DRM_KGSL_GEM_TYPE_MEM 0x010000
129
130/* Caching controls */
131#define DRM_KGSL_GEM_CACHE_NONE 0x000000
132#define DRM_KGSL_GEM_CACHE_WCOMBINE 0x100000
133#define DRM_KGSL_GEM_CACHE_WTHROUGH 0x200000
134#define DRM_KGSL_GEM_CACHE_WBACK 0x400000
135#define DRM_KGSL_GEM_CACHE_WBACKWA 0x800000
136#define DRM_KGSL_GEM_CACHE_MASK 0xF00000
137
138/* FD based objects */
139#define DRM_KGSL_GEM_TYPE_FD_FBMEM 0x1000000
140#define DRM_KGSL_GEM_TYPE_FD_MASK 0xF000000
141
142/* Timestamp types */
143#define DRM_KGSL_GEM_TS_3D 0x00000430
144#define DRM_KGSL_GEM_TS_2D 0x00000180
145
146
147struct drm_kgsl_gem_create {
148 uint32_t size;
149 uint32_t handle;
150};
151
152struct drm_kgsl_gem_prep {
153 uint32_t handle;
154 uint32_t phys;
155 uint64_t offset;
156};
157
158struct drm_kgsl_gem_memtype {
159 uint32_t handle;
160 uint32_t type;
161};
162
163struct drm_kgsl_gem_mmap {
164 uint32_t handle;
165 uint32_t size;
166 uint32_t hostptr;
167 uint64_t offset;
168};
169
170struct drm_kgsl_gem_alloc {
171 uint32_t handle;
172 uint64_t offset;
173};
174
175struct drm_kgsl_gem_bind_gpu {
176 uint32_t handle;
177 uint32_t gpuptr;
178};
179
180struct drm_kgsl_gem_bufinfo {
181 uint32_t handle;
182 uint32_t count;
183 uint32_t active;
184 uint32_t offset[DRM_KGSL_GEM_MAX_BUFFERS];
185 uint32_t gpuaddr[DRM_KGSL_GEM_MAX_BUFFERS];
186};
187
Alex Wong33be4942013-04-05 00:01:57 -0700188struct drm_kgsl_gem_glockinfo {
189 uint32_t handle;
190 int glockhandle[DRM_KGSL_GEM_MAX_BUFFERS];
191};
192
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700193struct drm_kgsl_gem_bufcount {
194 uint32_t handle;
195 uint32_t bufcount;
196};
197
198struct drm_kgsl_gem_active {
199 uint32_t handle;
200 uint32_t active;
201};
202
203struct drm_kgsl_gem_lock_handles {
204 uint32_t num_handles;
205 uint32_t *handle_list;
206 uint32_t pid;
207 uint32_t lock_id; /* Returned lock id used for unlocking */
208};
209
210struct drm_kgsl_gem_unlock_handles {
211 uint32_t lock_id;
212};
213
214struct drm_kgsl_gem_unlock_on_ts {
215 uint32_t lock_id;
216 uint32_t timestamp; /* This field is a hw generated ts */
217 uint32_t type; /* Which pipe to check for ts generation */
218};
219
220struct drm_kgsl_gem_create_fd {
221 uint32_t fd;
222 uint32_t handle;
223};
224
Michael Street536af832012-11-08 22:36:04 -0800225struct drm_kgsl_gem_get_ion_fd {
226 uint32_t ion_fd;
227 uint32_t handle;
228};
229
Michael Street8ebe7032013-02-20 16:04:18 -0800230struct drm_kgsl_gem_create_from_ion {
231 uint32_t ion_fd;
232 uint32_t handle;
233};
234
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700235#endif