Mark Brown | 7d4d0a3 | 2009-07-27 14:45:53 +0100 | [diff] [blame] | 1 | /* |
| 2 | * wm831x-irq.c -- Interrupt controller support for Wolfson WM831x PMICs |
| 3 | * |
| 4 | * Copyright 2009 Wolfson Microelectronics PLC. |
| 5 | * |
| 6 | * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify it |
| 9 | * under the terms of the GNU General Public License as published by the |
| 10 | * Free Software Foundation; either version 2 of the License, or (at your |
| 11 | * option) any later version. |
| 12 | * |
| 13 | */ |
| 14 | |
| 15 | #include <linux/kernel.h> |
| 16 | #include <linux/module.h> |
| 17 | #include <linux/i2c.h> |
Mark Brown | 5fb4d38 | 2009-11-11 16:10:22 +0000 | [diff] [blame] | 18 | #include <linux/irq.h> |
Mark Brown | 7d4d0a3 | 2009-07-27 14:45:53 +0100 | [diff] [blame] | 19 | #include <linux/mfd/core.h> |
| 20 | #include <linux/interrupt.h> |
| 21 | |
| 22 | #include <linux/mfd/wm831x/core.h> |
| 23 | #include <linux/mfd/wm831x/pdata.h> |
Mark Brown | 896060c | 2010-05-07 18:39:25 +0100 | [diff] [blame] | 24 | #include <linux/mfd/wm831x/gpio.h> |
Mark Brown | 7d4d0a3 | 2009-07-27 14:45:53 +0100 | [diff] [blame] | 25 | #include <linux/mfd/wm831x/irq.h> |
| 26 | |
| 27 | #include <linux/delay.h> |
| 28 | |
| 29 | /* |
| 30 | * Since generic IRQs don't currently support interrupt controllers on |
| 31 | * interrupt driven buses we don't use genirq but instead provide an |
| 32 | * interface that looks very much like the standard ones. This leads |
| 33 | * to some bodges, including storing interrupt handler information in |
| 34 | * the static irq_data table we use to look up the data for individual |
| 35 | * interrupts, but hopefully won't last too long. |
| 36 | */ |
| 37 | |
| 38 | struct wm831x_irq_data { |
| 39 | int primary; |
| 40 | int reg; |
| 41 | int mask; |
Mark Brown | 7d4d0a3 | 2009-07-27 14:45:53 +0100 | [diff] [blame] | 42 | }; |
| 43 | |
| 44 | static struct wm831x_irq_data wm831x_irqs[] = { |
| 45 | [WM831X_IRQ_TEMP_THW] = { |
| 46 | .primary = WM831X_TEMP_INT, |
| 47 | .reg = 1, |
| 48 | .mask = WM831X_TEMP_THW_EINT, |
| 49 | }, |
| 50 | [WM831X_IRQ_GPIO_1] = { |
| 51 | .primary = WM831X_GP_INT, |
| 52 | .reg = 5, |
| 53 | .mask = WM831X_GP1_EINT, |
| 54 | }, |
| 55 | [WM831X_IRQ_GPIO_2] = { |
| 56 | .primary = WM831X_GP_INT, |
| 57 | .reg = 5, |
| 58 | .mask = WM831X_GP2_EINT, |
| 59 | }, |
| 60 | [WM831X_IRQ_GPIO_3] = { |
| 61 | .primary = WM831X_GP_INT, |
| 62 | .reg = 5, |
| 63 | .mask = WM831X_GP3_EINT, |
| 64 | }, |
| 65 | [WM831X_IRQ_GPIO_4] = { |
| 66 | .primary = WM831X_GP_INT, |
| 67 | .reg = 5, |
| 68 | .mask = WM831X_GP4_EINT, |
| 69 | }, |
| 70 | [WM831X_IRQ_GPIO_5] = { |
| 71 | .primary = WM831X_GP_INT, |
| 72 | .reg = 5, |
| 73 | .mask = WM831X_GP5_EINT, |
| 74 | }, |
| 75 | [WM831X_IRQ_GPIO_6] = { |
| 76 | .primary = WM831X_GP_INT, |
| 77 | .reg = 5, |
| 78 | .mask = WM831X_GP6_EINT, |
| 79 | }, |
| 80 | [WM831X_IRQ_GPIO_7] = { |
| 81 | .primary = WM831X_GP_INT, |
| 82 | .reg = 5, |
| 83 | .mask = WM831X_GP7_EINT, |
| 84 | }, |
| 85 | [WM831X_IRQ_GPIO_8] = { |
| 86 | .primary = WM831X_GP_INT, |
| 87 | .reg = 5, |
| 88 | .mask = WM831X_GP8_EINT, |
| 89 | }, |
| 90 | [WM831X_IRQ_GPIO_9] = { |
| 91 | .primary = WM831X_GP_INT, |
| 92 | .reg = 5, |
| 93 | .mask = WM831X_GP9_EINT, |
| 94 | }, |
| 95 | [WM831X_IRQ_GPIO_10] = { |
| 96 | .primary = WM831X_GP_INT, |
| 97 | .reg = 5, |
| 98 | .mask = WM831X_GP10_EINT, |
| 99 | }, |
| 100 | [WM831X_IRQ_GPIO_11] = { |
| 101 | .primary = WM831X_GP_INT, |
| 102 | .reg = 5, |
| 103 | .mask = WM831X_GP11_EINT, |
| 104 | }, |
| 105 | [WM831X_IRQ_GPIO_12] = { |
| 106 | .primary = WM831X_GP_INT, |
| 107 | .reg = 5, |
| 108 | .mask = WM831X_GP12_EINT, |
| 109 | }, |
| 110 | [WM831X_IRQ_GPIO_13] = { |
| 111 | .primary = WM831X_GP_INT, |
| 112 | .reg = 5, |
| 113 | .mask = WM831X_GP13_EINT, |
| 114 | }, |
| 115 | [WM831X_IRQ_GPIO_14] = { |
| 116 | .primary = WM831X_GP_INT, |
| 117 | .reg = 5, |
| 118 | .mask = WM831X_GP14_EINT, |
| 119 | }, |
| 120 | [WM831X_IRQ_GPIO_15] = { |
| 121 | .primary = WM831X_GP_INT, |
| 122 | .reg = 5, |
| 123 | .mask = WM831X_GP15_EINT, |
| 124 | }, |
| 125 | [WM831X_IRQ_GPIO_16] = { |
| 126 | .primary = WM831X_GP_INT, |
| 127 | .reg = 5, |
| 128 | .mask = WM831X_GP16_EINT, |
| 129 | }, |
| 130 | [WM831X_IRQ_ON] = { |
| 131 | .primary = WM831X_ON_PIN_INT, |
| 132 | .reg = 1, |
| 133 | .mask = WM831X_ON_PIN_EINT, |
| 134 | }, |
| 135 | [WM831X_IRQ_PPM_SYSLO] = { |
| 136 | .primary = WM831X_PPM_INT, |
| 137 | .reg = 1, |
| 138 | .mask = WM831X_PPM_SYSLO_EINT, |
| 139 | }, |
| 140 | [WM831X_IRQ_PPM_PWR_SRC] = { |
| 141 | .primary = WM831X_PPM_INT, |
| 142 | .reg = 1, |
| 143 | .mask = WM831X_PPM_PWR_SRC_EINT, |
| 144 | }, |
| 145 | [WM831X_IRQ_PPM_USB_CURR] = { |
| 146 | .primary = WM831X_PPM_INT, |
| 147 | .reg = 1, |
| 148 | .mask = WM831X_PPM_USB_CURR_EINT, |
| 149 | }, |
| 150 | [WM831X_IRQ_WDOG_TO] = { |
| 151 | .primary = WM831X_WDOG_INT, |
| 152 | .reg = 1, |
| 153 | .mask = WM831X_WDOG_TO_EINT, |
| 154 | }, |
| 155 | [WM831X_IRQ_RTC_PER] = { |
| 156 | .primary = WM831X_RTC_INT, |
| 157 | .reg = 1, |
| 158 | .mask = WM831X_RTC_PER_EINT, |
| 159 | }, |
| 160 | [WM831X_IRQ_RTC_ALM] = { |
| 161 | .primary = WM831X_RTC_INT, |
| 162 | .reg = 1, |
| 163 | .mask = WM831X_RTC_ALM_EINT, |
| 164 | }, |
| 165 | [WM831X_IRQ_CHG_BATT_HOT] = { |
| 166 | .primary = WM831X_CHG_INT, |
| 167 | .reg = 2, |
| 168 | .mask = WM831X_CHG_BATT_HOT_EINT, |
| 169 | }, |
| 170 | [WM831X_IRQ_CHG_BATT_COLD] = { |
| 171 | .primary = WM831X_CHG_INT, |
| 172 | .reg = 2, |
| 173 | .mask = WM831X_CHG_BATT_COLD_EINT, |
| 174 | }, |
| 175 | [WM831X_IRQ_CHG_BATT_FAIL] = { |
| 176 | .primary = WM831X_CHG_INT, |
| 177 | .reg = 2, |
| 178 | .mask = WM831X_CHG_BATT_FAIL_EINT, |
| 179 | }, |
| 180 | [WM831X_IRQ_CHG_OV] = { |
| 181 | .primary = WM831X_CHG_INT, |
| 182 | .reg = 2, |
| 183 | .mask = WM831X_CHG_OV_EINT, |
| 184 | }, |
| 185 | [WM831X_IRQ_CHG_END] = { |
| 186 | .primary = WM831X_CHG_INT, |
| 187 | .reg = 2, |
| 188 | .mask = WM831X_CHG_END_EINT, |
| 189 | }, |
| 190 | [WM831X_IRQ_CHG_TO] = { |
| 191 | .primary = WM831X_CHG_INT, |
| 192 | .reg = 2, |
| 193 | .mask = WM831X_CHG_TO_EINT, |
| 194 | }, |
| 195 | [WM831X_IRQ_CHG_MODE] = { |
| 196 | .primary = WM831X_CHG_INT, |
| 197 | .reg = 2, |
| 198 | .mask = WM831X_CHG_MODE_EINT, |
| 199 | }, |
| 200 | [WM831X_IRQ_CHG_START] = { |
| 201 | .primary = WM831X_CHG_INT, |
| 202 | .reg = 2, |
| 203 | .mask = WM831X_CHG_START_EINT, |
| 204 | }, |
| 205 | [WM831X_IRQ_TCHDATA] = { |
| 206 | .primary = WM831X_TCHDATA_INT, |
| 207 | .reg = 1, |
| 208 | .mask = WM831X_TCHDATA_EINT, |
| 209 | }, |
| 210 | [WM831X_IRQ_TCHPD] = { |
| 211 | .primary = WM831X_TCHPD_INT, |
| 212 | .reg = 1, |
| 213 | .mask = WM831X_TCHPD_EINT, |
| 214 | }, |
| 215 | [WM831X_IRQ_AUXADC_DATA] = { |
| 216 | .primary = WM831X_AUXADC_INT, |
| 217 | .reg = 1, |
| 218 | .mask = WM831X_AUXADC_DATA_EINT, |
| 219 | }, |
| 220 | [WM831X_IRQ_AUXADC_DCOMP1] = { |
| 221 | .primary = WM831X_AUXADC_INT, |
| 222 | .reg = 1, |
| 223 | .mask = WM831X_AUXADC_DCOMP1_EINT, |
| 224 | }, |
| 225 | [WM831X_IRQ_AUXADC_DCOMP2] = { |
| 226 | .primary = WM831X_AUXADC_INT, |
| 227 | .reg = 1, |
| 228 | .mask = WM831X_AUXADC_DCOMP2_EINT, |
| 229 | }, |
| 230 | [WM831X_IRQ_AUXADC_DCOMP3] = { |
| 231 | .primary = WM831X_AUXADC_INT, |
| 232 | .reg = 1, |
| 233 | .mask = WM831X_AUXADC_DCOMP3_EINT, |
| 234 | }, |
| 235 | [WM831X_IRQ_AUXADC_DCOMP4] = { |
| 236 | .primary = WM831X_AUXADC_INT, |
| 237 | .reg = 1, |
| 238 | .mask = WM831X_AUXADC_DCOMP4_EINT, |
| 239 | }, |
| 240 | [WM831X_IRQ_CS1] = { |
| 241 | .primary = WM831X_CS_INT, |
| 242 | .reg = 2, |
| 243 | .mask = WM831X_CS1_EINT, |
| 244 | }, |
| 245 | [WM831X_IRQ_CS2] = { |
| 246 | .primary = WM831X_CS_INT, |
| 247 | .reg = 2, |
| 248 | .mask = WM831X_CS2_EINT, |
| 249 | }, |
| 250 | [WM831X_IRQ_HC_DC1] = { |
| 251 | .primary = WM831X_HC_INT, |
| 252 | .reg = 4, |
| 253 | .mask = WM831X_HC_DC1_EINT, |
| 254 | }, |
| 255 | [WM831X_IRQ_HC_DC2] = { |
| 256 | .primary = WM831X_HC_INT, |
| 257 | .reg = 4, |
| 258 | .mask = WM831X_HC_DC2_EINT, |
| 259 | }, |
| 260 | [WM831X_IRQ_UV_LDO1] = { |
| 261 | .primary = WM831X_UV_INT, |
| 262 | .reg = 3, |
| 263 | .mask = WM831X_UV_LDO1_EINT, |
| 264 | }, |
| 265 | [WM831X_IRQ_UV_LDO2] = { |
| 266 | .primary = WM831X_UV_INT, |
| 267 | .reg = 3, |
| 268 | .mask = WM831X_UV_LDO2_EINT, |
| 269 | }, |
| 270 | [WM831X_IRQ_UV_LDO3] = { |
| 271 | .primary = WM831X_UV_INT, |
| 272 | .reg = 3, |
| 273 | .mask = WM831X_UV_LDO3_EINT, |
| 274 | }, |
| 275 | [WM831X_IRQ_UV_LDO4] = { |
| 276 | .primary = WM831X_UV_INT, |
| 277 | .reg = 3, |
| 278 | .mask = WM831X_UV_LDO4_EINT, |
| 279 | }, |
| 280 | [WM831X_IRQ_UV_LDO5] = { |
| 281 | .primary = WM831X_UV_INT, |
| 282 | .reg = 3, |
| 283 | .mask = WM831X_UV_LDO5_EINT, |
| 284 | }, |
| 285 | [WM831X_IRQ_UV_LDO6] = { |
| 286 | .primary = WM831X_UV_INT, |
| 287 | .reg = 3, |
| 288 | .mask = WM831X_UV_LDO6_EINT, |
| 289 | }, |
| 290 | [WM831X_IRQ_UV_LDO7] = { |
| 291 | .primary = WM831X_UV_INT, |
| 292 | .reg = 3, |
| 293 | .mask = WM831X_UV_LDO7_EINT, |
| 294 | }, |
| 295 | [WM831X_IRQ_UV_LDO8] = { |
| 296 | .primary = WM831X_UV_INT, |
| 297 | .reg = 3, |
| 298 | .mask = WM831X_UV_LDO8_EINT, |
| 299 | }, |
| 300 | [WM831X_IRQ_UV_LDO9] = { |
| 301 | .primary = WM831X_UV_INT, |
| 302 | .reg = 3, |
| 303 | .mask = WM831X_UV_LDO9_EINT, |
| 304 | }, |
| 305 | [WM831X_IRQ_UV_LDO10] = { |
| 306 | .primary = WM831X_UV_INT, |
| 307 | .reg = 3, |
| 308 | .mask = WM831X_UV_LDO10_EINT, |
| 309 | }, |
| 310 | [WM831X_IRQ_UV_DC1] = { |
| 311 | .primary = WM831X_UV_INT, |
| 312 | .reg = 4, |
| 313 | .mask = WM831X_UV_DC1_EINT, |
| 314 | }, |
| 315 | [WM831X_IRQ_UV_DC2] = { |
| 316 | .primary = WM831X_UV_INT, |
| 317 | .reg = 4, |
| 318 | .mask = WM831X_UV_DC2_EINT, |
| 319 | }, |
| 320 | [WM831X_IRQ_UV_DC3] = { |
| 321 | .primary = WM831X_UV_INT, |
| 322 | .reg = 4, |
| 323 | .mask = WM831X_UV_DC3_EINT, |
| 324 | }, |
| 325 | [WM831X_IRQ_UV_DC4] = { |
| 326 | .primary = WM831X_UV_INT, |
| 327 | .reg = 4, |
| 328 | .mask = WM831X_UV_DC4_EINT, |
| 329 | }, |
| 330 | }; |
| 331 | |
| 332 | static inline int irq_data_to_status_reg(struct wm831x_irq_data *irq_data) |
| 333 | { |
| 334 | return WM831X_INTERRUPT_STATUS_1 - 1 + irq_data->reg; |
| 335 | } |
| 336 | |
| 337 | static inline int irq_data_to_mask_reg(struct wm831x_irq_data *irq_data) |
| 338 | { |
| 339 | return WM831X_INTERRUPT_STATUS_1_MASK - 1 + irq_data->reg; |
| 340 | } |
| 341 | |
Mark Brown | 5fb4d38 | 2009-11-11 16:10:22 +0000 | [diff] [blame] | 342 | static inline struct wm831x_irq_data *irq_to_wm831x_irq(struct wm831x *wm831x, |
| 343 | int irq) |
Mark Brown | 7d4d0a3 | 2009-07-27 14:45:53 +0100 | [diff] [blame] | 344 | { |
Mark Brown | 5fb4d38 | 2009-11-11 16:10:22 +0000 | [diff] [blame] | 345 | return &wm831x_irqs[irq - wm831x->irq_base]; |
Mark Brown | 7d4d0a3 | 2009-07-27 14:45:53 +0100 | [diff] [blame] | 346 | } |
| 347 | |
Mark Brown | ba81cd3 | 2010-11-24 18:01:42 +0000 | [diff] [blame] | 348 | static void wm831x_irq_lock(struct irq_data *data) |
Mark Brown | 7d4d0a3 | 2009-07-27 14:45:53 +0100 | [diff] [blame] | 349 | { |
Mark Brown | 25a947f | 2010-12-11 13:21:21 +0000 | [diff] [blame] | 350 | struct wm831x *wm831x = irq_data_get_irq_chip_data(data); |
Mark Brown | 7d4d0a3 | 2009-07-27 14:45:53 +0100 | [diff] [blame] | 351 | |
| 352 | mutex_lock(&wm831x->irq_lock); |
Mark Brown | 5fb4d38 | 2009-11-11 16:10:22 +0000 | [diff] [blame] | 353 | } |
Mark Brown | 7d4d0a3 | 2009-07-27 14:45:53 +0100 | [diff] [blame] | 354 | |
Mark Brown | ba81cd3 | 2010-11-24 18:01:42 +0000 | [diff] [blame] | 355 | static void wm831x_irq_sync_unlock(struct irq_data *data) |
Mark Brown | 5fb4d38 | 2009-11-11 16:10:22 +0000 | [diff] [blame] | 356 | { |
Mark Brown | 25a947f | 2010-12-11 13:21:21 +0000 | [diff] [blame] | 357 | struct wm831x *wm831x = irq_data_get_irq_chip_data(data); |
Mark Brown | 5fb4d38 | 2009-11-11 16:10:22 +0000 | [diff] [blame] | 358 | int i; |
| 359 | |
| 360 | for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks_cur); i++) { |
| 361 | /* If there's been a change in the mask write it back |
| 362 | * to the hardware. */ |
| 363 | if (wm831x->irq_masks_cur[i] != wm831x->irq_masks_cache[i]) { |
| 364 | wm831x->irq_masks_cache[i] = wm831x->irq_masks_cur[i]; |
| 365 | wm831x_reg_write(wm831x, |
| 366 | WM831X_INTERRUPT_STATUS_1_MASK + i, |
| 367 | wm831x->irq_masks_cur[i]); |
| 368 | } |
Mark Brown | 7d4d0a3 | 2009-07-27 14:45:53 +0100 | [diff] [blame] | 369 | } |
| 370 | |
Mark Brown | 7d4d0a3 | 2009-07-27 14:45:53 +0100 | [diff] [blame] | 371 | mutex_unlock(&wm831x->irq_lock); |
| 372 | } |
Mark Brown | 7d4d0a3 | 2009-07-27 14:45:53 +0100 | [diff] [blame] | 373 | |
Mark Brown | ba81cd3 | 2010-11-24 18:01:42 +0000 | [diff] [blame] | 374 | static void wm831x_irq_unmask(struct irq_data *data) |
Mark Brown | 7d4d0a3 | 2009-07-27 14:45:53 +0100 | [diff] [blame] | 375 | { |
Mark Brown | 25a947f | 2010-12-11 13:21:21 +0000 | [diff] [blame] | 376 | struct wm831x *wm831x = irq_data_get_irq_chip_data(data); |
Mark Brown | ba81cd3 | 2010-11-24 18:01:42 +0000 | [diff] [blame] | 377 | struct wm831x_irq_data *irq_data = irq_to_wm831x_irq(wm831x, |
| 378 | data->irq); |
Mark Brown | 7d4d0a3 | 2009-07-27 14:45:53 +0100 | [diff] [blame] | 379 | |
Mark Brown | 5fb4d38 | 2009-11-11 16:10:22 +0000 | [diff] [blame] | 380 | wm831x->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask; |
Mark Brown | 7d4d0a3 | 2009-07-27 14:45:53 +0100 | [diff] [blame] | 381 | } |
| 382 | |
Mark Brown | ba81cd3 | 2010-11-24 18:01:42 +0000 | [diff] [blame] | 383 | static void wm831x_irq_mask(struct irq_data *data) |
Mark Brown | 7d4d0a3 | 2009-07-27 14:45:53 +0100 | [diff] [blame] | 384 | { |
Mark Brown | 25a947f | 2010-12-11 13:21:21 +0000 | [diff] [blame] | 385 | struct wm831x *wm831x = irq_data_get_irq_chip_data(data); |
Mark Brown | ba81cd3 | 2010-11-24 18:01:42 +0000 | [diff] [blame] | 386 | struct wm831x_irq_data *irq_data = irq_to_wm831x_irq(wm831x, |
| 387 | data->irq); |
Mark Brown | 5fb4d38 | 2009-11-11 16:10:22 +0000 | [diff] [blame] | 388 | |
| 389 | wm831x->irq_masks_cur[irq_data->reg - 1] |= irq_data->mask; |
| 390 | } |
| 391 | |
Mark Brown | ba81cd3 | 2010-11-24 18:01:42 +0000 | [diff] [blame] | 392 | static int wm831x_irq_set_type(struct irq_data *data, unsigned int type) |
Mark Brown | 896060c | 2010-05-07 18:39:25 +0100 | [diff] [blame] | 393 | { |
Mark Brown | 25a947f | 2010-12-11 13:21:21 +0000 | [diff] [blame] | 394 | struct wm831x *wm831x = irq_data_get_irq_chip_data(data); |
Mark Brown | ba81cd3 | 2010-11-24 18:01:42 +0000 | [diff] [blame] | 395 | int val, irq; |
Mark Brown | 896060c | 2010-05-07 18:39:25 +0100 | [diff] [blame] | 396 | |
Mark Brown | ba81cd3 | 2010-11-24 18:01:42 +0000 | [diff] [blame] | 397 | irq = data->irq - wm831x->irq_base; |
Mark Brown | 896060c | 2010-05-07 18:39:25 +0100 | [diff] [blame] | 398 | |
Mark Brown | c9d66d3 | 2010-08-16 20:26:51 +0100 | [diff] [blame] | 399 | if (irq < WM831X_IRQ_GPIO_1 || irq > WM831X_IRQ_GPIO_11) { |
| 400 | /* Ignore internal-only IRQs */ |
| 401 | if (irq >= 0 && irq < WM831X_NUM_IRQS) |
| 402 | return 0; |
| 403 | else |
| 404 | return -EINVAL; |
| 405 | } |
Mark Brown | 896060c | 2010-05-07 18:39:25 +0100 | [diff] [blame] | 406 | |
| 407 | switch (type) { |
| 408 | case IRQ_TYPE_EDGE_BOTH: |
| 409 | val = WM831X_GPN_INT_MODE; |
| 410 | break; |
| 411 | case IRQ_TYPE_EDGE_RISING: |
| 412 | val = WM831X_GPN_POL; |
| 413 | break; |
| 414 | case IRQ_TYPE_EDGE_FALLING: |
| 415 | val = 0; |
| 416 | break; |
| 417 | default: |
| 418 | return -EINVAL; |
| 419 | } |
| 420 | |
| 421 | return wm831x_set_bits(wm831x, WM831X_GPIO1_CONTROL + irq, |
| 422 | WM831X_GPN_INT_MODE | WM831X_GPN_POL, val); |
| 423 | } |
| 424 | |
Mark Brown | 5fb4d38 | 2009-11-11 16:10:22 +0000 | [diff] [blame] | 425 | static struct irq_chip wm831x_irq_chip = { |
Mark Brown | ba81cd3 | 2010-11-24 18:01:42 +0000 | [diff] [blame] | 426 | .name = "wm831x", |
| 427 | .irq_bus_lock = wm831x_irq_lock, |
| 428 | .irq_bus_sync_unlock = wm831x_irq_sync_unlock, |
| 429 | .irq_mask = wm831x_irq_mask, |
| 430 | .irq_unmask = wm831x_irq_unmask, |
| 431 | .irq_set_type = wm831x_irq_set_type, |
Mark Brown | 5fb4d38 | 2009-11-11 16:10:22 +0000 | [diff] [blame] | 432 | }; |
| 433 | |
| 434 | /* The processing of the primary interrupt occurs in a thread so that |
| 435 | * we can interact with the device over I2C or SPI. */ |
| 436 | static irqreturn_t wm831x_irq_thread(int irq, void *data) |
| 437 | { |
| 438 | struct wm831x *wm831x = data; |
Mark Brown | 7d4d0a3 | 2009-07-27 14:45:53 +0100 | [diff] [blame] | 439 | unsigned int i; |
| 440 | int primary; |
Mark Brown | 5fb4d38 | 2009-11-11 16:10:22 +0000 | [diff] [blame] | 441 | int status_regs[WM831X_NUM_IRQ_REGS] = { 0 }; |
| 442 | int read[WM831X_NUM_IRQ_REGS] = { 0 }; |
Mark Brown | 7d4d0a3 | 2009-07-27 14:45:53 +0100 | [diff] [blame] | 443 | int *status; |
| 444 | |
| 445 | primary = wm831x_reg_read(wm831x, WM831X_SYSTEM_INTERRUPTS); |
| 446 | if (primary < 0) { |
| 447 | dev_err(wm831x->dev, "Failed to read system interrupt: %d\n", |
| 448 | primary); |
| 449 | goto out; |
| 450 | } |
| 451 | |
Mark Brown | 7d4d0a3 | 2009-07-27 14:45:53 +0100 | [diff] [blame] | 452 | for (i = 0; i < ARRAY_SIZE(wm831x_irqs); i++) { |
| 453 | int offset = wm831x_irqs[i].reg - 1; |
| 454 | |
| 455 | if (!(primary & wm831x_irqs[i].primary)) |
| 456 | continue; |
| 457 | |
| 458 | status = &status_regs[offset]; |
| 459 | |
| 460 | /* Hopefully there should only be one register to read |
| 461 | * each time otherwise we ought to do a block read. */ |
| 462 | if (!read[offset]) { |
| 463 | *status = wm831x_reg_read(wm831x, |
| 464 | irq_data_to_status_reg(&wm831x_irqs[i])); |
| 465 | if (*status < 0) { |
| 466 | dev_err(wm831x->dev, |
| 467 | "Failed to read IRQ status: %d\n", |
| 468 | *status); |
Mark Brown | 5fb4d38 | 2009-11-11 16:10:22 +0000 | [diff] [blame] | 469 | goto out; |
Mark Brown | 7d4d0a3 | 2009-07-27 14:45:53 +0100 | [diff] [blame] | 470 | } |
| 471 | |
Mark Brown | 7d4d0a3 | 2009-07-27 14:45:53 +0100 | [diff] [blame] | 472 | read[offset] = 1; |
| 473 | } |
| 474 | |
Mark Brown | 5fb4d38 | 2009-11-11 16:10:22 +0000 | [diff] [blame] | 475 | /* Report it if it isn't masked, or forget the status. */ |
| 476 | if ((*status & ~wm831x->irq_masks_cur[offset]) |
| 477 | & wm831x_irqs[i].mask) |
| 478 | handle_nested_irq(wm831x->irq_base + i); |
| 479 | else |
| 480 | *status &= ~wm831x_irqs[i].mask; |
Mark Brown | 7d4d0a3 | 2009-07-27 14:45:53 +0100 | [diff] [blame] | 481 | } |
| 482 | |
Mark Brown | 7d4d0a3 | 2009-07-27 14:45:53 +0100 | [diff] [blame] | 483 | out: |
Mark Brown | df50845 | 2011-01-14 13:38:16 +0000 | [diff] [blame] | 484 | /* Touchscreen interrupts are handled specially in the driver */ |
| 485 | status_regs[0] &= ~(WM831X_TCHDATA_EINT | WM831X_TCHPD_EINT); |
| 486 | |
Mark Brown | 5fb4d38 | 2009-11-11 16:10:22 +0000 | [diff] [blame] | 487 | for (i = 0; i < ARRAY_SIZE(status_regs); i++) { |
| 488 | if (status_regs[i]) |
| 489 | wm831x_reg_write(wm831x, WM831X_INTERRUPT_STATUS_1 + i, |
| 490 | status_regs[i]); |
| 491 | } |
Mark Brown | 7d4d0a3 | 2009-07-27 14:45:53 +0100 | [diff] [blame] | 492 | |
| 493 | return IRQ_HANDLED; |
| 494 | } |
| 495 | |
| 496 | int wm831x_irq_init(struct wm831x *wm831x, int irq) |
| 497 | { |
Mark Brown | 5fb4d38 | 2009-11-11 16:10:22 +0000 | [diff] [blame] | 498 | struct wm831x_pdata *pdata = wm831x->dev->platform_data; |
| 499 | int i, cur_irq, ret; |
Mark Brown | 7d4d0a3 | 2009-07-27 14:45:53 +0100 | [diff] [blame] | 500 | |
Mark Brown | 14f572f | 2009-10-19 11:07:05 +0100 | [diff] [blame] | 501 | mutex_init(&wm831x->irq_lock); |
| 502 | |
Mark Brown | 0d7e0e3 | 2010-04-05 16:14:17 +0100 | [diff] [blame] | 503 | /* Mask the individual interrupt sources */ |
| 504 | for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks_cur); i++) { |
| 505 | wm831x->irq_masks_cur[i] = 0xffff; |
| 506 | wm831x->irq_masks_cache[i] = 0xffff; |
| 507 | wm831x_reg_write(wm831x, WM831X_INTERRUPT_STATUS_1_MASK + i, |
| 508 | 0xffff); |
| 509 | } |
| 510 | |
Mark Brown | 7d4d0a3 | 2009-07-27 14:45:53 +0100 | [diff] [blame] | 511 | if (!irq) { |
| 512 | dev_warn(wm831x->dev, |
| 513 | "No interrupt specified - functionality limited\n"); |
| 514 | return 0; |
| 515 | } |
| 516 | |
Mark Brown | 5fb4d38 | 2009-11-11 16:10:22 +0000 | [diff] [blame] | 517 | if (!pdata || !pdata->irq_base) { |
| 518 | dev_err(wm831x->dev, |
| 519 | "No interrupt base specified, no interrupts\n"); |
| 520 | return 0; |
Mark Brown | 7d4d0a3 | 2009-07-27 14:45:53 +0100 | [diff] [blame] | 521 | } |
| 522 | |
Mark Brown | b103e0b | 2011-01-21 13:26:46 +0000 | [diff] [blame^] | 523 | if (pdata->irq_cmos) |
| 524 | i = 0; |
| 525 | else |
| 526 | i = WM831X_IRQ_OD; |
| 527 | |
| 528 | wm831x_set_bits(wm831x, WM831X_IRQ_CONFIG, |
| 529 | WM831X_IRQ_OD, i); |
| 530 | |
Mark Brown | 180e4f5 | 2011-01-05 17:56:01 +0000 | [diff] [blame] | 531 | /* Try to flag /IRQ as a wake source; there are a number of |
| 532 | * unconditional wake sources in the PMIC so this isn't |
| 533 | * conditional but we don't actually care *too* much if it |
| 534 | * fails. |
| 535 | */ |
| 536 | ret = enable_irq_wake(irq); |
| 537 | if (ret != 0) { |
| 538 | dev_warn(wm831x->dev, "Can't enable IRQ as wake source: %d\n", |
| 539 | ret); |
| 540 | } |
| 541 | |
Mark Brown | 7d4d0a3 | 2009-07-27 14:45:53 +0100 | [diff] [blame] | 542 | wm831x->irq = irq; |
Mark Brown | 5fb4d38 | 2009-11-11 16:10:22 +0000 | [diff] [blame] | 543 | wm831x->irq_base = pdata->irq_base; |
Mark Brown | 7d4d0a3 | 2009-07-27 14:45:53 +0100 | [diff] [blame] | 544 | |
Mark Brown | 5fb4d38 | 2009-11-11 16:10:22 +0000 | [diff] [blame] | 545 | /* Register them with genirq */ |
| 546 | for (cur_irq = wm831x->irq_base; |
| 547 | cur_irq < ARRAY_SIZE(wm831x_irqs) + wm831x->irq_base; |
| 548 | cur_irq++) { |
| 549 | set_irq_chip_data(cur_irq, wm831x); |
| 550 | set_irq_chip_and_handler(cur_irq, &wm831x_irq_chip, |
| 551 | handle_edge_irq); |
| 552 | set_irq_nested_thread(cur_irq, 1); |
Mark Brown | 7d4d0a3 | 2009-07-27 14:45:53 +0100 | [diff] [blame] | 553 | |
Mark Brown | 5fb4d38 | 2009-11-11 16:10:22 +0000 | [diff] [blame] | 554 | /* ARM needs us to explicitly flag the IRQ as valid |
| 555 | * and will set them noprobe when we do so. */ |
| 556 | #ifdef CONFIG_ARM |
| 557 | set_irq_flags(cur_irq, IRQF_VALID); |
| 558 | #else |
| 559 | set_irq_noprobe(cur_irq); |
| 560 | #endif |
| 561 | } |
| 562 | |
| 563 | ret = request_threaded_irq(irq, NULL, wm831x_irq_thread, |
| 564 | IRQF_TRIGGER_LOW | IRQF_ONESHOT, |
| 565 | "wm831x", wm831x); |
Mark Brown | 7d4d0a3 | 2009-07-27 14:45:53 +0100 | [diff] [blame] | 566 | if (ret != 0) { |
| 567 | dev_err(wm831x->dev, "Failed to request IRQ %d: %d\n", |
| 568 | irq, ret); |
| 569 | return ret; |
| 570 | } |
| 571 | |
Mark Brown | 5fb4d38 | 2009-11-11 16:10:22 +0000 | [diff] [blame] | 572 | /* Enable top level interrupts, we mask at secondary level */ |
| 573 | wm831x_reg_write(wm831x, WM831X_SYSTEM_INTERRUPTS_MASK, 0); |
| 574 | |
Mark Brown | 7d4d0a3 | 2009-07-27 14:45:53 +0100 | [diff] [blame] | 575 | return 0; |
| 576 | } |
| 577 | |
| 578 | void wm831x_irq_exit(struct wm831x *wm831x) |
| 579 | { |
| 580 | if (wm831x->irq) |
| 581 | free_irq(wm831x->irq, wm831x); |
| 582 | } |