blob: 4e2944ee76d8ac9ae6f584563e02ad19d0bd1b32 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * Support for IDE interfaces on PowerMacs.
Bartlomiej Zolnierkiewicz58f189f2008-02-01 23:09:33 +01003 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07004 * These IDE interfaces are memory-mapped and have a DBDMA channel
5 * for doing DMA.
6 *
7 * Copyright (C) 1998-2003 Paul Mackerras & Ben. Herrenschmidt
Bartlomiej Zolnierkiewicz8a972062008-07-16 20:33:38 +02008 * Copyright (C) 2007-2008 Bartlomiej Zolnierkiewicz
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 *
15 * Some code taken from drivers/ide/ide-dma.c:
16 *
17 * Copyright (c) 1995-1998 Mark Lord
18 *
19 * TODO: - Use pre-calculated (kauai) timing tables all the time and
20 * get rid of the "rounded" tables used previously, so we have the
21 * same table format for all controllers and can then just have one
22 * big table
23 *
24 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070025#include <linux/types.h>
26#include <linux/kernel.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070027#include <linux/init.h>
28#include <linux/delay.h>
29#include <linux/ide.h>
30#include <linux/notifier.h>
31#include <linux/reboot.h>
32#include <linux/pci.h>
33#include <linux/adb.h>
34#include <linux/pmu.h>
35#include <linux/scatterlist.h>
36
37#include <asm/prom.h>
38#include <asm/io.h>
39#include <asm/dbdma.h>
40#include <asm/ide.h>
41#include <asm/pci-bridge.h>
42#include <asm/machdep.h>
43#include <asm/pmac_feature.h>
44#include <asm/sections.h>
45#include <asm/irq.h>
46
47#ifndef CONFIG_PPC64
48#include <asm/mediabay.h>
49#endif
50
Bartlomiej Zolnierkiewiczb36ba532008-07-23 19:55:49 +020051#define DRV_NAME "ide-pmac"
52
Linus Torvalds1da177e2005-04-16 15:20:36 -070053#undef IDE_PMAC_DEBUG
54
55#define DMA_WAIT_TIMEOUT 50
56
57typedef struct pmac_ide_hwif {
58 unsigned long regbase;
59 int irq;
60 int kind;
61 int aapl_bus_id;
Linus Torvalds1da177e2005-04-16 15:20:36 -070062 unsigned mediabay : 1;
63 unsigned broken_dma : 1;
64 unsigned broken_dma_warn : 1;
65 struct device_node* node;
66 struct macio_dev *mdev;
67 u32 timings[4];
68 volatile u32 __iomem * *kauai_fcr;
69#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
70 /* Those fields are duplicating what is in hwif. We currently
71 * can't use the hwif ones because of some assumptions that are
72 * beeing done by the generic code about the kind of dma controller
73 * and format of the dma table. This will have to be fixed though.
74 */
75 volatile struct dbdma_regs __iomem * dma_regs;
76 struct dbdma_cmd* dma_table_cpu;
77#endif
78
79} pmac_ide_hwif_t;
80
Linus Torvalds1da177e2005-04-16 15:20:36 -070081enum {
82 controller_ohare, /* OHare based */
83 controller_heathrow, /* Heathrow/Paddington */
84 controller_kl_ata3, /* KeyLargo ATA-3 */
85 controller_kl_ata4, /* KeyLargo ATA-4 */
86 controller_un_ata6, /* UniNorth2 ATA-6 */
87 controller_k2_ata6, /* K2 ATA-6 */
88 controller_sh_ata6, /* Shasta ATA-6 */
89};
90
91static const char* model_name[] = {
92 "OHare ATA", /* OHare based */
93 "Heathrow ATA", /* Heathrow/Paddington */
94 "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
95 "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */
96 "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */
97 "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */
98 "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */
99};
100
101/*
102 * Extra registers, both 32-bit little-endian
103 */
104#define IDE_TIMING_CONFIG 0x200
105#define IDE_INTERRUPT 0x300
106
107/* Kauai (U2) ATA has different register setup */
108#define IDE_KAUAI_PIO_CONFIG 0x200
109#define IDE_KAUAI_ULTRA_CONFIG 0x210
110#define IDE_KAUAI_POLL_CONFIG 0x220
111
112/*
113 * Timing configuration register definitions
114 */
115
116/* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
117#define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
118#define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
119#define IDE_SYSCLK_NS 30 /* 33Mhz cell */
120#define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */
121
122/* 133Mhz cell, found in shasta.
123 * See comments about 100 Mhz Uninorth 2...
124 * Note that PIO_MASK and MDMA_MASK seem to overlap
125 */
126#define TR_133_PIOREG_PIO_MASK 0xff000fff
127#define TR_133_PIOREG_MDMA_MASK 0x00fff800
128#define TR_133_UDMAREG_UDMA_MASK 0x0003ffff
129#define TR_133_UDMAREG_UDMA_EN 0x00000001
130
131/* 100Mhz cell, found in Uninorth 2. I don't have much infos about
132 * this one yet, it appears as a pci device (106b/0033) on uninorth
133 * internal PCI bus and it's clock is controlled like gem or fw. It
134 * appears to be an evolution of keylargo ATA4 with a timing register
135 * extended to 2 32bits registers and a similar DBDMA channel. Other
136 * registers seem to exist but I can't tell much about them.
137 *
138 * So far, I'm using pre-calculated tables for this extracted from
139 * the values used by the MacOS X driver.
140 *
141 * The "PIO" register controls PIO and MDMA timings, the "ULTRA"
142 * register controls the UDMA timings. At least, it seems bit 0
143 * of this one enables UDMA vs. MDMA, and bits 4..7 are the
144 * cycle time in units of 10ns. Bits 8..15 are used by I don't
145 * know their meaning yet
146 */
147#define TR_100_PIOREG_PIO_MASK 0xff000fff
148#define TR_100_PIOREG_MDMA_MASK 0x00fff000
149#define TR_100_UDMAREG_UDMA_MASK 0x0000ffff
150#define TR_100_UDMAREG_UDMA_EN 0x00000001
151
152
153/* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
154 * 40 connector cable and to 4 on 80 connector one.
155 * Clock unit is 15ns (66Mhz)
156 *
157 * 3 Values can be programmed:
158 * - Write data setup, which appears to match the cycle time. They
159 * also call it DIOW setup.
160 * - Ready to pause time (from spec)
161 * - Address setup. That one is weird. I don't see where exactly
162 * it fits in UDMA cycles, I got it's name from an obscure piece
163 * of commented out code in Darwin. They leave it to 0, we do as
164 * well, despite a comment that would lead to think it has a
165 * min value of 45ns.
166 * Apple also add 60ns to the write data setup (or cycle time ?) on
167 * reads.
168 */
169#define TR_66_UDMA_MASK 0xfff00000
170#define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */
171#define TR_66_UDMA_ADDRSETUP_MASK 0xe0000000 /* Address setup */
172#define TR_66_UDMA_ADDRSETUP_SHIFT 29
173#define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */
174#define TR_66_UDMA_RDY2PAUS_SHIFT 25
175#define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */
176#define TR_66_UDMA_WRDATASETUP_SHIFT 21
177#define TR_66_MDMA_MASK 0x000ffc00
178#define TR_66_MDMA_RECOVERY_MASK 0x000f8000
179#define TR_66_MDMA_RECOVERY_SHIFT 15
180#define TR_66_MDMA_ACCESS_MASK 0x00007c00
181#define TR_66_MDMA_ACCESS_SHIFT 10
182#define TR_66_PIO_MASK 0x000003ff
183#define TR_66_PIO_RECOVERY_MASK 0x000003e0
184#define TR_66_PIO_RECOVERY_SHIFT 5
185#define TR_66_PIO_ACCESS_MASK 0x0000001f
186#define TR_66_PIO_ACCESS_SHIFT 0
187
188/* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo
189 * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
190 *
191 * The access time and recovery time can be programmed. Some older
192 * Darwin code base limit OHare to 150ns cycle time. I decided to do
193 * the same here fore safety against broken old hardware ;)
194 * The HalfTick bit, when set, adds half a clock (15ns) to the access
195 * time and removes one from recovery. It's not supported on KeyLargo
196 * implementation afaik. The E bit appears to be set for PIO mode 0 and
197 * is used to reach long timings used in this mode.
198 */
199#define TR_33_MDMA_MASK 0x003ff800
200#define TR_33_MDMA_RECOVERY_MASK 0x001f0000
201#define TR_33_MDMA_RECOVERY_SHIFT 16
202#define TR_33_MDMA_ACCESS_MASK 0x0000f800
203#define TR_33_MDMA_ACCESS_SHIFT 11
204#define TR_33_MDMA_HALFTICK 0x00200000
205#define TR_33_PIO_MASK 0x000007ff
206#define TR_33_PIO_E 0x00000400
207#define TR_33_PIO_RECOVERY_MASK 0x000003e0
208#define TR_33_PIO_RECOVERY_SHIFT 5
209#define TR_33_PIO_ACCESS_MASK 0x0000001f
210#define TR_33_PIO_ACCESS_SHIFT 0
211
212/*
213 * Interrupt register definitions
214 */
215#define IDE_INTR_DMA 0x80000000
216#define IDE_INTR_DEVICE 0x40000000
217
218/*
219 * FCR Register on Kauai. Not sure what bit 0x4 is ...
220 */
221#define KAUAI_FCR_UATA_MAGIC 0x00000004
222#define KAUAI_FCR_UATA_RESET_N 0x00000002
223#define KAUAI_FCR_UATA_ENABLE 0x00000001
224
225#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
226
227/* Rounded Multiword DMA timings
228 *
229 * I gave up finding a generic formula for all controller
230 * types and instead, built tables based on timing values
231 * used by Apple in Darwin's implementation.
232 */
233struct mdma_timings_t {
234 int accessTime;
235 int recoveryTime;
236 int cycleTime;
237};
238
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500239struct mdma_timings_t mdma_timings_33[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700240{
241 { 240, 240, 480 },
242 { 180, 180, 360 },
243 { 135, 135, 270 },
244 { 120, 120, 240 },
245 { 105, 105, 210 },
246 { 90, 90, 180 },
247 { 75, 75, 150 },
248 { 75, 45, 120 },
249 { 0, 0, 0 }
250};
251
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500252struct mdma_timings_t mdma_timings_33k[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700253{
254 { 240, 240, 480 },
255 { 180, 180, 360 },
256 { 150, 150, 300 },
257 { 120, 120, 240 },
258 { 90, 120, 210 },
259 { 90, 90, 180 },
260 { 90, 60, 150 },
261 { 90, 30, 120 },
262 { 0, 0, 0 }
263};
264
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500265struct mdma_timings_t mdma_timings_66[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700266{
267 { 240, 240, 480 },
268 { 180, 180, 360 },
269 { 135, 135, 270 },
270 { 120, 120, 240 },
271 { 105, 105, 210 },
272 { 90, 90, 180 },
273 { 90, 75, 165 },
274 { 75, 45, 120 },
275 { 0, 0, 0 }
276};
277
278/* KeyLargo ATA-4 Ultra DMA timings (rounded) */
279struct {
280 int addrSetup; /* ??? */
281 int rdy2pause;
282 int wrDataSetup;
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500283} kl66_udma_timings[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700284{
285 { 0, 180, 120 }, /* Mode 0 */
286 { 0, 150, 90 }, /* 1 */
287 { 0, 120, 60 }, /* 2 */
288 { 0, 90, 45 }, /* 3 */
289 { 0, 90, 30 } /* 4 */
290};
291
292/* UniNorth 2 ATA/100 timings */
293struct kauai_timing {
294 int cycle_time;
295 u32 timing_reg;
296};
297
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500298static struct kauai_timing kauai_pio_timings[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700299{
300 { 930 , 0x08000fff },
301 { 600 , 0x08000a92 },
302 { 383 , 0x0800060f },
303 { 360 , 0x08000492 },
304 { 330 , 0x0800048f },
305 { 300 , 0x080003cf },
306 { 270 , 0x080003cc },
307 { 240 , 0x0800038b },
308 { 239 , 0x0800030c },
309 { 180 , 0x05000249 },
Bartlomiej Zolnierkiewiczc15d5d42007-10-11 23:54:01 +0200310 { 120 , 0x04000148 },
311 { 0 , 0 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700312};
313
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500314static struct kauai_timing kauai_mdma_timings[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700315{
316 { 1260 , 0x00fff000 },
317 { 480 , 0x00618000 },
318 { 360 , 0x00492000 },
319 { 270 , 0x0038e000 },
320 { 240 , 0x0030c000 },
321 { 210 , 0x002cb000 },
322 { 180 , 0x00249000 },
323 { 150 , 0x00209000 },
324 { 120 , 0x00148000 },
325 { 0 , 0 },
326};
327
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500328static struct kauai_timing kauai_udma_timings[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700329{
330 { 120 , 0x000070c0 },
331 { 90 , 0x00005d80 },
332 { 60 , 0x00004a60 },
333 { 45 , 0x00003a50 },
334 { 30 , 0x00002a30 },
335 { 20 , 0x00002921 },
336 { 0 , 0 },
337};
338
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500339static struct kauai_timing shasta_pio_timings[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700340{
341 { 930 , 0x08000fff },
342 { 600 , 0x0A000c97 },
343 { 383 , 0x07000712 },
344 { 360 , 0x040003cd },
345 { 330 , 0x040003cd },
346 { 300 , 0x040003cd },
347 { 270 , 0x040003cd },
348 { 240 , 0x040003cd },
349 { 239 , 0x040003cd },
350 { 180 , 0x0400028b },
Bartlomiej Zolnierkiewiczc15d5d42007-10-11 23:54:01 +0200351 { 120 , 0x0400010a },
352 { 0 , 0 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700353};
354
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500355static struct kauai_timing shasta_mdma_timings[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700356{
357 { 1260 , 0x00fff000 },
358 { 480 , 0x00820800 },
359 { 360 , 0x00820800 },
360 { 270 , 0x00820800 },
361 { 240 , 0x00820800 },
362 { 210 , 0x00820800 },
363 { 180 , 0x00820800 },
364 { 150 , 0x0028b000 },
365 { 120 , 0x001ca000 },
366 { 0 , 0 },
367};
368
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500369static struct kauai_timing shasta_udma133_timings[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700370{
371 { 120 , 0x00035901, },
372 { 90 , 0x000348b1, },
373 { 60 , 0x00033881, },
374 { 45 , 0x00033861, },
375 { 30 , 0x00033841, },
376 { 20 , 0x00033031, },
377 { 15 , 0x00033021, },
378 { 0 , 0 },
379};
380
381
382static inline u32
383kauai_lookup_timing(struct kauai_timing* table, int cycle_time)
384{
385 int i;
386
387 for (i=0; table[i].cycle_time; i++)
388 if (cycle_time > table[i+1].cycle_time)
389 return table[i].timing_reg;
Bartlomiej Zolnierkiewicz90a87ea2007-10-13 17:47:48 +0200390 BUG();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700391 return 0;
392}
393
394/* allow up to 256 DBDMA commands per xfer */
395#define MAX_DCMDS 256
396
397/*
398 * Wait 1s for disk to answer on IDE bus after a hard reset
399 * of the device (via GPIO/FCR).
400 *
401 * Some devices seem to "pollute" the bus even after dropping
402 * the BSY bit (typically some combo drives slave on the UDMA
403 * bus) after a hard reset. Since we hard reset all drives on
404 * KeyLargo ATA66, we have to keep that delay around. I may end
405 * up not hard resetting anymore on these and keep the delay only
406 * for older interfaces instead (we have to reset when coming
407 * from MacOS...) --BenH.
408 */
409#define IDE_WAKEUP_DELAY (1*HZ)
410
Bartlomiej Zolnierkiewicz0d071922008-04-26 22:25:22 +0200411static int pmac_ide_init_dma(ide_hwif_t *, const struct ide_port_info *);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700412static int pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700413static void pmac_ide_selectproc(ide_drive_t *drive);
414static void pmac_ide_kauai_selectproc(ide_drive_t *drive);
415
416#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
417
Bartlomiej Zolnierkiewicz23579a22008-04-18 00:46:26 +0200418#define PMAC_IDE_REG(x) \
Bartlomiej Zolnierkiewicz4c3032d2008-04-27 15:38:32 +0200419 ((void __iomem *)((drive)->hwif->io_ports.data_addr + (x)))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700420
421/*
422 * Apply the timings of the proper unit (master/slave) to the shared
423 * timing register when selecting that unit. This version is for
424 * ASICs with a single timing register
425 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500426static void
Linus Torvalds1da177e2005-04-16 15:20:36 -0700427pmac_ide_selectproc(ide_drive_t *drive)
428{
Bartlomiej Zolnierkiewicz7b8797a2008-07-23 19:55:48 +0200429 ide_hwif_t *hwif = drive->hwif;
430 pmac_ide_hwif_t *pmif =
431 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700432
433 if (pmif == NULL)
434 return;
435
436 if (drive->select.b.unit & 0x01)
437 writel(pmif->timings[1], PMAC_IDE_REG(IDE_TIMING_CONFIG));
438 else
439 writel(pmif->timings[0], PMAC_IDE_REG(IDE_TIMING_CONFIG));
440 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
441}
442
443/*
444 * Apply the timings of the proper unit (master/slave) to the shared
445 * timing register when selecting that unit. This version is for
446 * ASICs with a dual timing register (Kauai)
447 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500448static void
Linus Torvalds1da177e2005-04-16 15:20:36 -0700449pmac_ide_kauai_selectproc(ide_drive_t *drive)
450{
Bartlomiej Zolnierkiewicz7b8797a2008-07-23 19:55:48 +0200451 ide_hwif_t *hwif = drive->hwif;
452 pmac_ide_hwif_t *pmif =
453 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700454
455 if (pmif == NULL)
456 return;
457
458 if (drive->select.b.unit & 0x01) {
459 writel(pmif->timings[1], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
460 writel(pmif->timings[3], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
461 } else {
462 writel(pmif->timings[0], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
463 writel(pmif->timings[2], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
464 }
465 (void)readl(PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
466}
467
468/*
469 * Force an update of controller timing values for a given drive
470 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500471static void
Linus Torvalds1da177e2005-04-16 15:20:36 -0700472pmac_ide_do_update_timings(ide_drive_t *drive)
473{
Bartlomiej Zolnierkiewicz7b8797a2008-07-23 19:55:48 +0200474 ide_hwif_t *hwif = drive->hwif;
475 pmac_ide_hwif_t *pmif =
476 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700477
478 if (pmif == NULL)
479 return;
480
481 if (pmif->kind == controller_sh_ata6 ||
482 pmif->kind == controller_un_ata6 ||
483 pmif->kind == controller_k2_ata6)
484 pmac_ide_kauai_selectproc(drive);
485 else
486 pmac_ide_selectproc(drive);
487}
488
Bartlomiej Zolnierkiewiczf8c4bd0a2008-07-15 21:21:49 +0200489static void pmac_outbsync(ide_hwif_t *hwif, u8 value, unsigned long port)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700490{
491 u32 tmp;
492
493 writeb(value, (void __iomem *) port);
Bartlomiej Zolnierkiewiczf8c4bd0a2008-07-15 21:21:49 +0200494 tmp = readl((void __iomem *)(hwif->io_ports.data_addr
495 + IDE_TIMING_CONFIG));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700496}
497
498/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700499 * Old tuning functions (called on hdparm -p), sets up drive PIO timings
500 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500501static void
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +0200502pmac_ide_set_pio_mode(ide_drive_t *drive, const u8 pio)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700503{
Bartlomiej Zolnierkiewicz7b8797a2008-07-23 19:55:48 +0200504 ide_hwif_t *hwif = drive->hwif;
505 pmac_ide_hwif_t *pmif =
506 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
Bartlomiej Zolnierkiewicz8a972062008-07-16 20:33:38 +0200507 struct ide_timing *tim = ide_timing_find_mode(XFER_PIO_0 + pio);
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200508 u32 *timings, t;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700509 unsigned accessTicks, recTicks;
510 unsigned accessTime, recTime;
Bartlomiej Zolnierkiewicz7dd00082007-07-20 01:11:56 +0200511 unsigned int cycle_time;
512
Linus Torvalds1da177e2005-04-16 15:20:36 -0700513 if (pmif == NULL)
514 return;
515
516 /* which drive is it ? */
517 timings = &pmif->timings[drive->select.b.unit & 0x01];
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200518 t = *timings;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700519
Bartlomiej Zolnierkiewicz7dd00082007-07-20 01:11:56 +0200520 cycle_time = ide_pio_cycle_time(drive, pio);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700521
522 switch (pmif->kind) {
523 case controller_sh_ata6: {
524 /* 133Mhz cell */
Bartlomiej Zolnierkiewicz7dd00082007-07-20 01:11:56 +0200525 u32 tr = kauai_lookup_timing(shasta_pio_timings, cycle_time);
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200526 t = (t & ~TR_133_PIOREG_PIO_MASK) | tr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700527 break;
528 }
529 case controller_un_ata6:
530 case controller_k2_ata6: {
531 /* 100Mhz cell */
Bartlomiej Zolnierkiewicz7dd00082007-07-20 01:11:56 +0200532 u32 tr = kauai_lookup_timing(kauai_pio_timings, cycle_time);
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200533 t = (t & ~TR_100_PIOREG_PIO_MASK) | tr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700534 break;
535 }
536 case controller_kl_ata4:
537 /* 66Mhz cell */
Bartlomiej Zolnierkiewicz8a972062008-07-16 20:33:38 +0200538 recTime = cycle_time - tim->active - tim->setup;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700539 recTime = max(recTime, 150U);
Bartlomiej Zolnierkiewicz8a972062008-07-16 20:33:38 +0200540 accessTime = tim->active;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700541 accessTime = max(accessTime, 150U);
542 accessTicks = SYSCLK_TICKS_66(accessTime);
543 accessTicks = min(accessTicks, 0x1fU);
544 recTicks = SYSCLK_TICKS_66(recTime);
545 recTicks = min(recTicks, 0x1fU);
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200546 t = (t & ~TR_66_PIO_MASK) |
547 (accessTicks << TR_66_PIO_ACCESS_SHIFT) |
548 (recTicks << TR_66_PIO_RECOVERY_SHIFT);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700549 break;
550 default: {
551 /* 33Mhz cell */
552 int ebit = 0;
Bartlomiej Zolnierkiewicz8a972062008-07-16 20:33:38 +0200553 recTime = cycle_time - tim->active - tim->setup;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700554 recTime = max(recTime, 150U);
Bartlomiej Zolnierkiewicz8a972062008-07-16 20:33:38 +0200555 accessTime = tim->active;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700556 accessTime = max(accessTime, 150U);
557 accessTicks = SYSCLK_TICKS(accessTime);
558 accessTicks = min(accessTicks, 0x1fU);
559 accessTicks = max(accessTicks, 4U);
560 recTicks = SYSCLK_TICKS(recTime);
561 recTicks = min(recTicks, 0x1fU);
562 recTicks = max(recTicks, 5U) - 4;
563 if (recTicks > 9) {
564 recTicks--; /* guess, but it's only for PIO0, so... */
565 ebit = 1;
566 }
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200567 t = (t & ~TR_33_PIO_MASK) |
Linus Torvalds1da177e2005-04-16 15:20:36 -0700568 (accessTicks << TR_33_PIO_ACCESS_SHIFT) |
569 (recTicks << TR_33_PIO_RECOVERY_SHIFT);
570 if (ebit)
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200571 t |= TR_33_PIO_E;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700572 break;
573 }
574 }
575
576#ifdef IDE_PMAC_DEBUG
577 printk(KERN_ERR "%s: Set PIO timing for mode %d, reg: 0x%08x\n",
578 drive->name, pio, *timings);
579#endif
580
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200581 *timings = t;
Bartlomiej Zolnierkiewiczc15d5d42007-10-11 23:54:01 +0200582 pmac_ide_do_update_timings(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700583}
584
585#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
586
587/*
588 * Calculate KeyLargo ATA/66 UDMA timings
589 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500590static int
Linus Torvalds1da177e2005-04-16 15:20:36 -0700591set_timings_udma_ata4(u32 *timings, u8 speed)
592{
593 unsigned rdyToPauseTicks, wrDataSetupTicks, addrTicks;
594
595 if (speed > XFER_UDMA_4)
596 return 1;
597
598 rdyToPauseTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].rdy2pause);
599 wrDataSetupTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].wrDataSetup);
600 addrTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].addrSetup);
601
602 *timings = ((*timings) & ~(TR_66_UDMA_MASK | TR_66_MDMA_MASK)) |
603 (wrDataSetupTicks << TR_66_UDMA_WRDATASETUP_SHIFT) |
604 (rdyToPauseTicks << TR_66_UDMA_RDY2PAUS_SHIFT) |
605 (addrTicks <<TR_66_UDMA_ADDRSETUP_SHIFT) |
606 TR_66_UDMA_EN;
607#ifdef IDE_PMAC_DEBUG
608 printk(KERN_ERR "ide_pmac: Set UDMA timing for mode %d, reg: 0x%08x\n",
609 speed & 0xf, *timings);
610#endif
611
612 return 0;
613}
614
615/*
616 * Calculate Kauai ATA/100 UDMA timings
617 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500618static int
Linus Torvalds1da177e2005-04-16 15:20:36 -0700619set_timings_udma_ata6(u32 *pio_timings, u32 *ultra_timings, u8 speed)
620{
621 struct ide_timing *t = ide_timing_find_mode(speed);
622 u32 tr;
623
624 if (speed > XFER_UDMA_5 || t == NULL)
625 return 1;
626 tr = kauai_lookup_timing(kauai_udma_timings, (int)t->udma);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700627 *ultra_timings = ((*ultra_timings) & ~TR_100_UDMAREG_UDMA_MASK) | tr;
628 *ultra_timings = (*ultra_timings) | TR_100_UDMAREG_UDMA_EN;
629
630 return 0;
631}
632
633/*
634 * Calculate Shasta ATA/133 UDMA timings
635 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500636static int
Linus Torvalds1da177e2005-04-16 15:20:36 -0700637set_timings_udma_shasta(u32 *pio_timings, u32 *ultra_timings, u8 speed)
638{
639 struct ide_timing *t = ide_timing_find_mode(speed);
640 u32 tr;
641
642 if (speed > XFER_UDMA_6 || t == NULL)
643 return 1;
644 tr = kauai_lookup_timing(shasta_udma133_timings, (int)t->udma);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700645 *ultra_timings = ((*ultra_timings) & ~TR_133_UDMAREG_UDMA_MASK) | tr;
646 *ultra_timings = (*ultra_timings) | TR_133_UDMAREG_UDMA_EN;
647
648 return 0;
649}
650
651/*
652 * Calculate MDMA timings for all cells
653 */
Bartlomiej Zolnierkiewicz90f72ec2007-10-13 17:47:48 +0200654static void
Linus Torvalds1da177e2005-04-16 15:20:36 -0700655set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2,
Bartlomiej Zolnierkiewicz90f72ec2007-10-13 17:47:48 +0200656 u8 speed)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700657{
658 int cycleTime, accessTime = 0, recTime = 0;
659 unsigned accessTicks, recTicks;
Bartlomiej Zolnierkiewicz90f72ec2007-10-13 17:47:48 +0200660 struct hd_driveid *id = drive->id;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700661 struct mdma_timings_t* tm = NULL;
662 int i;
663
664 /* Get default cycle time for mode */
665 switch(speed & 0xf) {
666 case 0: cycleTime = 480; break;
667 case 1: cycleTime = 150; break;
668 case 2: cycleTime = 120; break;
669 default:
Bartlomiej Zolnierkiewicz90f72ec2007-10-13 17:47:48 +0200670 BUG();
671 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700672 }
Bartlomiej Zolnierkiewicz90f72ec2007-10-13 17:47:48 +0200673
674 /* Check if drive provides explicit DMA cycle time */
675 if ((id->field_valid & 2) && id->eide_dma_time)
676 cycleTime = max_t(int, id->eide_dma_time, cycleTime);
677
Linus Torvalds1da177e2005-04-16 15:20:36 -0700678 /* OHare limits according to some old Apple sources */
679 if ((intf_type == controller_ohare) && (cycleTime < 150))
680 cycleTime = 150;
681 /* Get the proper timing array for this controller */
682 switch(intf_type) {
683 case controller_sh_ata6:
684 case controller_un_ata6:
685 case controller_k2_ata6:
686 break;
687 case controller_kl_ata4:
688 tm = mdma_timings_66;
689 break;
690 case controller_kl_ata3:
691 tm = mdma_timings_33k;
692 break;
693 default:
694 tm = mdma_timings_33;
695 break;
696 }
697 if (tm != NULL) {
698 /* Lookup matching access & recovery times */
699 i = -1;
700 for (;;) {
701 if (tm[i+1].cycleTime < cycleTime)
702 break;
703 i++;
704 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700705 cycleTime = tm[i].cycleTime;
706 accessTime = tm[i].accessTime;
707 recTime = tm[i].recoveryTime;
708
709#ifdef IDE_PMAC_DEBUG
710 printk(KERN_ERR "%s: MDMA, cycleTime: %d, accessTime: %d, recTime: %d\n",
711 drive->name, cycleTime, accessTime, recTime);
712#endif
713 }
714 switch(intf_type) {
715 case controller_sh_ata6: {
716 /* 133Mhz cell */
717 u32 tr = kauai_lookup_timing(shasta_mdma_timings, cycleTime);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700718 *timings = ((*timings) & ~TR_133_PIOREG_MDMA_MASK) | tr;
719 *timings2 = (*timings2) & ~TR_133_UDMAREG_UDMA_EN;
720 }
721 case controller_un_ata6:
722 case controller_k2_ata6: {
723 /* 100Mhz cell */
724 u32 tr = kauai_lookup_timing(kauai_mdma_timings, cycleTime);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700725 *timings = ((*timings) & ~TR_100_PIOREG_MDMA_MASK) | tr;
726 *timings2 = (*timings2) & ~TR_100_UDMAREG_UDMA_EN;
727 }
728 break;
729 case controller_kl_ata4:
730 /* 66Mhz cell */
731 accessTicks = SYSCLK_TICKS_66(accessTime);
732 accessTicks = min(accessTicks, 0x1fU);
733 accessTicks = max(accessTicks, 0x1U);
734 recTicks = SYSCLK_TICKS_66(recTime);
735 recTicks = min(recTicks, 0x1fU);
736 recTicks = max(recTicks, 0x3U);
737 /* Clear out mdma bits and disable udma */
738 *timings = ((*timings) & ~(TR_66_MDMA_MASK | TR_66_UDMA_MASK)) |
739 (accessTicks << TR_66_MDMA_ACCESS_SHIFT) |
740 (recTicks << TR_66_MDMA_RECOVERY_SHIFT);
741 break;
742 case controller_kl_ata3:
743 /* 33Mhz cell on KeyLargo */
744 accessTicks = SYSCLK_TICKS(accessTime);
745 accessTicks = max(accessTicks, 1U);
746 accessTicks = min(accessTicks, 0x1fU);
747 accessTime = accessTicks * IDE_SYSCLK_NS;
748 recTicks = SYSCLK_TICKS(recTime);
749 recTicks = max(recTicks, 1U);
750 recTicks = min(recTicks, 0x1fU);
751 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
752 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
753 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
754 break;
755 default: {
756 /* 33Mhz cell on others */
757 int halfTick = 0;
758 int origAccessTime = accessTime;
759 int origRecTime = recTime;
760
761 accessTicks = SYSCLK_TICKS(accessTime);
762 accessTicks = max(accessTicks, 1U);
763 accessTicks = min(accessTicks, 0x1fU);
764 accessTime = accessTicks * IDE_SYSCLK_NS;
765 recTicks = SYSCLK_TICKS(recTime);
766 recTicks = max(recTicks, 2U) - 1;
767 recTicks = min(recTicks, 0x1fU);
768 recTime = (recTicks + 1) * IDE_SYSCLK_NS;
769 if ((accessTicks > 1) &&
770 ((accessTime - IDE_SYSCLK_NS/2) >= origAccessTime) &&
771 ((recTime - IDE_SYSCLK_NS/2) >= origRecTime)) {
772 halfTick = 1;
773 accessTicks--;
774 }
775 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
776 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
777 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
778 if (halfTick)
779 *timings |= TR_33_MDMA_HALFTICK;
780 }
781 }
782#ifdef IDE_PMAC_DEBUG
783 printk(KERN_ERR "%s: Set MDMA timing for mode %d, reg: 0x%08x\n",
784 drive->name, speed & 0xf, *timings);
785#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700786}
787#endif /* #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC */
788
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200789static void pmac_ide_set_dma_mode(ide_drive_t *drive, const u8 speed)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700790{
Bartlomiej Zolnierkiewicz7b8797a2008-07-23 19:55:48 +0200791 ide_hwif_t *hwif = drive->hwif;
792 pmac_ide_hwif_t *pmif =
793 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700794 int unit = (drive->select.b.unit & 0x01);
795 int ret = 0;
Bartlomiej Zolnierkiewicz085798b2007-10-13 17:47:48 +0200796 u32 *timings, *timings2, tl[2];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700797
Linus Torvalds1da177e2005-04-16 15:20:36 -0700798 timings = &pmif->timings[unit];
799 timings2 = &pmif->timings[unit+2];
Bartlomiej Zolnierkiewicz085798b2007-10-13 17:47:48 +0200800
801 /* Copy timings to local image */
802 tl[0] = *timings;
803 tl[1] = *timings2;
804
Linus Torvalds1da177e2005-04-16 15:20:36 -0700805#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
Bartlomiej Zolnierkiewicz4db90a12008-01-25 22:17:18 +0100806 if (speed >= XFER_UDMA_0) {
807 if (pmif->kind == controller_kl_ata4)
808 ret = set_timings_udma_ata4(&tl[0], speed);
809 else if (pmif->kind == controller_un_ata6
810 || pmif->kind == controller_k2_ata6)
811 ret = set_timings_udma_ata6(&tl[0], &tl[1], speed);
812 else if (pmif->kind == controller_sh_ata6)
813 ret = set_timings_udma_shasta(&tl[0], &tl[1], speed);
814 else
815 ret = -1;
816 } else
817 set_timings_mdma(drive, pmif->kind, &tl[0], &tl[1], speed);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700818#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700819 if (ret)
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200820 return;
Bartlomiej Zolnierkiewicz085798b2007-10-13 17:47:48 +0200821
822 /* Apply timings to controller */
823 *timings = tl[0];
824 *timings2 = tl[1];
825
Linus Torvalds1da177e2005-04-16 15:20:36 -0700826 pmac_ide_do_update_timings(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700827}
828
829/*
830 * Blast some well known "safe" values to the timing registers at init or
831 * wakeup from sleep time, before we do real calculation
832 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500833static void
Linus Torvalds1da177e2005-04-16 15:20:36 -0700834sanitize_timings(pmac_ide_hwif_t *pmif)
835{
836 unsigned int value, value2 = 0;
837
838 switch(pmif->kind) {
839 case controller_sh_ata6:
840 value = 0x0a820c97;
841 value2 = 0x00033031;
842 break;
843 case controller_un_ata6:
844 case controller_k2_ata6:
845 value = 0x08618a92;
846 value2 = 0x00002921;
847 break;
848 case controller_kl_ata4:
849 value = 0x0008438c;
850 break;
851 case controller_kl_ata3:
852 value = 0x00084526;
853 break;
854 case controller_heathrow:
855 case controller_ohare:
856 default:
857 value = 0x00074526;
858 break;
859 }
860 pmif->timings[0] = pmif->timings[1] = value;
861 pmif->timings[2] = pmif->timings[3] = value2;
862}
863
Linus Torvalds1da177e2005-04-16 15:20:36 -0700864/* Suspend call back, should be called after the child devices
865 * have actually been suspended
866 */
Bartlomiej Zolnierkiewicz7b8797a2008-07-23 19:55:48 +0200867static int pmac_ide_do_suspend(pmac_ide_hwif_t *pmif)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700868{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700869 /* We clear the timings */
870 pmif->timings[0] = 0;
871 pmif->timings[1] = 0;
872
Benjamin Herrenschmidt616299a2005-05-01 08:58:41 -0700873 disable_irq(pmif->irq);
874
Linus Torvalds1da177e2005-04-16 15:20:36 -0700875 /* The media bay will handle itself just fine */
876 if (pmif->mediabay)
877 return 0;
878
879 /* Kauai has bus control FCRs directly here */
880 if (pmif->kauai_fcr) {
881 u32 fcr = readl(pmif->kauai_fcr);
882 fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE);
883 writel(fcr, pmif->kauai_fcr);
884 }
885
886 /* Disable the bus on older machines and the cell on kauai */
887 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id,
888 0);
889
890 return 0;
891}
892
893/* Resume call back, should be called before the child devices
894 * are resumed
895 */
Bartlomiej Zolnierkiewicz7b8797a2008-07-23 19:55:48 +0200896static int pmac_ide_do_resume(pmac_ide_hwif_t *pmif)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700897{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700898 /* Hard reset & re-enable controller (do we really need to reset ? -BenH) */
899 if (!pmif->mediabay) {
900 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 1);
901 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id, 1);
902 msleep(10);
903 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700904
905 /* Kauai has it different */
906 if (pmif->kauai_fcr) {
907 u32 fcr = readl(pmif->kauai_fcr);
908 fcr |= KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE;
909 writel(fcr, pmif->kauai_fcr);
910 }
Benjamin Herrenschmidt616299a2005-05-01 08:58:41 -0700911
912 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700913 }
914
915 /* Sanitize drive timings */
916 sanitize_timings(pmif);
917
Benjamin Herrenschmidt616299a2005-05-01 08:58:41 -0700918 enable_irq(pmif->irq);
919
Linus Torvalds1da177e2005-04-16 15:20:36 -0700920 return 0;
921}
922
Bartlomiej Zolnierkiewicz07a6c662008-06-15 21:00:23 +0200923static u8 pmac_ide_cable_detect(ide_hwif_t *hwif)
924{
Bartlomiej Zolnierkiewicz7b8797a2008-07-23 19:55:48 +0200925 pmac_ide_hwif_t *pmif =
926 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
Bartlomiej Zolnierkiewicz07a6c662008-06-15 21:00:23 +0200927 struct device_node *np = pmif->node;
928 const char *cable = of_get_property(np, "cable-type", NULL);
929
930 /* Get cable type from device-tree. */
931 if (cable && !strncmp(cable, "80-", 3))
932 return ATA_CBL_PATA80;
933
934 /*
935 * G5's seem to have incorrect cable type in device-tree.
936 * Let's assume they have a 80 conductor cable, this seem
937 * to be always the case unless the user mucked around.
938 */
939 if (of_device_is_compatible(np, "K2-UATA") ||
940 of_device_is_compatible(np, "shasta-ata"))
941 return ATA_CBL_PATA80;
942
943 return ATA_CBL_PATA40;
944}
945
Bartlomiej Zolnierkiewicz07eb1062008-07-23 19:55:49 +0200946static void pmac_ide_init_dev(ide_drive_t *drive)
947{
948 ide_hwif_t *hwif = drive->hwif;
949 pmac_ide_hwif_t *pmif =
950 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
951
952 if (pmif->mediabay) {
953#ifdef CONFIG_PMAC_MEDIABAY
954 if (check_media_bay_by_base(pmif->regbase, MB_CD) == 0) {
955 drive->noprobe = 0;
956 return;
957 }
958#endif
959 drive->noprobe = 1;
960 }
961}
962
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +0200963static const struct ide_port_ops pmac_ide_ata6_port_ops = {
Bartlomiej Zolnierkiewicz07eb1062008-07-23 19:55:49 +0200964 .init_dev = pmac_ide_init_dev,
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +0200965 .set_pio_mode = pmac_ide_set_pio_mode,
966 .set_dma_mode = pmac_ide_set_dma_mode,
967 .selectproc = pmac_ide_kauai_selectproc,
Bartlomiej Zolnierkiewicz07a6c662008-06-15 21:00:23 +0200968 .cable_detect = pmac_ide_cable_detect,
969};
970
971static const struct ide_port_ops pmac_ide_ata4_port_ops = {
Bartlomiej Zolnierkiewicz07eb1062008-07-23 19:55:49 +0200972 .init_dev = pmac_ide_init_dev,
Bartlomiej Zolnierkiewicz07a6c662008-06-15 21:00:23 +0200973 .set_pio_mode = pmac_ide_set_pio_mode,
974 .set_dma_mode = pmac_ide_set_dma_mode,
975 .selectproc = pmac_ide_selectproc,
976 .cable_detect = pmac_ide_cable_detect,
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +0200977};
978
979static const struct ide_port_ops pmac_ide_port_ops = {
Bartlomiej Zolnierkiewicz07eb1062008-07-23 19:55:49 +0200980 .init_dev = pmac_ide_init_dev,
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +0200981 .set_pio_mode = pmac_ide_set_pio_mode,
982 .set_dma_mode = pmac_ide_set_dma_mode,
983 .selectproc = pmac_ide_selectproc,
984};
985
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +0200986static const struct ide_dma_ops pmac_dma_ops;
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200987
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +0100988static const struct ide_port_info pmac_port_info = {
Bartlomiej Zolnierkiewiczb36ba532008-07-23 19:55:49 +0200989 .name = DRV_NAME,
Bartlomiej Zolnierkiewicz0d071922008-04-26 22:25:22 +0200990 .init_dma = pmac_ide_init_dma,
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +0100991 .chipset = ide_pmac,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200992#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
993 .dma_ops = &pmac_dma_ops,
994#endif
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +0200995 .port_ops = &pmac_ide_port_ops,
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +0100996 .host_flags = IDE_HFLAG_SET_PIO_MODE_KEEP_DMA |
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +0100997 IDE_HFLAG_POST_SET_MODE |
Bartlomiej Zolnierkiewiczc5dd43e2008-04-28 23:44:37 +0200998 IDE_HFLAG_MMIO |
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +0100999 IDE_HFLAG_UNMASK_IRQS,
1000 .pio_mask = ATA_PIO4,
1001 .mwdma_mask = ATA_MWDMA2,
1002};
1003
Linus Torvalds1da177e2005-04-16 15:20:36 -07001004/*
1005 * Setup, register & probe an IDE channel driven by this driver, this is
Bartlomiej Zolnierkiewicz5b164642008-06-15 21:00:23 +02001006 * called by one of the 2 probe functions (macio or PCI).
Linus Torvalds1da177e2005-04-16 15:20:36 -07001007 */
Bartlomiej Zolnierkiewiczb36ba532008-07-23 19:55:49 +02001008static int __devinit pmac_ide_setup_device(pmac_ide_hwif_t *pmif, hw_regs_t *hw)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001009{
1010 struct device_node *np = pmif->node;
Jeremy Kerr018a3d12006-07-12 15:40:29 +10001011 const int *bidp;
Bartlomiej Zolnierkiewiczb36ba532008-07-23 19:55:49 +02001012 ide_hwif_t *hwif;
Bartlomiej Zolnierkiewicz8447d9d2007-10-20 00:32:31 +02001013 u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +01001014 struct ide_port_info d = pmac_port_info;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001015
Linus Torvalds1da177e2005-04-16 15:20:36 -07001016 pmif->broken_dma = pmif->broken_dma_warn = 0;
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +01001017 if (of_device_is_compatible(np, "shasta-ata")) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001018 pmif->kind = controller_sh_ata6;
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +02001019 d.port_ops = &pmac_ide_ata6_port_ops;
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +01001020 d.udma_mask = ATA_UDMA6;
1021 } else if (of_device_is_compatible(np, "kauai-ata")) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001022 pmif->kind = controller_un_ata6;
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +02001023 d.port_ops = &pmac_ide_ata6_port_ops;
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +01001024 d.udma_mask = ATA_UDMA5;
1025 } else if (of_device_is_compatible(np, "K2-UATA")) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001026 pmif->kind = controller_k2_ata6;
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +02001027 d.port_ops = &pmac_ide_ata6_port_ops;
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +01001028 d.udma_mask = ATA_UDMA5;
1029 } else if (of_device_is_compatible(np, "keylargo-ata")) {
1030 if (strcmp(np->name, "ata-4") == 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001031 pmif->kind = controller_kl_ata4;
Bartlomiej Zolnierkiewicz07a6c662008-06-15 21:00:23 +02001032 d.port_ops = &pmac_ide_ata4_port_ops;
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +01001033 d.udma_mask = ATA_UDMA4;
1034 } else
Linus Torvalds1da177e2005-04-16 15:20:36 -07001035 pmif->kind = controller_kl_ata3;
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +01001036 } else if (of_device_is_compatible(np, "heathrow-ata")) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001037 pmif->kind = controller_heathrow;
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +01001038 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001039 pmif->kind = controller_ohare;
1040 pmif->broken_dma = 1;
1041 }
1042
Stephen Rothwell40cd3a42007-05-01 13:54:02 +10001043 bidp = of_get_property(np, "AAPL,bus-id", NULL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001044 pmif->aapl_bus_id = bidp ? *bidp : 0;
1045
Linus Torvalds1da177e2005-04-16 15:20:36 -07001046 /* On Kauai-type controllers, we make sure the FCR is correct */
1047 if (pmif->kauai_fcr)
1048 writel(KAUAI_FCR_UATA_MAGIC |
1049 KAUAI_FCR_UATA_RESET_N |
1050 KAUAI_FCR_UATA_ENABLE, pmif->kauai_fcr);
1051
1052 pmif->mediabay = 0;
1053
1054 /* Make sure we have sane timings */
1055 sanitize_timings(pmif);
1056
1057#ifndef CONFIG_PPC64
1058 /* XXX FIXME: Media bay stuff need re-organizing */
1059 if (np->parent && np->parent->name
1060 && strcasecmp(np->parent->name, "media-bay") == 0) {
Benjamin Herrenschmidt8c870932005-06-27 14:36:34 -07001061#ifdef CONFIG_PMAC_MEDIABAY
Bartlomiej Zolnierkiewicz2dde7862008-04-18 00:46:23 +02001062 media_bay_set_ide_infos(np->parent, pmif->regbase, pmif->irq,
1063 hwif);
Benjamin Herrenschmidt8c870932005-06-27 14:36:34 -07001064#endif /* CONFIG_PMAC_MEDIABAY */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001065 pmif->mediabay = 1;
1066 if (!bidp)
1067 pmif->aapl_bus_id = 1;
1068 } else if (pmif->kind == controller_ohare) {
1069 /* The code below is having trouble on some ohare machines
1070 * (timing related ?). Until I can put my hand on one of these
1071 * units, I keep the old way
1072 */
1073 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, 0, 1);
1074 } else
1075#endif
1076 {
1077 /* This is necessary to enable IDE when net-booting */
1078 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 1);
1079 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, pmif->aapl_bus_id, 1);
1080 msleep(10);
1081 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 0);
1082 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
1083 }
1084
Bartlomiej Zolnierkiewiczb36ba532008-07-23 19:55:49 +02001085 printk(KERN_INFO DRV_NAME ": Found Apple %s controller (%s), "
1086 "bus ID %d%s, irq %d\n", model_name[pmif->kind],
1087 pmif->mdev ? "macio" : "PCI", pmif->aapl_bus_id,
1088 pmif->mediabay ? " (mediabay)" : "", hw->irq);
1089
1090 hwif = ide_find_port_slot(&d);
1091 if (hwif == NULL)
1092 return -ENOENT;
1093
Linus Torvalds1da177e2005-04-16 15:20:36 -07001094 /* Setup MMIO ops */
1095 default_hwif_mmiops(hwif);
1096 hwif->OUTBSYNC = pmac_outbsync;
1097
Bartlomiej Zolnierkiewicz57c802e2008-01-26 20:13:05 +01001098 ide_init_port_hw(hwif, hw);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001099
Bartlomiej Zolnierkiewicz8447d9d2007-10-20 00:32:31 +02001100 idx[0] = hwif->index;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001101
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +01001102 ide_device_add(idx, &d);
Bartlomiej Zolnierkiewicz5cbf79c2007-05-10 00:01:11 +02001103
Linus Torvalds1da177e2005-04-16 15:20:36 -07001104 return 0;
1105}
1106
Bartlomiej Zolnierkiewicz5c586662008-04-18 00:46:29 +02001107static void __devinit pmac_ide_init_ports(hw_regs_t *hw, unsigned long base)
1108{
1109 int i;
1110
1111 for (i = 0; i < 8; ++i)
Bartlomiej Zolnierkiewicz4c3032d2008-04-27 15:38:32 +02001112 hw->io_ports_array[i] = base + i * 0x10;
1113
1114 hw->io_ports.ctl_addr = base + 0x160;
Bartlomiej Zolnierkiewicz5c586662008-04-18 00:46:29 +02001115}
1116
Linus Torvalds1da177e2005-04-16 15:20:36 -07001117/*
1118 * Attach to a macio probed interface
1119 */
1120static int __devinit
Jeff Mahoney5e655772005-07-06 15:44:41 -04001121pmac_ide_macio_attach(struct macio_dev *mdev, const struct of_device_id *match)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001122{
1123 void __iomem *base;
1124 unsigned long regbase;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001125 pmac_ide_hwif_t *pmif;
Bartlomiej Zolnierkiewicz939b0f12008-04-26 17:36:33 +02001126 int irq, rc;
Bartlomiej Zolnierkiewicz57c802e2008-01-26 20:13:05 +01001127 hw_regs_t hw;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001128
Bartlomiej Zolnierkiewicz5297a3e2008-04-26 17:36:32 +02001129 pmif = kzalloc(sizeof(*pmif), GFP_KERNEL);
1130 if (pmif == NULL)
1131 return -ENOMEM;
1132
Benjamin Herrenschmidtcc5d0182005-12-13 18:01:21 +11001133 if (macio_resource_count(mdev) == 0) {
Bartlomiej Zolnierkiewicz939b0f12008-04-26 17:36:33 +02001134 printk(KERN_WARNING "ide-pmac: no address for %s\n",
1135 mdev->ofdev.node->full_name);
Bartlomiej Zolnierkiewicz5297a3e2008-04-26 17:36:32 +02001136 rc = -ENXIO;
1137 goto out_free_pmif;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001138 }
1139
1140 /* Request memory resource for IO ports */
1141 if (macio_request_resource(mdev, 0, "ide-pmac (ports)")) {
Bartlomiej Zolnierkiewicz939b0f12008-04-26 17:36:33 +02001142 printk(KERN_ERR "ide-pmac: can't request MMIO resource for "
1143 "%s!\n", mdev->ofdev.node->full_name);
Bartlomiej Zolnierkiewicz5297a3e2008-04-26 17:36:32 +02001144 rc = -EBUSY;
1145 goto out_free_pmif;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001146 }
1147
1148 /* XXX This is bogus. Should be fixed in the registry by checking
1149 * the kind of host interrupt controller, a bit like gatwick
1150 * fixes in irq.c. That works well enough for the single case
1151 * where that happens though...
1152 */
1153 if (macio_irq_count(mdev) == 0) {
Bartlomiej Zolnierkiewicz939b0f12008-04-26 17:36:33 +02001154 printk(KERN_WARNING "ide-pmac: no intrs for device %s, using "
1155 "13\n", mdev->ofdev.node->full_name);
Benjamin Herrenschmidt69917c22006-09-22 12:56:30 +10001156 irq = irq_create_mapping(NULL, 13);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001157 } else
1158 irq = macio_irq(mdev, 0);
1159
1160 base = ioremap(macio_resource_start(mdev, 0), 0x400);
1161 regbase = (unsigned long) base;
1162
Linus Torvalds1da177e2005-04-16 15:20:36 -07001163 pmif->mdev = mdev;
1164 pmif->node = mdev->ofdev.node;
1165 pmif->regbase = regbase;
1166 pmif->irq = irq;
1167 pmif->kauai_fcr = NULL;
1168#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1169 if (macio_resource_count(mdev) >= 2) {
1170 if (macio_request_resource(mdev, 1, "ide-pmac (dma)"))
Bartlomiej Zolnierkiewicz939b0f12008-04-26 17:36:33 +02001171 printk(KERN_WARNING "ide-pmac: can't request DMA "
1172 "resource for %s!\n",
1173 mdev->ofdev.node->full_name);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001174 else
1175 pmif->dma_regs = ioremap(macio_resource_start(mdev, 1), 0x1000);
1176 } else
1177 pmif->dma_regs = NULL;
1178#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
Bartlomiej Zolnierkiewicz7b8797a2008-07-23 19:55:48 +02001179 dev_set_drvdata(&mdev->ofdev.dev, pmif);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001180
Bartlomiej Zolnierkiewicz57c802e2008-01-26 20:13:05 +01001181 memset(&hw, 0, sizeof(hw));
Bartlomiej Zolnierkiewicz5c586662008-04-18 00:46:29 +02001182 pmac_ide_init_ports(&hw, pmif->regbase);
Bartlomiej Zolnierkiewicz57c802e2008-01-26 20:13:05 +01001183 hw.irq = irq;
Bartlomiej Zolnierkiewiczc56c5642008-07-16 20:33:40 +02001184 hw.dev = &mdev->bus->pdev->dev;
1185 hw.parent = &mdev->ofdev.dev;
Bartlomiej Zolnierkiewicz57c802e2008-01-26 20:13:05 +01001186
Bartlomiej Zolnierkiewiczb36ba532008-07-23 19:55:49 +02001187 rc = pmac_ide_setup_device(pmif, &hw);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001188 if (rc != 0) {
1189 /* The inteface is released to the common IDE layer */
1190 dev_set_drvdata(&mdev->ofdev.dev, NULL);
1191 iounmap(base);
Bartlomiej Zolnierkiewiczed908fa2008-02-01 23:09:32 +01001192 if (pmif->dma_regs) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001193 iounmap(pmif->dma_regs);
Bartlomiej Zolnierkiewiczed908fa2008-02-01 23:09:32 +01001194 macio_release_resource(mdev, 1);
1195 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001196 macio_release_resource(mdev, 0);
Bartlomiej Zolnierkiewicz5297a3e2008-04-26 17:36:32 +02001197 kfree(pmif);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001198 }
1199
1200 return rc;
Bartlomiej Zolnierkiewicz5297a3e2008-04-26 17:36:32 +02001201
1202out_free_pmif:
1203 kfree(pmif);
1204 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001205}
1206
1207static int
David Brownell8b4b8a22006-08-14 23:11:03 -07001208pmac_ide_macio_suspend(struct macio_dev *mdev, pm_message_t mesg)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001209{
Bartlomiej Zolnierkiewicz7b8797a2008-07-23 19:55:48 +02001210 pmac_ide_hwif_t *pmif =
1211 (pmac_ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1212 int rc = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001213
David Brownell8b4b8a22006-08-14 23:11:03 -07001214 if (mesg.event != mdev->ofdev.dev.power.power_state.event
Rafael J. Wysocki3a2d5b72008-02-23 19:13:25 +01001215 && (mesg.event & PM_EVENT_SLEEP)) {
Bartlomiej Zolnierkiewicz7b8797a2008-07-23 19:55:48 +02001216 rc = pmac_ide_do_suspend(pmif);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001217 if (rc == 0)
David Brownell8b4b8a22006-08-14 23:11:03 -07001218 mdev->ofdev.dev.power.power_state = mesg;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001219 }
1220
1221 return rc;
1222}
1223
1224static int
1225pmac_ide_macio_resume(struct macio_dev *mdev)
1226{
Bartlomiej Zolnierkiewicz7b8797a2008-07-23 19:55:48 +02001227 pmac_ide_hwif_t *pmif =
1228 (pmac_ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1229 int rc = 0;
1230
Pavel Machekca078ba2005-09-03 15:56:57 -07001231 if (mdev->ofdev.dev.power.power_state.event != PM_EVENT_ON) {
Bartlomiej Zolnierkiewicz7b8797a2008-07-23 19:55:48 +02001232 rc = pmac_ide_do_resume(pmif);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001233 if (rc == 0)
Pavel Machek829ca9a2005-09-03 15:56:56 -07001234 mdev->ofdev.dev.power.power_state = PMSG_ON;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001235 }
1236
1237 return rc;
1238}
1239
1240/*
1241 * Attach to a PCI probed interface
1242 */
1243static int __devinit
1244pmac_ide_pci_attach(struct pci_dev *pdev, const struct pci_device_id *id)
1245{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001246 struct device_node *np;
1247 pmac_ide_hwif_t *pmif;
1248 void __iomem *base;
1249 unsigned long rbase, rlen;
Bartlomiej Zolnierkiewicz939b0f12008-04-26 17:36:33 +02001250 int rc;
Bartlomiej Zolnierkiewicz57c802e2008-01-26 20:13:05 +01001251 hw_regs_t hw;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001252
1253 np = pci_device_to_OF_node(pdev);
1254 if (np == NULL) {
1255 printk(KERN_ERR "ide-pmac: cannot find MacIO node for Kauai ATA interface\n");
1256 return -ENODEV;
1257 }
Bartlomiej Zolnierkiewicz5297a3e2008-04-26 17:36:32 +02001258
1259 pmif = kzalloc(sizeof(*pmif), GFP_KERNEL);
1260 if (pmif == NULL)
1261 return -ENOMEM;
1262
Linus Torvalds1da177e2005-04-16 15:20:36 -07001263 if (pci_enable_device(pdev)) {
Bartlomiej Zolnierkiewicz939b0f12008-04-26 17:36:33 +02001264 printk(KERN_WARNING "ide-pmac: Can't enable PCI device for "
1265 "%s\n", np->full_name);
Bartlomiej Zolnierkiewicz5297a3e2008-04-26 17:36:32 +02001266 rc = -ENXIO;
1267 goto out_free_pmif;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001268 }
1269 pci_set_master(pdev);
1270
1271 if (pci_request_regions(pdev, "Kauai ATA")) {
Bartlomiej Zolnierkiewicz939b0f12008-04-26 17:36:33 +02001272 printk(KERN_ERR "ide-pmac: Cannot obtain PCI resources for "
1273 "%s\n", np->full_name);
Bartlomiej Zolnierkiewicz5297a3e2008-04-26 17:36:32 +02001274 rc = -ENXIO;
1275 goto out_free_pmif;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001276 }
1277
Linus Torvalds1da177e2005-04-16 15:20:36 -07001278 pmif->mdev = NULL;
1279 pmif->node = np;
1280
1281 rbase = pci_resource_start(pdev, 0);
1282 rlen = pci_resource_len(pdev, 0);
1283
1284 base = ioremap(rbase, rlen);
1285 pmif->regbase = (unsigned long) base + 0x2000;
1286#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1287 pmif->dma_regs = base + 0x1000;
1288#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1289 pmif->kauai_fcr = base;
1290 pmif->irq = pdev->irq;
1291
Bartlomiej Zolnierkiewicz7b8797a2008-07-23 19:55:48 +02001292 pci_set_drvdata(pdev, pmif);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001293
Bartlomiej Zolnierkiewicz57c802e2008-01-26 20:13:05 +01001294 memset(&hw, 0, sizeof(hw));
Bartlomiej Zolnierkiewicz5c586662008-04-18 00:46:29 +02001295 pmac_ide_init_ports(&hw, pmif->regbase);
Bartlomiej Zolnierkiewicz57c802e2008-01-26 20:13:05 +01001296 hw.irq = pdev->irq;
1297 hw.dev = &pdev->dev;
1298
Bartlomiej Zolnierkiewiczb36ba532008-07-23 19:55:49 +02001299 rc = pmac_ide_setup_device(pmif, &hw);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001300 if (rc != 0) {
1301 /* The inteface is released to the common IDE layer */
1302 pci_set_drvdata(pdev, NULL);
1303 iounmap(base);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001304 pci_release_regions(pdev);
Bartlomiej Zolnierkiewicz5297a3e2008-04-26 17:36:32 +02001305 kfree(pmif);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001306 }
1307
1308 return rc;
Bartlomiej Zolnierkiewicz5297a3e2008-04-26 17:36:32 +02001309
1310out_free_pmif:
1311 kfree(pmif);
1312 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001313}
1314
1315static int
David Brownell8b4b8a22006-08-14 23:11:03 -07001316pmac_ide_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001317{
Bartlomiej Zolnierkiewicz7b8797a2008-07-23 19:55:48 +02001318 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)pci_get_drvdata(pdev);
1319 int rc = 0;
1320
David Brownell8b4b8a22006-08-14 23:11:03 -07001321 if (mesg.event != pdev->dev.power.power_state.event
Rafael J. Wysocki3a2d5b72008-02-23 19:13:25 +01001322 && (mesg.event & PM_EVENT_SLEEP)) {
Bartlomiej Zolnierkiewicz7b8797a2008-07-23 19:55:48 +02001323 rc = pmac_ide_do_suspend(pmif);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001324 if (rc == 0)
David Brownell8b4b8a22006-08-14 23:11:03 -07001325 pdev->dev.power.power_state = mesg;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001326 }
1327
1328 return rc;
1329}
1330
1331static int
1332pmac_ide_pci_resume(struct pci_dev *pdev)
1333{
Bartlomiej Zolnierkiewicz7b8797a2008-07-23 19:55:48 +02001334 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)pci_get_drvdata(pdev);
1335 int rc = 0;
1336
Pavel Machekca078ba2005-09-03 15:56:57 -07001337 if (pdev->dev.power.power_state.event != PM_EVENT_ON) {
Bartlomiej Zolnierkiewicz7b8797a2008-07-23 19:55:48 +02001338 rc = pmac_ide_do_resume(pmif);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001339 if (rc == 0)
Pavel Machek829ca9a2005-09-03 15:56:56 -07001340 pdev->dev.power.power_state = PMSG_ON;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001341 }
1342
1343 return rc;
1344}
1345
Jeff Mahoney5e655772005-07-06 15:44:41 -04001346static struct of_device_id pmac_ide_macio_match[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -07001347{
1348 {
1349 .name = "IDE",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001350 },
1351 {
1352 .name = "ATA",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001353 },
1354 {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001355 .type = "ide",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001356 },
1357 {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001358 .type = "ata",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001359 },
1360 {},
1361};
1362
1363static struct macio_driver pmac_ide_macio_driver =
1364{
1365 .name = "ide-pmac",
1366 .match_table = pmac_ide_macio_match,
1367 .probe = pmac_ide_macio_attach,
1368 .suspend = pmac_ide_macio_suspend,
1369 .resume = pmac_ide_macio_resume,
1370};
1371
Bartlomiej Zolnierkiewicz9cbcc5e2007-10-16 22:29:56 +02001372static const struct pci_device_id pmac_ide_pci_match[] = {
1373 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA), 0 },
1374 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100), 0 },
1375 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100), 0 },
1376 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_SH_ATA), 0 },
1377 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID2_ATA), 0 },
Benjamin Herrenschmidt71e4eda2007-10-06 18:52:27 +10001378 {},
Linus Torvalds1da177e2005-04-16 15:20:36 -07001379};
1380
1381static struct pci_driver pmac_ide_pci_driver = {
1382 .name = "ide-pmac",
1383 .id_table = pmac_ide_pci_match,
1384 .probe = pmac_ide_pci_attach,
1385 .suspend = pmac_ide_pci_suspend,
1386 .resume = pmac_ide_pci_resume,
1387};
1388MODULE_DEVICE_TABLE(pci, pmac_ide_pci_match);
1389
Andrew Morton9e5755b2007-03-03 17:48:54 +01001390int __init pmac_ide_probe(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001391{
Andrew Morton9e5755b2007-03-03 17:48:54 +01001392 int error;
1393
Benjamin Herrenschmidte8222502006-03-28 23:15:54 +11001394 if (!machine_is(powermac))
Andrew Morton9e5755b2007-03-03 17:48:54 +01001395 return -ENODEV;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001396
1397#ifdef CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST
Andrew Morton9e5755b2007-03-03 17:48:54 +01001398 error = pci_register_driver(&pmac_ide_pci_driver);
1399 if (error)
1400 goto out;
1401 error = macio_register_driver(&pmac_ide_macio_driver);
1402 if (error) {
1403 pci_unregister_driver(&pmac_ide_pci_driver);
1404 goto out;
1405 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001406#else
Andrew Morton9e5755b2007-03-03 17:48:54 +01001407 error = macio_register_driver(&pmac_ide_macio_driver);
1408 if (error)
1409 goto out;
1410 error = pci_register_driver(&pmac_ide_pci_driver);
1411 if (error) {
1412 macio_unregister_driver(&pmac_ide_macio_driver);
1413 goto out;
1414 }
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +11001415#endif
Andrew Morton9e5755b2007-03-03 17:48:54 +01001416out:
1417 return error;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001418}
1419
1420#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1421
1422/*
1423 * pmac_ide_build_dmatable builds the DBDMA command list
1424 * for a transfer and sets the DBDMA channel to point to it.
1425 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -05001426static int
Linus Torvalds1da177e2005-04-16 15:20:36 -07001427pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq)
1428{
Bartlomiej Zolnierkiewicz7b8797a2008-07-23 19:55:48 +02001429 ide_hwif_t *hwif = drive->hwif;
1430 pmac_ide_hwif_t *pmif =
1431 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001432 struct dbdma_cmd *table;
1433 int i, count = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001434 volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1435 struct scatterlist *sg;
1436 int wr = (rq_data_dir(rq) == WRITE);
1437
1438 /* DMA table is already aligned */
1439 table = (struct dbdma_cmd *) pmif->dma_table_cpu;
1440
1441 /* Make sure DMA controller is stopped (necessary ?) */
1442 writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma->control);
1443 while (readl(&dma->status) & RUN)
1444 udelay(1);
1445
1446 hwif->sg_nents = i = ide_build_sglist(drive, rq);
1447
1448 if (!i)
1449 return 0;
1450
1451 /* Build DBDMA commands list */
1452 sg = hwif->sg_table;
1453 while (i && sg_dma_len(sg)) {
1454 u32 cur_addr;
1455 u32 cur_len;
1456
1457 cur_addr = sg_dma_address(sg);
1458 cur_len = sg_dma_len(sg);
1459
1460 if (pmif->broken_dma && cur_addr & (L1_CACHE_BYTES - 1)) {
1461 if (pmif->broken_dma_warn == 0) {
Joe Perchesaca38a52007-11-27 21:35:55 +01001462 printk(KERN_WARNING "%s: DMA on non aligned address, "
Linus Torvalds1da177e2005-04-16 15:20:36 -07001463 "switching to PIO on Ohare chipset\n", drive->name);
1464 pmif->broken_dma_warn = 1;
1465 }
1466 goto use_pio_instead;
1467 }
1468 while (cur_len) {
1469 unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
1470
1471 if (count++ >= MAX_DCMDS) {
1472 printk(KERN_WARNING "%s: DMA table too small\n",
1473 drive->name);
1474 goto use_pio_instead;
1475 }
1476 st_le16(&table->command, wr? OUTPUT_MORE: INPUT_MORE);
1477 st_le16(&table->req_count, tc);
1478 st_le32(&table->phy_addr, cur_addr);
1479 table->cmd_dep = 0;
1480 table->xfer_status = 0;
1481 table->res_count = 0;
1482 cur_addr += tc;
1483 cur_len -= tc;
1484 ++table;
1485 }
Jens Axboe55c16a72007-07-25 08:13:56 +02001486 sg = sg_next(sg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001487 i--;
1488 }
1489
1490 /* convert the last command to an input/output last command */
1491 if (count) {
1492 st_le16(&table[-1].command, wr? OUTPUT_LAST: INPUT_LAST);
1493 /* add the stop command to the end of the list */
1494 memset(table, 0, sizeof(struct dbdma_cmd));
1495 st_le16(&table->command, DBDMA_STOP);
1496 mb();
1497 writel(hwif->dmatable_dma, &dma->cmdptr);
1498 return 1;
1499 }
1500
1501 printk(KERN_DEBUG "%s: empty DMA table?\n", drive->name);
Bartlomiej Zolnierkiewiczf6fb7862008-02-01 23:09:31 +01001502
1503use_pio_instead:
1504 ide_destroy_dmatable(drive);
1505
Linus Torvalds1da177e2005-04-16 15:20:36 -07001506 return 0; /* revert to PIO for this request */
1507}
1508
1509/* Teardown mappings after DMA has completed. */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -05001510static void
Linus Torvalds1da177e2005-04-16 15:20:36 -07001511pmac_ide_destroy_dmatable (ide_drive_t *drive)
1512{
1513 ide_hwif_t *hwif = drive->hwif;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001514
Bartlomiej Zolnierkiewiczf6fb7862008-02-01 23:09:31 +01001515 if (hwif->sg_nents) {
1516 ide_destroy_dmatable(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001517 hwif->sg_nents = 0;
1518 }
1519}
1520
1521/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001522 * Prepare a DMA transfer. We build the DMA table, adjust the timings for
1523 * a read on KeyLargo ATA/66 and mark us as waiting for DMA completion
1524 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -05001525static int
Linus Torvalds1da177e2005-04-16 15:20:36 -07001526pmac_ide_dma_setup(ide_drive_t *drive)
1527{
1528 ide_hwif_t *hwif = HWIF(drive);
Bartlomiej Zolnierkiewicz7b8797a2008-07-23 19:55:48 +02001529 pmac_ide_hwif_t *pmif =
1530 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001531 struct request *rq = HWGROUP(drive)->rq;
1532 u8 unit = (drive->select.b.unit & 0x01);
1533 u8 ata4;
1534
1535 if (pmif == NULL)
1536 return 1;
1537 ata4 = (pmif->kind == controller_kl_ata4);
1538
1539 if (!pmac_ide_build_dmatable(drive, rq)) {
1540 ide_map_sg(drive, rq);
1541 return 1;
1542 }
1543
1544 /* Apple adds 60ns to wrDataSetup on reads */
1545 if (ata4 && (pmif->timings[unit] & TR_66_UDMA_EN)) {
1546 writel(pmif->timings[unit] + (!rq_data_dir(rq) ? 0x00800000UL : 0),
1547 PMAC_IDE_REG(IDE_TIMING_CONFIG));
1548 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
1549 }
1550
1551 drive->waiting_for_dma = 1;
1552
1553 return 0;
1554}
1555
Jon Loeligeraacaf9b2005-09-17 10:36:54 -05001556static void
Linus Torvalds1da177e2005-04-16 15:20:36 -07001557pmac_ide_dma_exec_cmd(ide_drive_t *drive, u8 command)
1558{
1559 /* issue cmd to drive */
1560 ide_execute_command(drive, command, &ide_dma_intr, 2*WAIT_CMD, NULL);
1561}
1562
1563/*
1564 * Kick the DMA controller into life after the DMA command has been issued
1565 * to the drive.
1566 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -05001567static void
Linus Torvalds1da177e2005-04-16 15:20:36 -07001568pmac_ide_dma_start(ide_drive_t *drive)
1569{
Bartlomiej Zolnierkiewicz7b8797a2008-07-23 19:55:48 +02001570 ide_hwif_t *hwif = drive->hwif;
1571 pmac_ide_hwif_t *pmif =
1572 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001573 volatile struct dbdma_regs __iomem *dma;
1574
1575 dma = pmif->dma_regs;
1576
1577 writel((RUN << 16) | RUN, &dma->control);
1578 /* Make sure it gets to the controller right now */
1579 (void)readl(&dma->control);
1580}
1581
1582/*
1583 * After a DMA transfer, make sure the controller is stopped
1584 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -05001585static int
Linus Torvalds1da177e2005-04-16 15:20:36 -07001586pmac_ide_dma_end (ide_drive_t *drive)
1587{
Bartlomiej Zolnierkiewicz7b8797a2008-07-23 19:55:48 +02001588 ide_hwif_t *hwif = drive->hwif;
1589 pmac_ide_hwif_t *pmif =
1590 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001591 volatile struct dbdma_regs __iomem *dma;
1592 u32 dstat;
1593
1594 if (pmif == NULL)
1595 return 0;
1596 dma = pmif->dma_regs;
1597
1598 drive->waiting_for_dma = 0;
1599 dstat = readl(&dma->status);
1600 writel(((RUN|WAKE|DEAD) << 16), &dma->control);
1601 pmac_ide_destroy_dmatable(drive);
1602 /* verify good dma status. we don't check for ACTIVE beeing 0. We should...
1603 * in theory, but with ATAPI decices doing buffer underruns, that would
1604 * cause us to disable DMA, which isn't what we want
1605 */
1606 return (dstat & (RUN|DEAD)) != RUN;
1607}
1608
1609/*
1610 * Check out that the interrupt we got was for us. We can't always know this
1611 * for sure with those Apple interfaces (well, we could on the recent ones but
1612 * that's not implemented yet), on the other hand, we don't have shared interrupts
1613 * so it's not really a problem
1614 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -05001615static int
Linus Torvalds1da177e2005-04-16 15:20:36 -07001616pmac_ide_dma_test_irq (ide_drive_t *drive)
1617{
Bartlomiej Zolnierkiewicz7b8797a2008-07-23 19:55:48 +02001618 ide_hwif_t *hwif = drive->hwif;
1619 pmac_ide_hwif_t *pmif =
1620 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001621 volatile struct dbdma_regs __iomem *dma;
1622 unsigned long status, timeout;
1623
1624 if (pmif == NULL)
1625 return 0;
1626 dma = pmif->dma_regs;
1627
1628 /* We have to things to deal with here:
1629 *
1630 * - The dbdma won't stop if the command was started
1631 * but completed with an error without transferring all
1632 * datas. This happens when bad blocks are met during
1633 * a multi-block transfer.
1634 *
1635 * - The dbdma fifo hasn't yet finished flushing to
1636 * to system memory when the disk interrupt occurs.
1637 *
1638 */
1639
1640 /* If ACTIVE is cleared, the STOP command have passed and
1641 * transfer is complete.
1642 */
1643 status = readl(&dma->status);
1644 if (!(status & ACTIVE))
1645 return 1;
1646 if (!drive->waiting_for_dma)
1647 printk(KERN_WARNING "ide%d, ide_dma_test_irq \
1648 called while not waiting\n", HWIF(drive)->index);
1649
1650 /* If dbdma didn't execute the STOP command yet, the
1651 * active bit is still set. We consider that we aren't
1652 * sharing interrupts (which is hopefully the case with
1653 * those controllers) and so we just try to flush the
1654 * channel for pending data in the fifo
1655 */
1656 udelay(1);
1657 writel((FLUSH << 16) | FLUSH, &dma->control);
1658 timeout = 0;
1659 for (;;) {
1660 udelay(1);
1661 status = readl(&dma->status);
1662 if ((status & FLUSH) == 0)
1663 break;
1664 if (++timeout > 100) {
1665 printk(KERN_WARNING "ide%d, ide_dma_test_irq \
1666 timeout flushing channel\n", HWIF(drive)->index);
1667 break;
1668 }
1669 }
1670 return 1;
1671}
1672
Bartlomiej Zolnierkiewicz15ce9262008-01-26 20:13:03 +01001673static void pmac_ide_dma_host_set(ide_drive_t *drive, int on)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001674{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001675}
1676
Sergei Shtylyov841d2a92007-07-09 23:17:54 +02001677static void
1678pmac_ide_dma_lost_irq (ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001679{
Bartlomiej Zolnierkiewicz7b8797a2008-07-23 19:55:48 +02001680 ide_hwif_t *hwif = drive->hwif;
1681 pmac_ide_hwif_t *pmif =
1682 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001683 volatile struct dbdma_regs __iomem *dma;
1684 unsigned long status;
1685
1686 if (pmif == NULL)
Sergei Shtylyov841d2a92007-07-09 23:17:54 +02001687 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001688 dma = pmif->dma_regs;
1689
1690 status = readl(&dma->status);
1691 printk(KERN_ERR "ide-pmac lost interrupt, dma status: %lx\n", status);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001692}
1693
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001694static const struct ide_dma_ops pmac_dma_ops = {
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001695 .dma_host_set = pmac_ide_dma_host_set,
1696 .dma_setup = pmac_ide_dma_setup,
1697 .dma_exec_cmd = pmac_ide_dma_exec_cmd,
1698 .dma_start = pmac_ide_dma_start,
1699 .dma_end = pmac_ide_dma_end,
1700 .dma_test_irq = pmac_ide_dma_test_irq,
1701 .dma_timeout = ide_dma_timeout,
1702 .dma_lost_irq = pmac_ide_dma_lost_irq,
1703};
1704
Linus Torvalds1da177e2005-04-16 15:20:36 -07001705/*
1706 * Allocate the data structures needed for using DMA with an interface
1707 * and fill the proper list of functions pointers
1708 */
Bartlomiej Zolnierkiewicz0d071922008-04-26 22:25:22 +02001709static int __devinit pmac_ide_init_dma(ide_hwif_t *hwif,
1710 const struct ide_port_info *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001711{
Bartlomiej Zolnierkiewicz7b8797a2008-07-23 19:55:48 +02001712 pmac_ide_hwif_t *pmif =
1713 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +01001714 struct pci_dev *dev = to_pci_dev(hwif->dev);
1715
Linus Torvalds1da177e2005-04-16 15:20:36 -07001716 /* We won't need pci_dev if we switch to generic consistent
1717 * DMA routines ...
1718 */
Bartlomiej Zolnierkiewicz0d071922008-04-26 22:25:22 +02001719 if (dev == NULL || pmif->dma_regs == 0)
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +01001720 return -ENODEV;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001721 /*
1722 * Allocate space for the DBDMA commands.
1723 * The +2 is +1 for the stop command and +1 to allow for
1724 * aligning the start address to a multiple of 16 bytes.
1725 */
1726 pmif->dma_table_cpu = (struct dbdma_cmd*)pci_alloc_consistent(
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +01001727 dev,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001728 (MAX_DCMDS + 2) * sizeof(struct dbdma_cmd),
1729 &hwif->dmatable_dma);
1730 if (pmif->dma_table_cpu == NULL) {
1731 printk(KERN_ERR "%s: unable to allocate DMA command list\n",
1732 hwif->name);
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +01001733 return -ENOMEM;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001734 }
1735
Bartlomiej Zolnierkiewicz4f52a322008-01-26 20:13:08 +01001736 hwif->sg_max_nents = MAX_DCMDS;
1737
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +01001738 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001739}
Bartlomiej Zolnierkiewicz0d071922008-04-26 22:25:22 +02001740#else
1741static int __devinit pmac_ide_init_dma(ide_hwif_t *hwif,
1742 const struct ide_port_info *d)
1743{
1744 return -EOPNOTSUPP;
1745}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001746#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
Bartlomiej Zolnierkiewiczade2daf2008-01-26 20:13:07 +01001747
1748module_init(pmac_ide_probe);
Adrian Bunkde9facb2008-04-02 21:22:03 +02001749
1750MODULE_LICENSE("GPL");