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gerrit-public.fairphone.software / kernel / msm / b3ebd1d862d6c23caa58e40d341eefc426f835e1 / . / include / asm-powerpc / cputable.h
blob: 12707ab9dc98db6bcc6bf75556dd925e9a56818e [file] [log] [blame]
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]1#ifndef __ASM_POWERPC_CPUTABLE_H
2#define __ASM_POWERPC_CPUTABLE_H
3
David Gibson3ddfbcf2005-11-10 12:56:55 +1100[diff] [blame]4#include <asm/asm-compat.h>
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]5
6#define PPC_FEATURE_32 0x80000000
7#define PPC_FEATURE_64 0x40000000
8#define PPC_FEATURE_601_INSTR 0x20000000
9#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
10#define PPC_FEATURE_HAS_FPU 0x08000000
11#define PPC_FEATURE_HAS_MMU 0x04000000
12#define PPC_FEATURE_HAS_4xxMAC 0x02000000
13#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
14#define PPC_FEATURE_HAS_SPE 0x00800000
15#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
16#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
Paul Mackerras98599012005-10-22 16:51:34 +1000[diff] [blame]17#define PPC_FEATURE_NO_TB 0x00100000
Paul Mackerrasa7ddc5e2005-11-10 14:29:18 +1100[diff] [blame]18#define PPC_FEATURE_POWER4 0x00080000
19#define PPC_FEATURE_POWER5 0x00040000
20#define PPC_FEATURE_POWER5_PLUS 0x00020000
21#define PPC_FEATURE_CELL 0x00010000
Paul Mackerras80f15dc2006-01-14 10:11:39 +1100[diff] [blame]22#define PPC_FEATURE_BOOKE 0x00008000
Benjamin Herrenschmidtaa5cb022006-03-01 15:07:07 +1100[diff] [blame]23#define PPC_FEATURE_SMT 0x00004000
24#define PPC_FEATURE_ICACHE_SNOOP 0x00002000
Anton Blanchard03054d52006-04-29 09:51:06 +1000[diff] [blame]25#define PPC_FEATURE_ARCH_2_05 0x00001000
Olof Johanssonb3ebd1d2006-09-06 14:35:57 -0500[diff] [blame^]26#define PPC_FEATURE_PA6T 0x00000800
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]27
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]28#define PPC_FEATURE_TRUE_LE 0x00000002
29#define PPC_FEATURE_PPC_LE 0x00000001
30
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]31#ifdef __KERNEL__
32#ifndef __ASSEMBLY__
33
34/* This structure can grow, it's real size is used by head.S code
35 * via the mkdefs mechanism.
36 */
37struct cpu_spec;
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]38
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]39typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
Olof Johanssonf39b7a52006-08-11 00:07:08 -0500[diff] [blame]40typedef void (*cpu_restore_t)(void);
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]41
Anton Blanchard32a33992006-01-09 15:41:31 +1100[diff] [blame]42enum powerpc_oprofile_type {
Andy Whitcroft7a45fb12006-01-13 12:35:49 +0000[diff] [blame]43 PPC_OPROFILE_INVALID = 0,
44 PPC_OPROFILE_RS64 = 1,
45 PPC_OPROFILE_POWER4 = 2,
46 PPC_OPROFILE_G4 = 3,
47 PPC_OPROFILE_BOOKE = 4,
Anton Blanchard32a33992006-01-09 15:41:31 +1100[diff] [blame]48};
49
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]50struct cpu_spec {
51 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
52 unsigned int pvr_mask;
53 unsigned int pvr_value;
54
55 char *cpu_name;
56 unsigned long cpu_features; /* Kernel features */
57 unsigned int cpu_user_features; /* Userland features */
58
59 /* cache line sizes */
60 unsigned int icache_bsize;
61 unsigned int dcache_bsize;
62
63 /* number of performance monitor counters */
64 unsigned int num_pmcs;
65
66 /* this is called to initialize various CPU bits like L1 cache,
67 * BHT, SPD, etc... from head.S before branching to identify_machine
68 */
69 cpu_setup_t cpu_setup;
Olof Johanssonf39b7a52006-08-11 00:07:08 -0500[diff] [blame]70 /* Used to restore cpu setup on secondary processors and at resume */
71 cpu_restore_t cpu_restore;
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]72
73 /* Used by oprofile userspace to select the right counters */
74 char *oprofile_cpu_type;
75
76 /* Processor specific oprofile operations */
Anton Blanchard32a33992006-01-09 15:41:31 +1100[diff] [blame]77 enum powerpc_oprofile_type oprofile_type;
Paul Mackerras80f15dc2006-01-14 10:11:39 +1100[diff] [blame]78
Michael Neulinge78dbc82006-06-08 14:42:34 +1000[diff] [blame]79 /* Bit locations inside the mmcra change */
80 unsigned long oprofile_mmcra_sihv;
81 unsigned long oprofile_mmcra_sipr;
82
83 /* Bits to clear during an oprofile exception */
84 unsigned long oprofile_mmcra_clear;
85
Paul Mackerras80f15dc2006-01-14 10:11:39 +1100[diff] [blame]86 /* Name of processor class, for the ELF AT_PLATFORM entry */
87 char *platform;
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]88};
89
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]90extern struct cpu_spec *cur_cpu_spec;
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]91
Paul Mackerras9b6b5632005-10-06 12:06:20 +1000[diff] [blame]92extern void identify_cpu(unsigned long offset, unsigned long cpu);
93extern void do_cpu_ftr_fixups(unsigned long offset);
94
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]95#endif /* __ASSEMBLY__ */
96
97/* CPU kernel features */
98
99/* Retain the 32b definitions all use bottom half of word */
100#define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001)
101#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
102#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
103#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
104#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
105#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
106#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
107#define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080)
108#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
109#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
110#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
111#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
112#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
113#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
114#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
115#define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
116#define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000)
117#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
118#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
119#define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000)
Michael Ellerman3d159102006-03-21 20:45:58 +1100[diff] [blame]120#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]121#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000)
122#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]123
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000[diff] [blame]124/*
125 * Add the 64-bit processor unique features in the top half of the word;
126 * on 32-bit, make the names available but defined to be 0.
127 */
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]128#ifdef __powerpc64__
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000[diff] [blame]129#define LONG_ASM_CONST(x) ASM_CONST(x)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]130#else
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000[diff] [blame]131#define LONG_ASM_CONST(x) 0
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]132#endif
133
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000[diff] [blame]134#define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000)
135#define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000)
136#define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000)
137#define CPU_FTR_NOEXECUTE LONG_ASM_CONST(0x0000000800000000)
138#define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000)
139#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
140#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
141#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
142#define CPU_FTR_COHERENT_ICACHE LONG_ASM_CONST(0x0000020000000000)
143#define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000)
144#define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000)
145#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
146#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
147
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]148#ifndef __ASSEMBLY__
149
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]150#define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
151 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
Olof Johansson00243002006-09-06 14:35:19 -0500[diff] [blame]152 CPU_FTR_NODSISRALIGN)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]153
154/* iSeries doesn't support large pages */
155#ifdef CONFIG_PPC_ISERIES
156#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE)
157#else
158#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE | CPU_FTR_16M_PAGE)
159#endif /* CONFIG_PPC_ISERIES */
160
161/* We only set the altivec features if the kernel was compiled with altivec
162 * support
163 */
164#ifdef CONFIG_ALTIVEC
165#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
166#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
167#else
168#define CPU_FTR_ALTIVEC_COMP 0
169#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
170#endif
171
172/* We need to mark all pages as being coherent if we're SMP or we
Kumar Gala1775dbb2006-02-22 09:46:02 -0600[diff] [blame]173 * have a 74[45]x and an MPC107 host bridge. Also 83xx requires
174 * it for PCI "streaming/prefetch" to work properly.
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]175 */
Kumar Gala1775dbb2006-02-22 09:46:02 -0600[diff] [blame]176#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
177 || defined(CONFIG_PPC_83xx)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]178#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
179#else
180#define CPU_FTR_COMMON 0
181#endif
182
183/* The powersave features NAP & DOZE seems to confuse BDI when
184 debugging. So if a BDI is used, disable theses
185 */
186#ifndef CONFIG_BDI_SWITCH
187#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
188#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
189#else
190#define CPU_FTR_MAYBE_CAN_DOZE 0
191#define CPU_FTR_MAYBE_CAN_NAP 0
192#endif
193
194#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
195 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
196 !defined(CONFIG_BOOKE))
197
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]198#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE)
199#define CPU_FTRS_603 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
200 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]201 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]202#define CPU_FTRS_604 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]203 CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE | \
204 CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]205#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
206 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]207 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]208#define CPU_FTRS_740 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
209 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]210 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
211 CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]212#define CPU_FTRS_750 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
213 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]214 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
215 CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]216#define CPU_FTRS_750FX1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
217 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
218 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]219 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]220#define CPU_FTRS_750FX2 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
221 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
222 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]223 CPU_FTR_NO_DPM | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]224#define CPU_FTRS_750FX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
225 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
226 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]227 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]228#define CPU_FTRS_750GX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
229 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU | \
230 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]231 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]232#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
233 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
234 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]235 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]236#define CPU_FTRS_7400 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
237 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
238 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]239 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]240#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
241 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
242 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]243 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]244#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
245 CPU_FTR_USE_TB | \
246 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
247 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
248 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]249 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]250#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
251 CPU_FTR_USE_TB | \
252 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
253 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]254 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]255#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
256 CPU_FTR_USE_TB | \
257 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
258 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]259 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]260#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
261 CPU_FTR_USE_TB | \
262 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
263 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
264 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]265 CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]266#define CPU_FTRS_7455 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
267 CPU_FTR_USE_TB | \
268 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
269 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
270 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]271 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]272#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
273 CPU_FTR_USE_TB | \
274 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
275 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
276 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]277 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]278#define CPU_FTRS_7447 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
279 CPU_FTR_USE_TB | \
280 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
281 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
282 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]283 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]284#define CPU_FTRS_7447A (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
285 CPU_FTR_USE_TB | \
286 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
287 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
288 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]289 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]290#define CPU_FTRS_82XX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
291 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
292#define CPU_FTRS_G2_LE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
293 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS)
294#define CPU_FTRS_E300 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
295 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
296 CPU_FTR_COMMON)
297#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
298 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]299#define CPU_FTRS_8XX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB)
300#define CPU_FTRS_40X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
301 CPU_FTR_NODSISRALIGN)
302#define CPU_FTRS_44X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
303 CPU_FTR_NODSISRALIGN)
304#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
305#define CPU_FTRS_E500 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
306 CPU_FTR_NODSISRALIGN)
307#define CPU_FTRS_E500_2 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
308 CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN)
309#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]310#ifdef __powerpc64__
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]311#define CPU_FTRS_POWER3 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]312 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]313#define CPU_FTRS_RS64 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
314 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \
315 CPU_FTR_MMCRA | CPU_FTR_CTRL)
316#define CPU_FTRS_POWER4 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
Olof Johansson00243002006-09-06 14:35:19 -0500[diff] [blame]317 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
318 CPU_FTR_MMCRA)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]319#define CPU_FTRS_PPC970 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
Olof Johansson00243002006-09-06 14:35:19 -0500[diff] [blame]320 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]321 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA)
322#define CPU_FTRS_POWER5 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
Olof Johansson00243002006-09-06 14:35:19 -0500[diff] [blame]323 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]324 CPU_FTR_MMCRA | CPU_FTR_SMT | \
325 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
Michael Neulinge78dbc82006-06-08 14:42:34 +1000[diff] [blame]326 CPU_FTR_PURR)
Anton Blanchard03054d52006-04-29 09:51:06 +1000[diff] [blame]327#define CPU_FTRS_POWER6 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
Olof Johansson00243002006-09-06 14:35:19 -0500[diff] [blame]328 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
Anton Blanchard03054d52006-04-29 09:51:06 +1000[diff] [blame]329 CPU_FTR_MMCRA | CPU_FTR_SMT | \
330 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]331 CPU_FTR_PURR | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_REAL_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]332#define CPU_FTRS_CELL (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
Olof Johansson00243002006-09-06 14:35:19 -0500[diff] [blame]333 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]334 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
Olof Johansson00243002006-09-06 14:35:19 -0500[diff] [blame]335 CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE)
Olof Johanssonb3ebd1d2006-09-06 14:35:57 -0500[diff] [blame^]336#define CPU_FTRS_PA6T (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
337 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
338 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
339 CPU_FTR_PURR | CPU_FTR_REAL_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]340#define CPU_FTRS_COMPATIBLE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
341 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]342#endif
343
Anton Blanchard2406f602005-12-13 07:45:33 +1100[diff] [blame]344#ifdef __powerpc64__
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]345#define CPU_FTRS_POSSIBLE \
346 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
Anton Blanchard03054d52006-04-29 09:51:06 +1000[diff] [blame]347 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
Olof Johanssonb3ebd1d2006-09-06 14:35:57 -0500[diff] [blame^]348 CPU_FTRS_CELL | CPU_FTRS_PA6T)
Anton Blanchard2406f602005-12-13 07:45:33 +1100[diff] [blame]349#else
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]350enum {
351 CPU_FTRS_POSSIBLE =
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]352#if CLASSIC_PPC
353 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
354 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
355 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
356 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
357 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
358 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
359 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
360 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_CLASSIC32 |
361#else
362 CPU_FTRS_GENERIC_32 |
363#endif
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]364#ifdef CONFIG_8xx
365 CPU_FTRS_8XX |
366#endif
367#ifdef CONFIG_40x
368 CPU_FTRS_40X |
369#endif
370#ifdef CONFIG_44x
371 CPU_FTRS_44X |
372#endif
373#ifdef CONFIG_E200
374 CPU_FTRS_E200 |
375#endif
376#ifdef CONFIG_E500
377 CPU_FTRS_E500 | CPU_FTRS_E500_2 |
378#endif
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]379 0,
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]380};
381#endif /* __powerpc64__ */
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]382
Anton Blanchard2406f602005-12-13 07:45:33 +1100[diff] [blame]383#ifdef __powerpc64__
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]384#define CPU_FTRS_ALWAYS \
385 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
Anton Blanchard03054d52006-04-29 09:51:06 +1000[diff] [blame]386 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \
Olof Johanssonb3ebd1d2006-09-06 14:35:57 -0500[diff] [blame^]387 CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
Anton Blanchard2406f602005-12-13 07:45:33 +1100[diff] [blame]388#else
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]389enum {
390 CPU_FTRS_ALWAYS =
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]391#if CLASSIC_PPC
392 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
393 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
394 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
395 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
396 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
397 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
398 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
399 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_CLASSIC32 &
400#else
401 CPU_FTRS_GENERIC_32 &
402#endif
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]403#ifdef CONFIG_8xx
404 CPU_FTRS_8XX &
405#endif
406#ifdef CONFIG_40x
407 CPU_FTRS_40X &
408#endif
409#ifdef CONFIG_44x
410 CPU_FTRS_44X &
411#endif
412#ifdef CONFIG_E200
413 CPU_FTRS_E200 &
414#endif
415#ifdef CONFIG_E500
416 CPU_FTRS_E500 & CPU_FTRS_E500_2 &
417#endif
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]418 CPU_FTRS_POSSIBLE,
419};
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]420#endif /* __powerpc64__ */
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]421
422static inline int cpu_has_feature(unsigned long feature)
423{
424 return (CPU_FTRS_ALWAYS & feature) ||
425 (CPU_FTRS_POSSIBLE
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]426 & cur_cpu_spec->cpu_features
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]427 & feature);
428}
429
430#endif /* !__ASSEMBLY__ */
431
432#ifdef __ASSEMBLY__
433
434#define BEGIN_FTR_SECTION 98:
435
436#ifndef __powerpc64__
437#define END_FTR_SECTION(msk, val) \
43899: \
439 .section __ftr_fixup,"a"; \
440 .align 2; \
441 .long msk; \
442 .long val; \
443 .long 98b; \
444 .long 99b; \
445 .previous
446#else /* __powerpc64__ */
447#define END_FTR_SECTION(msk, val) \
44899: \
449 .section __ftr_fixup,"a"; \
450 .align 3; \
451 .llong msk; \
452 .llong val; \
453 .llong 98b; \
454 .llong 99b; \
455 .previous
456#endif /* __powerpc64__ */
457
458#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
459#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
460#endif /* __ASSEMBLY__ */
461
462#endif /* __KERNEL__ */
463#endif /* __ASM_POWERPC_CPUTABLE_H */