Vitaly Wool | 78818e4 | 2006-05-16 11:54:37 +0100 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/mach-pnx4008/irq.c |
| 3 | * |
| 4 | * PNX4008 IRQ controller driver |
| 5 | * |
| 6 | * Author: Dmitry Chigirev <source@mvista.com> |
| 7 | * |
| 8 | * Based on reference code received from Philips: |
| 9 | * Copyright (C) 2003 Philips Semiconductors |
| 10 | * |
| 11 | * 2005 (c) MontaVista Software, Inc. This file is licensed under |
| 12 | * the terms of the GNU General Public License version 2. This program |
| 13 | * is licensed "as is" without any warranty of any kind, whether express |
| 14 | * or implied. |
| 15 | */ |
| 16 | |
| 17 | #include <linux/kernel.h> |
| 18 | #include <linux/types.h> |
| 19 | #include <linux/mm.h> |
| 20 | #include <linux/interrupt.h> |
| 21 | #include <linux/list.h> |
| 22 | #include <linux/init.h> |
| 23 | #include <linux/ioport.h> |
| 24 | #include <linux/device.h> |
Vitaly Wool | 5904a7f | 2006-07-05 14:47:20 +0100 | [diff] [blame] | 25 | #include <linux/irq.h> |
Russell King | fced80c | 2008-09-06 12:10:45 +0100 | [diff] [blame] | 26 | #include <linux/io.h> |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 27 | #include <mach/hardware.h> |
Vitaly Wool | 78818e4 | 2006-05-16 11:54:37 +0100 | [diff] [blame] | 28 | #include <asm/setup.h> |
Vitaly Wool | 78818e4 | 2006-05-16 11:54:37 +0100 | [diff] [blame] | 29 | #include <asm/pgtable.h> |
| 30 | #include <asm/page.h> |
| 31 | #include <asm/system.h> |
| 32 | #include <asm/mach/arch.h> |
| 33 | #include <asm/mach/irq.h> |
| 34 | #include <asm/mach/map.h> |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 35 | #include <mach/irq.h> |
Vitaly Wool | 78818e4 | 2006-05-16 11:54:37 +0100 | [diff] [blame] | 36 | |
| 37 | static u8 pnx4008_irq_type[NR_IRQS] = PNX4008_IRQ_TYPES; |
| 38 | |
Lennert Buytenhek | 406b005 | 2010-11-29 10:40:16 +0100 | [diff] [blame] | 39 | static void pnx4008_mask_irq(struct irq_data *d) |
Vitaly Wool | 78818e4 | 2006-05-16 11:54:37 +0100 | [diff] [blame] | 40 | { |
Lennert Buytenhek | 406b005 | 2010-11-29 10:40:16 +0100 | [diff] [blame] | 41 | __raw_writel(__raw_readl(INTC_ER(d->irq)) & ~INTC_BIT(d->irq), INTC_ER(d->irq)); /* mask interrupt */ |
Vitaly Wool | 78818e4 | 2006-05-16 11:54:37 +0100 | [diff] [blame] | 42 | } |
| 43 | |
Lennert Buytenhek | 406b005 | 2010-11-29 10:40:16 +0100 | [diff] [blame] | 44 | static void pnx4008_unmask_irq(struct irq_data *d) |
Vitaly Wool | 78818e4 | 2006-05-16 11:54:37 +0100 | [diff] [blame] | 45 | { |
Lennert Buytenhek | 406b005 | 2010-11-29 10:40:16 +0100 | [diff] [blame] | 46 | __raw_writel(__raw_readl(INTC_ER(d->irq)) | INTC_BIT(d->irq), INTC_ER(d->irq)); /* unmask interrupt */ |
Vitaly Wool | 78818e4 | 2006-05-16 11:54:37 +0100 | [diff] [blame] | 47 | } |
| 48 | |
Lennert Buytenhek | 406b005 | 2010-11-29 10:40:16 +0100 | [diff] [blame] | 49 | static void pnx4008_mask_ack_irq(struct irq_data *d) |
Vitaly Wool | 78818e4 | 2006-05-16 11:54:37 +0100 | [diff] [blame] | 50 | { |
Lennert Buytenhek | 406b005 | 2010-11-29 10:40:16 +0100 | [diff] [blame] | 51 | __raw_writel(__raw_readl(INTC_ER(d->irq)) & ~INTC_BIT(d->irq), INTC_ER(d->irq)); /* mask interrupt */ |
| 52 | __raw_writel(INTC_BIT(d->irq), INTC_SR(d->irq)); /* clear interrupt status */ |
Vitaly Wool | 78818e4 | 2006-05-16 11:54:37 +0100 | [diff] [blame] | 53 | } |
| 54 | |
Lennert Buytenhek | 406b005 | 2010-11-29 10:40:16 +0100 | [diff] [blame] | 55 | static int pnx4008_set_irq_type(struct irq_data *d, unsigned int type) |
Vitaly Wool | 78818e4 | 2006-05-16 11:54:37 +0100 | [diff] [blame] | 56 | { |
| 57 | switch (type) { |
Dmitry Baryshkov | 6cab486 | 2008-07-27 04:23:31 +0100 | [diff] [blame] | 58 | case IRQ_TYPE_EDGE_RISING: |
Lennert Buytenhek | 406b005 | 2010-11-29 10:40:16 +0100 | [diff] [blame] | 59 | __raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive */ |
| 60 | __raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq)); /*rising edge */ |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 61 | irq_set_handler(d->irq, handle_edge_irq); |
Vitaly Wool | 78818e4 | 2006-05-16 11:54:37 +0100 | [diff] [blame] | 62 | break; |
Dmitry Baryshkov | 6cab486 | 2008-07-27 04:23:31 +0100 | [diff] [blame] | 63 | case IRQ_TYPE_EDGE_FALLING: |
Lennert Buytenhek | 406b005 | 2010-11-29 10:40:16 +0100 | [diff] [blame] | 64 | __raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive */ |
| 65 | __raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*falling edge */ |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 66 | irq_set_handler(d->irq, handle_edge_irq); |
Vitaly Wool | 78818e4 | 2006-05-16 11:54:37 +0100 | [diff] [blame] | 67 | break; |
Dmitry Baryshkov | 6cab486 | 2008-07-27 04:23:31 +0100 | [diff] [blame] | 68 | case IRQ_TYPE_LEVEL_LOW: |
Lennert Buytenhek | 406b005 | 2010-11-29 10:40:16 +0100 | [diff] [blame] | 69 | __raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq)); /*level sensitive */ |
| 70 | __raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*low level */ |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 71 | irq_set_handler(d->irq, handle_level_irq); |
Vitaly Wool | 78818e4 | 2006-05-16 11:54:37 +0100 | [diff] [blame] | 72 | break; |
Dmitry Baryshkov | 6cab486 | 2008-07-27 04:23:31 +0100 | [diff] [blame] | 73 | case IRQ_TYPE_LEVEL_HIGH: |
Lennert Buytenhek | 406b005 | 2010-11-29 10:40:16 +0100 | [diff] [blame] | 74 | __raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq)); /*level sensitive */ |
| 75 | __raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq)); /* high level */ |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 76 | irq_set_handler(d->irq, handle_level_irq); |
Vitaly Wool | 78818e4 | 2006-05-16 11:54:37 +0100 | [diff] [blame] | 77 | break; |
| 78 | |
Dmitry Baryshkov | 6cab486 | 2008-07-27 04:23:31 +0100 | [diff] [blame] | 79 | /* IRQ_TYPE_EDGE_BOTH is not supported */ |
Vitaly Wool | 78818e4 | 2006-05-16 11:54:37 +0100 | [diff] [blame] | 80 | default: |
| 81 | printk(KERN_ERR "PNX4008 IRQ: Unsupported irq type %d\n", type); |
| 82 | return -1; |
| 83 | } |
| 84 | return 0; |
| 85 | } |
| 86 | |
Russell King | 10dd5ce | 2006-11-23 11:41:32 +0000 | [diff] [blame] | 87 | static struct irq_chip pnx4008_irq_chip = { |
Lennert Buytenhek | 406b005 | 2010-11-29 10:40:16 +0100 | [diff] [blame] | 88 | .irq_ack = pnx4008_mask_ack_irq, |
| 89 | .irq_mask = pnx4008_mask_irq, |
| 90 | .irq_unmask = pnx4008_unmask_irq, |
| 91 | .irq_set_type = pnx4008_set_irq_type, |
Vitaly Wool | 78818e4 | 2006-05-16 11:54:37 +0100 | [diff] [blame] | 92 | }; |
| 93 | |
| 94 | void __init pnx4008_init_irq(void) |
| 95 | { |
| 96 | unsigned int i; |
| 97 | |
Vitaly Wool | 5904a7f | 2006-07-05 14:47:20 +0100 | [diff] [blame] | 98 | /* configure IRQ's */ |
| 99 | for (i = 0; i < NR_IRQS; i++) { |
| 100 | set_irq_flags(i, IRQF_VALID); |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 101 | irq_set_chip(i, &pnx4008_irq_chip); |
Lennert Buytenhek | 406b005 | 2010-11-29 10:40:16 +0100 | [diff] [blame] | 102 | pnx4008_set_irq_type(irq_get_irq_data(i), pnx4008_irq_type[i]); |
Vitaly Wool | 5904a7f | 2006-07-05 14:47:20 +0100 | [diff] [blame] | 103 | } |
| 104 | |
| 105 | /* configure and enable IRQ 0,1,30,31 (cascade interrupts) */ |
Lennert Buytenhek | 406b005 | 2010-11-29 10:40:16 +0100 | [diff] [blame] | 106 | pnx4008_set_irq_type(irq_get_irq_data(SUB1_IRQ_N), |
| 107 | pnx4008_irq_type[SUB1_IRQ_N]); |
| 108 | pnx4008_set_irq_type(irq_get_irq_data(SUB2_IRQ_N), |
| 109 | pnx4008_irq_type[SUB2_IRQ_N]); |
| 110 | pnx4008_set_irq_type(irq_get_irq_data(SUB1_FIQ_N), |
| 111 | pnx4008_irq_type[SUB1_FIQ_N]); |
| 112 | pnx4008_set_irq_type(irq_get_irq_data(SUB2_FIQ_N), |
| 113 | pnx4008_irq_type[SUB2_FIQ_N]); |
Vitaly Wool | 78818e4 | 2006-05-16 11:54:37 +0100 | [diff] [blame] | 114 | |
Vitaly Wool | 5904a7f | 2006-07-05 14:47:20 +0100 | [diff] [blame] | 115 | /* mask all others */ |
Vitaly Wool | 78818e4 | 2006-05-16 11:54:37 +0100 | [diff] [blame] | 116 | __raw_writel((1 << SUB2_FIQ_N) | (1 << SUB1_FIQ_N) | |
| 117 | (1 << SUB2_IRQ_N) | (1 << SUB1_IRQ_N), |
| 118 | INTC_ER(MAIN_BASE_INT)); |
| 119 | __raw_writel(0, INTC_ER(SIC1_BASE_INT)); |
| 120 | __raw_writel(0, INTC_ER(SIC2_BASE_INT)); |
Vitaly Wool | 78818e4 | 2006-05-16 11:54:37 +0100 | [diff] [blame] | 121 | } |
| 122 | |