Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 1 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3 | * Due to massive hardware bugs, UltraDMA is only supported |
| 4 | * on the 646U2 and not on the 646U. |
| 5 | * |
| 6 | * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) |
| 7 | * Copyright (C) 1998 David S. Miller (davem@redhat.com) |
| 8 | * |
| 9 | * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org> |
Sergei Shtylyov | 30e5ffc | 2009-06-15 18:52:56 +0200 | [diff] [blame] | 10 | * Copyright (C) 2007,2009 MontaVista Software, Inc. <source@mvista.com> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 11 | */ |
| 12 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13 | #include <linux/module.h> |
| 14 | #include <linux/types.h> |
| 15 | #include <linux/pci.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 16 | #include <linux/ide.h> |
| 17 | #include <linux/init.h> |
| 18 | |
| 19 | #include <asm/io.h> |
| 20 | |
Bartlomiej Zolnierkiewicz | ced3ec8 | 2008-07-24 22:53:32 +0200 | [diff] [blame] | 21 | #define DRV_NAME "cmd64x" |
| 22 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 23 | /* |
| 24 | * CMD64x specific registers definition. |
| 25 | */ |
| 26 | #define CFR 0x50 |
Sergei Shtylyov | e51e252 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 27 | #define CFR_INTR_CH0 0x04 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 28 | |
| 29 | #define CMDTIM 0x52 |
| 30 | #define ARTTIM0 0x53 |
| 31 | #define DRWTIM0 0x54 |
| 32 | #define ARTTIM1 0x55 |
| 33 | #define DRWTIM1 0x56 |
| 34 | #define ARTTIM23 0x57 |
| 35 | #define ARTTIM23_DIS_RA2 0x04 |
| 36 | #define ARTTIM23_DIS_RA3 0x08 |
| 37 | #define ARTTIM23_INTR_CH1 0x10 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 38 | #define DRWTIM2 0x58 |
| 39 | #define BRST 0x59 |
| 40 | #define DRWTIM3 0x5b |
| 41 | |
| 42 | #define BMIDECR0 0x70 |
| 43 | #define MRDMODE 0x71 |
| 44 | #define MRDMODE_INTR_CH0 0x04 |
| 45 | #define MRDMODE_INTR_CH1 0x08 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 46 | #define UDIDETCR0 0x73 |
| 47 | #define DTPR0 0x74 |
| 48 | #define BMIDECR1 0x78 |
| 49 | #define BMIDECSR 0x79 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 50 | #define UDIDETCR1 0x7B |
| 51 | #define DTPR1 0x7C |
| 52 | |
Sergei Shtylyov | e277a1a | 2007-03-17 21:57:24 +0100 | [diff] [blame] | 53 | static u8 quantize_timing(int timing, int quant) |
| 54 | { |
| 55 | return (timing + quant - 1) / quant; |
| 56 | } |
| 57 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 58 | /* |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 59 | * This routine calculates active/recovery counts and then writes them into |
| 60 | * the chipset registers. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 61 | */ |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 62 | static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_time) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 63 | { |
Bartlomiej Zolnierkiewicz | ebae41a | 2008-04-27 15:38:29 +0200 | [diff] [blame] | 64 | struct pci_dev *dev = to_pci_dev(drive->hwif->dev); |
Bartlomiej Zolnierkiewicz | 30e5ee4 | 2008-07-15 21:21:46 +0200 | [diff] [blame] | 65 | int clock_time = 1000 / (ide_pci_clk ? ide_pci_clk : 33); |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 66 | u8 cycle_count, active_count, recovery_count, drwtim; |
| 67 | static const u8 recovery_values[] = |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 68 | {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0}; |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 69 | static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3}; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 70 | |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 71 | cycle_count = quantize_timing( cycle_time, clock_time); |
| 72 | active_count = quantize_timing(active_time, clock_time); |
| 73 | recovery_count = cycle_count - active_count; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 74 | |
| 75 | /* |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 76 | * In case we've got too long recovery phase, try to lengthen |
| 77 | * the active phase |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 78 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 79 | if (recovery_count > 16) { |
| 80 | active_count += recovery_count - 16; |
| 81 | recovery_count = 16; |
| 82 | } |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 83 | if (active_count > 16) /* shouldn't actually happen... */ |
| 84 | active_count = 16; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 85 | |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 86 | /* |
| 87 | * Convert values to internal chipset representation |
| 88 | */ |
| 89 | recovery_count = recovery_values[recovery_count]; |
| 90 | active_count &= 0x0f; |
| 91 | |
| 92 | /* Program the active/recovery counts into the DRWTIM register */ |
| 93 | drwtim = (active_count << 4) | recovery_count; |
| 94 | (void) pci_write_config_byte(dev, drwtim_regs[drive->dn], drwtim); |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 95 | } |
| 96 | |
| 97 | /* |
Bartlomiej Zolnierkiewicz | 26bcb87 | 2007-10-11 23:54:00 +0200 | [diff] [blame] | 98 | * This routine writes into the chipset registers |
| 99 | * PIO setup/active/recovery timings. |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 100 | */ |
Bartlomiej Zolnierkiewicz | 26bcb87 | 2007-10-11 23:54:00 +0200 | [diff] [blame] | 101 | static void cmd64x_tune_pio(ide_drive_t *drive, const u8 pio) |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 102 | { |
Bartlomiej Zolnierkiewicz | 898ec22 | 2009-01-06 17:20:52 +0100 | [diff] [blame] | 103 | ide_hwif_t *hwif = drive->hwif; |
Bartlomiej Zolnierkiewicz | 3650165 | 2008-02-01 23:09:31 +0100 | [diff] [blame] | 104 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
Bartlomiej Zolnierkiewicz | 86a0e12 | 2008-07-16 20:33:38 +0200 | [diff] [blame] | 105 | struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio); |
Joao Ramos | 5bfb151 | 2009-06-15 22:13:44 +0200 | [diff] [blame] | 106 | unsigned long setup_count; |
Bartlomiej Zolnierkiewicz | 7dd0008 | 2007-07-20 01:11:56 +0200 | [diff] [blame] | 107 | unsigned int cycle_time; |
Joao Ramos | 5bfb151 | 2009-06-15 22:13:44 +0200 | [diff] [blame] | 108 | u8 arttim = 0; |
Bartlomiej Zolnierkiewicz | 26bcb87 | 2007-10-11 23:54:00 +0200 | [diff] [blame] | 109 | |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 110 | static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0}; |
| 111 | static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23}; |
Bartlomiej Zolnierkiewicz | 7dd0008 | 2007-07-20 01:11:56 +0200 | [diff] [blame] | 112 | |
Bartlomiej Zolnierkiewicz | 26bcb87 | 2007-10-11 23:54:00 +0200 | [diff] [blame] | 113 | cycle_time = ide_pio_cycle_time(drive, pio); |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 114 | |
Bartlomiej Zolnierkiewicz | 86a0e12 | 2008-07-16 20:33:38 +0200 | [diff] [blame] | 115 | program_cycle_times(drive, cycle_time, t->active); |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 116 | |
Bartlomiej Zolnierkiewicz | 86a0e12 | 2008-07-16 20:33:38 +0200 | [diff] [blame] | 117 | setup_count = quantize_timing(t->setup, |
Bartlomiej Zolnierkiewicz | 30e5ee4 | 2008-07-15 21:21:46 +0200 | [diff] [blame] | 118 | 1000 / (ide_pci_clk ? ide_pci_clk : 33)); |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 119 | |
| 120 | /* |
| 121 | * The primary channel has individual address setup timing registers |
| 122 | * for each drive and the hardware selects the slowest timing itself. |
| 123 | * The secondary channel has one common register and we have to select |
| 124 | * the slowest address setup timing ourselves. |
| 125 | */ |
| 126 | if (hwif->channel) { |
Bartlomiej Zolnierkiewicz | 5d44a15 | 2009-01-06 17:20:55 +0100 | [diff] [blame] | 127 | ide_drive_t *pair = ide_get_pair_dev(drive); |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 128 | |
Joao Ramos | 5bfb151 | 2009-06-15 22:13:44 +0200 | [diff] [blame] | 129 | ide_set_drivedata(drive, (void *)setup_count); |
Bartlomiej Zolnierkiewicz | 5d44a15 | 2009-01-06 17:20:55 +0100 | [diff] [blame] | 130 | |
| 131 | if (pair) |
Joao Ramos | 5bfb151 | 2009-06-15 22:13:44 +0200 | [diff] [blame] | 132 | setup_count = max_t(u8, setup_count, |
| 133 | (unsigned long)ide_get_drivedata(pair)); |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 134 | } |
| 135 | |
| 136 | if (setup_count > 5) /* shouldn't actually happen... */ |
| 137 | setup_count = 5; |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 138 | |
| 139 | /* |
| 140 | * Program the address setup clocks into the ARTTIM registers. |
| 141 | * Avoid clearing the secondary channel's interrupt bit. |
| 142 | */ |
| 143 | (void) pci_read_config_byte (dev, arttim_regs[drive->dn], &arttim); |
| 144 | if (hwif->channel) |
| 145 | arttim &= ~ARTTIM23_INTR_CH1; |
| 146 | arttim &= ~0xc0; |
| 147 | arttim |= setup_values[setup_count]; |
| 148 | (void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim); |
Sergei Shtylyov | f92d50e | 2007-03-03 17:48:53 +0100 | [diff] [blame] | 149 | } |
| 150 | |
| 151 | /* |
| 152 | * Attempts to set drive's PIO mode. |
Bartlomiej Zolnierkiewicz | 26bcb87 | 2007-10-11 23:54:00 +0200 | [diff] [blame] | 153 | * Special cases are 8: prefetch off, 9: prefetch on (both never worked) |
Sergei Shtylyov | f92d50e | 2007-03-03 17:48:53 +0100 | [diff] [blame] | 154 | */ |
Bartlomiej Zolnierkiewicz | 26bcb87 | 2007-10-11 23:54:00 +0200 | [diff] [blame] | 155 | |
| 156 | static void cmd64x_set_pio_mode(ide_drive_t *drive, const u8 pio) |
Sergei Shtylyov | f92d50e | 2007-03-03 17:48:53 +0100 | [diff] [blame] | 157 | { |
| 158 | /* |
| 159 | * Filter out the prefetch control values |
| 160 | * to prevent PIO5 from being programmed |
| 161 | */ |
| 162 | if (pio == 8 || pio == 9) |
| 163 | return; |
| 164 | |
Bartlomiej Zolnierkiewicz | 26bcb87 | 2007-10-11 23:54:00 +0200 | [diff] [blame] | 165 | cmd64x_tune_pio(drive, pio); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 166 | } |
| 167 | |
Bartlomiej Zolnierkiewicz | 88b2b32 | 2007-10-13 17:47:51 +0200 | [diff] [blame] | 168 | static void cmd64x_set_dma_mode(ide_drive_t *drive, const u8 speed) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 169 | { |
Bartlomiej Zolnierkiewicz | 898ec22 | 2009-01-06 17:20:52 +0100 | [diff] [blame] | 170 | ide_hwif_t *hwif = drive->hwif; |
Bartlomiej Zolnierkiewicz | 3650165 | 2008-02-01 23:09:31 +0100 | [diff] [blame] | 171 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 172 | u8 unit = drive->dn & 0x01; |
| 173 | u8 regU = 0, pciU = hwif->channel ? UDIDETCR1 : UDIDETCR0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 174 | |
Sergei Shtylyov | f92d50e | 2007-03-03 17:48:53 +0100 | [diff] [blame] | 175 | if (speed >= XFER_SW_DMA_0) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 176 | (void) pci_read_config_byte(dev, pciU, ®U); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 177 | regU &= ~(unit ? 0xCA : 0x35); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 178 | } |
| 179 | |
| 180 | switch(speed) { |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 181 | case XFER_UDMA_5: |
| 182 | regU |= unit ? 0x0A : 0x05; |
| 183 | break; |
| 184 | case XFER_UDMA_4: |
| 185 | regU |= unit ? 0x4A : 0x15; |
| 186 | break; |
| 187 | case XFER_UDMA_3: |
| 188 | regU |= unit ? 0x8A : 0x25; |
| 189 | break; |
| 190 | case XFER_UDMA_2: |
| 191 | regU |= unit ? 0x42 : 0x11; |
| 192 | break; |
| 193 | case XFER_UDMA_1: |
| 194 | regU |= unit ? 0x82 : 0x21; |
| 195 | break; |
| 196 | case XFER_UDMA_0: |
| 197 | regU |= unit ? 0xC2 : 0x31; |
| 198 | break; |
| 199 | case XFER_MW_DMA_2: |
| 200 | program_cycle_times(drive, 120, 70); |
| 201 | break; |
| 202 | case XFER_MW_DMA_1: |
| 203 | program_cycle_times(drive, 150, 80); |
| 204 | break; |
| 205 | case XFER_MW_DMA_0: |
| 206 | program_cycle_times(drive, 480, 215); |
| 207 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 208 | } |
| 209 | |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 210 | if (speed >= XFER_SW_DMA_0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 211 | (void) pci_write_config_byte(dev, pciU, regU); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 212 | } |
| 213 | |
Sergei Shtylyov | 30e5ffc | 2009-06-15 18:52:56 +0200 | [diff] [blame] | 214 | static void cmd648_clear_irq(ide_drive_t *drive) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 215 | { |
Bartlomiej Zolnierkiewicz | 898ec22 | 2009-01-06 17:20:52 +0100 | [diff] [blame] | 216 | ide_hwif_t *hwif = drive->hwif; |
Sergei Shtylyov | 30e5ffc | 2009-06-15 18:52:56 +0200 | [diff] [blame] | 217 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
| 218 | unsigned long base = pci_resource_start(dev, 4); |
Sergei Shtylyov | 66602c8 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 219 | u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 : |
| 220 | MRDMODE_INTR_CH0; |
Bartlomiej Zolnierkiewicz | 1c029fd | 2008-01-25 22:17:05 +0100 | [diff] [blame] | 221 | u8 mrdmode = inb(base + 1); |
Sergei Shtylyov | 66602c8 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 222 | |
| 223 | /* clear the interrupt bit */ |
Sergei Shtylyov | 6183289 | 2007-11-13 22:09:14 +0100 | [diff] [blame] | 224 | outb((mrdmode & ~(MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1)) | irq_mask, |
Bartlomiej Zolnierkiewicz | 1c029fd | 2008-01-25 22:17:05 +0100 | [diff] [blame] | 225 | base + 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 226 | } |
| 227 | |
Sergei Shtylyov | 30e5ffc | 2009-06-15 18:52:56 +0200 | [diff] [blame] | 228 | static void cmd64x_clear_irq(ide_drive_t *drive) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 229 | { |
Bartlomiej Zolnierkiewicz | 898ec22 | 2009-01-06 17:20:52 +0100 | [diff] [blame] | 230 | ide_hwif_t *hwif = drive->hwif; |
Bartlomiej Zolnierkiewicz | 3650165 | 2008-02-01 23:09:31 +0100 | [diff] [blame] | 231 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
Sergei Shtylyov | 66602c8 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 232 | int irq_reg = hwif->channel ? ARTTIM23 : CFR; |
| 233 | u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 : |
| 234 | CFR_INTR_CH0; |
| 235 | u8 irq_stat = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 236 | |
Sergei Shtylyov | 66602c8 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 237 | (void) pci_read_config_byte(dev, irq_reg, &irq_stat); |
| 238 | /* clear the interrupt bit */ |
| 239 | (void) pci_write_config_byte(dev, irq_reg, irq_stat | irq_mask); |
Sergei Shtylyov | 66602c8 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 240 | } |
| 241 | |
Sergei Shtylyov | 628df2f | 2009-06-15 18:52:59 +0200 | [diff] [blame] | 242 | static int cmd648_test_irq(ide_hwif_t *hwif) |
Sergei Shtylyov | 66602c8 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 243 | { |
Sergei Shtylyov | 628df2f | 2009-06-15 18:52:59 +0200 | [diff] [blame] | 244 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
| 245 | unsigned long base = pci_resource_start(dev, 4); |
Sergei Shtylyov | 66602c8 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 246 | u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 : |
| 247 | MRDMODE_INTR_CH0; |
Bartlomiej Zolnierkiewicz | 1c029fd | 2008-01-25 22:17:05 +0100 | [diff] [blame] | 248 | u8 mrdmode = inb(base + 1); |
Sergei Shtylyov | 66602c8 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 249 | |
Sergei Shtylyov | 628df2f | 2009-06-15 18:52:59 +0200 | [diff] [blame] | 250 | pr_debug("%s: mrdmode: 0x%02x irq_mask: 0x%02x\n", |
| 251 | hwif->name, mrdmode, irq_mask); |
Sergei Shtylyov | 66602c8 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 252 | |
Sergei Shtylyov | 628df2f | 2009-06-15 18:52:59 +0200 | [diff] [blame] | 253 | return (mrdmode & irq_mask) ? 1 : 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 254 | } |
| 255 | |
Sergei Shtylyov | 628df2f | 2009-06-15 18:52:59 +0200 | [diff] [blame] | 256 | static int cmd64x_test_irq(ide_hwif_t *hwif) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 257 | { |
Bartlomiej Zolnierkiewicz | 3650165 | 2008-02-01 23:09:31 +0100 | [diff] [blame] | 258 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
Sergei Shtylyov | 66602c8 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 259 | int irq_reg = hwif->channel ? ARTTIM23 : CFR; |
| 260 | u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 : |
| 261 | CFR_INTR_CH0; |
Sergei Shtylyov | 66602c8 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 262 | u8 irq_stat = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 263 | |
Sergei Shtylyov | e51e252 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 264 | (void) pci_read_config_byte(dev, irq_reg, &irq_stat); |
| 265 | |
Sergei Shtylyov | 628df2f | 2009-06-15 18:52:59 +0200 | [diff] [blame] | 266 | pr_debug("%s: irq_stat: 0x%02x irq_mask: 0x%02x\n", |
| 267 | hwif->name, irq_stat, irq_mask); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 268 | |
Sergei Shtylyov | 628df2f | 2009-06-15 18:52:59 +0200 | [diff] [blame] | 269 | return (irq_stat & irq_mask) ? 1 : 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 270 | } |
| 271 | |
| 272 | /* |
| 273 | * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old |
| 274 | * event order for DMA transfers. |
| 275 | */ |
| 276 | |
Bartlomiej Zolnierkiewicz | 5e37bdc | 2008-04-26 22:25:24 +0200 | [diff] [blame] | 277 | static int cmd646_1_dma_end(ide_drive_t *drive) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 278 | { |
Bartlomiej Zolnierkiewicz | 898ec22 | 2009-01-06 17:20:52 +0100 | [diff] [blame] | 279 | ide_hwif_t *hwif = drive->hwif; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 280 | u8 dma_stat = 0, dma_cmd = 0; |
| 281 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 282 | /* get DMA status */ |
Bartlomiej Zolnierkiewicz | cab7f8e | 2008-07-23 19:55:51 +0200 | [diff] [blame] | 283 | dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 284 | /* read DMA command state */ |
Bartlomiej Zolnierkiewicz | cab7f8e | 2008-07-23 19:55:51 +0200 | [diff] [blame] | 285 | dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 286 | /* stop DMA */ |
Bartlomiej Zolnierkiewicz | cab7f8e | 2008-07-23 19:55:51 +0200 | [diff] [blame] | 287 | outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 288 | /* clear the INTR & ERROR bits */ |
Bartlomiej Zolnierkiewicz | cab7f8e | 2008-07-23 19:55:51 +0200 | [diff] [blame] | 289 | outb(dma_stat | 6, hwif->dma_base + ATA_DMA_STATUS); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 290 | /* verify good DMA status */ |
| 291 | return (dma_stat & 7) != 4; |
| 292 | } |
| 293 | |
Bartlomiej Zolnierkiewicz | 2ed0ef5 | 2009-03-24 23:22:53 +0100 | [diff] [blame] | 294 | static int init_chipset_cmd64x(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 295 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 296 | u8 mrdmode = 0; |
| 297 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 298 | /* Set a good latency timer and cache line size value. */ |
| 299 | (void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); |
| 300 | /* FIXME: pci_set_master() to ensure a good latency timer value */ |
| 301 | |
Sergei Shtylyov | 83a6d4a | 2007-07-09 23:17:55 +0200 | [diff] [blame] | 302 | /* |
| 303 | * Enable interrupts, select MEMORY READ LINE for reads. |
| 304 | * |
| 305 | * NOTE: although not mentioned in the PCI0646U specs, |
| 306 | * bits 0-1 are write only and won't be read back as |
| 307 | * set or not -- PCI0646U2 specs clarify this point. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 308 | */ |
Sergei Shtylyov | 83a6d4a | 2007-07-09 23:17:55 +0200 | [diff] [blame] | 309 | (void) pci_read_config_byte (dev, MRDMODE, &mrdmode); |
| 310 | mrdmode &= ~0x30; |
| 311 | (void) pci_write_config_byte(dev, MRDMODE, (mrdmode | 0x02)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 312 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 313 | return 0; |
| 314 | } |
| 315 | |
Bartlomiej Zolnierkiewicz | f454cbe | 2008-08-05 18:17:04 +0200 | [diff] [blame] | 316 | static u8 cmd64x_cable_detect(ide_hwif_t *hwif) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 317 | { |
Bartlomiej Zolnierkiewicz | 3650165 | 2008-02-01 23:09:31 +0100 | [diff] [blame] | 318 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
Sergei Shtylyov | 83a6d4a | 2007-07-09 23:17:55 +0200 | [diff] [blame] | 319 | u8 bmidecsr = 0, mask = hwif->channel ? 0x02 : 0x01; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 320 | |
Sergei Shtylyov | 83a6d4a | 2007-07-09 23:17:55 +0200 | [diff] [blame] | 321 | switch (dev->device) { |
| 322 | case PCI_DEVICE_ID_CMD_648: |
| 323 | case PCI_DEVICE_ID_CMD_649: |
| 324 | pci_read_config_byte(dev, BMIDECSR, &bmidecsr); |
Bartlomiej Zolnierkiewicz | 49521f9 | 2007-07-09 23:17:58 +0200 | [diff] [blame] | 325 | return (bmidecsr & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40; |
Sergei Shtylyov | 83a6d4a | 2007-07-09 23:17:55 +0200 | [diff] [blame] | 326 | default: |
Bartlomiej Zolnierkiewicz | 49521f9 | 2007-07-09 23:17:58 +0200 | [diff] [blame] | 327 | return ATA_CBL_PATA40; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 328 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 329 | } |
| 330 | |
Bartlomiej Zolnierkiewicz | ac95bee | 2008-04-26 22:25:14 +0200 | [diff] [blame] | 331 | static const struct ide_port_ops cmd64x_port_ops = { |
| 332 | .set_pio_mode = cmd64x_set_pio_mode, |
| 333 | .set_dma_mode = cmd64x_set_dma_mode, |
Sergei Shtylyov | 30e5ffc | 2009-06-15 18:52:56 +0200 | [diff] [blame] | 334 | .clear_irq = cmd64x_clear_irq, |
Sergei Shtylyov | 628df2f | 2009-06-15 18:52:59 +0200 | [diff] [blame] | 335 | .test_irq = cmd64x_test_irq, |
Sergei Shtylyov | 30e5ffc | 2009-06-15 18:52:56 +0200 | [diff] [blame] | 336 | .cable_detect = cmd64x_cable_detect, |
| 337 | }; |
| 338 | |
| 339 | static const struct ide_port_ops cmd648_port_ops = { |
| 340 | .set_pio_mode = cmd64x_set_pio_mode, |
| 341 | .set_dma_mode = cmd64x_set_dma_mode, |
| 342 | .clear_irq = cmd648_clear_irq, |
Sergei Shtylyov | 628df2f | 2009-06-15 18:52:59 +0200 | [diff] [blame] | 343 | .test_irq = cmd648_test_irq, |
Bartlomiej Zolnierkiewicz | ac95bee | 2008-04-26 22:25:14 +0200 | [diff] [blame] | 344 | .cable_detect = cmd64x_cable_detect, |
| 345 | }; |
| 346 | |
Bartlomiej Zolnierkiewicz | f37afda | 2008-04-26 22:25:24 +0200 | [diff] [blame] | 347 | static const struct ide_dma_ops cmd646_rev1_dma_ops = { |
| 348 | .dma_host_set = ide_dma_host_set, |
| 349 | .dma_setup = ide_dma_setup, |
Bartlomiej Zolnierkiewicz | f37afda | 2008-04-26 22:25:24 +0200 | [diff] [blame] | 350 | .dma_start = ide_dma_start, |
Bartlomiej Zolnierkiewicz | 5e37bdc | 2008-04-26 22:25:24 +0200 | [diff] [blame] | 351 | .dma_end = cmd646_1_dma_end, |
Bartlomiej Zolnierkiewicz | f37afda | 2008-04-26 22:25:24 +0200 | [diff] [blame] | 352 | .dma_test_irq = ide_dma_test_irq, |
| 353 | .dma_lost_irq = ide_dma_lost_irq, |
Bartlomiej Zolnierkiewicz | 22117d6 | 2009-03-27 12:46:47 +0100 | [diff] [blame] | 354 | .dma_timer_expiry = ide_dma_sff_timer_expiry, |
Sergei Shtylyov | 592b531 | 2009-01-06 17:21:02 +0100 | [diff] [blame] | 355 | .dma_sff_read_status = ide_dma_sff_read_status, |
Bartlomiej Zolnierkiewicz | 5e37bdc | 2008-04-26 22:25:24 +0200 | [diff] [blame] | 356 | }; |
| 357 | |
Bartlomiej Zolnierkiewicz | 8562043 | 2007-10-20 00:32:34 +0200 | [diff] [blame] | 358 | static const struct ide_port_info cmd64x_chipsets[] __devinitdata = { |
Bartlomiej Zolnierkiewicz | ced3ec8 | 2008-07-24 22:53:32 +0200 | [diff] [blame] | 359 | { /* 0: CMD643 */ |
| 360 | .name = DRV_NAME, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 361 | .init_chipset = init_chipset_cmd64x, |
Sergei Shtylyov | 7accbff | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 362 | .enablebits = {{0x00,0x00,0x00}, {0x51,0x08,0x08}}, |
Bartlomiej Zolnierkiewicz | ac95bee | 2008-04-26 22:25:14 +0200 | [diff] [blame] | 363 | .port_ops = &cmd64x_port_ops, |
Bartlomiej Zolnierkiewicz | 8ac2b42 | 2008-02-01 23:09:30 +0100 | [diff] [blame] | 364 | .host_flags = IDE_HFLAG_CLEAR_SIMPLEX | |
Mikulas Patocka | 9bd7496 | 2009-10-21 08:55:28 +0000 | [diff] [blame] | 365 | IDE_HFLAG_ABUSE_PREFETCH | |
| 366 | IDE_HFLAG_SERIALIZE, |
Bartlomiej Zolnierkiewicz | 4099d14 | 2007-07-20 01:11:59 +0200 | [diff] [blame] | 367 | .pio_mask = ATA_PIO5, |
Bartlomiej Zolnierkiewicz | 5f8b6c3 | 2007-10-19 00:30:07 +0200 | [diff] [blame] | 368 | .mwdma_mask = ATA_MWDMA2, |
Bartlomiej Zolnierkiewicz | 1813720 | 2007-05-10 00:01:07 +0200 | [diff] [blame] | 369 | .udma_mask = 0x00, /* no udma */ |
Bartlomiej Zolnierkiewicz | ced3ec8 | 2008-07-24 22:53:32 +0200 | [diff] [blame] | 370 | }, |
| 371 | { /* 1: CMD646 */ |
| 372 | .name = DRV_NAME, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 373 | .init_chipset = init_chipset_cmd64x, |
Sergei Shtylyov | 7accbff | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 374 | .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}}, |
Sergei Shtylyov | 30e5ffc | 2009-06-15 18:52:56 +0200 | [diff] [blame] | 375 | .port_ops = &cmd648_port_ops, |
Mikulas Patocka | 9bd7496 | 2009-10-21 08:55:28 +0000 | [diff] [blame] | 376 | .host_flags = IDE_HFLAG_ABUSE_PREFETCH | |
| 377 | IDE_HFLAG_SERIALIZE, |
Bartlomiej Zolnierkiewicz | 4099d14 | 2007-07-20 01:11:59 +0200 | [diff] [blame] | 378 | .pio_mask = ATA_PIO5, |
Bartlomiej Zolnierkiewicz | 5f8b6c3 | 2007-10-19 00:30:07 +0200 | [diff] [blame] | 379 | .mwdma_mask = ATA_MWDMA2, |
| 380 | .udma_mask = ATA_UDMA2, |
Bartlomiej Zolnierkiewicz | ced3ec8 | 2008-07-24 22:53:32 +0200 | [diff] [blame] | 381 | }, |
| 382 | { /* 2: CMD648 */ |
| 383 | .name = DRV_NAME, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 384 | .init_chipset = init_chipset_cmd64x, |
Sergei Shtylyov | 7accbff | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 385 | .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}}, |
Sergei Shtylyov | 30e5ffc | 2009-06-15 18:52:56 +0200 | [diff] [blame] | 386 | .port_ops = &cmd648_port_ops, |
Bartlomiej Zolnierkiewicz | 5e71d9c | 2008-04-26 17:36:35 +0200 | [diff] [blame] | 387 | .host_flags = IDE_HFLAG_ABUSE_PREFETCH, |
Bartlomiej Zolnierkiewicz | 4099d14 | 2007-07-20 01:11:59 +0200 | [diff] [blame] | 388 | .pio_mask = ATA_PIO5, |
Bartlomiej Zolnierkiewicz | 5f8b6c3 | 2007-10-19 00:30:07 +0200 | [diff] [blame] | 389 | .mwdma_mask = ATA_MWDMA2, |
| 390 | .udma_mask = ATA_UDMA4, |
Bartlomiej Zolnierkiewicz | ced3ec8 | 2008-07-24 22:53:32 +0200 | [diff] [blame] | 391 | }, |
| 392 | { /* 3: CMD649 */ |
| 393 | .name = DRV_NAME, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 394 | .init_chipset = init_chipset_cmd64x, |
Sergei Shtylyov | 7accbff | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 395 | .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}}, |
Sergei Shtylyov | 30e5ffc | 2009-06-15 18:52:56 +0200 | [diff] [blame] | 396 | .port_ops = &cmd648_port_ops, |
Bartlomiej Zolnierkiewicz | 5e71d9c | 2008-04-26 17:36:35 +0200 | [diff] [blame] | 397 | .host_flags = IDE_HFLAG_ABUSE_PREFETCH, |
Bartlomiej Zolnierkiewicz | 4099d14 | 2007-07-20 01:11:59 +0200 | [diff] [blame] | 398 | .pio_mask = ATA_PIO5, |
Bartlomiej Zolnierkiewicz | 5f8b6c3 | 2007-10-19 00:30:07 +0200 | [diff] [blame] | 399 | .mwdma_mask = ATA_MWDMA2, |
| 400 | .udma_mask = ATA_UDMA5, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 401 | } |
| 402 | }; |
| 403 | |
| 404 | static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
| 405 | { |
Bartlomiej Zolnierkiewicz | 039788e | 2007-10-20 00:32:34 +0200 | [diff] [blame] | 406 | struct ide_port_info d; |
Bartlomiej Zolnierkiewicz | bfd314a | 2007-10-19 00:30:09 +0200 | [diff] [blame] | 407 | u8 idx = id->driver_data; |
Sergei Shtylyov | 7accbff | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 408 | |
Bartlomiej Zolnierkiewicz | bfd314a | 2007-10-19 00:30:09 +0200 | [diff] [blame] | 409 | d = cmd64x_chipsets[idx]; |
| 410 | |
Bartlomiej Zolnierkiewicz | 5e37bdc | 2008-04-26 22:25:24 +0200 | [diff] [blame] | 411 | if (idx == 1) { |
| 412 | /* |
| 413 | * UltraDMA only supported on PCI646U and PCI646U2, which |
| 414 | * correspond to revisions 0x03, 0x05 and 0x07 respectively. |
| 415 | * Actually, although the CMD tech support people won't |
| 416 | * tell me the details, the 0x03 revision cannot support |
| 417 | * UDMA correctly without hardware modifications, and even |
| 418 | * then it only works with Quantum disks due to some |
| 419 | * hold time assumptions in the 646U part which are fixed |
| 420 | * in the 646U2. |
| 421 | * |
| 422 | * So we only do UltraDMA on revision 0x05 and 0x07 chipsets. |
| 423 | */ |
| 424 | if (dev->revision < 5) { |
| 425 | d.udma_mask = 0x00; |
| 426 | /* |
| 427 | * The original PCI0646 didn't have the primary |
| 428 | * channel enable bit, it appeared starting with |
| 429 | * PCI0646U (i.e. revision ID 3). |
| 430 | */ |
| 431 | if (dev->revision < 3) { |
| 432 | d.enablebits[0].reg = 0; |
Sergei Shtylyov | 30e5ffc | 2009-06-15 18:52:56 +0200 | [diff] [blame] | 433 | d.port_ops = &cmd64x_port_ops; |
Bartlomiej Zolnierkiewicz | 5e37bdc | 2008-04-26 22:25:24 +0200 | [diff] [blame] | 434 | if (dev->revision == 1) |
| 435 | d.dma_ops = &cmd646_rev1_dma_ops; |
Bartlomiej Zolnierkiewicz | 5e37bdc | 2008-04-26 22:25:24 +0200 | [diff] [blame] | 436 | } |
| 437 | } |
| 438 | } |
Bartlomiej Zolnierkiewicz | bfd314a | 2007-10-19 00:30:09 +0200 | [diff] [blame] | 439 | |
Bartlomiej Zolnierkiewicz | 6cdf6eb | 2008-07-24 22:53:14 +0200 | [diff] [blame] | 440 | return ide_pci_init_one(dev, &d, NULL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 441 | } |
| 442 | |
Bartlomiej Zolnierkiewicz | 9cbcc5e | 2007-10-16 22:29:56 +0200 | [diff] [blame] | 443 | static const struct pci_device_id cmd64x_pci_tbl[] = { |
| 444 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 }, |
| 445 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 }, |
| 446 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 2 }, |
| 447 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 3 }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 448 | { 0, }, |
| 449 | }; |
| 450 | MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl); |
| 451 | |
Bartlomiej Zolnierkiewicz | a9ab09e | 2008-10-13 21:39:41 +0200 | [diff] [blame] | 452 | static struct pci_driver cmd64x_pci_driver = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 453 | .name = "CMD64x_IDE", |
| 454 | .id_table = cmd64x_pci_tbl, |
| 455 | .probe = cmd64x_init_one, |
Bartlomiej Zolnierkiewicz | e2b15b4 | 2008-07-24 22:53:20 +0200 | [diff] [blame] | 456 | .remove = ide_pci_remove, |
Bartlomiej Zolnierkiewicz | feb22b7 | 2008-10-10 22:39:32 +0200 | [diff] [blame] | 457 | .suspend = ide_pci_suspend, |
| 458 | .resume = ide_pci_resume, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 459 | }; |
| 460 | |
Bartlomiej Zolnierkiewicz | 82ab1ee | 2007-01-27 13:46:56 +0100 | [diff] [blame] | 461 | static int __init cmd64x_ide_init(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 462 | { |
Bartlomiej Zolnierkiewicz | a9ab09e | 2008-10-13 21:39:41 +0200 | [diff] [blame] | 463 | return ide_pci_register_driver(&cmd64x_pci_driver); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 464 | } |
| 465 | |
Bartlomiej Zolnierkiewicz | e2b15b4 | 2008-07-24 22:53:20 +0200 | [diff] [blame] | 466 | static void __exit cmd64x_ide_exit(void) |
| 467 | { |
Bartlomiej Zolnierkiewicz | a9ab09e | 2008-10-13 21:39:41 +0200 | [diff] [blame] | 468 | pci_unregister_driver(&cmd64x_pci_driver); |
Bartlomiej Zolnierkiewicz | e2b15b4 | 2008-07-24 22:53:20 +0200 | [diff] [blame] | 469 | } |
| 470 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 471 | module_init(cmd64x_ide_init); |
Bartlomiej Zolnierkiewicz | e2b15b4 | 2008-07-24 22:53:20 +0200 | [diff] [blame] | 472 | module_exit(cmd64x_ide_exit); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 473 | |
| 474 | MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick"); |
| 475 | MODULE_DESCRIPTION("PCI driver module for CMD64x IDE"); |
| 476 | MODULE_LICENSE("GPL"); |