blob: a574875842f799ac66bfa9c3de89c21b09ffd23d [file] [log] [blame]
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/err.h>
16#include <linux/ctype.h>
17#include <linux/bitops.h>
18#include <linux/io.h>
19#include <linux/spinlock.h>
20#include <linux/delay.h>
21#include <linux/clk.h>
22
23#include <asm/clkdev.h>
24#include <asm/mach-types.h>
25
26#include <mach/msm_iomap.h>
27#include <mach/clk.h>
28#include <mach/rpm-regulator.h>
29#include <mach/msm_xo.h>
Stephen Boyd94625ef2011-07-12 17:06:01 -070030#include <mach/socinfo.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070031
32#include "clock-local.h"
33#include "clock-rpm.h"
34#include "clock-voter.h"
35#include "clock-dss-8960.h"
36#include "devices.h"
37
38#define REG(off) (MSM_CLK_CTL_BASE + (off))
39#define REG_MM(off) (MSM_MMSS_CLK_CTL_BASE + (off))
40#define REG_LPA(off) (MSM_LPASS_CLK_CTL_BASE + (off))
Matt Wagantall8b38f942011-08-02 18:23:18 -070041#define REG_GCC(off) (MSM_APCS_GCC_BASE + (off))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070042
43/* Peripheral clock registers. */
44#define CE1_HCLK_CTL_REG REG(0x2720)
45#define CE1_CORE_CLK_CTL_REG REG(0x2724)
46#define DMA_BAM_HCLK_CTL REG(0x25C0)
47#define CLK_HALT_CFPB_STATEA_REG REG(0x2FCC)
48#define CLK_HALT_CFPB_STATEB_REG REG(0x2FD0)
49#define CLK_HALT_CFPB_STATEC_REG REG(0x2FD4)
50#define CLK_HALT_DFAB_STATE_REG REG(0x2FC8)
51#define CLK_HALT_MSS_SMPSS_MISC_STATE_REG REG(0x2FDC)
52#define CLK_HALT_SFPB_MISC_STATE_REG REG(0x2FD8)
Stephen Boyd973e4ba2011-07-12 17:06:01 -070053#define CLK_HALT_AFAB_SFAB_STATEB_REG REG(0x2FC4)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070054#define CLK_TEST_REG REG(0x2FA0)
55#define GSBIn_HCLK_CTL_REG(n) REG(0x29C0+(0x20*((n)-1)))
56#define GSBIn_QUP_APPS_MD_REG(n) REG(0x29C8+(0x20*((n)-1)))
57#define GSBIn_QUP_APPS_NS_REG(n) REG(0x29CC+(0x20*((n)-1)))
58#define GSBIn_RESET_REG(n) REG(0x29DC+(0x20*((n)-1)))
59#define GSBIn_UART_APPS_MD_REG(n) REG(0x29D0+(0x20*((n)-1)))
60#define GSBIn_UART_APPS_NS_REG(n) REG(0x29D4+(0x20*((n)-1)))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070061#define PDM_CLK_NS_REG REG(0x2CC0)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070062#define BB_PLL_ENA_SC0_REG REG(0x34C0)
63#define BB_PLL0_STATUS_REG REG(0x30D8)
64#define BB_PLL5_STATUS_REG REG(0x30F8)
65#define BB_PLL6_STATUS_REG REG(0x3118)
66#define BB_PLL7_STATUS_REG REG(0x3138)
67#define BB_PLL8_L_VAL_REG REG(0x3144)
68#define BB_PLL8_M_VAL_REG REG(0x3148)
69#define BB_PLL8_MODE_REG REG(0x3140)
70#define BB_PLL8_N_VAL_REG REG(0x314C)
71#define BB_PLL8_STATUS_REG REG(0x3158)
72#define BB_PLL8_CONFIG_REG REG(0x3154)
73#define BB_PLL8_TEST_CTL_REG REG(0x3150)
Stephen Boyd94625ef2011-07-12 17:06:01 -070074#define BB_MMCC_PLL2_MODE_REG REG(0x3160)
75#define BB_MMCC_PLL2_TEST_CTL_REG REG(0x3170)
76#define BB_PLL14_STATUS_REG REG(0x31D8)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070077#define PLLTEST_PAD_CFG_REG REG(0x2FA4)
78#define PMEM_ACLK_CTL_REG REG(0x25A0)
Stephen Boyd973e4ba2011-07-12 17:06:01 -070079#define QDSS_AT_CLK_SRC0_NS_REG REG(0x2180)
80#define QDSS_AT_CLK_SRC1_NS_REG REG(0x2184)
81#define QDSS_AT_CLK_SRC_CTL_REG REG(0x2188)
82#define QDSS_AT_CLK_NS_REG REG(0x218C)
83#define QDSS_HCLK_CTL_REG REG(0x22A0)
84#define QDSS_RESETS_REG REG(0x2260)
85#define QDSS_STM_CLK_CTL_REG REG(0x2060)
86#define QDSS_TRACECLKIN_CLK_SRC0_NS_REG REG(0x21A0)
87#define QDSS_TRACECLKIN_CLK_SRC1_NS_REG REG(0x21A4)
88#define QDSS_TRACECLKIN_CLK_SRC_CTL_REG REG(0x21A8)
89#define QDSS_TRACECLKIN_CTL_REG REG(0x21AC)
90#define QDSS_TSCTR_CLK_SRC0_NS_REG REG(0x21C0)
91#define QDSS_TSCTR_CLK_SRC1_NS_REG REG(0x21C4)
92#define QDSS_TSCTR_CLK_SRC_CTL_REG REG(0x21C8)
93#define QDSS_TSCTR_CLK_SRC_CTL_REG REG(0x21C8)
94#define QDSS_TSCTR_CTL_REG REG(0x21CC)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070095#define RINGOSC_NS_REG REG(0x2DC0)
96#define RINGOSC_STATUS_REG REG(0x2DCC)
97#define RINGOSC_TCXO_CTL_REG REG(0x2DC4)
98#define SC0_U_CLK_BRANCH_ENA_VOTE_REG REG(0x3080)
99#define SDCn_APPS_CLK_MD_REG(n) REG(0x2828+(0x20*((n)-1)))
100#define SDCn_APPS_CLK_NS_REG(n) REG(0x282C+(0x20*((n)-1)))
101#define SDCn_HCLK_CTL_REG(n) REG(0x2820+(0x20*((n)-1)))
102#define SDCn_RESET_REG(n) REG(0x2830+(0x20*((n)-1)))
103#define SLIMBUS_XO_SRC_CLK_CTL_REG REG(0x2628)
104#define TSIF_HCLK_CTL_REG REG(0x2700)
105#define TSIF_REF_CLK_MD_REG REG(0x270C)
106#define TSIF_REF_CLK_NS_REG REG(0x2710)
107#define TSSC_CLK_CTL_REG REG(0x2CA0)
108#define USB_FSn_HCLK_CTL_REG(n) REG(0x2960+(0x20*((n)-1)))
109#define USB_FSn_RESET_REG(n) REG(0x2974+(0x20*((n)-1)))
110#define USB_FSn_SYSTEM_CLK_CTL_REG(n) REG(0x296C+(0x20*((n)-1)))
111#define USB_FSn_XCVR_FS_CLK_MD_REG(n) REG(0x2964+(0x20*((n)-1)))
112#define USB_FSn_XCVR_FS_CLK_NS_REG(n) REG(0x2968+(0x20*((n)-1)))
113#define USB_HS1_HCLK_CTL_REG REG(0x2900)
114#define USB_HS1_RESET_REG REG(0x2910)
115#define USB_HS1_XCVR_FS_CLK_MD_REG REG(0x2908)
116#define USB_HS1_XCVR_FS_CLK_NS_REG REG(0x290C)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700117#define USB_HSIC_HCLK_CTL_REG REG(0x2920)
118#define USB_HSIC_HSIC_CLK_CTL_REG REG(0x2B44)
119#define USB_HSIC_HSIC_CLK_SRC_CTL_REG REG(0x2B40)
120#define USB_HSIC_HSIO_CAL_CLK_CTL_REG REG(0x2B48)
121#define USB_HSIC_RESET_REG REG(0x2934)
122#define USB_HSIC_SYSTEM_CLK_CTL_REG REG(0x292C)
123#define USB_HSIC_XCVR_FS_CLK_MD_REG REG(0x2924)
124#define USB_HSIC_XCVR_FS_CLK_NS_REG REG(0x2928)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700125#define USB_PHY0_RESET_REG REG(0x2E20)
126
127/* Multimedia clock registers. */
128#define AHB_EN_REG REG_MM(0x0008)
129#define AHB_EN2_REG REG_MM(0x0038)
130#define AHB_NS_REG REG_MM(0x0004)
131#define AXI_NS_REG REG_MM(0x0014)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700132#define CAMCLK0_NS_REG REG_MM(0x0148)
133#define CAMCLK0_CC_REG REG_MM(0x0140)
134#define CAMCLK0_MD_REG REG_MM(0x0144)
135#define CAMCLK1_NS_REG REG_MM(0x015C)
136#define CAMCLK1_CC_REG REG_MM(0x0154)
137#define CAMCLK1_MD_REG REG_MM(0x0158)
138#define CAMCLK2_NS_REG REG_MM(0x0228)
139#define CAMCLK2_CC_REG REG_MM(0x0220)
140#define CAMCLK2_MD_REG REG_MM(0x0224)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700141#define CSI0_NS_REG REG_MM(0x0048)
142#define CSI0_CC_REG REG_MM(0x0040)
143#define CSI0_MD_REG REG_MM(0x0044)
144#define CSI1_NS_REG REG_MM(0x0010)
145#define CSI1_CC_REG REG_MM(0x0024)
146#define CSI1_MD_REG REG_MM(0x0028)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700147#define CSI2_NS_REG REG_MM(0x0234)
148#define CSI2_CC_REG REG_MM(0x022C)
149#define CSI2_MD_REG REG_MM(0x0230)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700150#define CSIPHYTIMER_CC_REG REG_MM(0x0160)
151#define CSIPHYTIMER_MD_REG REG_MM(0x0164)
152#define CSIPHYTIMER_NS_REG REG_MM(0x0168)
153#define DSI1_BYTE_NS_REG REG_MM(0x00B0)
154#define DSI1_BYTE_CC_REG REG_MM(0x0090)
155#define DSI2_BYTE_NS_REG REG_MM(0x00BC)
156#define DSI2_BYTE_CC_REG REG_MM(0x00B4)
157#define DSI1_ESC_NS_REG REG_MM(0x011C)
158#define DSI1_ESC_CC_REG REG_MM(0x00CC)
159#define DSI2_ESC_NS_REG REG_MM(0x0150)
160#define DSI2_ESC_CC_REG REG_MM(0x013C)
161#define DSI_PIXEL_CC_REG REG_MM(0x0130)
162#define DSI2_PIXEL_CC_REG REG_MM(0x0094)
163#define DBG_BUS_VEC_A_REG REG_MM(0x01C8)
164#define DBG_BUS_VEC_B_REG REG_MM(0x01CC)
165#define DBG_BUS_VEC_C_REG REG_MM(0x01D0)
166#define DBG_BUS_VEC_D_REG REG_MM(0x01D4)
167#define DBG_BUS_VEC_E_REG REG_MM(0x01D8)
168#define DBG_BUS_VEC_F_REG REG_MM(0x01DC)
169#define DBG_BUS_VEC_G_REG REG_MM(0x01E0)
170#define DBG_BUS_VEC_H_REG REG_MM(0x01E4)
171#define DBG_BUS_VEC_I_REG REG_MM(0x01E8)
172#define DBG_CFG_REG_HS_REG REG_MM(0x01B4)
173#define DBG_CFG_REG_LS_REG REG_MM(0x01B8)
174#define GFX2D0_CC_REG REG_MM(0x0060)
175#define GFX2D0_MD0_REG REG_MM(0x0064)
176#define GFX2D0_MD1_REG REG_MM(0x0068)
177#define GFX2D0_NS_REG REG_MM(0x0070)
178#define GFX2D1_CC_REG REG_MM(0x0074)
179#define GFX2D1_MD0_REG REG_MM(0x0078)
180#define GFX2D1_MD1_REG REG_MM(0x006C)
181#define GFX2D1_NS_REG REG_MM(0x007C)
182#define GFX3D_CC_REG REG_MM(0x0080)
183#define GFX3D_MD0_REG REG_MM(0x0084)
184#define GFX3D_MD1_REG REG_MM(0x0088)
185#define GFX3D_NS_REG REG_MM(0x008C)
186#define IJPEG_CC_REG REG_MM(0x0098)
187#define IJPEG_MD_REG REG_MM(0x009C)
188#define IJPEG_NS_REG REG_MM(0x00A0)
189#define JPEGD_CC_REG REG_MM(0x00A4)
190#define JPEGD_NS_REG REG_MM(0x00AC)
191#define MAXI_EN_REG REG_MM(0x0018)
192#define MAXI_EN2_REG REG_MM(0x0020)
193#define MAXI_EN3_REG REG_MM(0x002C)
194#define MAXI_EN4_REG REG_MM(0x0114)
195#define MDP_CC_REG REG_MM(0x00C0)
196#define MDP_LUT_CC_REG REG_MM(0x016C)
197#define MDP_MD0_REG REG_MM(0x00C4)
198#define MDP_MD1_REG REG_MM(0x00C8)
199#define MDP_NS_REG REG_MM(0x00D0)
200#define MISC_CC_REG REG_MM(0x0058)
201#define MISC_CC2_REG REG_MM(0x005C)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700202#define MISC_CC3_REG REG_MM(0x0238)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700203#define MM_PLL1_MODE_REG REG_MM(0x031C)
204#define ROT_CC_REG REG_MM(0x00E0)
205#define ROT_NS_REG REG_MM(0x00E8)
206#define SAXI_EN_REG REG_MM(0x0030)
207#define SW_RESET_AHB_REG REG_MM(0x020C)
208#define SW_RESET_AHB2_REG REG_MM(0x0200)
209#define SW_RESET_ALL_REG REG_MM(0x0204)
210#define SW_RESET_AXI_REG REG_MM(0x0208)
211#define SW_RESET_CORE_REG REG_MM(0x0210)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700212#define SW_RESET_CORE2_REG REG_MM(0x0214)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700213#define TV_CC_REG REG_MM(0x00EC)
214#define TV_CC2_REG REG_MM(0x0124)
215#define TV_MD_REG REG_MM(0x00F0)
216#define TV_NS_REG REG_MM(0x00F4)
217#define VCODEC_CC_REG REG_MM(0x00F8)
218#define VCODEC_MD0_REG REG_MM(0x00FC)
219#define VCODEC_MD1_REG REG_MM(0x0128)
220#define VCODEC_NS_REG REG_MM(0x0100)
221#define VFE_CC_REG REG_MM(0x0104)
222#define VFE_MD_REG REG_MM(0x0108)
223#define VFE_NS_REG REG_MM(0x010C)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700224#define VFE_CC2_REG REG_MM(0x023C)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700225#define VPE_CC_REG REG_MM(0x0110)
226#define VPE_NS_REG REG_MM(0x0118)
227
228/* Low-power Audio clock registers. */
Stephen Boyd3939c8d2011-08-29 17:36:22 -0700229#define LCC_CLK_HS_DEBUG_CFG_REG REG_LPA(0x00A4)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700230#define LCC_CLK_LS_DEBUG_CFG_REG REG_LPA(0x00A8)
231#define LCC_CODEC_I2S_MIC_MD_REG REG_LPA(0x0064)
232#define LCC_CODEC_I2S_MIC_NS_REG REG_LPA(0x0060)
233#define LCC_CODEC_I2S_MIC_STATUS_REG REG_LPA(0x0068)
234#define LCC_CODEC_I2S_SPKR_MD_REG REG_LPA(0x0070)
235#define LCC_CODEC_I2S_SPKR_NS_REG REG_LPA(0x006C)
236#define LCC_CODEC_I2S_SPKR_STATUS_REG REG_LPA(0x0074)
237#define LCC_MI2S_MD_REG REG_LPA(0x004C)
238#define LCC_MI2S_NS_REG REG_LPA(0x0048)
239#define LCC_MI2S_STATUS_REG REG_LPA(0x0050)
240#define LCC_PCM_MD_REG REG_LPA(0x0058)
241#define LCC_PCM_NS_REG REG_LPA(0x0054)
242#define LCC_PCM_STATUS_REG REG_LPA(0x005C)
243#define LCC_PLL0_STATUS_REG REG_LPA(0x0018)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700244#define LCC_SPARE_I2S_MIC_MD_REG REG_LPA(0x007C)
245#define LCC_SPARE_I2S_MIC_NS_REG REG_LPA(0x0078)
246#define LCC_SPARE_I2S_MIC_STATUS_REG REG_LPA(0x0080)
247#define LCC_SPARE_I2S_SPKR_MD_REG REG_LPA(0x0088)
248#define LCC_SPARE_I2S_SPKR_NS_REG REG_LPA(0x0084)
249#define LCC_SPARE_I2S_SPKR_STATUS_REG REG_LPA(0x008C)
250#define LCC_SLIMBUS_NS_REG REG_LPA(0x00CC)
251#define LCC_SLIMBUS_MD_REG REG_LPA(0x00D0)
252#define LCC_SLIMBUS_STATUS_REG REG_LPA(0x00D4)
253#define LCC_AHBEX_BRANCH_CTL_REG REG_LPA(0x00E4)
254
Matt Wagantall8b38f942011-08-02 18:23:18 -0700255#define GCC_APCS_CLK_DIAG REG_GCC(0x001C)
256
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700257/* MUX source input identifiers. */
258#define pxo_to_bb_mux 0
259#define cxo_to_bb_mux pxo_to_bb_mux
260#define pll0_to_bb_mux 2
261#define pll8_to_bb_mux 3
262#define pll6_to_bb_mux 4
263#define gnd_to_bb_mux 5
Stephen Boyd94625ef2011-07-12 17:06:01 -0700264#define pll3_to_bb_mux 6
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700265#define pxo_to_mm_mux 0
266#define pll1_to_mm_mux 1
267#define pll2_to_mm_mux 1
268#define pll8_to_mm_mux 2
269#define pll0_to_mm_mux 3
270#define gnd_to_mm_mux 4
Stephen Boyd94625ef2011-07-12 17:06:01 -0700271#define pll3_to_mm_mux 5
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700272#define hdmi_pll_to_mm_mux 3
273#define cxo_to_xo_mux 0
274#define pxo_to_xo_mux 1
275#define gnd_to_xo_mux 3
276#define pxo_to_lpa_mux 0
277#define cxo_to_lpa_mux 1
278#define pll4_to_lpa_mux 2
279#define gnd_to_lpa_mux 6
280
281/* Test Vector Macros */
282#define TEST_TYPE_PER_LS 1
283#define TEST_TYPE_PER_HS 2
284#define TEST_TYPE_MM_LS 3
285#define TEST_TYPE_MM_HS 4
286#define TEST_TYPE_LPA 5
Matt Wagantall8b38f942011-08-02 18:23:18 -0700287#define TEST_TYPE_CPUL2 6
Stephen Boyd3939c8d2011-08-29 17:36:22 -0700288#define TEST_TYPE_LPA_HS 7
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700289#define TEST_TYPE_SHIFT 24
290#define TEST_CLK_SEL_MASK BM(23, 0)
291#define TEST_VECTOR(s, t) (((t) << TEST_TYPE_SHIFT) | BVAL(23, 0, (s)))
292#define TEST_PER_LS(s) TEST_VECTOR((s), TEST_TYPE_PER_LS)
293#define TEST_PER_HS(s) TEST_VECTOR((s), TEST_TYPE_PER_HS)
294#define TEST_MM_LS(s) TEST_VECTOR((s), TEST_TYPE_MM_LS)
295#define TEST_MM_HS(s) TEST_VECTOR((s), TEST_TYPE_MM_HS)
296#define TEST_LPA(s) TEST_VECTOR((s), TEST_TYPE_LPA)
Stephen Boyd3939c8d2011-08-29 17:36:22 -0700297#define TEST_LPA_HS(s) TEST_VECTOR((s), TEST_TYPE_LPA_HS)
Matt Wagantall8b38f942011-08-02 18:23:18 -0700298#define TEST_CPUL2(s) TEST_VECTOR((s), TEST_TYPE_CPUL2)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700299
300#define MN_MODE_DUAL_EDGE 0x2
301
302/* MD Registers */
303#define MD4(m_lsb, m, n_lsb, n) \
304 (BVAL((m_lsb+3), m_lsb, m) | BVAL((n_lsb+3), n_lsb, ~(n)))
305#define MD8(m_lsb, m, n_lsb, n) \
306 (BVAL((m_lsb+7), m_lsb, m) | BVAL((n_lsb+7), n_lsb, ~(n)))
307#define MD16(m, n) (BVAL(31, 16, m) | BVAL(15, 0, ~(n)))
308
309/* NS Registers */
310#define NS(n_msb, n_lsb, n, m, mde_lsb, d_msb, d_lsb, d, s_msb, s_lsb, s) \
311 (BVAL(n_msb, n_lsb, ~(n-m)) \
312 | (BVAL((mde_lsb+1), mde_lsb, MN_MODE_DUAL_EDGE) * !!(n)) \
313 | BVAL(d_msb, d_lsb, (d-1)) | BVAL(s_msb, s_lsb, s))
314
315#define NS_MM(n_msb, n_lsb, n, m, d_msb, d_lsb, d, s_msb, s_lsb, s) \
316 (BVAL(n_msb, n_lsb, ~(n-m)) | BVAL(d_msb, d_lsb, (d-1)) \
317 | BVAL(s_msb, s_lsb, s))
318
319#define NS_DIVSRC(d_msb , d_lsb, d, s_msb, s_lsb, s) \
320 (BVAL(d_msb, d_lsb, (d-1)) | BVAL(s_msb, s_lsb, s))
321
322#define NS_DIV(d_msb , d_lsb, d) \
323 BVAL(d_msb, d_lsb, (d-1))
324
325#define NS_SRC_SEL(s_msb, s_lsb, s) \
326 BVAL(s_msb, s_lsb, s)
327
328#define NS_MND_BANKED4(n0_lsb, n1_lsb, n, m, s0_lsb, s1_lsb, s) \
329 (BVAL((n0_lsb+3), n0_lsb, ~(n-m)) \
330 | BVAL((n1_lsb+3), n1_lsb, ~(n-m)) \
331 | BVAL((s0_lsb+2), s0_lsb, s) \
332 | BVAL((s1_lsb+2), s1_lsb, s))
333
334#define NS_MND_BANKED8(n0_lsb, n1_lsb, n, m, s0_lsb, s1_lsb, s) \
335 (BVAL((n0_lsb+7), n0_lsb, ~(n-m)) \
336 | BVAL((n1_lsb+7), n1_lsb, ~(n-m)) \
337 | BVAL((s0_lsb+2), s0_lsb, s) \
338 | BVAL((s1_lsb+2), s1_lsb, s))
339
340#define NS_DIVSRC_BANKED(d0_msb, d0_lsb, d1_msb, d1_lsb, d, \
341 s0_msb, s0_lsb, s1_msb, s1_lsb, s) \
342 (BVAL(d0_msb, d0_lsb, (d-1)) | BVAL(d1_msb, d1_lsb, (d-1)) \
343 | BVAL(s0_msb, s0_lsb, s) \
344 | BVAL(s1_msb, s1_lsb, s))
345
346/* CC Registers */
347#define CC(mde_lsb, n) (BVAL((mde_lsb+1), mde_lsb, MN_MODE_DUAL_EDGE) * !!(n))
348#define CC_BANKED(mde0_lsb, mde1_lsb, n) \
349 ((BVAL((mde0_lsb+1), mde0_lsb, MN_MODE_DUAL_EDGE) \
350 | BVAL((mde1_lsb+1), mde1_lsb, MN_MODE_DUAL_EDGE)) \
351 * !!(n))
352
353struct pll_rate {
354 const uint32_t l_val;
355 const uint32_t m_val;
356 const uint32_t n_val;
357 const uint32_t vco;
358 const uint32_t post_div;
359 const uint32_t i_bits;
360};
361#define PLL_RATE(l, m, n, v, d, i) { l, m, n, v, (d>>1), i }
362
363/*
364 * Clock Descriptions
365 */
366
367static struct msm_xo_voter *xo_pxo, *xo_cxo;
368
369static int pxo_clk_enable(struct clk *clk)
370{
371 return msm_xo_mode_vote(xo_pxo, MSM_XO_MODE_ON);
372}
373
374static void pxo_clk_disable(struct clk *clk)
375{
376 msm_xo_mode_vote(xo_pxo, MSM_XO_MODE_OFF);
377}
378
379static struct clk_ops clk_ops_pxo = {
380 .enable = pxo_clk_enable,
381 .disable = pxo_clk_disable,
382 .get_rate = fixed_clk_get_rate,
383 .is_local = local_clk_is_local,
384};
385
386static struct fixed_clk pxo_clk = {
387 .rate = 27000000,
388 .c = {
389 .dbg_name = "pxo_clk",
390 .ops = &clk_ops_pxo,
391 CLK_INIT(pxo_clk.c),
392 },
393};
394
395static int cxo_clk_enable(struct clk *clk)
396{
397 return msm_xo_mode_vote(xo_cxo, MSM_XO_MODE_ON);
398}
399
400static void cxo_clk_disable(struct clk *clk)
401{
402 msm_xo_mode_vote(xo_cxo, MSM_XO_MODE_OFF);
403}
404
405static struct clk_ops clk_ops_cxo = {
406 .enable = cxo_clk_enable,
407 .disable = cxo_clk_disable,
408 .get_rate = fixed_clk_get_rate,
409 .is_local = local_clk_is_local,
410};
411
412static struct fixed_clk cxo_clk = {
413 .rate = 19200000,
414 .c = {
415 .dbg_name = "cxo_clk",
416 .ops = &clk_ops_cxo,
417 CLK_INIT(cxo_clk.c),
418 },
419};
420
421static struct pll_clk pll2_clk = {
422 .rate = 800000000,
423 .mode_reg = MM_PLL1_MODE_REG,
424 .parent = &pxo_clk.c,
425 .c = {
426 .dbg_name = "pll2_clk",
427 .ops = &clk_ops_pll,
428 CLK_INIT(pll2_clk.c),
429 },
430};
431
Stephen Boyd94625ef2011-07-12 17:06:01 -0700432static struct pll_clk pll3_clk = {
433 .rate = 1200000000,
434 .mode_reg = BB_MMCC_PLL2_MODE_REG,
435 .parent = &pxo_clk.c,
436 .c = {
437 .dbg_name = "pll3_clk",
438 .ops = &clk_ops_pll,
439 CLK_INIT(pll3_clk.c),
440 },
441};
442
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700443static struct pll_vote_clk pll4_clk = {
444 .rate = 393216000,
445 .en_reg = BB_PLL_ENA_SC0_REG,
446 .en_mask = BIT(4),
447 .status_reg = LCC_PLL0_STATUS_REG,
448 .parent = &pxo_clk.c,
449 .c = {
450 .dbg_name = "pll4_clk",
451 .ops = &clk_ops_pll_vote,
452 CLK_INIT(pll4_clk.c),
453 },
454};
455
456static struct pll_vote_clk pll8_clk = {
457 .rate = 384000000,
458 .en_reg = BB_PLL_ENA_SC0_REG,
459 .en_mask = BIT(8),
460 .status_reg = BB_PLL8_STATUS_REG,
461 .parent = &pxo_clk.c,
462 .c = {
463 .dbg_name = "pll8_clk",
464 .ops = &clk_ops_pll_vote,
465 CLK_INIT(pll8_clk.c),
466 },
467};
468
Stephen Boyd94625ef2011-07-12 17:06:01 -0700469static struct pll_vote_clk pll14_clk = {
470 .rate = 480000000,
471 .en_reg = BB_PLL_ENA_SC0_REG,
472 .en_mask = BIT(14),
473 .status_reg = BB_PLL14_STATUS_REG,
474 .parent = &pxo_clk.c,
475 .c = {
476 .dbg_name = "pll14_clk",
477 .ops = &clk_ops_pll_vote,
478 CLK_INIT(pll14_clk.c),
479 },
480};
481
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700482/*
483 * SoC-specific functions required by clock-local driver
484 */
485
486/* Update the sys_vdd voltage given a level. */
487static int msm8960_update_sys_vdd(enum sys_vdd_level level)
488{
489 static const int vdd_uv[] = {
Matt Wagantallb6f30f02011-09-07 16:48:56 -0700490 [NONE] = 0,
491 [LOW] = 945000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700492 [NOMINAL] = 1050000,
493 [HIGH] = 1150000,
494 };
495
496 return rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S3, RPM_VREG_VOTER3,
497 vdd_uv[level], vdd_uv[HIGH], 1);
498}
499
500static int soc_clk_reset(struct clk *clk, enum clk_reset_action action)
501{
502 return branch_reset(&to_rcg_clk(clk)->b, action);
503}
504
Matt Wagantall84f43fd2011-08-16 23:28:38 -0700505static struct clk_ops clk_ops_rcg_8960 = {
Matt Wagantall0625ea02011-07-13 18:51:56 -0700506 .enable = rcg_clk_enable,
507 .disable = rcg_clk_disable,
508 .auto_off = rcg_clk_auto_off,
Matt Wagantall53d968f2011-07-19 13:22:53 -0700509 .handoff = rcg_clk_handoff,
Matt Wagantall0625ea02011-07-13 18:51:56 -0700510 .set_rate = rcg_clk_set_rate,
511 .set_min_rate = rcg_clk_set_min_rate,
Matt Wagantall0625ea02011-07-13 18:51:56 -0700512 .get_rate = rcg_clk_get_rate,
513 .list_rate = rcg_clk_list_rate,
514 .is_enabled = rcg_clk_is_enabled,
515 .round_rate = rcg_clk_round_rate,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700516 .reset = soc_clk_reset,
517 .is_local = local_clk_is_local,
Matt Wagantall0625ea02011-07-13 18:51:56 -0700518 .get_parent = rcg_clk_get_parent,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700519};
520
521static struct clk_ops clk_ops_branch = {
522 .enable = branch_clk_enable,
523 .disable = branch_clk_disable,
524 .auto_off = branch_clk_auto_off,
525 .is_enabled = branch_clk_is_enabled,
526 .reset = branch_clk_reset,
527 .is_local = local_clk_is_local,
528 .get_parent = branch_clk_get_parent,
529 .set_parent = branch_clk_set_parent,
530};
531
532static struct clk_ops clk_ops_reset = {
533 .reset = branch_clk_reset,
534 .is_local = local_clk_is_local,
535};
536
537/* AXI Interfaces */
538static struct branch_clk gmem_axi_clk = {
539 .b = {
540 .ctl_reg = MAXI_EN_REG,
541 .en_mask = BIT(24),
542 .halt_reg = DBG_BUS_VEC_E_REG,
543 .halt_bit = 6,
544 },
545 .c = {
546 .dbg_name = "gmem_axi_clk",
547 .ops = &clk_ops_branch,
548 CLK_INIT(gmem_axi_clk.c),
549 },
550};
551
552static struct branch_clk ijpeg_axi_clk = {
553 .b = {
554 .ctl_reg = MAXI_EN_REG,
555 .en_mask = BIT(21),
556 .reset_reg = SW_RESET_AXI_REG,
557 .reset_mask = BIT(14),
558 .halt_reg = DBG_BUS_VEC_E_REG,
559 .halt_bit = 4,
560 },
561 .c = {
562 .dbg_name = "ijpeg_axi_clk",
563 .ops = &clk_ops_branch,
564 CLK_INIT(ijpeg_axi_clk.c),
565 },
566};
567
568static struct branch_clk imem_axi_clk = {
569 .b = {
570 .ctl_reg = MAXI_EN_REG,
571 .en_mask = BIT(22),
572 .reset_reg = SW_RESET_CORE_REG,
573 .reset_mask = BIT(10),
574 .halt_reg = DBG_BUS_VEC_E_REG,
575 .halt_bit = 7,
576 },
577 .c = {
578 .dbg_name = "imem_axi_clk",
579 .ops = &clk_ops_branch,
580 CLK_INIT(imem_axi_clk.c),
581 },
582};
583
584static struct branch_clk jpegd_axi_clk = {
585 .b = {
586 .ctl_reg = MAXI_EN_REG,
587 .en_mask = BIT(25),
588 .halt_reg = DBG_BUS_VEC_E_REG,
589 .halt_bit = 5,
590 },
591 .c = {
592 .dbg_name = "jpegd_axi_clk",
593 .ops = &clk_ops_branch,
594 CLK_INIT(jpegd_axi_clk.c),
595 },
596};
597
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700598static struct branch_clk vcodec_axi_b_clk = {
599 .b = {
600 .ctl_reg = MAXI_EN4_REG,
601 .en_mask = BIT(23),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700602 .halt_reg = DBG_BUS_VEC_I_REG,
603 .halt_bit = 25,
604 },
605 .c = {
606 .dbg_name = "vcodec_axi_b_clk",
607 .ops = &clk_ops_branch,
608 CLK_INIT(vcodec_axi_b_clk.c),
609 },
610};
611
Matt Wagantall91f42702011-07-14 12:01:15 -0700612static struct branch_clk vcodec_axi_a_clk = {
613 .b = {
614 .ctl_reg = MAXI_EN4_REG,
615 .en_mask = BIT(25),
Matt Wagantall91f42702011-07-14 12:01:15 -0700616 .halt_reg = DBG_BUS_VEC_I_REG,
617 .halt_bit = 26,
618 },
Matt Wagantall91f42702011-07-14 12:01:15 -0700619 .c = {
620 .dbg_name = "vcodec_axi_a_clk",
621 .ops = &clk_ops_branch,
622 CLK_INIT(vcodec_axi_a_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -0700623 .depends = &vcodec_axi_b_clk.c,
Matt Wagantall91f42702011-07-14 12:01:15 -0700624 },
625};
626
627static struct branch_clk vcodec_axi_clk = {
628 .b = {
629 .ctl_reg = MAXI_EN_REG,
630 .en_mask = BIT(19),
631 .reset_reg = SW_RESET_AXI_REG,
Matt Wagantallfe2ee052011-07-14 13:33:44 -0700632 .reset_mask = BIT(4)|BIT(5)|BIT(7),
Matt Wagantall91f42702011-07-14 12:01:15 -0700633 .halt_reg = DBG_BUS_VEC_E_REG,
634 .halt_bit = 3,
635 },
Matt Wagantall91f42702011-07-14 12:01:15 -0700636 .c = {
637 .dbg_name = "vcodec_axi_clk",
638 .ops = &clk_ops_branch,
639 CLK_INIT(vcodec_axi_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -0700640 .depends = &vcodec_axi_a_clk.c,
Matt Wagantall91f42702011-07-14 12:01:15 -0700641 },
642};
643
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700644static struct branch_clk vfe_axi_clk = {
645 .b = {
646 .ctl_reg = MAXI_EN_REG,
647 .en_mask = BIT(18),
648 .reset_reg = SW_RESET_AXI_REG,
649 .reset_mask = BIT(9),
650 .halt_reg = DBG_BUS_VEC_E_REG,
651 .halt_bit = 0,
652 },
653 .c = {
654 .dbg_name = "vfe_axi_clk",
655 .ops = &clk_ops_branch,
656 CLK_INIT(vfe_axi_clk.c),
657 },
658};
659
660static struct branch_clk mdp_axi_clk = {
661 .b = {
662 .ctl_reg = MAXI_EN_REG,
663 .en_mask = BIT(23),
664 .reset_reg = SW_RESET_AXI_REG,
665 .reset_mask = BIT(13),
666 .halt_reg = DBG_BUS_VEC_E_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700667 .halt_bit = 8,
668 },
669 .c = {
670 .dbg_name = "mdp_axi_clk",
671 .ops = &clk_ops_branch,
672 CLK_INIT(mdp_axi_clk.c),
673 },
674};
675
676static struct branch_clk rot_axi_clk = {
677 .b = {
678 .ctl_reg = MAXI_EN2_REG,
679 .en_mask = BIT(24),
680 .reset_reg = SW_RESET_AXI_REG,
681 .reset_mask = BIT(6),
682 .halt_reg = DBG_BUS_VEC_E_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700683 .halt_bit = 2,
684 },
685 .c = {
686 .dbg_name = "rot_axi_clk",
687 .ops = &clk_ops_branch,
688 CLK_INIT(rot_axi_clk.c),
689 },
690};
691
692static struct branch_clk vpe_axi_clk = {
693 .b = {
694 .ctl_reg = MAXI_EN2_REG,
695 .en_mask = BIT(26),
696 .reset_reg = SW_RESET_AXI_REG,
697 .reset_mask = BIT(15),
698 .halt_reg = DBG_BUS_VEC_E_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700699 .halt_bit = 1,
700 },
701 .c = {
702 .dbg_name = "vpe_axi_clk",
703 .ops = &clk_ops_branch,
704 CLK_INIT(vpe_axi_clk.c),
705 },
706};
707
708/* AHB Interfaces */
709static struct branch_clk amp_p_clk = {
710 .b = {
711 .ctl_reg = AHB_EN_REG,
712 .en_mask = BIT(24),
713 .halt_reg = DBG_BUS_VEC_F_REG,
714 .halt_bit = 18,
715 },
716 .c = {
717 .dbg_name = "amp_p_clk",
718 .ops = &clk_ops_branch,
719 CLK_INIT(amp_p_clk.c),
720 },
721};
722
Matt Wagantallc23eee92011-08-16 23:06:52 -0700723static struct branch_clk csi_p_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700724 .b = {
725 .ctl_reg = AHB_EN_REG,
726 .en_mask = BIT(7),
727 .reset_reg = SW_RESET_AHB_REG,
728 .reset_mask = BIT(17),
729 .halt_reg = DBG_BUS_VEC_F_REG,
730 .halt_bit = 16,
731 },
732 .c = {
Matt Wagantallc23eee92011-08-16 23:06:52 -0700733 .dbg_name = "csi_p_clk",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700734 .ops = &clk_ops_branch,
Matt Wagantallc23eee92011-08-16 23:06:52 -0700735 CLK_INIT(csi_p_clk.c),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700736 },
737};
738
739static struct branch_clk dsi1_m_p_clk = {
740 .b = {
741 .ctl_reg = AHB_EN_REG,
742 .en_mask = BIT(9),
743 .reset_reg = SW_RESET_AHB_REG,
744 .reset_mask = BIT(6),
745 .halt_reg = DBG_BUS_VEC_F_REG,
746 .halt_bit = 19,
747 },
748 .c = {
749 .dbg_name = "dsi1_m_p_clk",
750 .ops = &clk_ops_branch,
751 CLK_INIT(dsi1_m_p_clk.c),
752 },
753};
754
755static struct branch_clk dsi1_s_p_clk = {
756 .b = {
757 .ctl_reg = AHB_EN_REG,
758 .en_mask = BIT(18),
759 .reset_reg = SW_RESET_AHB_REG,
760 .reset_mask = BIT(5),
761 .halt_reg = DBG_BUS_VEC_F_REG,
762 .halt_bit = 21,
763 },
764 .c = {
765 .dbg_name = "dsi1_s_p_clk",
766 .ops = &clk_ops_branch,
767 CLK_INIT(dsi1_s_p_clk.c),
768 },
769};
770
771static struct branch_clk dsi2_m_p_clk = {
772 .b = {
773 .ctl_reg = AHB_EN_REG,
774 .en_mask = BIT(17),
775 .reset_reg = SW_RESET_AHB2_REG,
776 .reset_mask = BIT(1),
777 .halt_reg = DBG_BUS_VEC_E_REG,
778 .halt_bit = 18,
779 },
780 .c = {
781 .dbg_name = "dsi2_m_p_clk",
782 .ops = &clk_ops_branch,
783 CLK_INIT(dsi2_m_p_clk.c),
784 },
785};
786
787static struct branch_clk dsi2_s_p_clk = {
788 .b = {
789 .ctl_reg = AHB_EN_REG,
790 .en_mask = BIT(22),
791 .reset_reg = SW_RESET_AHB2_REG,
792 .reset_mask = BIT(0),
793 .halt_reg = DBG_BUS_VEC_F_REG,
794 .halt_bit = 20,
795 },
796 .c = {
797 .dbg_name = "dsi2_s_p_clk",
798 .ops = &clk_ops_branch,
799 CLK_INIT(dsi2_s_p_clk.c),
800 },
801};
802
803static struct branch_clk gfx2d0_p_clk = {
804 .b = {
805 .ctl_reg = AHB_EN_REG,
806 .en_mask = BIT(19),
807 .reset_reg = SW_RESET_AHB_REG,
808 .reset_mask = BIT(12),
809 .halt_reg = DBG_BUS_VEC_F_REG,
810 .halt_bit = 2,
811 },
812 .c = {
813 .dbg_name = "gfx2d0_p_clk",
814 .ops = &clk_ops_branch,
815 CLK_INIT(gfx2d0_p_clk.c),
816 },
817};
818
819static struct branch_clk gfx2d1_p_clk = {
820 .b = {
821 .ctl_reg = AHB_EN_REG,
822 .en_mask = BIT(2),
823 .reset_reg = SW_RESET_AHB_REG,
824 .reset_mask = BIT(11),
825 .halt_reg = DBG_BUS_VEC_F_REG,
826 .halt_bit = 3,
827 },
828 .c = {
829 .dbg_name = "gfx2d1_p_clk",
830 .ops = &clk_ops_branch,
831 CLK_INIT(gfx2d1_p_clk.c),
832 },
833};
834
835static struct branch_clk gfx3d_p_clk = {
836 .b = {
837 .ctl_reg = AHB_EN_REG,
838 .en_mask = BIT(3),
839 .reset_reg = SW_RESET_AHB_REG,
840 .reset_mask = BIT(10),
841 .halt_reg = DBG_BUS_VEC_F_REG,
842 .halt_bit = 4,
843 },
844 .c = {
845 .dbg_name = "gfx3d_p_clk",
846 .ops = &clk_ops_branch,
847 CLK_INIT(gfx3d_p_clk.c),
848 },
849};
850
851static struct branch_clk hdmi_m_p_clk = {
852 .b = {
853 .ctl_reg = AHB_EN_REG,
854 .en_mask = BIT(14),
855 .reset_reg = SW_RESET_AHB_REG,
856 .reset_mask = BIT(9),
857 .halt_reg = DBG_BUS_VEC_F_REG,
858 .halt_bit = 5,
859 },
860 .c = {
861 .dbg_name = "hdmi_m_p_clk",
862 .ops = &clk_ops_branch,
863 CLK_INIT(hdmi_m_p_clk.c),
864 },
865};
866
867static struct branch_clk hdmi_s_p_clk = {
868 .b = {
869 .ctl_reg = AHB_EN_REG,
870 .en_mask = BIT(4),
871 .reset_reg = SW_RESET_AHB_REG,
872 .reset_mask = BIT(9),
873 .halt_reg = DBG_BUS_VEC_F_REG,
874 .halt_bit = 6,
875 },
876 .c = {
877 .dbg_name = "hdmi_s_p_clk",
878 .ops = &clk_ops_branch,
879 CLK_INIT(hdmi_s_p_clk.c),
880 },
881};
882
883static struct branch_clk ijpeg_p_clk = {
884 .b = {
885 .ctl_reg = AHB_EN_REG,
886 .en_mask = BIT(5),
887 .reset_reg = SW_RESET_AHB_REG,
888 .reset_mask = BIT(7),
889 .halt_reg = DBG_BUS_VEC_F_REG,
890 .halt_bit = 9,
891 },
892 .c = {
893 .dbg_name = "ijpeg_p_clk",
894 .ops = &clk_ops_branch,
895 CLK_INIT(ijpeg_p_clk.c),
896 },
897};
898
899static struct branch_clk imem_p_clk = {
900 .b = {
901 .ctl_reg = AHB_EN_REG,
902 .en_mask = BIT(6),
903 .reset_reg = SW_RESET_AHB_REG,
904 .reset_mask = BIT(8),
905 .halt_reg = DBG_BUS_VEC_F_REG,
906 .halt_bit = 10,
907 },
908 .c = {
909 .dbg_name = "imem_p_clk",
910 .ops = &clk_ops_branch,
911 CLK_INIT(imem_p_clk.c),
912 },
913};
914
915static struct branch_clk jpegd_p_clk = {
916 .b = {
917 .ctl_reg = AHB_EN_REG,
918 .en_mask = BIT(21),
919 .reset_reg = SW_RESET_AHB_REG,
920 .reset_mask = BIT(4),
921 .halt_reg = DBG_BUS_VEC_F_REG,
922 .halt_bit = 7,
923 },
924 .c = {
925 .dbg_name = "jpegd_p_clk",
926 .ops = &clk_ops_branch,
927 CLK_INIT(jpegd_p_clk.c),
928 },
929};
930
931static struct branch_clk mdp_p_clk = {
932 .b = {
933 .ctl_reg = AHB_EN_REG,
934 .en_mask = BIT(10),
935 .reset_reg = SW_RESET_AHB_REG,
936 .reset_mask = BIT(3),
937 .halt_reg = DBG_BUS_VEC_F_REG,
938 .halt_bit = 11,
939 },
940 .c = {
941 .dbg_name = "mdp_p_clk",
942 .ops = &clk_ops_branch,
943 CLK_INIT(mdp_p_clk.c),
944 },
945};
946
947static struct branch_clk rot_p_clk = {
948 .b = {
949 .ctl_reg = AHB_EN_REG,
950 .en_mask = BIT(12),
951 .reset_reg = SW_RESET_AHB_REG,
952 .reset_mask = BIT(2),
953 .halt_reg = DBG_BUS_VEC_F_REG,
954 .halt_bit = 13,
955 },
956 .c = {
957 .dbg_name = "rot_p_clk",
958 .ops = &clk_ops_branch,
959 CLK_INIT(rot_p_clk.c),
960 },
961};
962
963static struct branch_clk smmu_p_clk = {
964 .b = {
965 .ctl_reg = AHB_EN_REG,
966 .en_mask = BIT(15),
967 .halt_reg = DBG_BUS_VEC_F_REG,
968 .halt_bit = 22,
969 },
970 .c = {
971 .dbg_name = "smmu_p_clk",
972 .ops = &clk_ops_branch,
973 CLK_INIT(smmu_p_clk.c),
974 },
975};
976
977static struct branch_clk tv_enc_p_clk = {
978 .b = {
979 .ctl_reg = AHB_EN_REG,
980 .en_mask = BIT(25),
981 .reset_reg = SW_RESET_AHB_REG,
982 .reset_mask = BIT(15),
983 .halt_reg = DBG_BUS_VEC_F_REG,
984 .halt_bit = 23,
985 },
986 .c = {
987 .dbg_name = "tv_enc_p_clk",
988 .ops = &clk_ops_branch,
989 CLK_INIT(tv_enc_p_clk.c),
990 },
991};
992
993static struct branch_clk vcodec_p_clk = {
994 .b = {
995 .ctl_reg = AHB_EN_REG,
996 .en_mask = BIT(11),
997 .reset_reg = SW_RESET_AHB_REG,
998 .reset_mask = BIT(1),
999 .halt_reg = DBG_BUS_VEC_F_REG,
1000 .halt_bit = 12,
1001 },
1002 .c = {
1003 .dbg_name = "vcodec_p_clk",
1004 .ops = &clk_ops_branch,
1005 CLK_INIT(vcodec_p_clk.c),
1006 },
1007};
1008
1009static struct branch_clk vfe_p_clk = {
1010 .b = {
1011 .ctl_reg = AHB_EN_REG,
1012 .en_mask = BIT(13),
1013 .reset_reg = SW_RESET_AHB_REG,
1014 .reset_mask = BIT(0),
1015 .halt_reg = DBG_BUS_VEC_F_REG,
1016 .halt_bit = 14,
1017 },
1018 .c = {
1019 .dbg_name = "vfe_p_clk",
1020 .ops = &clk_ops_branch,
1021 CLK_INIT(vfe_p_clk.c),
1022 },
1023};
1024
1025static struct branch_clk vpe_p_clk = {
1026 .b = {
1027 .ctl_reg = AHB_EN_REG,
1028 .en_mask = BIT(16),
1029 .reset_reg = SW_RESET_AHB_REG,
1030 .reset_mask = BIT(14),
1031 .halt_reg = DBG_BUS_VEC_F_REG,
1032 .halt_bit = 15,
1033 },
1034 .c = {
1035 .dbg_name = "vpe_p_clk",
1036 .ops = &clk_ops_branch,
1037 CLK_INIT(vpe_p_clk.c),
1038 },
1039};
1040
1041/*
1042 * Peripheral Clocks
1043 */
1044#define CLK_GSBI_UART(i, n, h_r, h_b) \
1045 struct rcg_clk i##_clk = { \
1046 .b = { \
1047 .ctl_reg = GSBIn_UART_APPS_NS_REG(n), \
1048 .en_mask = BIT(9), \
1049 .reset_reg = GSBIn_RESET_REG(n), \
1050 .reset_mask = BIT(0), \
1051 .halt_reg = h_r, \
1052 .halt_bit = h_b, \
1053 }, \
1054 .ns_reg = GSBIn_UART_APPS_NS_REG(n), \
1055 .md_reg = GSBIn_UART_APPS_MD_REG(n), \
1056 .root_en_mask = BIT(11), \
1057 .ns_mask = (BM(31, 16) | BM(6, 0)), \
1058 .set_rate = set_rate_mnd, \
1059 .freq_tbl = clk_tbl_gsbi_uart, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001060 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001061 .c = { \
1062 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001063 .ops = &clk_ops_rcg_8960, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001064 CLK_INIT(i##_clk.c), \
1065 }, \
1066 }
1067#define F_GSBI_UART(f, s, d, m, n, v) \
1068 { \
1069 .freq_hz = f, \
1070 .src_clk = &s##_clk.c, \
1071 .md_val = MD16(m, n), \
1072 .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
1073 .mnd_en_mask = BIT(8) * !!(n), \
1074 .sys_vdd = v, \
1075 }
1076static struct clk_freq_tbl clk_tbl_gsbi_uart[] = {
1077 F_GSBI_UART( 0, gnd, 1, 0, 0, NONE),
1078 F_GSBI_UART( 1843200, pll8, 1, 3, 625, LOW),
1079 F_GSBI_UART( 3686400, pll8, 1, 6, 625, LOW),
1080 F_GSBI_UART( 7372800, pll8, 1, 12, 625, LOW),
1081 F_GSBI_UART(14745600, pll8, 1, 24, 625, LOW),
1082 F_GSBI_UART(16000000, pll8, 4, 1, 6, LOW),
1083 F_GSBI_UART(24000000, pll8, 4, 1, 4, LOW),
1084 F_GSBI_UART(32000000, pll8, 4, 1, 3, LOW),
1085 F_GSBI_UART(40000000, pll8, 1, 5, 48, NOMINAL),
1086 F_GSBI_UART(46400000, pll8, 1, 29, 240, NOMINAL),
1087 F_GSBI_UART(48000000, pll8, 4, 1, 2, NOMINAL),
1088 F_GSBI_UART(51200000, pll8, 1, 2, 15, NOMINAL),
1089 F_GSBI_UART(56000000, pll8, 1, 7, 48, NOMINAL),
1090 F_GSBI_UART(58982400, pll8, 1, 96, 625, NOMINAL),
1091 F_GSBI_UART(64000000, pll8, 2, 1, 3, NOMINAL),
1092 F_END
1093};
1094
1095static CLK_GSBI_UART(gsbi1_uart, 1, CLK_HALT_CFPB_STATEA_REG, 10);
1096static CLK_GSBI_UART(gsbi2_uart, 2, CLK_HALT_CFPB_STATEA_REG, 6);
1097static CLK_GSBI_UART(gsbi3_uart, 3, CLK_HALT_CFPB_STATEA_REG, 2);
1098static CLK_GSBI_UART(gsbi4_uart, 4, CLK_HALT_CFPB_STATEB_REG, 26);
1099static CLK_GSBI_UART(gsbi5_uart, 5, CLK_HALT_CFPB_STATEB_REG, 22);
1100static CLK_GSBI_UART(gsbi6_uart, 6, CLK_HALT_CFPB_STATEB_REG, 18);
1101static CLK_GSBI_UART(gsbi7_uart, 7, CLK_HALT_CFPB_STATEB_REG, 14);
1102static CLK_GSBI_UART(gsbi8_uart, 8, CLK_HALT_CFPB_STATEB_REG, 10);
1103static CLK_GSBI_UART(gsbi9_uart, 9, CLK_HALT_CFPB_STATEB_REG, 6);
1104static CLK_GSBI_UART(gsbi10_uart, 10, CLK_HALT_CFPB_STATEB_REG, 2);
1105static CLK_GSBI_UART(gsbi11_uart, 11, CLK_HALT_CFPB_STATEC_REG, 17);
1106static CLK_GSBI_UART(gsbi12_uart, 12, CLK_HALT_CFPB_STATEC_REG, 13);
1107
1108#define CLK_GSBI_QUP(i, n, h_r, h_b) \
1109 struct rcg_clk i##_clk = { \
1110 .b = { \
1111 .ctl_reg = GSBIn_QUP_APPS_NS_REG(n), \
1112 .en_mask = BIT(9), \
1113 .reset_reg = GSBIn_RESET_REG(n), \
1114 .reset_mask = BIT(0), \
1115 .halt_reg = h_r, \
1116 .halt_bit = h_b, \
1117 }, \
1118 .ns_reg = GSBIn_QUP_APPS_NS_REG(n), \
1119 .md_reg = GSBIn_QUP_APPS_MD_REG(n), \
1120 .root_en_mask = BIT(11), \
1121 .ns_mask = (BM(23, 16) | BM(6, 0)), \
1122 .set_rate = set_rate_mnd, \
1123 .freq_tbl = clk_tbl_gsbi_qup, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001124 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001125 .c = { \
1126 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001127 .ops = &clk_ops_rcg_8960, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001128 CLK_INIT(i##_clk.c), \
1129 }, \
1130 }
1131#define F_GSBI_QUP(f, s, d, m, n, v) \
1132 { \
1133 .freq_hz = f, \
1134 .src_clk = &s##_clk.c, \
1135 .md_val = MD8(16, m, 0, n), \
1136 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
1137 .mnd_en_mask = BIT(8) * !!(n), \
1138 .sys_vdd = v, \
1139 }
1140static struct clk_freq_tbl clk_tbl_gsbi_qup[] = {
1141 F_GSBI_QUP( 0, gnd, 1, 0, 0, NONE),
1142 F_GSBI_QUP( 1100000, pxo, 1, 2, 49, LOW),
1143 F_GSBI_QUP( 5400000, pxo, 1, 1, 5, LOW),
1144 F_GSBI_QUP(10800000, pxo, 1, 2, 5, LOW),
1145 F_GSBI_QUP(15060000, pll8, 1, 2, 51, LOW),
1146 F_GSBI_QUP(24000000, pll8, 4, 1, 4, LOW),
1147 F_GSBI_QUP(25600000, pll8, 1, 1, 15, NOMINAL),
1148 F_GSBI_QUP(27000000, pxo, 1, 0, 0, NOMINAL),
1149 F_GSBI_QUP(48000000, pll8, 4, 1, 2, NOMINAL),
1150 F_GSBI_QUP(51200000, pll8, 1, 2, 15, NOMINAL),
1151 F_END
1152};
1153
1154static CLK_GSBI_QUP(gsbi1_qup, 1, CLK_HALT_CFPB_STATEA_REG, 9);
1155static CLK_GSBI_QUP(gsbi2_qup, 2, CLK_HALT_CFPB_STATEA_REG, 4);
1156static CLK_GSBI_QUP(gsbi3_qup, 3, CLK_HALT_CFPB_STATEA_REG, 0);
1157static CLK_GSBI_QUP(gsbi4_qup, 4, CLK_HALT_CFPB_STATEB_REG, 24);
1158static CLK_GSBI_QUP(gsbi5_qup, 5, CLK_HALT_CFPB_STATEB_REG, 20);
1159static CLK_GSBI_QUP(gsbi6_qup, 6, CLK_HALT_CFPB_STATEB_REG, 16);
1160static CLK_GSBI_QUP(gsbi7_qup, 7, CLK_HALT_CFPB_STATEB_REG, 12);
1161static CLK_GSBI_QUP(gsbi8_qup, 8, CLK_HALT_CFPB_STATEB_REG, 8);
1162static CLK_GSBI_QUP(gsbi9_qup, 9, CLK_HALT_CFPB_STATEB_REG, 4);
1163static CLK_GSBI_QUP(gsbi10_qup, 10, CLK_HALT_CFPB_STATEB_REG, 0);
1164static CLK_GSBI_QUP(gsbi11_qup, 11, CLK_HALT_CFPB_STATEC_REG, 15);
1165static CLK_GSBI_QUP(gsbi12_qup, 12, CLK_HALT_CFPB_STATEC_REG, 11);
1166
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001167#define F_QDSS(f, s, d, v) \
1168 { \
1169 .freq_hz = f, \
1170 .src_clk = &s##_clk.c, \
1171 .ns_val = NS_DIVSRC(6, 3, d, 2, 0, s##_to_bb_mux), \
1172 .sys_vdd = v, \
1173 }
1174static struct clk_freq_tbl clk_tbl_qdss[] = {
Stephen Boydd4de6d72011-09-13 13:01:40 -07001175 F_QDSS( 27000000, pxo, 1, LOW),
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001176 F_QDSS(128000000, pll8, 3, LOW),
1177 F_QDSS(300000000, pll3, 4, NOMINAL),
1178 F_END
1179};
1180
1181struct qdss_bank {
1182 const u32 bank_sel_mask;
1183 void __iomem *const ns_reg;
1184 const u32 ns_mask;
1185};
1186
Stephen Boydd4de6d72011-09-13 13:01:40 -07001187#define QDSS_CLK_ROOT_ENA BIT(1)
1188
1189static void qdss_clk_handoff(struct clk *c)
1190{
1191 struct rcg_clk *clk = to_rcg_clk(c);
1192 const struct qdss_bank *bank = clk->bank_info;
1193 u32 reg, ns_val, bank_sel;
1194 struct clk_freq_tbl *freq;
1195
1196 reg = readl_relaxed(clk->ns_reg);
1197 if (!(reg & QDSS_CLK_ROOT_ENA))
1198 return;
1199
1200 bank_sel = reg & bank->bank_sel_mask;
1201 /* Force bank 1 to PXO if bank 0 is in use */
1202 if (bank_sel == 0)
1203 writel_relaxed(0, bank->ns_reg);
1204 ns_val = readl_relaxed(bank->ns_reg) & bank->ns_mask;
1205 for (freq = clk->freq_tbl; freq->freq_hz != FREQ_END; freq++) {
1206 if ((freq->ns_val & bank->ns_mask) == ns_val) {
1207 pr_info("%s rate=%d\n", clk->c.dbg_name, freq->freq_hz);
1208 break;
1209 }
1210 }
1211 if (freq->freq_hz == FREQ_END)
1212 return;
1213
1214 clk->current_freq = freq;
1215 c->flags |= CLKFLAG_HANDOFF_RATE;
1216 clk_enable(c);
1217}
1218
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001219static void set_rate_qdss(struct rcg_clk *clk, struct clk_freq_tbl *nf)
1220{
1221 const struct qdss_bank *bank = clk->bank_info;
1222 u32 reg, bank_sel_mask = bank->bank_sel_mask;
1223
1224 /* Switch to bank 0 (always sourced from PXO) */
1225 reg = readl_relaxed(clk->ns_reg);
1226 reg &= ~bank_sel_mask;
1227 writel_relaxed(reg, clk->ns_reg);
1228 /*
1229 * Wait at least 6 cycles of slowest bank's clock for the glitch-free
1230 * MUX to fully switch sources.
1231 */
1232 mb();
1233 udelay(1);
1234
1235 /* Set source and divider */
1236 reg = readl_relaxed(bank->ns_reg);
1237 reg &= ~bank->ns_mask;
1238 reg |= nf->ns_val;
1239 writel_relaxed(reg, bank->ns_reg);
1240
1241 /* Switch to reprogrammed bank */
1242 reg = readl_relaxed(clk->ns_reg);
1243 reg |= bank_sel_mask;
1244 writel_relaxed(reg, clk->ns_reg);
1245 /*
1246 * Wait at least 6 cycles of slowest bank's clock for the glitch-free
1247 * MUX to fully switch sources.
1248 */
1249 mb();
1250 udelay(1);
1251}
1252
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001253static int qdss_clk_enable(struct clk *c)
1254{
1255 struct rcg_clk *clk = to_rcg_clk(c);
1256 const struct qdss_bank *bank = clk->bank_info;
1257 u32 reg, bank_sel_mask = bank->bank_sel_mask;
1258 int ret;
1259
1260 /* Switch to bank 1 */
1261 reg = readl_relaxed(clk->ns_reg);
1262 reg |= bank_sel_mask;
1263 writel_relaxed(reg, clk->ns_reg);
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001264
1265 ret = rcg_clk_enable(c);
1266 if (ret) {
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001267 /* Switch to bank 0 */
1268 reg &= ~bank_sel_mask;
1269 writel_relaxed(reg, clk->ns_reg);
1270 }
1271 return ret;
1272}
1273
1274static void qdss_clk_disable(struct clk *c)
1275{
1276 struct rcg_clk *clk = to_rcg_clk(c);
1277 const struct qdss_bank *bank = clk->bank_info;
1278 u32 reg, bank_sel_mask = bank->bank_sel_mask;
1279
1280 rcg_clk_disable(c);
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001281 /* Switch to bank 0 */
Stephen Boyddbeca472011-09-12 19:21:22 -07001282 reg = readl_relaxed(clk->ns_reg);
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001283 reg &= ~bank_sel_mask;
1284 writel_relaxed(reg, clk->ns_reg);
1285}
1286
1287static void qdss_clk_auto_off(struct clk *c)
1288{
1289 struct rcg_clk *clk = to_rcg_clk(c);
1290 const struct qdss_bank *bank = clk->bank_info;
1291 u32 reg, bank_sel_mask = bank->bank_sel_mask;
1292
1293 rcg_clk_auto_off(c);
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001294 /* Switch to bank 0 */
Stephen Boyddbeca472011-09-12 19:21:22 -07001295 reg = readl_relaxed(clk->ns_reg);
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001296 reg &= ~bank_sel_mask;
1297 writel_relaxed(reg, clk->ns_reg);
1298}
1299
1300static struct clk_ops clk_ops_qdss = {
1301 .enable = qdss_clk_enable,
1302 .disable = qdss_clk_disable,
1303 .auto_off = qdss_clk_auto_off,
Stephen Boydd4de6d72011-09-13 13:01:40 -07001304 .handoff = qdss_clk_handoff,
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001305 .set_rate = rcg_clk_set_rate,
1306 .set_min_rate = rcg_clk_set_min_rate,
1307 .get_rate = rcg_clk_get_rate,
1308 .list_rate = rcg_clk_list_rate,
1309 .is_enabled = rcg_clk_is_enabled,
1310 .round_rate = rcg_clk_round_rate,
1311 .reset = soc_clk_reset,
1312 .is_local = local_clk_is_local,
1313 .get_parent = rcg_clk_get_parent,
1314};
1315
1316static struct qdss_bank bdiv_info_qdss = {
1317 .bank_sel_mask = BIT(0),
1318 .ns_reg = QDSS_AT_CLK_SRC1_NS_REG,
1319 .ns_mask = BM(6, 0),
1320};
1321
1322static struct rcg_clk qdss_at_clk = {
1323 .b = {
1324 .ctl_reg = QDSS_AT_CLK_NS_REG,
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001325 .reset_reg = QDSS_RESETS_REG,
1326 .reset_mask = BIT(0),
Stephen Boydfcfd4dd2011-09-13 12:49:57 -07001327 .halt_check = NOCHECK,
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001328 },
1329 .ns_reg = QDSS_AT_CLK_SRC_CTL_REG,
1330 .set_rate = set_rate_qdss,
1331 .freq_tbl = clk_tbl_qdss,
1332 .bank_info = &bdiv_info_qdss,
1333 .current_freq = &rcg_dummy_freq,
1334 .c = {
1335 .dbg_name = "qdss_at_clk",
1336 .ops = &clk_ops_qdss,
1337 CLK_INIT(qdss_at_clk.c),
1338 },
1339};
1340
1341static struct branch_clk qdss_pclkdbg_clk = {
1342 .b = {
1343 .ctl_reg = QDSS_AT_CLK_NS_REG,
1344 .en_mask = BIT(4),
1345 .reset_reg = QDSS_RESETS_REG,
1346 .reset_mask = BIT(0),
1347 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
1348 .halt_bit = 9,
1349 .halt_check = HALT_VOTED
1350 },
1351 .parent = &qdss_at_clk.c,
1352 .c = {
1353 .dbg_name = "qdss_pclkdbg_clk",
1354 .ops = &clk_ops_branch,
1355 CLK_INIT(qdss_pclkdbg_clk.c),
1356 },
1357};
1358
1359static struct qdss_bank bdiv_info_qdss_trace = {
1360 .bank_sel_mask = BIT(0),
1361 .ns_reg = QDSS_TRACECLKIN_CLK_SRC1_NS_REG,
1362 .ns_mask = BM(6, 0),
1363};
1364
1365static struct rcg_clk qdss_traceclkin_clk = {
1366 .b = {
1367 .ctl_reg = QDSS_TRACECLKIN_CTL_REG,
1368 .en_mask = BIT(4),
1369 .reset_reg = QDSS_RESETS_REG,
1370 .reset_mask = BIT(0),
1371 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
1372 .halt_bit = 8,
1373 .halt_check = HALT_VOTED,
1374 },
1375 .ns_reg = QDSS_TRACECLKIN_CLK_SRC_CTL_REG,
1376 .set_rate = set_rate_qdss,
1377 .freq_tbl = clk_tbl_qdss,
1378 .bank_info = &bdiv_info_qdss_trace,
1379 .current_freq = &rcg_dummy_freq,
1380 .c = {
1381 .dbg_name = "qdss_traceclkin_clk",
1382 .ops = &clk_ops_qdss,
1383 CLK_INIT(qdss_traceclkin_clk.c),
1384 },
1385};
1386
1387static struct clk_freq_tbl clk_tbl_qdss_tsctr[] = {
Stephen Boydd4de6d72011-09-13 13:01:40 -07001388 F_QDSS( 27000000, pxo, 1, LOW),
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001389 F_QDSS(200000000, pll3, 6, LOW),
1390 F_QDSS(400000000, pll3, 3, NOMINAL),
1391 F_END
1392};
1393
1394static struct qdss_bank bdiv_info_qdss_tsctr = {
1395 .bank_sel_mask = BIT(0),
1396 .ns_reg = QDSS_TSCTR_CLK_SRC1_NS_REG,
1397 .ns_mask = BM(6, 0),
1398};
1399
1400static struct rcg_clk qdss_tsctr_clk = {
1401 .b = {
1402 .ctl_reg = QDSS_TSCTR_CTL_REG,
1403 .en_mask = BIT(4),
1404 .reset_reg = QDSS_RESETS_REG,
1405 .reset_mask = BIT(3),
1406 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
1407 .halt_bit = 7,
1408 .halt_check = HALT_VOTED,
1409 },
1410 .ns_reg = QDSS_TSCTR_CLK_SRC_CTL_REG,
1411 .set_rate = set_rate_qdss,
1412 .freq_tbl = clk_tbl_qdss_tsctr,
1413 .bank_info = &bdiv_info_qdss_tsctr,
1414 .current_freq = &rcg_dummy_freq,
1415 .c = {
1416 .dbg_name = "qdss_tsctr_clk",
1417 .ops = &clk_ops_qdss,
1418 CLK_INIT(qdss_tsctr_clk.c),
1419 },
1420};
1421
1422static struct branch_clk qdss_stm_clk = {
1423 .b = {
1424 .ctl_reg = QDSS_STM_CLK_CTL_REG,
1425 .en_mask = BIT(4),
1426 .reset_reg = QDSS_RESETS_REG,
1427 .reset_mask = BIT(1),
1428 .halt_reg = CLK_HALT_AFAB_SFAB_STATEB_REG,
1429 .halt_bit = 20,
1430 .halt_check = HALT_VOTED,
1431 },
1432 .c = {
1433 .dbg_name = "qdss_stm_clk",
1434 .ops = &clk_ops_branch,
1435 CLK_INIT(qdss_stm_clk.c),
1436 },
1437};
1438
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001439#define F_PDM(f, s, d, v) \
1440 { \
1441 .freq_hz = f, \
1442 .src_clk = &s##_clk.c, \
1443 .ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
1444 .sys_vdd = v, \
1445 }
1446static struct clk_freq_tbl clk_tbl_pdm[] = {
1447 F_PDM( 0, gnd, 1, NONE),
1448 F_PDM(27000000, pxo, 1, LOW),
1449 F_END
1450};
1451
1452static struct rcg_clk pdm_clk = {
1453 .b = {
1454 .ctl_reg = PDM_CLK_NS_REG,
1455 .en_mask = BIT(9),
1456 .reset_reg = PDM_CLK_NS_REG,
1457 .reset_mask = BIT(12),
1458 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1459 .halt_bit = 3,
1460 },
1461 .ns_reg = PDM_CLK_NS_REG,
1462 .root_en_mask = BIT(11),
1463 .ns_mask = BM(1, 0),
1464 .set_rate = set_rate_nop,
1465 .freq_tbl = clk_tbl_pdm,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001466 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001467 .c = {
1468 .dbg_name = "pdm_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001469 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001470 CLK_INIT(pdm_clk.c),
1471 },
1472};
1473
1474static struct branch_clk pmem_clk = {
1475 .b = {
1476 .ctl_reg = PMEM_ACLK_CTL_REG,
1477 .en_mask = BIT(4),
1478 .halt_reg = CLK_HALT_DFAB_STATE_REG,
1479 .halt_bit = 20,
1480 },
1481 .c = {
1482 .dbg_name = "pmem_clk",
1483 .ops = &clk_ops_branch,
1484 CLK_INIT(pmem_clk.c),
1485 },
1486};
1487
1488#define F_PRNG(f, s, v) \
1489 { \
1490 .freq_hz = f, \
1491 .src_clk = &s##_clk.c, \
1492 .sys_vdd = v, \
1493 }
1494static struct clk_freq_tbl clk_tbl_prng[] = {
1495 F_PRNG(64000000, pll8, NOMINAL),
1496 F_END
1497};
1498
1499static struct rcg_clk prng_clk = {
1500 .b = {
1501 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
1502 .en_mask = BIT(10),
1503 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
1504 .halt_check = HALT_VOTED,
1505 .halt_bit = 10,
1506 },
1507 .set_rate = set_rate_nop,
1508 .freq_tbl = clk_tbl_prng,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001509 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001510 .c = {
1511 .dbg_name = "prng_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001512 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001513 CLK_INIT(prng_clk.c),
1514 },
1515};
1516
Stephen Boyda78a7402011-08-02 11:23:39 -07001517#define CLK_SDC(name, n, h_b, f_table) \
1518 struct rcg_clk name = { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001519 .b = { \
1520 .ctl_reg = SDCn_APPS_CLK_NS_REG(n), \
1521 .en_mask = BIT(9), \
1522 .reset_reg = SDCn_RESET_REG(n), \
1523 .reset_mask = BIT(0), \
Stephen Boyda78a7402011-08-02 11:23:39 -07001524 .halt_reg = CLK_HALT_DFAB_STATE_REG, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001525 .halt_bit = h_b, \
1526 }, \
1527 .ns_reg = SDCn_APPS_CLK_NS_REG(n), \
1528 .md_reg = SDCn_APPS_CLK_MD_REG(n), \
1529 .root_en_mask = BIT(11), \
1530 .ns_mask = (BM(23, 16) | BM(6, 0)), \
1531 .set_rate = set_rate_mnd, \
Stephen Boyda78a7402011-08-02 11:23:39 -07001532 .freq_tbl = f_table, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001533 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001534 .c = { \
Stephen Boyda78a7402011-08-02 11:23:39 -07001535 .dbg_name = #name, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001536 .ops = &clk_ops_rcg_8960, \
Stephen Boyda78a7402011-08-02 11:23:39 -07001537 CLK_INIT(name.c), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001538 }, \
1539 }
1540#define F_SDC(f, s, d, m, n, v) \
1541 { \
1542 .freq_hz = f, \
1543 .src_clk = &s##_clk.c, \
1544 .md_val = MD8(16, m, 0, n), \
1545 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
1546 .mnd_en_mask = BIT(8) * !!(n), \
1547 .sys_vdd = v, \
1548 }
Stephen Boyda78a7402011-08-02 11:23:39 -07001549static struct clk_freq_tbl clk_tbl_sdc1_2[] = {
1550 F_SDC( 0, gnd, 1, 0, 0, NONE),
1551 F_SDC( 144000, pxo, 3, 2, 125, LOW),
1552 F_SDC( 400000, pll8, 4, 1, 240, LOW),
1553 F_SDC( 16000000, pll8, 4, 1, 6, LOW),
1554 F_SDC( 17070000, pll8, 1, 2, 45, LOW),
1555 F_SDC( 20210000, pll8, 1, 1, 19, LOW),
1556 F_SDC( 24000000, pll8, 4, 1, 4, LOW),
1557 F_SDC( 48000000, pll8, 4, 1, 2, LOW),
1558 F_SDC( 64000000, pll8, 3, 1, 2, NOMINAL),
1559 F_SDC( 96000000, pll8, 4, 0, 0, NOMINAL),
1560 F_END
1561};
1562
1563static CLK_SDC(sdc1_clk, 1, 6, clk_tbl_sdc1_2);
1564static CLK_SDC(sdc2_clk, 2, 5, clk_tbl_sdc1_2);
1565
1566static struct clk_freq_tbl clk_tbl_sdc3[] = {
1567 F_SDC( 0, gnd, 1, 0, 0, NONE),
1568 F_SDC( 144000, pxo, 3, 2, 125, LOW),
1569 F_SDC( 400000, pll8, 4, 1, 240, LOW),
1570 F_SDC( 16000000, pll8, 4, 1, 6, LOW),
1571 F_SDC( 17070000, pll8, 1, 2, 45, LOW),
1572 F_SDC( 20210000, pll8, 1, 1, 19, LOW),
1573 F_SDC( 24000000, pll8, 4, 1, 4, LOW),
1574 F_SDC( 48000000, pll8, 4, 1, 2, LOW),
1575 F_SDC( 64000000, pll8, 3, 1, 2, LOW),
1576 F_SDC( 96000000, pll8, 4, 0, 0, LOW),
1577 F_SDC(192000000, pll8, 2, 0, 0, NOMINAL),
1578 F_END
1579};
1580
1581static CLK_SDC(sdc3_clk, 3, 4, clk_tbl_sdc3);
1582
1583static struct clk_freq_tbl clk_tbl_sdc4_5[] = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001584 F_SDC( 0, gnd, 1, 0, 0, NONE),
1585 F_SDC( 144000, pxo, 3, 2, 125, LOW),
1586 F_SDC( 400000, pll8, 4, 1, 240, LOW),
1587 F_SDC( 16000000, pll8, 4, 1, 6, LOW),
1588 F_SDC( 17070000, pll8, 1, 2, 45, LOW),
1589 F_SDC( 20210000, pll8, 1, 1, 19, LOW),
1590 F_SDC( 24000000, pll8, 4, 1, 4, LOW),
1591 F_SDC( 48000000, pll8, 4, 1, 2, NOMINAL),
1592 F_SDC( 64000000, pll8, 3, 1, 2, NOMINAL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001593 F_END
1594};
1595
Stephen Boyda78a7402011-08-02 11:23:39 -07001596static CLK_SDC(sdc4_clk, 4, 3, clk_tbl_sdc4_5);
1597static CLK_SDC(sdc5_clk, 5, 2, clk_tbl_sdc4_5);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001598
1599#define F_TSIF_REF(f, s, d, m, n, v) \
1600 { \
1601 .freq_hz = f, \
1602 .src_clk = &s##_clk.c, \
1603 .md_val = MD16(m, n), \
1604 .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
1605 .mnd_en_mask = BIT(8) * !!(n), \
1606 .sys_vdd = v, \
1607 }
1608static struct clk_freq_tbl clk_tbl_tsif_ref[] = {
1609 F_TSIF_REF( 0, gnd, 1, 0, 0, NONE),
1610 F_TSIF_REF(105000, pxo, 1, 1, 256, LOW),
1611 F_END
1612};
1613
1614static struct rcg_clk tsif_ref_clk = {
1615 .b = {
1616 .ctl_reg = TSIF_REF_CLK_NS_REG,
1617 .en_mask = BIT(9),
1618 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1619 .halt_bit = 5,
1620 },
1621 .ns_reg = TSIF_REF_CLK_NS_REG,
1622 .md_reg = TSIF_REF_CLK_MD_REG,
1623 .root_en_mask = BIT(11),
1624 .ns_mask = (BM(31, 16) | BM(6, 0)),
1625 .set_rate = set_rate_mnd,
1626 .freq_tbl = clk_tbl_tsif_ref,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001627 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001628 .c = {
1629 .dbg_name = "tsif_ref_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001630 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001631 CLK_INIT(tsif_ref_clk.c),
1632 },
1633};
1634
1635#define F_TSSC(f, s, v) \
1636 { \
1637 .freq_hz = f, \
1638 .src_clk = &s##_clk.c, \
1639 .ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
1640 .sys_vdd = v, \
1641 }
1642static struct clk_freq_tbl clk_tbl_tssc[] = {
1643 F_TSSC( 0, gnd, NONE),
1644 F_TSSC(27000000, pxo, LOW),
1645 F_END
1646};
1647
1648static struct rcg_clk tssc_clk = {
1649 .b = {
1650 .ctl_reg = TSSC_CLK_CTL_REG,
1651 .en_mask = BIT(4),
1652 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1653 .halt_bit = 4,
1654 },
1655 .ns_reg = TSSC_CLK_CTL_REG,
1656 .ns_mask = BM(1, 0),
1657 .set_rate = set_rate_nop,
1658 .freq_tbl = clk_tbl_tssc,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001659 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001660 .c = {
1661 .dbg_name = "tssc_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001662 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001663 CLK_INIT(tssc_clk.c),
1664 },
1665};
1666
1667#define F_USB(f, s, d, m, n, v) \
1668 { \
1669 .freq_hz = f, \
1670 .src_clk = &s##_clk.c, \
1671 .md_val = MD8(16, m, 0, n), \
1672 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
1673 .mnd_en_mask = BIT(8) * !!(n), \
1674 .sys_vdd = v, \
1675 }
1676static struct clk_freq_tbl clk_tbl_usb[] = {
1677 F_USB( 0, gnd, 1, 0, 0, NONE),
1678 F_USB(60000000, pll8, 1, 5, 32, NOMINAL),
1679 F_END
1680};
1681
1682static struct rcg_clk usb_hs1_xcvr_clk = {
1683 .b = {
1684 .ctl_reg = USB_HS1_XCVR_FS_CLK_NS_REG,
1685 .en_mask = BIT(9),
1686 .reset_reg = USB_HS1_RESET_REG,
1687 .reset_mask = BIT(0),
1688 .halt_reg = CLK_HALT_DFAB_STATE_REG,
1689 .halt_bit = 0,
1690 },
1691 .ns_reg = USB_HS1_XCVR_FS_CLK_NS_REG,
1692 .md_reg = USB_HS1_XCVR_FS_CLK_MD_REG,
1693 .root_en_mask = BIT(11),
1694 .ns_mask = (BM(23, 16) | BM(6, 0)),
1695 .set_rate = set_rate_mnd,
1696 .freq_tbl = clk_tbl_usb,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001697 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001698 .c = {
1699 .dbg_name = "usb_hs1_xcvr_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001700 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001701 CLK_INIT(usb_hs1_xcvr_clk.c),
1702 },
1703};
1704
Stephen Boyd94625ef2011-07-12 17:06:01 -07001705static struct clk_freq_tbl clk_tbl_usb_hsic[] = {
1706 F_USB( 0, gnd, 1, 0, 0, NONE),
1707 F_USB(60000000, pll8, 1, 5, 32, LOW),
1708 F_END
1709};
1710
1711static struct rcg_clk usb_hsic_xcvr_fs_clk = {
1712 .b = {
1713 .ctl_reg = USB_HSIC_XCVR_FS_CLK_NS_REG,
1714 .en_mask = BIT(9),
1715 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1716 .halt_bit = 26,
1717 },
1718 .ns_reg = USB_HSIC_XCVR_FS_CLK_NS_REG,
1719 .md_reg = USB_HSIC_XCVR_FS_CLK_MD_REG,
1720 .root_en_mask = BIT(11),
1721 .ns_mask = (BM(23, 16) | BM(6, 0)),
1722 .set_rate = set_rate_mnd,
1723 .freq_tbl = clk_tbl_usb_hsic,
1724 .current_freq = &rcg_dummy_freq,
1725 .c = {
1726 .dbg_name = "usb_hsic_xcvr_fs_clk",
1727 .ops = &clk_ops_rcg_8960,
1728 CLK_INIT(usb_hsic_xcvr_fs_clk.c),
1729 },
1730};
1731
1732static struct branch_clk usb_hsic_system_clk = {
1733 .b = {
1734 .ctl_reg = USB_HSIC_SYSTEM_CLK_CTL_REG,
1735 .en_mask = BIT(4),
1736 .reset_reg = USB_HSIC_RESET_REG,
1737 .reset_mask = BIT(0),
1738 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1739 .halt_bit = 24,
1740 },
1741 .parent = &usb_hsic_xcvr_fs_clk.c,
1742 .c = {
1743 .dbg_name = "usb_hsic_system_clk",
1744 .ops = &clk_ops_branch,
1745 CLK_INIT(usb_hsic_system_clk.c),
1746 },
1747};
1748
1749#define F_USB_HSIC(f, s, v) \
1750 { \
1751 .freq_hz = f, \
1752 .src_clk = &s##_clk.c, \
1753 .sys_vdd = v, \
1754 }
1755static struct clk_freq_tbl clk_tbl_usb2_hsic[] = {
1756 F_USB_HSIC(480000000, pll14, LOW),
1757 F_END
1758};
1759
1760static struct rcg_clk usb_hsic_hsic_src_clk = {
1761 .b = {
1762 .ctl_reg = USB_HSIC_HSIC_CLK_SRC_CTL_REG,
1763 .halt_check = NOCHECK,
1764 },
1765 .root_en_mask = BIT(0),
1766 .set_rate = set_rate_nop,
1767 .freq_tbl = clk_tbl_usb2_hsic,
1768 .current_freq = &rcg_dummy_freq,
1769 .c = {
1770 .dbg_name = "usb_hsic_hsic_src_clk",
1771 .ops = &clk_ops_rcg_8960,
1772 CLK_INIT(usb_hsic_hsic_src_clk.c),
1773 },
1774};
1775
1776static struct branch_clk usb_hsic_hsic_clk = {
1777 .b = {
1778 .ctl_reg = USB_HSIC_HSIC_CLK_CTL_REG,
1779 .en_mask = BIT(0),
1780 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1781 .halt_bit = 19,
1782 },
1783 .parent = &usb_hsic_hsic_src_clk.c,
1784 .c = {
1785 .dbg_name = "usb_hsic_hsic_clk",
1786 .ops = &clk_ops_branch,
1787 CLK_INIT(usb_hsic_hsic_clk.c),
1788 },
1789};
1790
1791#define F_USB_HSIO_CAL(f, s, v) \
1792 { \
1793 .freq_hz = f, \
1794 .src_clk = &s##_clk.c, \
1795 .sys_vdd = v, \
1796 }
1797static struct clk_freq_tbl clk_tbl_usb_hsio_cal[] = {
1798 F_USB_HSIO_CAL(9000000, pxo, LOW),
1799 F_END
1800};
1801
1802static struct rcg_clk usb_hsic_hsio_cal_clk = {
1803 .b = {
1804 .ctl_reg = USB_HSIC_HSIO_CAL_CLK_CTL_REG,
1805 .en_mask = BIT(0),
1806 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1807 .halt_bit = 23,
1808 },
1809 .set_rate = set_rate_nop,
1810 .freq_tbl = clk_tbl_usb_hsio_cal,
1811 .current_freq = &rcg_dummy_freq,
1812 .c = {
1813 .dbg_name = "usb_hsic_hsio_cal_clk",
1814 .ops = &clk_ops_branch,
1815 CLK_INIT(usb_hsic_hsio_cal_clk.c),
1816 },
1817};
1818
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001819static struct branch_clk usb_phy0_clk = {
1820 .b = {
1821 .reset_reg = USB_PHY0_RESET_REG,
1822 .reset_mask = BIT(0),
1823 },
1824 .c = {
1825 .dbg_name = "usb_phy0_clk",
1826 .ops = &clk_ops_reset,
1827 CLK_INIT(usb_phy0_clk.c),
1828 },
1829};
1830
1831#define CLK_USB_FS(i, n) \
1832 struct rcg_clk i##_clk = { \
1833 .ns_reg = USB_FSn_XCVR_FS_CLK_NS_REG(n), \
1834 .b = { \
1835 .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(n), \
1836 .halt_check = NOCHECK, \
1837 }, \
1838 .md_reg = USB_FSn_XCVR_FS_CLK_MD_REG(n), \
1839 .root_en_mask = BIT(11), \
1840 .ns_mask = (BM(23, 16) | BM(6, 0)), \
1841 .set_rate = set_rate_mnd, \
1842 .freq_tbl = clk_tbl_usb, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001843 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001844 .c = { \
1845 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001846 .ops = &clk_ops_rcg_8960, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001847 CLK_INIT(i##_clk.c), \
1848 }, \
1849 }
1850
1851static CLK_USB_FS(usb_fs1_src, 1);
1852static struct branch_clk usb_fs1_xcvr_clk = {
1853 .b = {
1854 .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(1),
1855 .en_mask = BIT(9),
1856 .reset_reg = USB_FSn_RESET_REG(1),
1857 .reset_mask = BIT(1),
1858 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1859 .halt_bit = 15,
1860 },
1861 .parent = &usb_fs1_src_clk.c,
1862 .c = {
1863 .dbg_name = "usb_fs1_xcvr_clk",
1864 .ops = &clk_ops_branch,
1865 CLK_INIT(usb_fs1_xcvr_clk.c),
1866 },
1867};
1868
1869static struct branch_clk usb_fs1_sys_clk = {
1870 .b = {
1871 .ctl_reg = USB_FSn_SYSTEM_CLK_CTL_REG(1),
1872 .en_mask = BIT(4),
1873 .reset_reg = USB_FSn_RESET_REG(1),
1874 .reset_mask = BIT(0),
1875 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1876 .halt_bit = 16,
1877 },
1878 .parent = &usb_fs1_src_clk.c,
1879 .c = {
1880 .dbg_name = "usb_fs1_sys_clk",
1881 .ops = &clk_ops_branch,
1882 CLK_INIT(usb_fs1_sys_clk.c),
1883 },
1884};
1885
1886static CLK_USB_FS(usb_fs2_src, 2);
1887static struct branch_clk usb_fs2_xcvr_clk = {
1888 .b = {
1889 .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(2),
1890 .en_mask = BIT(9),
1891 .reset_reg = USB_FSn_RESET_REG(2),
1892 .reset_mask = BIT(1),
1893 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1894 .halt_bit = 12,
1895 },
1896 .parent = &usb_fs2_src_clk.c,
1897 .c = {
1898 .dbg_name = "usb_fs2_xcvr_clk",
1899 .ops = &clk_ops_branch,
1900 CLK_INIT(usb_fs2_xcvr_clk.c),
1901 },
1902};
1903
1904static struct branch_clk usb_fs2_sys_clk = {
1905 .b = {
1906 .ctl_reg = USB_FSn_SYSTEM_CLK_CTL_REG(2),
1907 .en_mask = BIT(4),
1908 .reset_reg = USB_FSn_RESET_REG(2),
1909 .reset_mask = BIT(0),
1910 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1911 .halt_bit = 13,
1912 },
1913 .parent = &usb_fs2_src_clk.c,
1914 .c = {
1915 .dbg_name = "usb_fs2_sys_clk",
1916 .ops = &clk_ops_branch,
1917 CLK_INIT(usb_fs2_sys_clk.c),
1918 },
1919};
1920
1921/* Fast Peripheral Bus Clocks */
1922static struct branch_clk ce1_core_clk = {
1923 .b = {
1924 .ctl_reg = CE1_CORE_CLK_CTL_REG,
1925 .en_mask = BIT(4),
1926 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1927 .halt_bit = 27,
1928 },
1929 .c = {
1930 .dbg_name = "ce1_core_clk",
1931 .ops = &clk_ops_branch,
1932 CLK_INIT(ce1_core_clk.c),
1933 },
1934};
1935static struct branch_clk ce1_p_clk = {
1936 .b = {
1937 .ctl_reg = CE1_HCLK_CTL_REG,
1938 .en_mask = BIT(4),
1939 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1940 .halt_bit = 1,
1941 },
1942 .c = {
1943 .dbg_name = "ce1_p_clk",
1944 .ops = &clk_ops_branch,
1945 CLK_INIT(ce1_p_clk.c),
1946 },
1947};
1948
1949static struct branch_clk dma_bam_p_clk = {
1950 .b = {
1951 .ctl_reg = DMA_BAM_HCLK_CTL,
1952 .en_mask = BIT(4),
1953 .halt_reg = CLK_HALT_DFAB_STATE_REG,
1954 .halt_bit = 12,
1955 },
1956 .c = {
1957 .dbg_name = "dma_bam_p_clk",
1958 .ops = &clk_ops_branch,
1959 CLK_INIT(dma_bam_p_clk.c),
1960 },
1961};
1962
1963static struct branch_clk gsbi1_p_clk = {
1964 .b = {
1965 .ctl_reg = GSBIn_HCLK_CTL_REG(1),
1966 .en_mask = BIT(4),
1967 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1968 .halt_bit = 11,
1969 },
1970 .c = {
1971 .dbg_name = "gsbi1_p_clk",
1972 .ops = &clk_ops_branch,
1973 CLK_INIT(gsbi1_p_clk.c),
1974 },
1975};
1976
1977static struct branch_clk gsbi2_p_clk = {
1978 .b = {
1979 .ctl_reg = GSBIn_HCLK_CTL_REG(2),
1980 .en_mask = BIT(4),
1981 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1982 .halt_bit = 7,
1983 },
1984 .c = {
1985 .dbg_name = "gsbi2_p_clk",
1986 .ops = &clk_ops_branch,
1987 CLK_INIT(gsbi2_p_clk.c),
1988 },
1989};
1990
1991static struct branch_clk gsbi3_p_clk = {
1992 .b = {
1993 .ctl_reg = GSBIn_HCLK_CTL_REG(3),
1994 .en_mask = BIT(4),
1995 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1996 .halt_bit = 3,
1997 },
1998 .c = {
1999 .dbg_name = "gsbi3_p_clk",
2000 .ops = &clk_ops_branch,
2001 CLK_INIT(gsbi3_p_clk.c),
2002 },
2003};
2004
2005static struct branch_clk gsbi4_p_clk = {
2006 .b = {
2007 .ctl_reg = GSBIn_HCLK_CTL_REG(4),
2008 .en_mask = BIT(4),
2009 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2010 .halt_bit = 27,
2011 },
2012 .c = {
2013 .dbg_name = "gsbi4_p_clk",
2014 .ops = &clk_ops_branch,
2015 CLK_INIT(gsbi4_p_clk.c),
2016 },
2017};
2018
2019static struct branch_clk gsbi5_p_clk = {
2020 .b = {
2021 .ctl_reg = GSBIn_HCLK_CTL_REG(5),
2022 .en_mask = BIT(4),
2023 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2024 .halt_bit = 23,
2025 },
2026 .c = {
2027 .dbg_name = "gsbi5_p_clk",
2028 .ops = &clk_ops_branch,
2029 CLK_INIT(gsbi5_p_clk.c),
2030 },
2031};
2032
2033static struct branch_clk gsbi6_p_clk = {
2034 .b = {
2035 .ctl_reg = GSBIn_HCLK_CTL_REG(6),
2036 .en_mask = BIT(4),
2037 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2038 .halt_bit = 19,
2039 },
2040 .c = {
2041 .dbg_name = "gsbi6_p_clk",
2042 .ops = &clk_ops_branch,
2043 CLK_INIT(gsbi6_p_clk.c),
2044 },
2045};
2046
2047static struct branch_clk gsbi7_p_clk = {
2048 .b = {
2049 .ctl_reg = GSBIn_HCLK_CTL_REG(7),
2050 .en_mask = BIT(4),
2051 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2052 .halt_bit = 15,
2053 },
2054 .c = {
2055 .dbg_name = "gsbi7_p_clk",
2056 .ops = &clk_ops_branch,
2057 CLK_INIT(gsbi7_p_clk.c),
2058 },
2059};
2060
2061static struct branch_clk gsbi8_p_clk = {
2062 .b = {
2063 .ctl_reg = GSBIn_HCLK_CTL_REG(8),
2064 .en_mask = BIT(4),
2065 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2066 .halt_bit = 11,
2067 },
2068 .c = {
2069 .dbg_name = "gsbi8_p_clk",
2070 .ops = &clk_ops_branch,
2071 CLK_INIT(gsbi8_p_clk.c),
2072 },
2073};
2074
2075static struct branch_clk gsbi9_p_clk = {
2076 .b = {
2077 .ctl_reg = GSBIn_HCLK_CTL_REG(9),
2078 .en_mask = BIT(4),
2079 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2080 .halt_bit = 7,
2081 },
2082 .c = {
2083 .dbg_name = "gsbi9_p_clk",
2084 .ops = &clk_ops_branch,
2085 CLK_INIT(gsbi9_p_clk.c),
2086 },
2087};
2088
2089static struct branch_clk gsbi10_p_clk = {
2090 .b = {
2091 .ctl_reg = GSBIn_HCLK_CTL_REG(10),
2092 .en_mask = BIT(4),
2093 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2094 .halt_bit = 3,
2095 },
2096 .c = {
2097 .dbg_name = "gsbi10_p_clk",
2098 .ops = &clk_ops_branch,
2099 CLK_INIT(gsbi10_p_clk.c),
2100 },
2101};
2102
2103static struct branch_clk gsbi11_p_clk = {
2104 .b = {
2105 .ctl_reg = GSBIn_HCLK_CTL_REG(11),
2106 .en_mask = BIT(4),
2107 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2108 .halt_bit = 18,
2109 },
2110 .c = {
2111 .dbg_name = "gsbi11_p_clk",
2112 .ops = &clk_ops_branch,
2113 CLK_INIT(gsbi11_p_clk.c),
2114 },
2115};
2116
2117static struct branch_clk gsbi12_p_clk = {
2118 .b = {
2119 .ctl_reg = GSBIn_HCLK_CTL_REG(12),
2120 .en_mask = BIT(4),
2121 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2122 .halt_bit = 14,
2123 },
2124 .c = {
2125 .dbg_name = "gsbi12_p_clk",
2126 .ops = &clk_ops_branch,
2127 CLK_INIT(gsbi12_p_clk.c),
2128 },
2129};
2130
Stephen Boyd973e4ba2011-07-12 17:06:01 -07002131static struct branch_clk qdss_p_clk = {
2132 .b = {
2133 .ctl_reg = QDSS_HCLK_CTL_REG,
2134 .en_mask = BIT(4),
2135 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2136 .halt_bit = 11,
2137 .halt_check = HALT_VOTED,
2138 .reset_reg = QDSS_RESETS_REG,
2139 .reset_mask = BIT(2),
2140 },
2141 .c = {
2142 .dbg_name = "qdss_p_clk",
2143 .ops = &clk_ops_branch,
2144 CLK_INIT(qdss_p_clk.c),
2145 },
2146};
2147
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002148static struct branch_clk tsif_p_clk = {
2149 .b = {
2150 .ctl_reg = TSIF_HCLK_CTL_REG,
2151 .en_mask = BIT(4),
2152 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2153 .halt_bit = 7,
2154 },
2155 .c = {
2156 .dbg_name = "tsif_p_clk",
2157 .ops = &clk_ops_branch,
2158 CLK_INIT(tsif_p_clk.c),
2159 },
2160};
2161
2162static struct branch_clk usb_fs1_p_clk = {
2163 .b = {
2164 .ctl_reg = USB_FSn_HCLK_CTL_REG(1),
2165 .en_mask = BIT(4),
2166 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2167 .halt_bit = 17,
2168 },
2169 .c = {
2170 .dbg_name = "usb_fs1_p_clk",
2171 .ops = &clk_ops_branch,
2172 CLK_INIT(usb_fs1_p_clk.c),
2173 },
2174};
2175
2176static struct branch_clk usb_fs2_p_clk = {
2177 .b = {
2178 .ctl_reg = USB_FSn_HCLK_CTL_REG(2),
2179 .en_mask = BIT(4),
2180 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2181 .halt_bit = 14,
2182 },
2183 .c = {
2184 .dbg_name = "usb_fs2_p_clk",
2185 .ops = &clk_ops_branch,
2186 CLK_INIT(usb_fs2_p_clk.c),
2187 },
2188};
2189
2190static struct branch_clk usb_hs1_p_clk = {
2191 .b = {
2192 .ctl_reg = USB_HS1_HCLK_CTL_REG,
2193 .en_mask = BIT(4),
2194 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2195 .halt_bit = 1,
2196 },
2197 .c = {
2198 .dbg_name = "usb_hs1_p_clk",
2199 .ops = &clk_ops_branch,
2200 CLK_INIT(usb_hs1_p_clk.c),
2201 },
2202};
2203
Stephen Boyd94625ef2011-07-12 17:06:01 -07002204static struct branch_clk usb_hsic_p_clk = {
2205 .b = {
2206 .ctl_reg = USB_HSIC_HCLK_CTL_REG,
2207 .en_mask = BIT(4),
2208 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2209 .halt_bit = 28,
2210 },
2211 .c = {
2212 .dbg_name = "usb_hsic_p_clk",
2213 .ops = &clk_ops_branch,
2214 CLK_INIT(usb_hsic_p_clk.c),
2215 },
2216};
2217
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002218static struct branch_clk sdc1_p_clk = {
2219 .b = {
2220 .ctl_reg = SDCn_HCLK_CTL_REG(1),
2221 .en_mask = BIT(4),
2222 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2223 .halt_bit = 11,
2224 },
2225 .c = {
2226 .dbg_name = "sdc1_p_clk",
2227 .ops = &clk_ops_branch,
2228 CLK_INIT(sdc1_p_clk.c),
2229 },
2230};
2231
2232static struct branch_clk sdc2_p_clk = {
2233 .b = {
2234 .ctl_reg = SDCn_HCLK_CTL_REG(2),
2235 .en_mask = BIT(4),
2236 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2237 .halt_bit = 10,
2238 },
2239 .c = {
2240 .dbg_name = "sdc2_p_clk",
2241 .ops = &clk_ops_branch,
2242 CLK_INIT(sdc2_p_clk.c),
2243 },
2244};
2245
2246static struct branch_clk sdc3_p_clk = {
2247 .b = {
2248 .ctl_reg = SDCn_HCLK_CTL_REG(3),
2249 .en_mask = BIT(4),
2250 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2251 .halt_bit = 9,
2252 },
2253 .c = {
2254 .dbg_name = "sdc3_p_clk",
2255 .ops = &clk_ops_branch,
2256 CLK_INIT(sdc3_p_clk.c),
2257 },
2258};
2259
2260static struct branch_clk sdc4_p_clk = {
2261 .b = {
2262 .ctl_reg = SDCn_HCLK_CTL_REG(4),
2263 .en_mask = BIT(4),
2264 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2265 .halt_bit = 8,
2266 },
2267 .c = {
2268 .dbg_name = "sdc4_p_clk",
2269 .ops = &clk_ops_branch,
2270 CLK_INIT(sdc4_p_clk.c),
2271 },
2272};
2273
2274static struct branch_clk sdc5_p_clk = {
2275 .b = {
2276 .ctl_reg = SDCn_HCLK_CTL_REG(5),
2277 .en_mask = BIT(4),
2278 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2279 .halt_bit = 7,
2280 },
2281 .c = {
2282 .dbg_name = "sdc5_p_clk",
2283 .ops = &clk_ops_branch,
2284 CLK_INIT(sdc5_p_clk.c),
2285 },
2286};
2287
2288/* HW-Voteable Clocks */
2289static struct branch_clk adm0_clk = {
2290 .b = {
2291 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2292 .en_mask = BIT(2),
2293 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
2294 .halt_check = HALT_VOTED,
2295 .halt_bit = 14,
2296 },
2297 .c = {
2298 .dbg_name = "adm0_clk",
2299 .ops = &clk_ops_branch,
2300 CLK_INIT(adm0_clk.c),
2301 },
2302};
2303
2304static struct branch_clk adm0_p_clk = {
2305 .b = {
2306 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2307 .en_mask = BIT(3),
2308 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
2309 .halt_check = HALT_VOTED,
2310 .halt_bit = 13,
2311 },
2312 .c = {
2313 .dbg_name = "adm0_p_clk",
2314 .ops = &clk_ops_branch,
2315 CLK_INIT(adm0_p_clk.c),
2316 },
2317};
2318
2319static struct branch_clk pmic_arb0_p_clk = {
2320 .b = {
2321 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2322 .en_mask = BIT(8),
2323 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2324 .halt_check = HALT_VOTED,
2325 .halt_bit = 22,
2326 },
2327 .c = {
2328 .dbg_name = "pmic_arb0_p_clk",
2329 .ops = &clk_ops_branch,
2330 CLK_INIT(pmic_arb0_p_clk.c),
2331 },
2332};
2333
2334static struct branch_clk pmic_arb1_p_clk = {
2335 .b = {
2336 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2337 .en_mask = BIT(9),
2338 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2339 .halt_check = HALT_VOTED,
2340 .halt_bit = 21,
2341 },
2342 .c = {
2343 .dbg_name = "pmic_arb1_p_clk",
2344 .ops = &clk_ops_branch,
2345 CLK_INIT(pmic_arb1_p_clk.c),
2346 },
2347};
2348
2349static struct branch_clk pmic_ssbi2_clk = {
2350 .b = {
2351 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2352 .en_mask = BIT(7),
2353 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2354 .halt_check = HALT_VOTED,
2355 .halt_bit = 23,
2356 },
2357 .c = {
2358 .dbg_name = "pmic_ssbi2_clk",
2359 .ops = &clk_ops_branch,
2360 CLK_INIT(pmic_ssbi2_clk.c),
2361 },
2362};
2363
2364static struct branch_clk rpm_msg_ram_p_clk = {
2365 .b = {
2366 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2367 .en_mask = BIT(6),
2368 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2369 .halt_check = HALT_VOTED,
2370 .halt_bit = 12,
2371 },
2372 .c = {
2373 .dbg_name = "rpm_msg_ram_p_clk",
2374 .ops = &clk_ops_branch,
2375 CLK_INIT(rpm_msg_ram_p_clk.c),
2376 },
2377};
2378
2379/*
2380 * Multimedia Clocks
2381 */
2382
2383static struct branch_clk amp_clk = {
2384 .b = {
2385 .reset_reg = SW_RESET_CORE_REG,
2386 .reset_mask = BIT(20),
2387 },
2388 .c = {
2389 .dbg_name = "amp_clk",
2390 .ops = &clk_ops_reset,
2391 CLK_INIT(amp_clk.c),
2392 },
2393};
2394
Stephen Boyd94625ef2011-07-12 17:06:01 -07002395#define CLK_CAM(name, n, hb) \
2396 struct rcg_clk name = { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002397 .b = { \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002398 .ctl_reg = CAMCLK##n##_CC_REG, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002399 .en_mask = BIT(0), \
2400 .halt_reg = DBG_BUS_VEC_I_REG, \
2401 .halt_bit = hb, \
2402 }, \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002403 .ns_reg = CAMCLK##n##_NS_REG, \
2404 .md_reg = CAMCLK##n##_MD_REG, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002405 .root_en_mask = BIT(2), \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002406 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002407 .ctl_mask = BM(7, 6), \
2408 .set_rate = set_rate_mnd_8, \
2409 .freq_tbl = clk_tbl_cam, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002410 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002411 .c = { \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002412 .dbg_name = #name, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002413 .ops = &clk_ops_rcg_8960, \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002414 CLK_INIT(name.c), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002415 }, \
2416 }
2417#define F_CAM(f, s, d, m, n, v) \
2418 { \
2419 .freq_hz = f, \
2420 .src_clk = &s##_clk.c, \
2421 .md_val = MD8(8, m, 0, n), \
2422 .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
2423 .ctl_val = CC(6, n), \
2424 .mnd_en_mask = BIT(5) * !!(n), \
2425 .sys_vdd = v, \
2426 }
2427static struct clk_freq_tbl clk_tbl_cam[] = {
2428 F_CAM( 0, gnd, 1, 0, 0, NONE),
2429 F_CAM( 6000000, pll8, 4, 1, 16, LOW),
2430 F_CAM( 8000000, pll8, 4, 1, 12, LOW),
2431 F_CAM( 12000000, pll8, 4, 1, 8, LOW),
2432 F_CAM( 16000000, pll8, 4, 1, 6, LOW),
2433 F_CAM( 19200000, pll8, 4, 1, 5, LOW),
2434 F_CAM( 24000000, pll8, 4, 1, 4, LOW),
2435 F_CAM( 32000000, pll8, 4, 1, 3, LOW),
2436 F_CAM( 48000000, pll8, 4, 1, 2, LOW),
2437 F_CAM( 64000000, pll8, 3, 1, 2, LOW),
2438 F_CAM( 96000000, pll8, 4, 0, 0, NOMINAL),
2439 F_CAM(128000000, pll8, 3, 0, 0, NOMINAL),
2440 F_END
2441};
2442
Stephen Boyd94625ef2011-07-12 17:06:01 -07002443static CLK_CAM(cam0_clk, 0, 15);
2444static CLK_CAM(cam1_clk, 1, 16);
2445static CLK_CAM(cam2_clk, 2, 31);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002446
2447#define F_CSI(f, s, d, m, n, v) \
2448 { \
2449 .freq_hz = f, \
2450 .src_clk = &s##_clk.c, \
2451 .md_val = MD8(8, m, 0, n), \
2452 .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
2453 .ctl_val = CC(6, n), \
2454 .mnd_en_mask = BIT(5) * !!(n), \
2455 .sys_vdd = v, \
2456 }
2457static struct clk_freq_tbl clk_tbl_csi[] = {
2458 F_CSI( 0, gnd, 1, 0, 0, NONE),
2459 F_CSI( 85330000, pll8, 1, 2, 9, LOW),
2460 F_CSI(177780000, pll2, 1, 2, 9, NOMINAL),
2461 F_END
2462};
2463
2464static struct rcg_clk csi0_src_clk = {
2465 .ns_reg = CSI0_NS_REG,
2466 .b = {
2467 .ctl_reg = CSI0_CC_REG,
2468 .halt_check = NOCHECK,
2469 },
2470 .md_reg = CSI0_MD_REG,
2471 .root_en_mask = BIT(2),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002472 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002473 .ctl_mask = BM(7, 6),
2474 .set_rate = set_rate_mnd,
2475 .freq_tbl = clk_tbl_csi,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002476 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002477 .c = {
2478 .dbg_name = "csi0_src_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002479 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002480 CLK_INIT(csi0_src_clk.c),
2481 },
2482};
2483
2484static struct branch_clk csi0_clk = {
2485 .b = {
2486 .ctl_reg = CSI0_CC_REG,
2487 .en_mask = BIT(0),
2488 .reset_reg = SW_RESET_CORE_REG,
2489 .reset_mask = BIT(8),
2490 .halt_reg = DBG_BUS_VEC_B_REG,
2491 .halt_bit = 13,
2492 },
2493 .parent = &csi0_src_clk.c,
2494 .c = {
2495 .dbg_name = "csi0_clk",
2496 .ops = &clk_ops_branch,
2497 CLK_INIT(csi0_clk.c),
2498 },
2499};
2500
2501static struct branch_clk csi0_phy_clk = {
2502 .b = {
2503 .ctl_reg = CSI0_CC_REG,
2504 .en_mask = BIT(8),
2505 .reset_reg = SW_RESET_CORE_REG,
2506 .reset_mask = BIT(29),
2507 .halt_reg = DBG_BUS_VEC_I_REG,
2508 .halt_bit = 9,
2509 },
2510 .parent = &csi0_src_clk.c,
2511 .c = {
2512 .dbg_name = "csi0_phy_clk",
2513 .ops = &clk_ops_branch,
2514 CLK_INIT(csi0_phy_clk.c),
2515 },
2516};
2517
2518static struct rcg_clk csi1_src_clk = {
2519 .ns_reg = CSI1_NS_REG,
2520 .b = {
2521 .ctl_reg = CSI1_CC_REG,
2522 .halt_check = NOCHECK,
2523 },
2524 .md_reg = CSI1_MD_REG,
2525 .root_en_mask = BIT(2),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002526 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002527 .ctl_mask = BM(7, 6),
2528 .set_rate = set_rate_mnd,
2529 .freq_tbl = clk_tbl_csi,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002530 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002531 .c = {
2532 .dbg_name = "csi1_src_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002533 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002534 CLK_INIT(csi1_src_clk.c),
2535 },
2536};
2537
2538static struct branch_clk csi1_clk = {
2539 .b = {
2540 .ctl_reg = CSI1_CC_REG,
2541 .en_mask = BIT(0),
2542 .reset_reg = SW_RESET_CORE_REG,
2543 .reset_mask = BIT(18),
2544 .halt_reg = DBG_BUS_VEC_B_REG,
2545 .halt_bit = 14,
2546 },
2547 .parent = &csi1_src_clk.c,
2548 .c = {
2549 .dbg_name = "csi1_clk",
2550 .ops = &clk_ops_branch,
2551 CLK_INIT(csi1_clk.c),
2552 },
2553};
2554
2555static struct branch_clk csi1_phy_clk = {
2556 .b = {
2557 .ctl_reg = CSI1_CC_REG,
2558 .en_mask = BIT(8),
2559 .reset_reg = SW_RESET_CORE_REG,
2560 .reset_mask = BIT(28),
2561 .halt_reg = DBG_BUS_VEC_I_REG,
2562 .halt_bit = 10,
2563 },
2564 .parent = &csi1_src_clk.c,
2565 .c = {
2566 .dbg_name = "csi1_phy_clk",
2567 .ops = &clk_ops_branch,
2568 CLK_INIT(csi1_phy_clk.c),
2569 },
2570};
2571
Stephen Boyd94625ef2011-07-12 17:06:01 -07002572static struct rcg_clk csi2_src_clk = {
2573 .ns_reg = CSI2_NS_REG,
2574 .b = {
2575 .ctl_reg = CSI2_CC_REG,
2576 .halt_check = NOCHECK,
2577 },
2578 .md_reg = CSI2_MD_REG,
2579 .root_en_mask = BIT(2),
2580 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0),
2581 .ctl_mask = BM(7, 6),
2582 .set_rate = set_rate_mnd,
2583 .freq_tbl = clk_tbl_csi,
2584 .current_freq = &rcg_dummy_freq,
2585 .c = {
2586 .dbg_name = "csi2_src_clk",
2587 .ops = &clk_ops_rcg_8960,
2588 CLK_INIT(csi2_src_clk.c),
2589 },
2590};
2591
2592static struct branch_clk csi2_clk = {
2593 .b = {
2594 .ctl_reg = CSI2_CC_REG,
2595 .en_mask = BIT(0),
2596 .reset_reg = SW_RESET_CORE2_REG,
2597 .reset_mask = BIT(2),
2598 .halt_reg = DBG_BUS_VEC_B_REG,
2599 .halt_bit = 29,
2600 },
2601 .parent = &csi2_src_clk.c,
2602 .c = {
2603 .dbg_name = "csi2_clk",
2604 .ops = &clk_ops_branch,
2605 CLK_INIT(csi2_clk.c),
2606 },
2607};
2608
2609static struct branch_clk csi2_phy_clk = {
2610 .b = {
2611 .ctl_reg = CSI2_CC_REG,
2612 .en_mask = BIT(8),
2613 .reset_reg = SW_RESET_CORE_REG,
2614 .reset_mask = BIT(31),
2615 .halt_reg = DBG_BUS_VEC_I_REG,
2616 .halt_bit = 29,
2617 },
2618 .parent = &csi2_src_clk.c,
2619 .c = {
2620 .dbg_name = "csi2_phy_clk",
2621 .ops = &clk_ops_branch,
2622 CLK_INIT(csi2_phy_clk.c),
2623 },
2624};
2625
2626/*
2627 * The csi pix and csi rdi clocks have two bits in two registers to control a
2628 * three input mux. So we have the generic rcg_clk_enable() path handle the
2629 * first bit, and this function handle the second bit.
2630 */
2631static void set_rate_pix_rdi(struct rcg_clk *clk, struct clk_freq_tbl *nf)
2632{
2633 u32 reg = readl_relaxed(MISC_CC3_REG);
2634 u32 bit = (u32)nf->extra_freq_data;
2635 if (nf->freq_hz == 2)
2636 reg |= bit;
2637 else
2638 reg &= ~bit;
2639 writel_relaxed(reg, MISC_CC3_REG);
2640}
2641
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002642#define F_CSI_PIX(s) \
2643 { \
2644 .src_clk = &csi##s##_clk.c, \
2645 .freq_hz = s, \
2646 .ns_val = BVAL(25, 25, s), \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002647 .extra_freq_data = (void *)BIT(13), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002648 }
2649static struct clk_freq_tbl clk_tbl_csi_pix[] = {
2650 F_CSI_PIX(0), /* CSI0 source */
2651 F_CSI_PIX(1), /* CSI1 source */
Stephen Boyd94625ef2011-07-12 17:06:01 -07002652 F_CSI_PIX(2), /* CSI2 source */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002653 F_END
2654};
2655
2656static struct rcg_clk csi_pix_clk = {
2657 .b = {
2658 .ctl_reg = MISC_CC_REG,
2659 .en_mask = BIT(26),
2660 .halt_check = DELAY,
2661 .reset_reg = SW_RESET_CORE_REG,
2662 .reset_mask = BIT(26),
2663 },
2664 .ns_reg = MISC_CC_REG,
2665 .ns_mask = BIT(25),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002666 .set_rate = set_rate_pix_rdi,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002667 .freq_tbl = clk_tbl_csi_pix,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002668 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002669 .c = {
2670 .dbg_name = "csi_pix_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002671 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002672 CLK_INIT(csi_pix_clk.c),
2673 },
2674};
2675
Stephen Boyd94625ef2011-07-12 17:06:01 -07002676#define F_CSI_PIX1(s) \
2677 { \
2678 .src_clk = &csi##s##_clk.c, \
2679 .freq_hz = s, \
2680 .ns_val = BVAL(9, 8, s), \
2681 }
2682static struct clk_freq_tbl clk_tbl_csi_pix1[] = {
2683 F_CSI_PIX1(0), /* CSI0 source */
2684 F_CSI_PIX1(1), /* CSI1 source */
2685 F_CSI_PIX1(2), /* CSI2 source */
2686 F_END
2687};
2688
2689static struct rcg_clk csi_pix1_clk = {
2690 .b = {
2691 .ctl_reg = MISC_CC3_REG,
2692 .en_mask = BIT(10),
2693 .halt_check = DELAY,
2694 .reset_reg = SW_RESET_CORE_REG,
2695 .reset_mask = BIT(30),
2696 },
2697 .ns_reg = MISC_CC3_REG,
2698 .ns_mask = BM(9, 8),
2699 .set_rate = set_rate_nop,
2700 .freq_tbl = clk_tbl_csi_pix1,
2701 .current_freq = &rcg_dummy_freq,
2702 .c = {
2703 .dbg_name = "csi_pix1_clk",
2704 .ops = &clk_ops_rcg_8960,
2705 CLK_INIT(csi_pix1_clk.c),
2706 },
2707};
2708
2709#define F_CSI_RDI(s) \
2710 { \
2711 .src_clk = &csi##s##_clk.c, \
2712 .freq_hz = s, \
2713 .ns_val = BVAL(12, 12, s), \
2714 .extra_freq_data = (void *)BIT(12), \
2715 }
2716static struct clk_freq_tbl clk_tbl_csi_rdi[] = {
2717 F_CSI_RDI(0), /* CSI0 source */
2718 F_CSI_RDI(1), /* CSI1 source */
2719 F_CSI_RDI(2), /* CSI2 source */
2720 F_END
2721};
2722
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002723static struct rcg_clk csi_rdi_clk = {
2724 .b = {
2725 .ctl_reg = MISC_CC_REG,
2726 .en_mask = BIT(13),
2727 .halt_check = DELAY,
2728 .reset_reg = SW_RESET_CORE_REG,
2729 .reset_mask = BIT(27),
2730 },
2731 .ns_reg = MISC_CC_REG,
2732 .ns_mask = BIT(12),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002733 .set_rate = set_rate_pix_rdi,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002734 .freq_tbl = clk_tbl_csi_rdi,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002735 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002736 .c = {
2737 .dbg_name = "csi_rdi_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002738 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002739 CLK_INIT(csi_rdi_clk.c),
2740 },
2741};
2742
Stephen Boyd94625ef2011-07-12 17:06:01 -07002743#define F_CSI_RDI1(s) \
2744 { \
2745 .src_clk = &csi##s##_clk.c, \
2746 .freq_hz = s, \
2747 .ns_val = BVAL(1, 0, s), \
2748 }
2749static struct clk_freq_tbl clk_tbl_csi_rdi1[] = {
2750 F_CSI_RDI1(0), /* CSI0 source */
2751 F_CSI_RDI1(1), /* CSI1 source */
2752 F_CSI_RDI1(2), /* CSI2 source */
2753 F_END
2754};
2755
2756static struct rcg_clk csi_rdi1_clk = {
2757 .b = {
2758 .ctl_reg = MISC_CC3_REG,
2759 .en_mask = BIT(2),
2760 .halt_check = DELAY,
2761 .reset_reg = SW_RESET_CORE2_REG,
2762 .reset_mask = BIT(1),
2763 },
2764 .ns_reg = MISC_CC3_REG,
2765 .ns_mask = BM(1, 0),
2766 .set_rate = set_rate_nop,
2767 .freq_tbl = clk_tbl_csi_rdi1,
2768 .current_freq = &rcg_dummy_freq,
2769 .c = {
2770 .dbg_name = "csi_rdi1_clk",
2771 .ops = &clk_ops_rcg_8960,
2772 CLK_INIT(csi_rdi1_clk.c),
2773 },
2774};
2775
2776#define F_CSI_RDI2(s) \
2777 { \
2778 .src_clk = &csi##s##_clk.c, \
2779 .freq_hz = s, \
2780 .ns_val = BVAL(5, 4, s), \
2781 }
2782static struct clk_freq_tbl clk_tbl_csi_rdi2[] = {
2783 F_CSI_RDI2(0), /* CSI0 source */
2784 F_CSI_RDI2(1), /* CSI1 source */
2785 F_CSI_RDI2(2), /* CSI2 source */
2786 F_END
2787};
2788
2789static struct rcg_clk csi_rdi2_clk = {
2790 .b = {
2791 .ctl_reg = MISC_CC3_REG,
2792 .en_mask = BIT(6),
2793 .halt_check = DELAY,
2794 .reset_reg = SW_RESET_CORE2_REG,
2795 .reset_mask = BIT(0),
2796 },
2797 .ns_reg = MISC_CC3_REG,
2798 .ns_mask = BM(5, 4),
2799 .set_rate = set_rate_nop,
2800 .freq_tbl = clk_tbl_csi_rdi2,
2801 .current_freq = &rcg_dummy_freq,
2802 .c = {
2803 .dbg_name = "csi_rdi2_clk",
2804 .ops = &clk_ops_rcg_8960,
2805 CLK_INIT(csi_rdi2_clk.c),
2806 },
2807};
2808
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002809#define F_CSI_PHYTIMER(f, s, d, m, n, v) \
2810 { \
2811 .freq_hz = f, \
2812 .src_clk = &s##_clk.c, \
2813 .md_val = MD8(8, m, 0, n), \
2814 .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
2815 .ctl_val = CC(6, n), \
2816 .mnd_en_mask = BIT(5) * !!(n), \
2817 .sys_vdd = v, \
2818 }
2819static struct clk_freq_tbl clk_tbl_csi_phytimer[] = {
2820 F_CSI_PHYTIMER( 0, gnd, 1, 0, 0, NONE),
2821 F_CSI_PHYTIMER( 85330000, pll8, 1, 2, 9, LOW),
2822 F_CSI_PHYTIMER(177780000, pll2, 1, 2, 9, NOMINAL),
2823 F_END
2824};
2825
2826static struct rcg_clk csiphy_timer_src_clk = {
2827 .ns_reg = CSIPHYTIMER_NS_REG,
2828 .b = {
2829 .ctl_reg = CSIPHYTIMER_CC_REG,
2830 .halt_check = NOCHECK,
2831 },
2832 .md_reg = CSIPHYTIMER_MD_REG,
2833 .root_en_mask = BIT(2),
2834 .ns_mask = (BM(31, 24) | BM(15, 14) | BM(2, 0)),
2835 .ctl_mask = BM(7, 6),
2836 .set_rate = set_rate_mnd_8,
2837 .freq_tbl = clk_tbl_csi_phytimer,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002838 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002839 .c = {
2840 .dbg_name = "csiphy_timer_src_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002841 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002842 CLK_INIT(csiphy_timer_src_clk.c),
2843 },
2844};
2845
2846static struct branch_clk csi0phy_timer_clk = {
2847 .b = {
2848 .ctl_reg = CSIPHYTIMER_CC_REG,
2849 .en_mask = BIT(0),
2850 .halt_reg = DBG_BUS_VEC_I_REG,
2851 .halt_bit = 17,
2852 },
2853 .parent = &csiphy_timer_src_clk.c,
2854 .c = {
2855 .dbg_name = "csi0phy_timer_clk",
2856 .ops = &clk_ops_branch,
2857 CLK_INIT(csi0phy_timer_clk.c),
2858 },
2859};
2860
2861static struct branch_clk csi1phy_timer_clk = {
2862 .b = {
2863 .ctl_reg = CSIPHYTIMER_CC_REG,
2864 .en_mask = BIT(9),
2865 .halt_reg = DBG_BUS_VEC_I_REG,
2866 .halt_bit = 18,
2867 },
2868 .parent = &csiphy_timer_src_clk.c,
2869 .c = {
2870 .dbg_name = "csi1phy_timer_clk",
2871 .ops = &clk_ops_branch,
2872 CLK_INIT(csi1phy_timer_clk.c),
2873 },
2874};
2875
Stephen Boyd94625ef2011-07-12 17:06:01 -07002876static struct branch_clk csi2phy_timer_clk = {
2877 .b = {
2878 .ctl_reg = CSIPHYTIMER_CC_REG,
2879 .en_mask = BIT(11),
2880 .halt_reg = DBG_BUS_VEC_I_REG,
2881 .halt_bit = 30,
2882 },
2883 .parent = &csiphy_timer_src_clk.c,
2884 .c = {
2885 .dbg_name = "csi2phy_timer_clk",
2886 .ops = &clk_ops_branch,
2887 CLK_INIT(csi2phy_timer_clk.c),
2888 },
2889};
2890
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002891#define F_DSI(d) \
2892 { \
2893 .freq_hz = d, \
2894 .ns_val = BVAL(15, 12, (d-1)), \
2895 }
2896/*
2897 * The DSI_BYTE/ESC clock is sourced from the DSI PHY PLL, which may change rate
2898 * without this clock driver knowing. So, overload the clk_set_rate() to set
2899 * the divider (1 to 16) of the clock with respect to the PLL rate.
2900 */
2901static struct clk_freq_tbl clk_tbl_dsi_byte[] = {
2902 F_DSI(1), F_DSI(2), F_DSI(3), F_DSI(4),
2903 F_DSI(5), F_DSI(6), F_DSI(7), F_DSI(8),
2904 F_DSI(9), F_DSI(10), F_DSI(11), F_DSI(12),
2905 F_DSI(13), F_DSI(14), F_DSI(15), F_DSI(16),
2906 F_END
2907};
2908
2909static struct rcg_clk dsi1_byte_clk = {
2910 .b = {
2911 .ctl_reg = DSI1_BYTE_CC_REG,
2912 .en_mask = BIT(0),
2913 .reset_reg = SW_RESET_CORE_REG,
2914 .reset_mask = BIT(7),
2915 .halt_reg = DBG_BUS_VEC_B_REG,
2916 .halt_bit = 21,
2917 },
2918 .ns_reg = DSI1_BYTE_NS_REG,
2919 .root_en_mask = BIT(2),
2920 .ns_mask = BM(15, 12),
2921 .set_rate = set_rate_nop,
2922 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002923 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002924 .c = {
2925 .dbg_name = "dsi1_byte_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002926 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002927 CLK_INIT(dsi1_byte_clk.c),
2928 },
2929};
2930
2931static struct rcg_clk dsi2_byte_clk = {
2932 .b = {
2933 .ctl_reg = DSI2_BYTE_CC_REG,
2934 .en_mask = BIT(0),
2935 .reset_reg = SW_RESET_CORE_REG,
2936 .reset_mask = BIT(25),
2937 .halt_reg = DBG_BUS_VEC_B_REG,
2938 .halt_bit = 20,
2939 },
2940 .ns_reg = DSI2_BYTE_NS_REG,
2941 .root_en_mask = BIT(2),
2942 .ns_mask = BM(15, 12),
2943 .set_rate = set_rate_nop,
2944 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002945 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002946 .c = {
2947 .dbg_name = "dsi2_byte_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002948 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002949 CLK_INIT(dsi2_byte_clk.c),
2950 },
2951};
2952
2953static struct rcg_clk dsi1_esc_clk = {
2954 .b = {
2955 .ctl_reg = DSI1_ESC_CC_REG,
2956 .en_mask = BIT(0),
2957 .reset_reg = SW_RESET_CORE_REG,
2958 .halt_reg = DBG_BUS_VEC_I_REG,
2959 .halt_bit = 1,
2960 },
2961 .ns_reg = DSI1_ESC_NS_REG,
2962 .root_en_mask = BIT(2),
2963 .ns_mask = BM(15, 12),
2964 .set_rate = set_rate_nop,
2965 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002966 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002967 .c = {
2968 .dbg_name = "dsi1_esc_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002969 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002970 CLK_INIT(dsi1_esc_clk.c),
2971 },
2972};
2973
2974static struct rcg_clk dsi2_esc_clk = {
2975 .b = {
2976 .ctl_reg = DSI2_ESC_CC_REG,
2977 .en_mask = BIT(0),
2978 .halt_reg = DBG_BUS_VEC_I_REG,
2979 .halt_bit = 3,
2980 },
2981 .ns_reg = DSI2_ESC_NS_REG,
2982 .root_en_mask = BIT(2),
2983 .ns_mask = BM(15, 12),
2984 .set_rate = set_rate_nop,
2985 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002986 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002987 .c = {
2988 .dbg_name = "dsi2_esc_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002989 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002990 CLK_INIT(dsi2_esc_clk.c),
2991 },
2992};
2993
2994#define F_GFX2D(f, s, m, n, v) \
2995 { \
2996 .freq_hz = f, \
2997 .src_clk = &s##_clk.c, \
2998 .md_val = MD4(4, m, 0, n), \
2999 .ns_val = NS_MND_BANKED4(20, 16, n, m, 3, 0, s##_to_mm_mux), \
3000 .ctl_val = CC_BANKED(9, 6, n), \
3001 .mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
3002 .sys_vdd = v, \
3003 }
3004static struct clk_freq_tbl clk_tbl_gfx2d[] = {
3005 F_GFX2D( 0, gnd, 0, 0, NONE),
3006 F_GFX2D( 27000000, pxo, 0, 0, LOW),
3007 F_GFX2D( 48000000, pll8, 1, 8, LOW),
3008 F_GFX2D( 54857000, pll8, 1, 7, LOW),
3009 F_GFX2D( 64000000, pll8, 1, 6, LOW),
3010 F_GFX2D( 76800000, pll8, 1, 5, LOW),
3011 F_GFX2D( 96000000, pll8, 1, 4, LOW),
3012 F_GFX2D(128000000, pll8, 1, 3, NOMINAL),
3013 F_GFX2D(145455000, pll2, 2, 11, NOMINAL),
3014 F_GFX2D(160000000, pll2, 1, 5, NOMINAL),
3015 F_GFX2D(177778000, pll2, 2, 9, NOMINAL),
3016 F_GFX2D(200000000, pll2, 1, 4, NOMINAL),
3017 F_GFX2D(228571000, pll2, 2, 7, HIGH),
3018 F_END
3019};
3020
3021static struct bank_masks bmnd_info_gfx2d0 = {
3022 .bank_sel_mask = BIT(11),
3023 .bank0_mask = {
3024 .md_reg = GFX2D0_MD0_REG,
3025 .ns_mask = BM(23, 20) | BM(5, 3),
3026 .rst_mask = BIT(25),
3027 .mnd_en_mask = BIT(8),
3028 .mode_mask = BM(10, 9),
3029 },
3030 .bank1_mask = {
3031 .md_reg = GFX2D0_MD1_REG,
3032 .ns_mask = BM(19, 16) | BM(2, 0),
3033 .rst_mask = BIT(24),
3034 .mnd_en_mask = BIT(5),
3035 .mode_mask = BM(7, 6),
3036 },
3037};
3038
3039static struct rcg_clk gfx2d0_clk = {
3040 .b = {
3041 .ctl_reg = GFX2D0_CC_REG,
3042 .en_mask = BIT(0),
3043 .reset_reg = SW_RESET_CORE_REG,
3044 .reset_mask = BIT(14),
3045 .halt_reg = DBG_BUS_VEC_A_REG,
3046 .halt_bit = 9,
3047 },
3048 .ns_reg = GFX2D0_NS_REG,
3049 .root_en_mask = BIT(2),
3050 .set_rate = set_rate_mnd_banked,
3051 .freq_tbl = clk_tbl_gfx2d,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003052 .bank_info = &bmnd_info_gfx2d0,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003053 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003054 .c = {
3055 .dbg_name = "gfx2d0_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003056 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003057 CLK_INIT(gfx2d0_clk.c),
3058 },
3059};
3060
3061static struct bank_masks bmnd_info_gfx2d1 = {
3062 .bank_sel_mask = BIT(11),
3063 .bank0_mask = {
3064 .md_reg = GFX2D1_MD0_REG,
3065 .ns_mask = BM(23, 20) | BM(5, 3),
3066 .rst_mask = BIT(25),
3067 .mnd_en_mask = BIT(8),
3068 .mode_mask = BM(10, 9),
3069 },
3070 .bank1_mask = {
3071 .md_reg = GFX2D1_MD1_REG,
3072 .ns_mask = BM(19, 16) | BM(2, 0),
3073 .rst_mask = BIT(24),
3074 .mnd_en_mask = BIT(5),
3075 .mode_mask = BM(7, 6),
3076 },
3077};
3078
3079static struct rcg_clk gfx2d1_clk = {
3080 .b = {
3081 .ctl_reg = GFX2D1_CC_REG,
3082 .en_mask = BIT(0),
3083 .reset_reg = SW_RESET_CORE_REG,
3084 .reset_mask = BIT(13),
3085 .halt_reg = DBG_BUS_VEC_A_REG,
3086 .halt_bit = 14,
3087 },
3088 .ns_reg = GFX2D1_NS_REG,
3089 .root_en_mask = BIT(2),
3090 .set_rate = set_rate_mnd_banked,
3091 .freq_tbl = clk_tbl_gfx2d,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003092 .bank_info = &bmnd_info_gfx2d1,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003093 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003094 .c = {
3095 .dbg_name = "gfx2d1_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003096 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003097 CLK_INIT(gfx2d1_clk.c),
3098 },
3099};
3100
3101#define F_GFX3D(f, s, m, n, v) \
3102 { \
3103 .freq_hz = f, \
3104 .src_clk = &s##_clk.c, \
3105 .md_val = MD4(4, m, 0, n), \
3106 .ns_val = NS_MND_BANKED4(18, 14, n, m, 3, 0, s##_to_mm_mux), \
3107 .ctl_val = CC_BANKED(9, 6, n), \
3108 .mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
3109 .sys_vdd = v, \
3110 }
3111static struct clk_freq_tbl clk_tbl_gfx3d[] = {
3112 F_GFX3D( 0, gnd, 0, 0, NONE),
3113 F_GFX3D( 27000000, pxo, 0, 0, LOW),
3114 F_GFX3D( 48000000, pll8, 1, 8, LOW),
3115 F_GFX3D( 54857000, pll8, 1, 7, LOW),
3116 F_GFX3D( 64000000, pll8, 1, 6, LOW),
3117 F_GFX3D( 76800000, pll8, 1, 5, LOW),
3118 F_GFX3D( 96000000, pll8, 1, 4, LOW),
Stephen Boydd7797422011-08-10 16:01:45 -07003119 F_GFX3D(128000000, pll8, 1, 3, LOW),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003120 F_GFX3D(145455000, pll2, 2, 11, NOMINAL),
3121 F_GFX3D(160000000, pll2, 1, 5, NOMINAL),
3122 F_GFX3D(177778000, pll2, 2, 9, NOMINAL),
3123 F_GFX3D(200000000, pll2, 1, 4, NOMINAL),
3124 F_GFX3D(228571000, pll2, 2, 7, NOMINAL),
3125 F_GFX3D(266667000, pll2, 1, 3, NOMINAL),
3126 F_GFX3D(320000000, pll2, 2, 5, HIGH),
3127 F_END
3128};
3129
Stephen Boyd94625ef2011-07-12 17:06:01 -07003130static struct clk_freq_tbl clk_tbl_gfx3d_v2[] = {
3131 F_GFX3D( 0, gnd, 0, 0, NONE),
3132 F_GFX3D( 27000000, pxo, 0, 0, LOW),
3133 F_GFX3D( 48000000, pll8, 1, 8, LOW),
3134 F_GFX3D( 54857000, pll8, 1, 7, LOW),
3135 F_GFX3D( 64000000, pll8, 1, 6, LOW),
3136 F_GFX3D( 76800000, pll8, 1, 5, LOW),
3137 F_GFX3D( 96000000, pll8, 1, 4, LOW),
3138 F_GFX3D(128000000, pll8, 1, 3, LOW),
3139 F_GFX3D(145455000, pll2, 2, 11, NOMINAL),
3140 F_GFX3D(160000000, pll2, 1, 5, NOMINAL),
3141 F_GFX3D(177778000, pll2, 2, 9, NOMINAL),
3142 F_GFX3D(200000000, pll2, 1, 4, NOMINAL),
3143 F_GFX3D(228571000, pll2, 2, 7, NOMINAL),
3144 F_GFX3D(266667000, pll2, 1, 3, NOMINAL),
3145 F_GFX3D(300000000, pll3, 1, 4, NOMINAL),
3146 F_GFX3D(320000000, pll2, 2, 5, HIGH),
3147 F_GFX3D(400000000, pll2, 1, 2, HIGH),
3148 F_END
3149};
3150
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003151static struct bank_masks bmnd_info_gfx3d = {
3152 .bank_sel_mask = BIT(11),
3153 .bank0_mask = {
3154 .md_reg = GFX3D_MD0_REG,
3155 .ns_mask = BM(21, 18) | BM(5, 3),
3156 .rst_mask = BIT(23),
3157 .mnd_en_mask = BIT(8),
3158 .mode_mask = BM(10, 9),
3159 },
3160 .bank1_mask = {
3161 .md_reg = GFX3D_MD1_REG,
3162 .ns_mask = BM(17, 14) | BM(2, 0),
3163 .rst_mask = BIT(22),
3164 .mnd_en_mask = BIT(5),
3165 .mode_mask = BM(7, 6),
3166 },
3167};
3168
3169static struct rcg_clk gfx3d_clk = {
3170 .b = {
3171 .ctl_reg = GFX3D_CC_REG,
3172 .en_mask = BIT(0),
3173 .reset_reg = SW_RESET_CORE_REG,
3174 .reset_mask = BIT(12),
3175 .halt_reg = DBG_BUS_VEC_A_REG,
3176 .halt_bit = 4,
3177 },
3178 .ns_reg = GFX3D_NS_REG,
3179 .root_en_mask = BIT(2),
3180 .set_rate = set_rate_mnd_banked,
3181 .freq_tbl = clk_tbl_gfx3d,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003182 .bank_info = &bmnd_info_gfx3d,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003183 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003184 .c = {
3185 .dbg_name = "gfx3d_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003186 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003187 CLK_INIT(gfx3d_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003188 .depends = &gmem_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003189 },
3190};
3191
3192#define F_IJPEG(f, s, d, m, n, v) \
3193 { \
3194 .freq_hz = f, \
3195 .src_clk = &s##_clk.c, \
3196 .md_val = MD8(8, m, 0, n), \
3197 .ns_val = NS_MM(23, 16, n, m, 15, 12, d, 2, 0, s##_to_mm_mux), \
3198 .ctl_val = CC(6, n), \
3199 .mnd_en_mask = BIT(5) * !!(n), \
3200 .sys_vdd = v, \
3201 }
3202static struct clk_freq_tbl clk_tbl_ijpeg[] = {
3203 F_IJPEG( 0, gnd, 1, 0, 0, NONE),
3204 F_IJPEG( 27000000, pxo, 1, 0, 0, LOW),
3205 F_IJPEG( 36570000, pll8, 1, 2, 21, LOW),
3206 F_IJPEG( 54860000, pll8, 7, 0, 0, LOW),
3207 F_IJPEG( 96000000, pll8, 4, 0, 0, LOW),
3208 F_IJPEG(109710000, pll8, 1, 2, 7, LOW),
3209 F_IJPEG(128000000, pll8, 3, 0, 0, NOMINAL),
3210 F_IJPEG(153600000, pll8, 1, 2, 5, NOMINAL),
3211 F_IJPEG(200000000, pll2, 4, 0, 0, NOMINAL),
3212 F_IJPEG(228571000, pll2, 1, 2, 7, NOMINAL),
Matt Wagantall393bdb52011-09-07 10:15:28 -07003213 F_IJPEG(266667000, pll2, 1, 1, 3, NOMINAL),
Stephen Boyd94625ef2011-07-12 17:06:01 -07003214 F_IJPEG(320000000, pll2, 1, 2, 5, HIGH),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003215 F_END
3216};
3217
3218static struct rcg_clk ijpeg_clk = {
3219 .b = {
3220 .ctl_reg = IJPEG_CC_REG,
3221 .en_mask = BIT(0),
3222 .reset_reg = SW_RESET_CORE_REG,
3223 .reset_mask = BIT(9),
3224 .halt_reg = DBG_BUS_VEC_A_REG,
3225 .halt_bit = 24,
3226 },
3227 .ns_reg = IJPEG_NS_REG,
3228 .md_reg = IJPEG_MD_REG,
3229 .root_en_mask = BIT(2),
3230 .ns_mask = (BM(23, 16) | BM(15, 12) | BM(2, 0)),
3231 .ctl_mask = BM(7, 6),
3232 .set_rate = set_rate_mnd,
3233 .freq_tbl = clk_tbl_ijpeg,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003234 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003235 .c = {
3236 .dbg_name = "ijpeg_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003237 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003238 CLK_INIT(ijpeg_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003239 .depends = &ijpeg_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003240 },
3241};
3242
3243#define F_JPEGD(f, s, d, v) \
3244 { \
3245 .freq_hz = f, \
3246 .src_clk = &s##_clk.c, \
3247 .ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
3248 .sys_vdd = v, \
3249 }
3250static struct clk_freq_tbl clk_tbl_jpegd[] = {
3251 F_JPEGD( 0, gnd, 1, NONE),
3252 F_JPEGD( 64000000, pll8, 6, LOW),
3253 F_JPEGD( 76800000, pll8, 5, LOW),
3254 F_JPEGD( 96000000, pll8, 4, LOW),
3255 F_JPEGD(160000000, pll2, 5, NOMINAL),
3256 F_JPEGD(200000000, pll2, 4, NOMINAL),
3257 F_END
3258};
3259
3260static struct rcg_clk jpegd_clk = {
3261 .b = {
3262 .ctl_reg = JPEGD_CC_REG,
3263 .en_mask = BIT(0),
3264 .reset_reg = SW_RESET_CORE_REG,
3265 .reset_mask = BIT(19),
3266 .halt_reg = DBG_BUS_VEC_A_REG,
3267 .halt_bit = 19,
3268 },
3269 .ns_reg = JPEGD_NS_REG,
3270 .root_en_mask = BIT(2),
3271 .ns_mask = (BM(15, 12) | BM(2, 0)),
3272 .set_rate = set_rate_nop,
3273 .freq_tbl = clk_tbl_jpegd,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003274 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003275 .c = {
3276 .dbg_name = "jpegd_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003277 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003278 CLK_INIT(jpegd_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003279 .depends = &jpegd_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003280 },
3281};
3282
3283#define F_MDP(f, s, m, n, v) \
3284 { \
3285 .freq_hz = f, \
3286 .src_clk = &s##_clk.c, \
3287 .md_val = MD8(8, m, 0, n), \
3288 .ns_val = NS_MND_BANKED8(22, 14, n, m, 3, 0, s##_to_mm_mux), \
3289 .ctl_val = CC_BANKED(9, 6, n), \
3290 .mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
3291 .sys_vdd = v, \
3292 }
3293static struct clk_freq_tbl clk_tbl_mdp[] = {
3294 F_MDP( 0, gnd, 0, 0, NONE),
3295 F_MDP( 9600000, pll8, 1, 40, LOW),
3296 F_MDP( 13710000, pll8, 1, 28, LOW),
3297 F_MDP( 27000000, pxo, 0, 0, LOW),
3298 F_MDP( 29540000, pll8, 1, 13, LOW),
3299 F_MDP( 34910000, pll8, 1, 11, LOW),
3300 F_MDP( 38400000, pll8, 1, 10, LOW),
3301 F_MDP( 59080000, pll8, 2, 13, LOW),
3302 F_MDP( 76800000, pll8, 1, 5, LOW),
3303 F_MDP( 85330000, pll8, 2, 9, LOW),
3304 F_MDP( 96000000, pll8, 1, 4, NOMINAL),
3305 F_MDP(128000000, pll8, 1, 3, NOMINAL),
3306 F_MDP(160000000, pll2, 1, 5, NOMINAL),
3307 F_MDP(177780000, pll2, 2, 9, NOMINAL),
3308 F_MDP(200000000, pll2, 1, 4, NOMINAL),
3309 F_END
3310};
3311
3312static struct bank_masks bmnd_info_mdp = {
3313 .bank_sel_mask = BIT(11),
3314 .bank0_mask = {
3315 .md_reg = MDP_MD0_REG,
3316 .ns_mask = BM(29, 22) | BM(5, 3),
3317 .rst_mask = BIT(31),
3318 .mnd_en_mask = BIT(8),
3319 .mode_mask = BM(10, 9),
3320 },
3321 .bank1_mask = {
3322 .md_reg = MDP_MD1_REG,
3323 .ns_mask = BM(21, 14) | BM(2, 0),
3324 .rst_mask = BIT(30),
3325 .mnd_en_mask = BIT(5),
3326 .mode_mask = BM(7, 6),
3327 },
3328};
3329
3330static struct rcg_clk mdp_clk = {
3331 .b = {
3332 .ctl_reg = MDP_CC_REG,
3333 .en_mask = BIT(0),
3334 .reset_reg = SW_RESET_CORE_REG,
3335 .reset_mask = BIT(21),
3336 .halt_reg = DBG_BUS_VEC_C_REG,
3337 .halt_bit = 10,
3338 },
3339 .ns_reg = MDP_NS_REG,
3340 .root_en_mask = BIT(2),
3341 .set_rate = set_rate_mnd_banked,
3342 .freq_tbl = clk_tbl_mdp,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003343 .bank_info = &bmnd_info_mdp,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003344 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003345 .c = {
3346 .dbg_name = "mdp_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003347 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003348 CLK_INIT(mdp_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003349 .depends = &mdp_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003350 },
3351};
3352
3353static struct branch_clk lut_mdp_clk = {
3354 .b = {
3355 .ctl_reg = MDP_LUT_CC_REG,
3356 .en_mask = BIT(0),
3357 .halt_reg = DBG_BUS_VEC_I_REG,
3358 .halt_bit = 13,
3359 },
3360 .parent = &mdp_clk.c,
3361 .c = {
3362 .dbg_name = "lut_mdp_clk",
3363 .ops = &clk_ops_branch,
3364 CLK_INIT(lut_mdp_clk.c),
3365 },
3366};
3367
3368#define F_MDP_VSYNC(f, s, v) \
3369 { \
3370 .freq_hz = f, \
3371 .src_clk = &s##_clk.c, \
3372 .ns_val = NS_SRC_SEL(13, 13, s##_to_bb_mux), \
3373 .sys_vdd = v, \
3374 }
3375static struct clk_freq_tbl clk_tbl_mdp_vsync[] = {
3376 F_MDP_VSYNC(27000000, pxo, LOW),
3377 F_END
3378};
3379
3380static struct rcg_clk mdp_vsync_clk = {
3381 .b = {
3382 .ctl_reg = MISC_CC_REG,
3383 .en_mask = BIT(6),
3384 .reset_reg = SW_RESET_CORE_REG,
3385 .reset_mask = BIT(3),
3386 .halt_reg = DBG_BUS_VEC_B_REG,
3387 .halt_bit = 22,
3388 },
3389 .ns_reg = MISC_CC2_REG,
3390 .ns_mask = BIT(13),
3391 .set_rate = set_rate_nop,
3392 .freq_tbl = clk_tbl_mdp_vsync,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003393 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003394 .c = {
3395 .dbg_name = "mdp_vsync_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003396 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003397 CLK_INIT(mdp_vsync_clk.c),
3398 },
3399};
3400
3401#define F_ROT(f, s, d, v) \
3402 { \
3403 .freq_hz = f, \
3404 .src_clk = &s##_clk.c, \
3405 .ns_val = NS_DIVSRC_BANKED(29, 26, 25, 22, d, \
3406 21, 19, 18, 16, s##_to_mm_mux), \
3407 .sys_vdd = v, \
3408 }
3409static struct clk_freq_tbl clk_tbl_rot[] = {
3410 F_ROT( 0, gnd, 1, NONE),
3411 F_ROT( 27000000, pxo, 1, LOW),
3412 F_ROT( 29540000, pll8, 13, LOW),
3413 F_ROT( 32000000, pll8, 12, LOW),
3414 F_ROT( 38400000, pll8, 10, LOW),
3415 F_ROT( 48000000, pll8, 8, LOW),
3416 F_ROT( 54860000, pll8, 7, LOW),
3417 F_ROT( 64000000, pll8, 6, LOW),
3418 F_ROT( 76800000, pll8, 5, LOW),
Matt Wagantall448db0f2011-09-07 10:17:40 -07003419 F_ROT( 96000000, pll8, 4, LOW),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003420 F_ROT(100000000, pll2, 8, NOMINAL),
3421 F_ROT(114290000, pll2, 7, NOMINAL),
3422 F_ROT(133330000, pll2, 6, NOMINAL),
3423 F_ROT(160000000, pll2, 5, NOMINAL),
Stephen Boyd8487f712011-08-29 12:10:09 -07003424 F_ROT(200000000, pll2, 4, NOMINAL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003425 F_END
3426};
3427
3428static struct bank_masks bdiv_info_rot = {
3429 .bank_sel_mask = BIT(30),
3430 .bank0_mask = {
3431 .ns_mask = BM(25, 22) | BM(18, 16),
3432 },
3433 .bank1_mask = {
3434 .ns_mask = BM(29, 26) | BM(21, 19),
3435 },
3436};
3437
3438static struct rcg_clk rot_clk = {
3439 .b = {
3440 .ctl_reg = ROT_CC_REG,
3441 .en_mask = BIT(0),
3442 .reset_reg = SW_RESET_CORE_REG,
3443 .reset_mask = BIT(2),
3444 .halt_reg = DBG_BUS_VEC_C_REG,
3445 .halt_bit = 15,
3446 },
3447 .ns_reg = ROT_NS_REG,
3448 .root_en_mask = BIT(2),
3449 .set_rate = set_rate_div_banked,
3450 .freq_tbl = clk_tbl_rot,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003451 .bank_info = &bdiv_info_rot,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003452 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003453 .c = {
3454 .dbg_name = "rot_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003455 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003456 CLK_INIT(rot_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003457 .depends = &rot_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003458 },
3459};
3460
3461static int hdmi_pll_clk_enable(struct clk *clk)
3462{
3463 int ret;
3464 unsigned long flags;
3465 spin_lock_irqsave(&local_clock_reg_lock, flags);
3466 ret = hdmi_pll_enable();
3467 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
3468 return ret;
3469}
3470
3471static void hdmi_pll_clk_disable(struct clk *clk)
3472{
3473 unsigned long flags;
3474 spin_lock_irqsave(&local_clock_reg_lock, flags);
3475 hdmi_pll_disable();
3476 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
3477}
3478
3479static unsigned hdmi_pll_clk_get_rate(struct clk *clk)
3480{
3481 return hdmi_pll_get_rate();
3482}
3483
3484static struct clk_ops clk_ops_hdmi_pll = {
3485 .enable = hdmi_pll_clk_enable,
3486 .disable = hdmi_pll_clk_disable,
3487 .get_rate = hdmi_pll_clk_get_rate,
3488 .is_local = local_clk_is_local,
3489};
3490
3491static struct clk hdmi_pll_clk = {
3492 .dbg_name = "hdmi_pll_clk",
3493 .ops = &clk_ops_hdmi_pll,
3494 CLK_INIT(hdmi_pll_clk),
3495};
3496
3497#define F_TV_GND(f, s, p_r, d, m, n, v) \
3498 { \
3499 .freq_hz = f, \
3500 .src_clk = &s##_clk.c, \
3501 .md_val = MD8(8, m, 0, n), \
3502 .ns_val = NS_MM(23, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
3503 .ctl_val = CC(6, n), \
3504 .mnd_en_mask = BIT(5) * !!(n), \
3505 .sys_vdd = v, \
3506 }
3507#define F_TV(f, s, p_r, d, m, n, v) \
3508 { \
3509 .freq_hz = f, \
3510 .src_clk = &s##_clk, \
3511 .md_val = MD8(8, m, 0, n), \
3512 .ns_val = NS_MM(23, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
3513 .ctl_val = CC(6, n), \
3514 .mnd_en_mask = BIT(5) * !!(n), \
3515 .sys_vdd = v, \
3516 .extra_freq_data = (void *)p_r, \
3517 }
3518/* Switching TV freqs requires PLL reconfiguration. */
3519static struct clk_freq_tbl clk_tbl_tv[] = {
3520 F_TV_GND( 0, gnd, 0, 1, 0, 0, NONE),
3521 F_TV( 25200000, hdmi_pll, 25200000, 1, 0, 0, LOW),
3522 F_TV( 27000000, hdmi_pll, 27000000, 1, 0, 0, LOW),
3523 F_TV( 27030000, hdmi_pll, 27030000, 1, 0, 0, LOW),
3524 F_TV( 74250000, hdmi_pll, 74250000, 1, 0, 0, NOMINAL),
3525 F_TV(148500000, hdmi_pll, 148500000, 1, 0, 0, NOMINAL),
3526 F_END
3527};
3528
3529/*
3530 * Unlike other clocks, the TV rate is adjusted through PLL
3531 * re-programming. It is also routed through an MND divider.
3532 */
3533void set_rate_tv(struct rcg_clk *clk, struct clk_freq_tbl *nf)
3534{
3535 unsigned long pll_rate = (unsigned long)nf->extra_freq_data;
3536 if (pll_rate)
3537 hdmi_pll_set_rate(pll_rate);
3538 set_rate_mnd(clk, nf);
3539}
3540
3541static struct rcg_clk tv_src_clk = {
3542 .ns_reg = TV_NS_REG,
3543 .b = {
3544 .ctl_reg = TV_CC_REG,
3545 .halt_check = NOCHECK,
3546 },
3547 .md_reg = TV_MD_REG,
3548 .root_en_mask = BIT(2),
3549 .ns_mask = (BM(23, 16) | BM(15, 14) | BM(2, 0)),
3550 .ctl_mask = BM(7, 6),
3551 .set_rate = set_rate_tv,
3552 .freq_tbl = clk_tbl_tv,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003553 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003554 .c = {
3555 .dbg_name = "tv_src_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003556 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003557 CLK_INIT(tv_src_clk.c),
3558 },
3559};
3560
3561static struct branch_clk tv_enc_clk = {
3562 .b = {
3563 .ctl_reg = TV_CC_REG,
3564 .en_mask = BIT(8),
3565 .reset_reg = SW_RESET_CORE_REG,
3566 .reset_mask = BIT(0),
3567 .halt_reg = DBG_BUS_VEC_D_REG,
3568 .halt_bit = 9,
3569 },
3570 .parent = &tv_src_clk.c,
3571 .c = {
3572 .dbg_name = "tv_enc_clk",
3573 .ops = &clk_ops_branch,
3574 CLK_INIT(tv_enc_clk.c),
3575 },
3576};
3577
3578static struct branch_clk tv_dac_clk = {
3579 .b = {
3580 .ctl_reg = TV_CC_REG,
3581 .en_mask = BIT(10),
3582 .halt_reg = DBG_BUS_VEC_D_REG,
3583 .halt_bit = 10,
3584 },
3585 .parent = &tv_src_clk.c,
3586 .c = {
3587 .dbg_name = "tv_dac_clk",
3588 .ops = &clk_ops_branch,
3589 CLK_INIT(tv_dac_clk.c),
3590 },
3591};
3592
3593static struct branch_clk mdp_tv_clk = {
3594 .b = {
3595 .ctl_reg = TV_CC_REG,
3596 .en_mask = BIT(0),
3597 .reset_reg = SW_RESET_CORE_REG,
3598 .reset_mask = BIT(4),
3599 .halt_reg = DBG_BUS_VEC_D_REG,
3600 .halt_bit = 12,
3601 },
3602 .parent = &tv_src_clk.c,
3603 .c = {
3604 .dbg_name = "mdp_tv_clk",
3605 .ops = &clk_ops_branch,
3606 CLK_INIT(mdp_tv_clk.c),
3607 },
3608};
3609
3610static struct branch_clk hdmi_tv_clk = {
3611 .b = {
3612 .ctl_reg = TV_CC_REG,
3613 .en_mask = BIT(12),
3614 .reset_reg = SW_RESET_CORE_REG,
3615 .reset_mask = BIT(1),
3616 .halt_reg = DBG_BUS_VEC_D_REG,
3617 .halt_bit = 11,
3618 },
3619 .parent = &tv_src_clk.c,
3620 .c = {
3621 .dbg_name = "hdmi_tv_clk",
3622 .ops = &clk_ops_branch,
3623 CLK_INIT(hdmi_tv_clk.c),
3624 },
3625};
3626
3627static struct branch_clk hdmi_app_clk = {
3628 .b = {
3629 .ctl_reg = MISC_CC2_REG,
3630 .en_mask = BIT(11),
3631 .reset_reg = SW_RESET_CORE_REG,
3632 .reset_mask = BIT(11),
3633 .halt_reg = DBG_BUS_VEC_B_REG,
3634 .halt_bit = 25,
3635 },
3636 .c = {
3637 .dbg_name = "hdmi_app_clk",
3638 .ops = &clk_ops_branch,
3639 CLK_INIT(hdmi_app_clk.c),
3640 },
3641};
3642
3643static struct bank_masks bmnd_info_vcodec = {
3644 .bank_sel_mask = BIT(13),
3645 .bank0_mask = {
3646 .md_reg = VCODEC_MD0_REG,
3647 .ns_mask = BM(18, 11) | BM(2, 0),
3648 .rst_mask = BIT(31),
3649 .mnd_en_mask = BIT(5),
3650 .mode_mask = BM(7, 6),
3651 },
3652 .bank1_mask = {
3653 .md_reg = VCODEC_MD1_REG,
3654 .ns_mask = BM(26, 19) | BM(29, 27),
3655 .rst_mask = BIT(30),
3656 .mnd_en_mask = BIT(10),
3657 .mode_mask = BM(12, 11),
3658 },
3659};
3660#define F_VCODEC(f, s, m, n, v) \
3661 { \
3662 .freq_hz = f, \
3663 .src_clk = &s##_clk.c, \
3664 .md_val = MD8(8, m, 0, n), \
3665 .ns_val = NS_MND_BANKED8(11, 19, n, m, 0, 27, s##_to_mm_mux), \
3666 .ctl_val = CC_BANKED(6, 11, n), \
3667 .mnd_en_mask = (BIT(10) | BIT(5)) * !!(n), \
3668 .sys_vdd = v, \
3669 }
3670static struct clk_freq_tbl clk_tbl_vcodec[] = {
3671 F_VCODEC( 0, gnd, 0, 0, NONE),
3672 F_VCODEC( 27000000, pxo, 0, 0, LOW),
3673 F_VCODEC( 32000000, pll8, 1, 12, LOW),
3674 F_VCODEC( 48000000, pll8, 1, 8, LOW),
3675 F_VCODEC( 54860000, pll8, 1, 7, LOW),
3676 F_VCODEC( 96000000, pll8, 1, 4, LOW),
3677 F_VCODEC(133330000, pll2, 1, 6, NOMINAL),
3678 F_VCODEC(200000000, pll2, 1, 4, NOMINAL),
3679 F_VCODEC(228570000, pll2, 2, 7, HIGH),
3680 F_END
3681};
3682
3683static struct rcg_clk vcodec_clk = {
3684 .b = {
3685 .ctl_reg = VCODEC_CC_REG,
3686 .en_mask = BIT(0),
3687 .reset_reg = SW_RESET_CORE_REG,
3688 .reset_mask = BIT(6),
3689 .halt_reg = DBG_BUS_VEC_C_REG,
3690 .halt_bit = 29,
3691 },
3692 .ns_reg = VCODEC_NS_REG,
3693 .root_en_mask = BIT(2),
3694 .set_rate = set_rate_mnd_banked,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003695 .bank_info = &bmnd_info_vcodec,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003696 .freq_tbl = clk_tbl_vcodec,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003697 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003698 .c = {
3699 .dbg_name = "vcodec_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003700 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003701 CLK_INIT(vcodec_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003702 .depends = &vcodec_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003703 },
3704};
3705
3706#define F_VPE(f, s, d, v) \
3707 { \
3708 .freq_hz = f, \
3709 .src_clk = &s##_clk.c, \
3710 .ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
3711 .sys_vdd = v, \
3712 }
3713static struct clk_freq_tbl clk_tbl_vpe[] = {
3714 F_VPE( 0, gnd, 1, NONE),
3715 F_VPE( 27000000, pxo, 1, LOW),
3716 F_VPE( 34909000, pll8, 11, LOW),
3717 F_VPE( 38400000, pll8, 10, LOW),
3718 F_VPE( 64000000, pll8, 6, LOW),
3719 F_VPE( 76800000, pll8, 5, LOW),
3720 F_VPE( 96000000, pll8, 4, NOMINAL),
3721 F_VPE(100000000, pll2, 8, NOMINAL),
3722 F_VPE(160000000, pll2, 5, NOMINAL),
3723 F_END
3724};
3725
3726static struct rcg_clk vpe_clk = {
3727 .b = {
3728 .ctl_reg = VPE_CC_REG,
3729 .en_mask = BIT(0),
3730 .reset_reg = SW_RESET_CORE_REG,
3731 .reset_mask = BIT(17),
3732 .halt_reg = DBG_BUS_VEC_A_REG,
3733 .halt_bit = 28,
3734 },
3735 .ns_reg = VPE_NS_REG,
3736 .root_en_mask = BIT(2),
3737 .ns_mask = (BM(15, 12) | BM(2, 0)),
3738 .set_rate = set_rate_nop,
3739 .freq_tbl = clk_tbl_vpe,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003740 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003741 .c = {
3742 .dbg_name = "vpe_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003743 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003744 CLK_INIT(vpe_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003745 .depends = &vpe_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003746 },
3747};
3748
3749#define F_VFE(f, s, d, m, n, v) \
3750 { \
3751 .freq_hz = f, \
3752 .src_clk = &s##_clk.c, \
3753 .md_val = MD8(8, m, 0, n), \
3754 .ns_val = NS_MM(23, 16, n, m, 11, 10, d, 2, 0, s##_to_mm_mux), \
3755 .ctl_val = CC(6, n), \
3756 .mnd_en_mask = BIT(5) * !!(n), \
3757 .sys_vdd = v, \
3758 }
3759static struct clk_freq_tbl clk_tbl_vfe[] = {
3760 F_VFE( 0, gnd, 1, 0, 0, NONE),
3761 F_VFE( 13960000, pll8, 1, 2, 55, LOW),
3762 F_VFE( 27000000, pxo, 1, 0, 0, LOW),
3763 F_VFE( 36570000, pll8, 1, 2, 21, LOW),
3764 F_VFE( 38400000, pll8, 2, 1, 5, LOW),
3765 F_VFE( 45180000, pll8, 1, 2, 17, LOW),
3766 F_VFE( 48000000, pll8, 2, 1, 4, LOW),
3767 F_VFE( 54860000, pll8, 1, 1, 7, LOW),
3768 F_VFE( 64000000, pll8, 2, 1, 3, LOW),
3769 F_VFE( 76800000, pll8, 1, 1, 5, LOW),
3770 F_VFE( 96000000, pll8, 2, 1, 2, LOW),
3771 F_VFE(109710000, pll8, 1, 2, 7, LOW),
3772 F_VFE(128000000, pll8, 1, 1, 3, NOMINAL),
3773 F_VFE(153600000, pll8, 1, 2, 5, NOMINAL),
3774 F_VFE(200000000, pll2, 2, 1, 2, NOMINAL),
3775 F_VFE(228570000, pll2, 1, 2, 7, NOMINAL),
3776 F_VFE(266667000, pll2, 1, 1, 3, NOMINAL),
Stephen Boyd94625ef2011-07-12 17:06:01 -07003777 F_VFE(320000000, pll2, 1, 2, 5, HIGH),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003778 F_END
3779};
3780
3781
3782static struct rcg_clk vfe_clk = {
3783 .b = {
3784 .ctl_reg = VFE_CC_REG,
3785 .reset_reg = SW_RESET_CORE_REG,
3786 .reset_mask = BIT(15),
3787 .halt_reg = DBG_BUS_VEC_B_REG,
3788 .halt_bit = 6,
3789 .en_mask = BIT(0),
3790 },
3791 .ns_reg = VFE_NS_REG,
3792 .md_reg = VFE_MD_REG,
3793 .root_en_mask = BIT(2),
3794 .ns_mask = (BM(23, 16) | BM(11, 10) | BM(2, 0)),
3795 .ctl_mask = BM(7, 6),
3796 .set_rate = set_rate_mnd,
3797 .freq_tbl = clk_tbl_vfe,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003798 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003799 .c = {
3800 .dbg_name = "vfe_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003801 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003802 CLK_INIT(vfe_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003803 .depends = &vfe_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003804 },
3805};
3806
Matt Wagantallc23eee92011-08-16 23:06:52 -07003807static struct branch_clk csi_vfe_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003808 .b = {
3809 .ctl_reg = VFE_CC_REG,
3810 .en_mask = BIT(12),
3811 .reset_reg = SW_RESET_CORE_REG,
3812 .reset_mask = BIT(24),
3813 .halt_reg = DBG_BUS_VEC_B_REG,
3814 .halt_bit = 8,
3815 },
3816 .parent = &vfe_clk.c,
3817 .c = {
Matt Wagantallc23eee92011-08-16 23:06:52 -07003818 .dbg_name = "csi_vfe_clk",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003819 .ops = &clk_ops_branch,
Matt Wagantallc23eee92011-08-16 23:06:52 -07003820 CLK_INIT(csi_vfe_clk.c),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003821 },
3822};
3823
3824/*
3825 * Low Power Audio Clocks
3826 */
3827#define F_AIF_OSR(f, s, d, m, n, v) \
3828 { \
3829 .freq_hz = f, \
3830 .src_clk = &s##_clk.c, \
3831 .md_val = MD8(8, m, 0, n), \
3832 .ns_val = NS(31, 24, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
3833 .mnd_en_mask = BIT(8) * !!(n), \
3834 .sys_vdd = v, \
3835 }
3836static struct clk_freq_tbl clk_tbl_aif_osr[] = {
3837 F_AIF_OSR( 0, gnd, 1, 0, 0, NONE),
3838 F_AIF_OSR( 768000, pll4, 4, 1, 128, LOW),
3839 F_AIF_OSR( 1024000, pll4, 4, 1, 96, LOW),
3840 F_AIF_OSR( 1536000, pll4, 4, 1, 64, LOW),
3841 F_AIF_OSR( 2048000, pll4, 4, 1, 48, LOW),
3842 F_AIF_OSR( 3072000, pll4, 4, 1, 32, LOW),
3843 F_AIF_OSR( 4096000, pll4, 4, 1, 24, LOW),
3844 F_AIF_OSR( 6144000, pll4, 4, 1, 16, LOW),
3845 F_AIF_OSR( 8192000, pll4, 4, 1, 12, LOW),
3846 F_AIF_OSR(12288000, pll4, 4, 1, 8, LOW),
3847 F_AIF_OSR(24576000, pll4, 4, 1, 4, LOW),
3848 F_END
3849};
3850
3851#define CLK_AIF_OSR(i, ns, md, h_r) \
3852 struct rcg_clk i##_clk = { \
3853 .b = { \
3854 .ctl_reg = ns, \
3855 .en_mask = BIT(17), \
3856 .reset_reg = ns, \
3857 .reset_mask = BIT(19), \
3858 .halt_reg = h_r, \
3859 .halt_check = ENABLE, \
3860 .halt_bit = 1, \
3861 }, \
3862 .ns_reg = ns, \
3863 .md_reg = md, \
3864 .root_en_mask = BIT(9), \
3865 .ns_mask = (BM(31, 24) | BM(6, 0)), \
3866 .set_rate = set_rate_mnd, \
3867 .freq_tbl = clk_tbl_aif_osr, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003868 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003869 .c = { \
3870 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003871 .ops = &clk_ops_rcg_8960, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003872 CLK_INIT(i##_clk.c), \
3873 }, \
3874 }
3875#define CLK_AIF_OSR_DIV(i, ns, md, h_r) \
3876 struct rcg_clk i##_clk = { \
3877 .b = { \
3878 .ctl_reg = ns, \
3879 .en_mask = BIT(21), \
3880 .reset_reg = ns, \
3881 .reset_mask = BIT(23), \
3882 .halt_reg = h_r, \
3883 .halt_check = ENABLE, \
3884 .halt_bit = 1, \
3885 }, \
3886 .ns_reg = ns, \
3887 .md_reg = md, \
3888 .root_en_mask = BIT(9), \
3889 .ns_mask = (BM(31, 24) | BM(6, 0)), \
3890 .set_rate = set_rate_mnd, \
3891 .freq_tbl = clk_tbl_aif_osr, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003892 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003893 .c = { \
3894 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003895 .ops = &clk_ops_rcg_8960, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003896 CLK_INIT(i##_clk.c), \
3897 }, \
3898 }
3899
3900#define F_AIF_BIT(d, s) \
3901 { \
3902 .freq_hz = d, \
3903 .ns_val = (BVAL(14, 14, s) | BVAL(13, 10, (d-1))) \
3904 }
3905static struct clk_freq_tbl clk_tbl_aif_bit[] = {
3906 F_AIF_BIT(0, 1), /* Use external clock. */
3907 F_AIF_BIT(1, 0), F_AIF_BIT(2, 0), F_AIF_BIT(3, 0), F_AIF_BIT(4, 0),
3908 F_AIF_BIT(5, 0), F_AIF_BIT(6, 0), F_AIF_BIT(7, 0), F_AIF_BIT(8, 0),
3909 F_AIF_BIT(9, 0), F_AIF_BIT(10, 0), F_AIF_BIT(11, 0), F_AIF_BIT(12, 0),
3910 F_AIF_BIT(13, 0), F_AIF_BIT(14, 0), F_AIF_BIT(15, 0), F_AIF_BIT(16, 0),
3911 F_END
3912};
3913
3914#define CLK_AIF_BIT(i, ns, h_r) \
3915 struct rcg_clk i##_clk = { \
3916 .b = { \
3917 .ctl_reg = ns, \
3918 .en_mask = BIT(15), \
3919 .halt_reg = h_r, \
3920 .halt_check = DELAY, \
3921 }, \
3922 .ns_reg = ns, \
3923 .ns_mask = BM(14, 10), \
3924 .set_rate = set_rate_nop, \
3925 .freq_tbl = clk_tbl_aif_bit, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003926 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003927 .c = { \
3928 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003929 .ops = &clk_ops_rcg_8960, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003930 CLK_INIT(i##_clk.c), \
3931 }, \
3932 }
3933
3934#define F_AIF_BIT_D(d, s) \
3935 { \
3936 .freq_hz = d, \
3937 .ns_val = (BVAL(18, 18, s) | BVAL(17, 10, (d-1))) \
3938 }
3939static struct clk_freq_tbl clk_tbl_aif_bit_div[] = {
3940 F_AIF_BIT_D(0, 1), /* Use external clock. */
3941 F_AIF_BIT_D(1, 0), F_AIF_BIT_D(2, 0), F_AIF_BIT_D(3, 0),
3942 F_AIF_BIT_D(4, 0), F_AIF_BIT_D(5, 0), F_AIF_BIT_D(6, 0),
3943 F_AIF_BIT_D(7, 0), F_AIF_BIT_D(8, 0), F_AIF_BIT_D(9, 0),
3944 F_AIF_BIT_D(10, 0), F_AIF_BIT_D(11, 0), F_AIF_BIT_D(12, 0),
3945 F_AIF_BIT_D(13, 0), F_AIF_BIT_D(14, 0), F_AIF_BIT_D(15, 0),
3946 F_AIF_BIT_D(16, 0),
3947 F_END
3948};
3949
3950#define CLK_AIF_BIT_DIV(i, ns, h_r) \
3951 struct rcg_clk i##_clk = { \
3952 .b = { \
3953 .ctl_reg = ns, \
3954 .en_mask = BIT(19), \
3955 .halt_reg = h_r, \
3956 .halt_check = ENABLE, \
3957 }, \
3958 .ns_reg = ns, \
3959 .ns_mask = BM(18, 10), \
3960 .set_rate = set_rate_nop, \
3961 .freq_tbl = clk_tbl_aif_bit_div, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003962 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003963 .c = { \
3964 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003965 .ops = &clk_ops_rcg_8960, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003966 CLK_INIT(i##_clk.c), \
3967 }, \
3968 }
3969
3970static CLK_AIF_OSR(mi2s_osr, LCC_MI2S_NS_REG, LCC_MI2S_MD_REG,
3971 LCC_MI2S_STATUS_REG);
3972static CLK_AIF_BIT(mi2s_bit, LCC_MI2S_NS_REG, LCC_MI2S_STATUS_REG);
3973
3974static CLK_AIF_OSR_DIV(codec_i2s_mic_osr, LCC_CODEC_I2S_MIC_NS_REG,
3975 LCC_CODEC_I2S_MIC_MD_REG, LCC_CODEC_I2S_MIC_STATUS_REG);
3976static CLK_AIF_BIT_DIV(codec_i2s_mic_bit, LCC_CODEC_I2S_MIC_NS_REG,
3977 LCC_CODEC_I2S_MIC_STATUS_REG);
3978
3979static CLK_AIF_OSR_DIV(spare_i2s_mic_osr, LCC_SPARE_I2S_MIC_NS_REG,
3980 LCC_SPARE_I2S_MIC_MD_REG, LCC_SPARE_I2S_MIC_STATUS_REG);
3981static CLK_AIF_BIT_DIV(spare_i2s_mic_bit, LCC_SPARE_I2S_MIC_NS_REG,
3982 LCC_SPARE_I2S_MIC_STATUS_REG);
3983
3984static CLK_AIF_OSR_DIV(codec_i2s_spkr_osr, LCC_CODEC_I2S_SPKR_NS_REG,
3985 LCC_CODEC_I2S_SPKR_MD_REG, LCC_CODEC_I2S_SPKR_STATUS_REG);
3986static CLK_AIF_BIT_DIV(codec_i2s_spkr_bit, LCC_CODEC_I2S_SPKR_NS_REG,
3987 LCC_CODEC_I2S_SPKR_STATUS_REG);
3988
3989static CLK_AIF_OSR_DIV(spare_i2s_spkr_osr, LCC_SPARE_I2S_SPKR_NS_REG,
3990 LCC_SPARE_I2S_SPKR_MD_REG, LCC_SPARE_I2S_SPKR_STATUS_REG);
3991static CLK_AIF_BIT_DIV(spare_i2s_spkr_bit, LCC_SPARE_I2S_SPKR_NS_REG,
3992 LCC_SPARE_I2S_SPKR_STATUS_REG);
3993
3994#define F_PCM(f, s, d, m, n, v) \
3995 { \
3996 .freq_hz = f, \
3997 .src_clk = &s##_clk.c, \
3998 .md_val = MD16(m, n), \
3999 .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
4000 .mnd_en_mask = BIT(8) * !!(n), \
4001 .sys_vdd = v, \
4002 }
4003static struct clk_freq_tbl clk_tbl_pcm[] = {
4004 F_PCM( 0, gnd, 1, 0, 0, NONE),
4005 F_PCM( 512000, pll4, 4, 1, 192, LOW),
4006 F_PCM( 768000, pll4, 4, 1, 128, LOW),
4007 F_PCM( 1024000, pll4, 4, 1, 96, LOW),
4008 F_PCM( 1536000, pll4, 4, 1, 64, LOW),
4009 F_PCM( 2048000, pll4, 4, 1, 48, LOW),
4010 F_PCM( 3072000, pll4, 4, 1, 32, LOW),
4011 F_PCM( 4096000, pll4, 4, 1, 24, LOW),
4012 F_PCM( 6144000, pll4, 4, 1, 16, LOW),
4013 F_PCM( 8192000, pll4, 4, 1, 12, LOW),
4014 F_PCM(12288000, pll4, 4, 1, 8, LOW),
4015 F_PCM(24576000, pll4, 4, 1, 4, LOW),
4016 F_END
4017};
4018
4019static struct rcg_clk pcm_clk = {
4020 .b = {
4021 .ctl_reg = LCC_PCM_NS_REG,
4022 .en_mask = BIT(11),
4023 .reset_reg = LCC_PCM_NS_REG,
4024 .reset_mask = BIT(13),
4025 .halt_reg = LCC_PCM_STATUS_REG,
4026 .halt_check = ENABLE,
4027 .halt_bit = 0,
4028 },
4029 .ns_reg = LCC_PCM_NS_REG,
4030 .md_reg = LCC_PCM_MD_REG,
4031 .root_en_mask = BIT(9),
4032 .ns_mask = (BM(31, 16) | BM(6, 0)),
4033 .set_rate = set_rate_mnd,
4034 .freq_tbl = clk_tbl_pcm,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004035 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004036 .c = {
4037 .dbg_name = "pcm_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004038 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004039 CLK_INIT(pcm_clk.c),
4040 },
4041};
4042
4043static struct rcg_clk audio_slimbus_clk = {
4044 .b = {
4045 .ctl_reg = LCC_SLIMBUS_NS_REG,
4046 .en_mask = BIT(10),
4047 .reset_reg = LCC_AHBEX_BRANCH_CTL_REG,
4048 .reset_mask = BIT(5),
4049 .halt_reg = LCC_SLIMBUS_STATUS_REG,
4050 .halt_check = ENABLE,
4051 .halt_bit = 0,
4052 },
4053 .ns_reg = LCC_SLIMBUS_NS_REG,
4054 .md_reg = LCC_SLIMBUS_MD_REG,
4055 .root_en_mask = BIT(9),
4056 .ns_mask = (BM(31, 24) | BM(6, 0)),
4057 .set_rate = set_rate_mnd,
4058 .freq_tbl = clk_tbl_aif_osr,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004059 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004060 .c = {
4061 .dbg_name = "audio_slimbus_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004062 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004063 CLK_INIT(audio_slimbus_clk.c),
4064 },
4065};
4066
4067static struct branch_clk sps_slimbus_clk = {
4068 .b = {
4069 .ctl_reg = LCC_SLIMBUS_NS_REG,
4070 .en_mask = BIT(12),
4071 .halt_reg = LCC_SLIMBUS_STATUS_REG,
4072 .halt_check = ENABLE,
4073 .halt_bit = 1,
4074 },
4075 .parent = &audio_slimbus_clk.c,
4076 .c = {
4077 .dbg_name = "sps_slimbus_clk",
4078 .ops = &clk_ops_branch,
4079 CLK_INIT(sps_slimbus_clk.c),
4080 },
4081};
4082
4083static struct branch_clk slimbus_xo_src_clk = {
4084 .b = {
4085 .ctl_reg = SLIMBUS_XO_SRC_CLK_CTL_REG,
4086 .en_mask = BIT(2),
4087 .halt_reg = CLK_HALT_DFAB_STATE_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004088 .halt_bit = 28,
4089 },
4090 .parent = &sps_slimbus_clk.c,
4091 .c = {
4092 .dbg_name = "slimbus_xo_src_clk",
4093 .ops = &clk_ops_branch,
4094 CLK_INIT(slimbus_xo_src_clk.c),
4095 },
4096};
4097
Matt Wagantall735f01a2011-08-12 12:40:28 -07004098DEFINE_CLK_RPM(afab_clk, afab_a_clk, APPS_FABRIC, NULL);
4099DEFINE_CLK_RPM(cfpb_clk, cfpb_a_clk, CFPB, NULL);
4100DEFINE_CLK_RPM(dfab_clk, dfab_a_clk, DAYTONA_FABRIC, NULL);
4101DEFINE_CLK_RPM(ebi1_clk, ebi1_a_clk, EBI1, NULL);
4102DEFINE_CLK_RPM(mmfab_clk, mmfab_a_clk, MM_FABRIC, NULL);
4103DEFINE_CLK_RPM(mmfpb_clk, mmfpb_a_clk, MMFPB, NULL);
4104DEFINE_CLK_RPM(sfab_clk, sfab_a_clk, SYSTEM_FABRIC, NULL);
4105DEFINE_CLK_RPM(sfpb_clk, sfpb_a_clk, SFPB, NULL);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004106
4107static DEFINE_CLK_VOTER(dfab_dsps_clk, &dfab_clk.c);
4108static DEFINE_CLK_VOTER(dfab_usb_hs_clk, &dfab_clk.c);
4109static DEFINE_CLK_VOTER(dfab_sdc1_clk, &dfab_clk.c);
4110static DEFINE_CLK_VOTER(dfab_sdc2_clk, &dfab_clk.c);
4111static DEFINE_CLK_VOTER(dfab_sdc3_clk, &dfab_clk.c);
4112static DEFINE_CLK_VOTER(dfab_sdc4_clk, &dfab_clk.c);
4113static DEFINE_CLK_VOTER(dfab_sdc5_clk, &dfab_clk.c);
4114static DEFINE_CLK_VOTER(dfab_sps_clk, &dfab_clk.c);
4115
4116static DEFINE_CLK_VOTER(ebi1_msmbus_clk, &ebi1_clk.c);
4117/*
4118 * TODO: replace dummy_clk below with ebi1_clk.c once the
4119 * bus driver starts voting on ebi1 rates.
4120 */
4121static DEFINE_CLK_VOTER(ebi1_adm_clk, &dummy_clk);
4122
4123#ifdef CONFIG_DEBUG_FS
4124struct measure_sel {
4125 u32 test_vector;
4126 struct clk *clk;
4127};
4128
Matt Wagantall8b38f942011-08-02 18:23:18 -07004129static DEFINE_CLK_MEASURE(l2_m_clk);
4130static DEFINE_CLK_MEASURE(krait0_m_clk);
4131static DEFINE_CLK_MEASURE(krait1_m_clk);
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004132static DEFINE_CLK_MEASURE(q6sw_clk);
4133static DEFINE_CLK_MEASURE(q6fw_clk);
4134static DEFINE_CLK_MEASURE(q6_func_clk);
Matt Wagantall8b38f942011-08-02 18:23:18 -07004135
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004136static struct measure_sel measure_mux[] = {
Stephen Boyd973e4ba2011-07-12 17:06:01 -07004137 { TEST_PER_LS(0x05), &qdss_p_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004138 { TEST_PER_LS(0x08), &slimbus_xo_src_clk.c },
4139 { TEST_PER_LS(0x12), &sdc1_p_clk.c },
4140 { TEST_PER_LS(0x13), &sdc1_clk.c },
4141 { TEST_PER_LS(0x14), &sdc2_p_clk.c },
4142 { TEST_PER_LS(0x15), &sdc2_clk.c },
4143 { TEST_PER_LS(0x16), &sdc3_p_clk.c },
4144 { TEST_PER_LS(0x17), &sdc3_clk.c },
4145 { TEST_PER_LS(0x18), &sdc4_p_clk.c },
4146 { TEST_PER_LS(0x19), &sdc4_clk.c },
4147 { TEST_PER_LS(0x1A), &sdc5_p_clk.c },
4148 { TEST_PER_LS(0x1B), &sdc5_clk.c },
4149 { TEST_PER_LS(0x25), &dfab_clk.c },
4150 { TEST_PER_LS(0x25), &dfab_a_clk.c },
4151 { TEST_PER_LS(0x26), &pmem_clk.c },
4152 { TEST_PER_LS(0x32), &dma_bam_p_clk.c },
4153 { TEST_PER_LS(0x33), &cfpb_clk.c },
4154 { TEST_PER_LS(0x33), &cfpb_a_clk.c },
4155 { TEST_PER_LS(0x3D), &gsbi1_p_clk.c },
4156 { TEST_PER_LS(0x3E), &gsbi1_uart_clk.c },
4157 { TEST_PER_LS(0x3F), &gsbi1_qup_clk.c },
4158 { TEST_PER_LS(0x41), &gsbi2_p_clk.c },
4159 { TEST_PER_LS(0x42), &gsbi2_uart_clk.c },
4160 { TEST_PER_LS(0x44), &gsbi2_qup_clk.c },
4161 { TEST_PER_LS(0x45), &gsbi3_p_clk.c },
4162 { TEST_PER_LS(0x46), &gsbi3_uart_clk.c },
4163 { TEST_PER_LS(0x48), &gsbi3_qup_clk.c },
4164 { TEST_PER_LS(0x49), &gsbi4_p_clk.c },
4165 { TEST_PER_LS(0x4A), &gsbi4_uart_clk.c },
4166 { TEST_PER_LS(0x4C), &gsbi4_qup_clk.c },
4167 { TEST_PER_LS(0x4D), &gsbi5_p_clk.c },
4168 { TEST_PER_LS(0x4E), &gsbi5_uart_clk.c },
4169 { TEST_PER_LS(0x50), &gsbi5_qup_clk.c },
4170 { TEST_PER_LS(0x51), &gsbi6_p_clk.c },
4171 { TEST_PER_LS(0x52), &gsbi6_uart_clk.c },
4172 { TEST_PER_LS(0x54), &gsbi6_qup_clk.c },
4173 { TEST_PER_LS(0x55), &gsbi7_p_clk.c },
4174 { TEST_PER_LS(0x56), &gsbi7_uart_clk.c },
4175 { TEST_PER_LS(0x58), &gsbi7_qup_clk.c },
4176 { TEST_PER_LS(0x59), &gsbi8_p_clk.c },
4177 { TEST_PER_LS(0x5A), &gsbi8_uart_clk.c },
4178 { TEST_PER_LS(0x5C), &gsbi8_qup_clk.c },
4179 { TEST_PER_LS(0x5D), &gsbi9_p_clk.c },
4180 { TEST_PER_LS(0x5E), &gsbi9_uart_clk.c },
4181 { TEST_PER_LS(0x60), &gsbi9_qup_clk.c },
4182 { TEST_PER_LS(0x61), &gsbi10_p_clk.c },
4183 { TEST_PER_LS(0x62), &gsbi10_uart_clk.c },
4184 { TEST_PER_LS(0x64), &gsbi10_qup_clk.c },
4185 { TEST_PER_LS(0x65), &gsbi11_p_clk.c },
4186 { TEST_PER_LS(0x66), &gsbi11_uart_clk.c },
4187 { TEST_PER_LS(0x68), &gsbi11_qup_clk.c },
4188 { TEST_PER_LS(0x69), &gsbi12_p_clk.c },
4189 { TEST_PER_LS(0x6A), &gsbi12_uart_clk.c },
4190 { TEST_PER_LS(0x6C), &gsbi12_qup_clk.c },
4191 { TEST_PER_LS(0x78), &sfpb_clk.c },
4192 { TEST_PER_LS(0x78), &sfpb_a_clk.c },
4193 { TEST_PER_LS(0x7A), &pmic_ssbi2_clk.c },
4194 { TEST_PER_LS(0x7B), &pmic_arb0_p_clk.c },
4195 { TEST_PER_LS(0x7C), &pmic_arb1_p_clk.c },
4196 { TEST_PER_LS(0x7D), &prng_clk.c },
4197 { TEST_PER_LS(0x7F), &rpm_msg_ram_p_clk.c },
4198 { TEST_PER_LS(0x80), &adm0_p_clk.c },
4199 { TEST_PER_LS(0x84), &usb_hs1_p_clk.c },
4200 { TEST_PER_LS(0x85), &usb_hs1_xcvr_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004201 { TEST_PER_LS(0x86), &usb_hsic_p_clk.c },
4202 { TEST_PER_LS(0x87), &usb_hsic_system_clk.c },
4203 { TEST_PER_LS(0x88), &usb_hsic_xcvr_fs_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004204 { TEST_PER_LS(0x89), &usb_fs1_p_clk.c },
4205 { TEST_PER_LS(0x8A), &usb_fs1_sys_clk.c },
4206 { TEST_PER_LS(0x8B), &usb_fs1_xcvr_clk.c },
4207 { TEST_PER_LS(0x8C), &usb_fs2_p_clk.c },
4208 { TEST_PER_LS(0x8D), &usb_fs2_sys_clk.c },
4209 { TEST_PER_LS(0x8E), &usb_fs2_xcvr_clk.c },
4210 { TEST_PER_LS(0x8F), &tsif_p_clk.c },
4211 { TEST_PER_LS(0x91), &tsif_ref_clk.c },
4212 { TEST_PER_LS(0x92), &ce1_p_clk.c },
4213 { TEST_PER_LS(0x94), &tssc_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004214 { TEST_PER_LS(0x9D), &usb_hsic_hsio_cal_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004215 { TEST_PER_LS(0xA4), &ce1_core_clk.c },
4216
4217 { TEST_PER_HS(0x07), &afab_clk.c },
4218 { TEST_PER_HS(0x07), &afab_a_clk.c },
4219 { TEST_PER_HS(0x18), &sfab_clk.c },
4220 { TEST_PER_HS(0x18), &sfab_a_clk.c },
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004221 { TEST_PER_HS(0x26), &q6sw_clk },
4222 { TEST_PER_HS(0x27), &q6fw_clk },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004223 { TEST_PER_HS(0x2A), &adm0_clk.c },
4224 { TEST_PER_HS(0x34), &ebi1_clk.c },
4225 { TEST_PER_HS(0x34), &ebi1_a_clk.c },
Stephen Boyd973e4ba2011-07-12 17:06:01 -07004226 { TEST_PER_HS(0x48), &qdss_at_clk.c },
4227 { TEST_PER_HS(0x49), &qdss_pclkdbg_clk.c },
4228 { TEST_PER_HS(0x4A), &qdss_traceclkin_clk.c },
4229 { TEST_PER_HS(0x4B), &qdss_tsctr_clk.c },
4230 { TEST_PER_HS(0x4F), &qdss_stm_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004231 { TEST_PER_HS(0x50), &usb_hsic_hsic_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004232
4233 { TEST_MM_LS(0x00), &dsi1_byte_clk.c },
4234 { TEST_MM_LS(0x01), &dsi2_byte_clk.c },
4235 { TEST_MM_LS(0x02), &cam1_clk.c },
4236 { TEST_MM_LS(0x06), &amp_p_clk.c },
Matt Wagantallc23eee92011-08-16 23:06:52 -07004237 { TEST_MM_LS(0x07), &csi_p_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004238 { TEST_MM_LS(0x08), &dsi2_s_p_clk.c },
4239 { TEST_MM_LS(0x09), &dsi1_m_p_clk.c },
4240 { TEST_MM_LS(0x0A), &dsi1_s_p_clk.c },
4241 { TEST_MM_LS(0x0C), &gfx2d0_p_clk.c },
4242 { TEST_MM_LS(0x0D), &gfx2d1_p_clk.c },
4243 { TEST_MM_LS(0x0E), &gfx3d_p_clk.c },
4244 { TEST_MM_LS(0x0F), &hdmi_m_p_clk.c },
4245 { TEST_MM_LS(0x10), &hdmi_s_p_clk.c },
4246 { TEST_MM_LS(0x11), &ijpeg_p_clk.c },
4247 { TEST_MM_LS(0x12), &imem_p_clk.c },
4248 { TEST_MM_LS(0x13), &jpegd_p_clk.c },
4249 { TEST_MM_LS(0x14), &mdp_p_clk.c },
4250 { TEST_MM_LS(0x16), &rot_p_clk.c },
4251 { TEST_MM_LS(0x17), &dsi1_esc_clk.c },
4252 { TEST_MM_LS(0x18), &smmu_p_clk.c },
4253 { TEST_MM_LS(0x19), &tv_enc_p_clk.c },
4254 { TEST_MM_LS(0x1A), &vcodec_p_clk.c },
4255 { TEST_MM_LS(0x1B), &vfe_p_clk.c },
4256 { TEST_MM_LS(0x1C), &vpe_p_clk.c },
4257 { TEST_MM_LS(0x1D), &cam0_clk.c },
4258 { TEST_MM_LS(0x1F), &hdmi_app_clk.c },
4259 { TEST_MM_LS(0x20), &mdp_vsync_clk.c },
4260 { TEST_MM_LS(0x21), &tv_dac_clk.c },
4261 { TEST_MM_LS(0x22), &tv_enc_clk.c },
4262 { TEST_MM_LS(0x23), &dsi2_esc_clk.c },
4263 { TEST_MM_LS(0x25), &mmfpb_clk.c },
4264 { TEST_MM_LS(0x25), &mmfpb_a_clk.c },
4265 { TEST_MM_LS(0x26), &dsi2_m_p_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004266 { TEST_MM_LS(0x27), &cam2_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004267
4268 { TEST_MM_HS(0x00), &csi0_clk.c },
4269 { TEST_MM_HS(0x01), &csi1_clk.c },
Matt Wagantallc23eee92011-08-16 23:06:52 -07004270 { TEST_MM_HS(0x04), &csi_vfe_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004271 { TEST_MM_HS(0x05), &ijpeg_clk.c },
4272 { TEST_MM_HS(0x06), &vfe_clk.c },
4273 { TEST_MM_HS(0x07), &gfx2d0_clk.c },
4274 { TEST_MM_HS(0x08), &gfx2d1_clk.c },
4275 { TEST_MM_HS(0x09), &gfx3d_clk.c },
4276 { TEST_MM_HS(0x0A), &jpegd_clk.c },
4277 { TEST_MM_HS(0x0B), &vcodec_clk.c },
4278 { TEST_MM_HS(0x0F), &mmfab_clk.c },
4279 { TEST_MM_HS(0x0F), &mmfab_a_clk.c },
4280 { TEST_MM_HS(0x11), &gmem_axi_clk.c },
4281 { TEST_MM_HS(0x12), &ijpeg_axi_clk.c },
4282 { TEST_MM_HS(0x13), &imem_axi_clk.c },
4283 { TEST_MM_HS(0x14), &jpegd_axi_clk.c },
4284 { TEST_MM_HS(0x15), &mdp_axi_clk.c },
4285 { TEST_MM_HS(0x16), &rot_axi_clk.c },
4286 { TEST_MM_HS(0x17), &vcodec_axi_clk.c },
4287 { TEST_MM_HS(0x18), &vfe_axi_clk.c },
4288 { TEST_MM_HS(0x19), &vpe_axi_clk.c },
4289 { TEST_MM_HS(0x1A), &mdp_clk.c },
4290 { TEST_MM_HS(0x1B), &rot_clk.c },
4291 { TEST_MM_HS(0x1C), &vpe_clk.c },
4292 { TEST_MM_HS(0x1E), &hdmi_tv_clk.c },
4293 { TEST_MM_HS(0x1F), &mdp_tv_clk.c },
4294 { TEST_MM_HS(0x24), &csi0_phy_clk.c },
4295 { TEST_MM_HS(0x25), &csi1_phy_clk.c },
4296 { TEST_MM_HS(0x26), &csi_pix_clk.c },
4297 { TEST_MM_HS(0x27), &csi_rdi_clk.c },
4298 { TEST_MM_HS(0x28), &lut_mdp_clk.c },
4299 { TEST_MM_HS(0x29), &vcodec_axi_a_clk.c },
4300 { TEST_MM_HS(0x2A), &vcodec_axi_b_clk.c },
4301 { TEST_MM_HS(0x2B), &csi1phy_timer_clk.c },
4302 { TEST_MM_HS(0x2C), &csi0phy_timer_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004303 { TEST_MM_HS(0x2D), &csi2_clk.c },
4304 { TEST_MM_HS(0x2E), &csi2_phy_clk.c },
4305 { TEST_MM_HS(0x2F), &csi2phy_timer_clk.c },
4306 { TEST_MM_HS(0x30), &csi_pix1_clk.c },
4307 { TEST_MM_HS(0x31), &csi_rdi1_clk.c },
4308 { TEST_MM_HS(0x32), &csi_rdi2_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004309
4310 { TEST_LPA(0x0F), &mi2s_bit_clk.c },
4311 { TEST_LPA(0x10), &codec_i2s_mic_bit_clk.c },
4312 { TEST_LPA(0x11), &codec_i2s_spkr_bit_clk.c },
4313 { TEST_LPA(0x12), &spare_i2s_mic_bit_clk.c },
4314 { TEST_LPA(0x13), &spare_i2s_spkr_bit_clk.c },
4315 { TEST_LPA(0x14), &pcm_clk.c },
4316 { TEST_LPA(0x1D), &audio_slimbus_clk.c },
Matt Wagantall8b38f942011-08-02 18:23:18 -07004317
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004318 { TEST_LPA_HS(0x00), &q6_func_clk },
4319
Matt Wagantall8b38f942011-08-02 18:23:18 -07004320 { TEST_CPUL2(0x1), &l2_m_clk },
4321 { TEST_CPUL2(0x2), &krait0_m_clk },
4322 { TEST_CPUL2(0x3), &krait1_m_clk },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004323};
4324
4325static struct measure_sel *find_measure_sel(struct clk *clk)
4326{
4327 int i;
4328
4329 for (i = 0; i < ARRAY_SIZE(measure_mux); i++)
4330 if (measure_mux[i].clk == clk)
4331 return &measure_mux[i];
4332 return NULL;
4333}
4334
Matt Wagantall8b38f942011-08-02 18:23:18 -07004335static int measure_clk_set_parent(struct clk *c, struct clk *parent)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004336{
4337 int ret = 0;
4338 u32 clk_sel;
4339 struct measure_sel *p;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004340 struct measure_clk *clk = to_measure_clk(c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004341 unsigned long flags;
4342
4343 if (!parent)
4344 return -EINVAL;
4345
4346 p = find_measure_sel(parent);
4347 if (!p)
4348 return -EINVAL;
4349
4350 spin_lock_irqsave(&local_clock_reg_lock, flags);
4351
Matt Wagantall8b38f942011-08-02 18:23:18 -07004352 /*
4353 * Program the test vector, measurement period (sample_ticks)
4354 * and scaling multiplier.
4355 */
4356 clk->sample_ticks = 0x10000;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004357 clk_sel = p->test_vector & TEST_CLK_SEL_MASK;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004358 clk->multiplier = 1;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004359 switch (p->test_vector >> TEST_TYPE_SHIFT) {
4360 case TEST_TYPE_PER_LS:
4361 writel_relaxed(0x4030D00|BVAL(7, 0, clk_sel), CLK_TEST_REG);
4362 break;
4363 case TEST_TYPE_PER_HS:
4364 writel_relaxed(0x4020000|BVAL(16, 10, clk_sel), CLK_TEST_REG);
4365 break;
4366 case TEST_TYPE_MM_LS:
4367 writel_relaxed(0x4030D97, CLK_TEST_REG);
4368 writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0), DBG_CFG_REG_LS_REG);
4369 break;
4370 case TEST_TYPE_MM_HS:
4371 writel_relaxed(0x402B800, CLK_TEST_REG);
4372 writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0), DBG_CFG_REG_HS_REG);
4373 break;
4374 case TEST_TYPE_LPA:
4375 writel_relaxed(0x4030D98, CLK_TEST_REG);
4376 writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0),
4377 LCC_CLK_LS_DEBUG_CFG_REG);
4378 break;
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004379 case TEST_TYPE_LPA_HS:
4380 writel_relaxed(0x402BC00, CLK_TEST_REG);
4381 writel_relaxed(BVAL(2, 1, clk_sel)|BIT(0),
4382 LCC_CLK_HS_DEBUG_CFG_REG);
4383 break;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004384 case TEST_TYPE_CPUL2:
4385 writel_relaxed(0x4030400, CLK_TEST_REG);
4386 writel_relaxed(0x80|BVAL(5, 3, clk_sel), GCC_APCS_CLK_DIAG);
4387 clk->sample_ticks = 0x4000;
4388 clk->multiplier = 2;
4389 break;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004390 default:
4391 ret = -EPERM;
4392 }
4393 /* Make sure test vector is set before starting measurements. */
4394 mb();
4395
4396 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
4397
4398 return ret;
4399}
4400
4401/* Sample clock for 'ticks' reference clock ticks. */
4402static u32 run_measurement(unsigned ticks)
4403{
4404 /* Stop counters and set the XO4 counter start value. */
4405 writel_relaxed(0x0, RINGOSC_TCXO_CTL_REG);
4406 writel_relaxed(ticks, RINGOSC_TCXO_CTL_REG);
4407
4408 /* Wait for timer to become ready. */
4409 while ((readl_relaxed(RINGOSC_STATUS_REG) & BIT(25)) != 0)
4410 cpu_relax();
4411
4412 /* Run measurement and wait for completion. */
4413 writel_relaxed(BIT(20)|ticks, RINGOSC_TCXO_CTL_REG);
4414 while ((readl_relaxed(RINGOSC_STATUS_REG) & BIT(25)) == 0)
4415 cpu_relax();
4416
4417 /* Stop counters. */
4418 writel_relaxed(0x0, RINGOSC_TCXO_CTL_REG);
4419
4420 /* Return measured ticks. */
4421 return readl_relaxed(RINGOSC_STATUS_REG) & BM(24, 0);
4422}
4423
4424
4425/* Perform a hardware rate measurement for a given clock.
4426 FOR DEBUG USE ONLY: Measurements take ~15 ms! */
Matt Wagantall8b38f942011-08-02 18:23:18 -07004427static unsigned measure_clk_get_rate(struct clk *c)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004428{
4429 unsigned long flags;
4430 u32 pdm_reg_backup, ringosc_reg_backup;
4431 u64 raw_count_short, raw_count_full;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004432 struct measure_clk *clk = to_measure_clk(c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004433 unsigned ret;
4434
4435 spin_lock_irqsave(&local_clock_reg_lock, flags);
4436
4437 /* Enable CXO/4 and RINGOSC branch and root. */
4438 pdm_reg_backup = readl_relaxed(PDM_CLK_NS_REG);
4439 ringosc_reg_backup = readl_relaxed(RINGOSC_NS_REG);
4440 writel_relaxed(0x2898, PDM_CLK_NS_REG);
4441 writel_relaxed(0xA00, RINGOSC_NS_REG);
4442
4443 /*
4444 * The ring oscillator counter will not reset if the measured clock
4445 * is not running. To detect this, run a short measurement before
4446 * the full measurement. If the raw results of the two are the same
4447 * then the clock must be off.
4448 */
4449
4450 /* Run a short measurement. (~1 ms) */
4451 raw_count_short = run_measurement(0x1000);
4452 /* Run a full measurement. (~14 ms) */
Matt Wagantall8b38f942011-08-02 18:23:18 -07004453 raw_count_full = run_measurement(clk->sample_ticks);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004454
4455 writel_relaxed(ringosc_reg_backup, RINGOSC_NS_REG);
4456 writel_relaxed(pdm_reg_backup, PDM_CLK_NS_REG);
4457
4458 /* Return 0 if the clock is off. */
4459 if (raw_count_full == raw_count_short)
4460 ret = 0;
4461 else {
4462 /* Compute rate in Hz. */
4463 raw_count_full = ((raw_count_full * 10) + 15) * 4800000;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004464 do_div(raw_count_full, ((clk->sample_ticks * 10) + 35));
4465 ret = (raw_count_full * clk->multiplier);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004466 }
4467
4468 /* Route dbg_hs_clk to PLLTEST. 300mV single-ended amplitude. */
Stephen Boyd69da8402011-07-14 17:45:31 -07004469 writel_relaxed(0x38F8, PLLTEST_PAD_CFG_REG);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004470 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
4471
4472 return ret;
4473}
4474#else /* !CONFIG_DEBUG_FS */
4475static int measure_clk_set_parent(struct clk *clk, struct clk *parent)
4476{
4477 return -EINVAL;
4478}
4479
4480static unsigned measure_clk_get_rate(struct clk *clk)
4481{
4482 return 0;
4483}
4484#endif /* CONFIG_DEBUG_FS */
4485
4486static struct clk_ops measure_clk_ops = {
4487 .set_parent = measure_clk_set_parent,
4488 .get_rate = measure_clk_get_rate,
4489 .is_local = local_clk_is_local,
4490};
4491
Matt Wagantall8b38f942011-08-02 18:23:18 -07004492static struct measure_clk measure_clk = {
4493 .c = {
4494 .dbg_name = "measure_clk",
4495 .ops = &measure_clk_ops,
4496 CLK_INIT(measure_clk.c),
4497 },
4498 .multiplier = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004499};
4500
Stephen Boyd94625ef2011-07-12 17:06:01 -07004501static struct clk_lookup msm_clocks_8960_v1[] __initdata = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004502 CLK_LOOKUP("cxo", cxo_clk.c, NULL),
4503 CLK_LOOKUP("pll2", pll2_clk.c, NULL),
4504 CLK_LOOKUP("pll8", pll8_clk.c, NULL),
4505 CLK_LOOKUP("pll4", pll4_clk.c, NULL),
Matt Wagantall8b38f942011-08-02 18:23:18 -07004506 CLK_LOOKUP("measure", measure_clk.c, "debug"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004507
4508 CLK_LOOKUP("afab_clk", afab_clk.c, NULL),
4509 CLK_LOOKUP("afab_a_clk", afab_a_clk.c, NULL),
4510 CLK_LOOKUP("cfpb_clk", cfpb_clk.c, NULL),
4511 CLK_LOOKUP("cfpb_a_clk", cfpb_a_clk.c, NULL),
4512 CLK_LOOKUP("dfab_clk", dfab_clk.c, NULL),
4513 CLK_LOOKUP("dfab_a_clk", dfab_a_clk.c, NULL),
4514 CLK_LOOKUP("ebi1_clk", ebi1_clk.c, NULL),
4515 CLK_LOOKUP("ebi1_a_clk", ebi1_a_clk.c, NULL),
4516 CLK_LOOKUP("mmfab_clk", mmfab_clk.c, NULL),
4517 CLK_LOOKUP("mmfab_a_clk", mmfab_a_clk.c, NULL),
4518 CLK_LOOKUP("mmfpb_clk", mmfpb_clk.c, NULL),
4519 CLK_LOOKUP("mmfpb_a_clk", mmfpb_a_clk.c, NULL),
4520 CLK_LOOKUP("sfab_clk", sfab_clk.c, NULL),
4521 CLK_LOOKUP("sfab_a_clk", sfab_a_clk.c, NULL),
4522 CLK_LOOKUP("sfpb_clk", sfpb_clk.c, NULL),
4523 CLK_LOOKUP("sfpb_a_clk", sfpb_a_clk.c, NULL),
4524
Matt Wagantalle2522372011-08-17 14:52:21 -07004525 CLK_LOOKUP("core_clk", gsbi1_uart_clk.c, NULL),
4526 CLK_LOOKUP("core_clk", gsbi2_uart_clk.c, NULL),
4527 CLK_LOOKUP("core_clk", gsbi3_uart_clk.c, NULL),
4528 CLK_LOOKUP("core_clk", gsbi4_uart_clk.c, NULL),
4529 CLK_LOOKUP("core_clk", gsbi5_uart_clk.c, "msm_serial_hsl.0"),
4530 CLK_LOOKUP("core_clk", gsbi6_uart_clk.c, "msm_serial_hs.0"),
4531 CLK_LOOKUP("core_clk", gsbi7_uart_clk.c, NULL),
4532 CLK_LOOKUP("core_clk", gsbi8_uart_clk.c, NULL),
4533 CLK_LOOKUP("core_clk", gsbi9_uart_clk.c, NULL),
4534 CLK_LOOKUP("core_clk", gsbi10_uart_clk.c, NULL),
4535 CLK_LOOKUP("core_clk", gsbi11_uart_clk.c, NULL),
4536 CLK_LOOKUP("core_clk", gsbi12_uart_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07004537 CLK_LOOKUP("core_clk", gsbi1_qup_clk.c, "spi_qsd.0"),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07004538 CLK_LOOKUP("core_clk", gsbi2_qup_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07004539 CLK_LOOKUP("core_clk", gsbi3_qup_clk.c, "qup_i2c.3"),
4540 CLK_LOOKUP("core_clk", gsbi4_qup_clk.c, "qup_i2c.4"),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07004541 CLK_LOOKUP("core_clk", gsbi5_qup_clk.c, NULL),
4542 CLK_LOOKUP("core_clk", gsbi6_qup_clk.c, NULL),
4543 CLK_LOOKUP("core_clk", gsbi7_qup_clk.c, NULL),
4544 CLK_LOOKUP("core_clk", gsbi8_qup_clk.c, NULL),
4545 CLK_LOOKUP("core_clk", gsbi9_qup_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07004546 CLK_LOOKUP("core_clk", gsbi10_qup_clk.c, "qup_i2c.10"),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07004547 CLK_LOOKUP("core_clk", gsbi11_qup_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07004548 CLK_LOOKUP("core_clk", gsbi12_qup_clk.c, "qup_i2c.12"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004549 CLK_LOOKUP("pdm_clk", pdm_clk.c, NULL),
Matt Wagantalld86d6832011-08-17 14:06:55 -07004550 CLK_LOOKUP("mem_clk", pmem_clk.c, NULL),
Matt Wagantallc1205292011-08-11 17:19:31 -07004551 CLK_LOOKUP("core_clk", prng_clk.c, "msm_rng.0"),
Matt Wagantall37ce3842011-08-17 16:00:36 -07004552 CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
4553 CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"),
4554 CLK_LOOKUP("core_clk", sdc3_clk.c, "msm_sdcc.3"),
4555 CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"),
4556 CLK_LOOKUP("core_clk", sdc5_clk.c, "msm_sdcc.5"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004557 CLK_LOOKUP("slimbus_xo_src_clk", slimbus_xo_src_clk.c, NULL),
Matt Wagantall640e5fd2011-08-17 16:08:53 -07004558 CLK_LOOKUP("ref_clk", tsif_ref_clk.c, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004559 CLK_LOOKUP("tssc_clk", tssc_clk.c, NULL),
4560 CLK_LOOKUP("usb_hs_clk", usb_hs1_xcvr_clk.c, NULL),
4561 CLK_LOOKUP("usb_phy_clk", usb_phy0_clk.c, NULL),
4562 CLK_LOOKUP("usb_fs_clk", usb_fs1_xcvr_clk.c, NULL),
4563 CLK_LOOKUP("usb_fs_sys_clk", usb_fs1_sys_clk.c, NULL),
4564 CLK_LOOKUP("usb_fs_src_clk", usb_fs1_src_clk.c, NULL),
4565 CLK_LOOKUP("usb_fs_clk", usb_fs2_xcvr_clk.c, NULL),
4566 CLK_LOOKUP("usb_fs_sys_clk", usb_fs2_sys_clk.c, NULL),
4567 CLK_LOOKUP("usb_fs_src_clk", usb_fs2_src_clk.c, NULL),
Matt Wagantallc4b3a4d2011-08-17 16:58:39 -07004568 CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qce.0"),
4569 CLK_LOOKUP("core_clk", ce1_core_clk.c, "qce.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004570 CLK_LOOKUP("dma_bam_pclk", dma_bam_p_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07004571 CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, "spi_qsd.0"),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07004572 CLK_LOOKUP("iface_clk", gsbi2_p_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07004573 CLK_LOOKUP("iface_clk", gsbi3_p_clk.c, "qup_i2c.3"),
4574 CLK_LOOKUP("iface_clk", gsbi4_p_clk.c, "qup_i2c.4"),
Matt Wagantalle2522372011-08-17 14:52:21 -07004575 CLK_LOOKUP("iface_clk", gsbi5_p_clk.c, "msm_serial_hsl.0"),
4576 CLK_LOOKUP("iface_clk", gsbi6_p_clk.c, "msm_serial_hs.0"),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07004577 CLK_LOOKUP("iface_clk", gsbi7_p_clk.c, NULL),
4578 CLK_LOOKUP("iface_clk", gsbi8_p_clk.c, NULL),
4579 CLK_LOOKUP("iface_clk", gsbi9_p_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07004580 CLK_LOOKUP("iface_clk", gsbi10_p_clk.c, "qup_i2c.10"),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07004581 CLK_LOOKUP("iface_clk", gsbi11_p_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07004582 CLK_LOOKUP("iface_clk", gsbi12_p_clk.c, "qup_i2c.12"),
Matt Wagantall640e5fd2011-08-17 16:08:53 -07004583 CLK_LOOKUP("iface_clk", tsif_p_clk.c, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004584 CLK_LOOKUP("usb_fs_pclk", usb_fs1_p_clk.c, NULL),
4585 CLK_LOOKUP("usb_fs_pclk", usb_fs2_p_clk.c, NULL),
4586 CLK_LOOKUP("usb_hs_pclk", usb_hs1_p_clk.c, NULL),
Matt Wagantall37ce3842011-08-17 16:00:36 -07004587 CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"),
4588 CLK_LOOKUP("iface_clk", sdc2_p_clk.c, "msm_sdcc.2"),
4589 CLK_LOOKUP("iface_clk", sdc3_p_clk.c, "msm_sdcc.3"),
4590 CLK_LOOKUP("iface_clk", sdc4_p_clk.c, "msm_sdcc.4"),
4591 CLK_LOOKUP("iface_clk", sdc5_p_clk.c, "msm_sdcc.5"),
Matt Wagantalle1a86062011-08-18 17:46:10 -07004592 CLK_LOOKUP("core_clk", adm0_clk.c, "msm_dmov"),
4593 CLK_LOOKUP("iface_clk", adm0_p_clk.c, "msm_dmov"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004594 CLK_LOOKUP("pmic_arb_pclk", pmic_arb0_p_clk.c, NULL),
4595 CLK_LOOKUP("pmic_arb_pclk", pmic_arb1_p_clk.c, NULL),
4596 CLK_LOOKUP("pmic_ssbi2", pmic_ssbi2_clk.c, NULL),
4597 CLK_LOOKUP("rpm_msg_ram_pclk", rpm_msg_ram_p_clk.c, NULL),
4598 CLK_LOOKUP("amp_clk", amp_clk.c, NULL),
4599 CLK_LOOKUP("cam_clk", cam0_clk.c, NULL),
4600 CLK_LOOKUP("cam_clk", cam1_clk.c, NULL),
4601 CLK_LOOKUP("cam_clk", cam0_clk.c, "msm_camera_imx074.0"),
4602 CLK_LOOKUP("cam_clk", cam0_clk.c, "msm_camera_ov2720.0"),
Kevin Chandfecce22011-07-13 10:52:41 -07004603 CLK_LOOKUP("cam_clk", cam0_clk.c, "msm_camera_qs_mt9p017.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004604 CLK_LOOKUP("csi_src_clk", csi0_src_clk.c, NULL),
4605 CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, NULL),
4606 CLK_LOOKUP("csi_src_clk", csi0_src_clk.c, "msm_camera_imx074.0"),
Kevin Chandfecce22011-07-13 10:52:41 -07004607 CLK_LOOKUP("csi_src_clk", csi0_src_clk.c, "msm_camera_qs_mt9p017.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004608 CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, "msm_camera_ov2720.0"),
4609 CLK_LOOKUP("csi_clk", csi0_clk.c, NULL),
4610 CLK_LOOKUP("csi_clk", csi1_clk.c, NULL),
4611 CLK_LOOKUP("csi_clk", csi0_clk.c, "msm_camera_imx074.0"),
Kevin Chandfecce22011-07-13 10:52:41 -07004612 CLK_LOOKUP("csi_clk", csi0_clk.c, "msm_camera_qs_mt9p017.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004613 CLK_LOOKUP("csi_clk", csi1_clk.c, "msm_camera_ov2720.0"),
4614 CLK_LOOKUP("csi_phy_clk", csi0_phy_clk.c, NULL),
4615 CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, NULL),
4616 CLK_LOOKUP("csi_phy_clk", csi0_phy_clk.c, "msm_camera_imx074.0"),
Kevin Chandfecce22011-07-13 10:52:41 -07004617 CLK_LOOKUP("csi_phy_clk", csi0_phy_clk.c, "msm_camera_qs_mt9p017.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004618 CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, "msm_camera_ov2720.0"),
4619 CLK_LOOKUP("csi_pix_clk", csi_pix_clk.c, NULL),
4620 CLK_LOOKUP("csi_rdi_clk", csi_rdi_clk.c, NULL),
4621 CLK_LOOKUP("csiphy_timer_src_clk", csiphy_timer_src_clk.c, NULL),
4622 CLK_LOOKUP("csi0phy_timer_clk", csi0phy_timer_clk.c, NULL),
4623 CLK_LOOKUP("csi1phy_timer_clk", csi1phy_timer_clk.c, NULL),
4624 CLK_LOOKUP("dsi_byte_div_clk", dsi1_byte_clk.c, NULL),
4625 CLK_LOOKUP("dsi_byte_div_clk", dsi2_byte_clk.c, NULL),
4626 CLK_LOOKUP("dsi_esc_clk", dsi1_esc_clk.c, NULL),
4627 CLK_LOOKUP("dsi_esc_clk", dsi2_esc_clk.c, NULL),
4628 CLK_LOOKUP("gfx2d0_clk", gfx2d0_clk.c, NULL),
4629 CLK_LOOKUP("gfx2d1_clk", gfx2d1_clk.c, NULL),
4630 CLK_LOOKUP("gfx3d_clk", gfx3d_clk.c, NULL),
4631 CLK_LOOKUP("ijpeg_axi_clk", ijpeg_axi_clk.c, NULL),
4632 CLK_LOOKUP("imem_axi_clk", imem_axi_clk.c, NULL),
4633 CLK_LOOKUP("ijpeg_clk", ijpeg_clk.c, NULL),
4634 CLK_LOOKUP("jpegd_clk", jpegd_clk.c, NULL),
4635 CLK_LOOKUP("mdp_clk", mdp_clk.c, NULL),
4636 CLK_LOOKUP("mdp_vsync_clk", mdp_vsync_clk.c, NULL),
4637 CLK_LOOKUP("lut_mdp", lut_mdp_clk.c, NULL),
Stephen Boyd973e4ba2011-07-12 17:06:01 -07004638 CLK_LOOKUP("qdss_pclk", qdss_p_clk.c, NULL),
4639 CLK_LOOKUP("qdss_at_clk", qdss_at_clk.c, NULL),
4640 CLK_LOOKUP("qdss_pclkdbg_clk", qdss_pclkdbg_clk.c, NULL),
4641 CLK_LOOKUP("qdss_traceclkin_clk", qdss_traceclkin_clk.c, NULL),
4642 CLK_LOOKUP("qdss_tsctr_clk", qdss_tsctr_clk.c, NULL),
4643 CLK_LOOKUP("qdss_stm_clk", qdss_stm_clk.c, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004644 CLK_LOOKUP("rot_clk", rot_clk.c, NULL),
4645 CLK_LOOKUP("tv_src_clk", tv_src_clk.c, NULL),
4646 CLK_LOOKUP("tv_enc_clk", tv_enc_clk.c, NULL),
4647 CLK_LOOKUP("tv_dac_clk", tv_dac_clk.c, NULL),
4648 CLK_LOOKUP("vcodec_clk", vcodec_clk.c, NULL),
4649 CLK_LOOKUP("mdp_tv_clk", mdp_tv_clk.c, NULL),
4650 CLK_LOOKUP("hdmi_clk", hdmi_tv_clk.c, NULL),
4651 CLK_LOOKUP("hdmi_app_clk", hdmi_app_clk.c, NULL),
4652 CLK_LOOKUP("vpe_clk", vpe_clk.c, NULL),
4653 CLK_LOOKUP("vfe_clk", vfe_clk.c, NULL),
Matt Wagantallc23eee92011-08-16 23:06:52 -07004654 CLK_LOOKUP("csi_vfe_clk", csi_vfe_clk.c, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004655 CLK_LOOKUP("vfe_axi_clk", vfe_axi_clk.c, NULL),
4656 CLK_LOOKUP("mdp_axi_clk", mdp_axi_clk.c, NULL),
4657 CLK_LOOKUP("rot_axi_clk", rot_axi_clk.c, NULL),
4658 CLK_LOOKUP("vcodec_axi_clk", vcodec_axi_clk.c, NULL),
4659 CLK_LOOKUP("vcodec_axi_a_clk", vcodec_axi_a_clk.c, NULL),
4660 CLK_LOOKUP("vcodec_axi_b_clk", vcodec_axi_b_clk.c, NULL),
4661 CLK_LOOKUP("vpe_axi_clk", vpe_axi_clk.c, NULL),
4662 CLK_LOOKUP("amp_pclk", amp_p_clk.c, NULL),
Matt Wagantallc23eee92011-08-16 23:06:52 -07004663 CLK_LOOKUP("csi_pclk", csi_p_clk.c, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004664 CLK_LOOKUP("dsi_m_pclk", dsi1_m_p_clk.c, NULL),
4665 CLK_LOOKUP("dsi_s_pclk", dsi1_s_p_clk.c, NULL),
4666 CLK_LOOKUP("dsi_m_pclk", dsi2_m_p_clk.c, NULL),
4667 CLK_LOOKUP("dsi_s_pclk", dsi2_s_p_clk.c, NULL),
4668 CLK_LOOKUP("gfx2d0_pclk", gfx2d0_p_clk.c, NULL),
4669 CLK_LOOKUP("gfx2d1_pclk", gfx2d1_p_clk.c, NULL),
4670 CLK_LOOKUP("gfx3d_pclk", gfx3d_p_clk.c, NULL),
4671 CLK_LOOKUP("hdmi_m_pclk", hdmi_m_p_clk.c, NULL),
4672 CLK_LOOKUP("hdmi_s_pclk", hdmi_s_p_clk.c, NULL),
4673 CLK_LOOKUP("ijpeg_pclk", ijpeg_p_clk.c, NULL),
4674 CLK_LOOKUP("jpegd_pclk", jpegd_p_clk.c, NULL),
4675 CLK_LOOKUP("imem_pclk", imem_p_clk.c, NULL),
4676 CLK_LOOKUP("mdp_pclk", mdp_p_clk.c, NULL),
4677 CLK_LOOKUP("smmu_pclk", smmu_p_clk.c, NULL),
4678 CLK_LOOKUP("rotator_pclk", rot_p_clk.c, NULL),
4679 CLK_LOOKUP("tv_enc_pclk", tv_enc_p_clk.c, NULL),
4680 CLK_LOOKUP("vcodec_pclk", vcodec_p_clk.c, NULL),
4681 CLK_LOOKUP("vfe_pclk", vfe_p_clk.c, NULL),
4682 CLK_LOOKUP("vpe_pclk", vpe_p_clk.c, NULL),
4683 CLK_LOOKUP("mi2s_bit_clk", mi2s_bit_clk.c, NULL),
4684 CLK_LOOKUP("mi2s_osr_clk", mi2s_osr_clk.c, NULL),
4685 CLK_LOOKUP("i2s_mic_bit_clk", codec_i2s_mic_bit_clk.c, NULL),
4686 CLK_LOOKUP("i2s_mic_osr_clk", codec_i2s_mic_osr_clk.c, NULL),
4687 CLK_LOOKUP("i2s_mic_bit_clk", spare_i2s_mic_bit_clk.c, NULL),
4688 CLK_LOOKUP("i2s_mic_osr_clk", spare_i2s_mic_osr_clk.c, NULL),
4689 CLK_LOOKUP("i2s_spkr_bit_clk", codec_i2s_spkr_bit_clk.c, NULL),
4690 CLK_LOOKUP("i2s_spkr_osr_clk", codec_i2s_spkr_osr_clk.c, NULL),
4691 CLK_LOOKUP("i2s_spkr_bit_clk", spare_i2s_spkr_bit_clk.c, NULL),
4692 CLK_LOOKUP("i2s_spkr_osr_clk", spare_i2s_spkr_osr_clk.c, NULL),
4693 CLK_LOOKUP("pcm_clk", pcm_clk.c, NULL),
4694 CLK_LOOKUP("sps_slimbus_clk", sps_slimbus_clk.c, NULL),
4695 CLK_LOOKUP("audio_slimbus_clk", audio_slimbus_clk.c, NULL),
4696 CLK_LOOKUP("iommu_clk", jpegd_axi_clk.c, "msm_iommu.0"),
4697 CLK_LOOKUP("iommu_clk", vpe_axi_clk.c, "msm_iommu.1"),
4698 CLK_LOOKUP("iommu_clk", mdp_axi_clk.c, "msm_iommu.2"),
4699 CLK_LOOKUP("iommu_clk", mdp_axi_clk.c, "msm_iommu.3"),
4700 CLK_LOOKUP("iommu_clk", rot_axi_clk.c, "msm_iommu.4"),
4701 CLK_LOOKUP("iommu_clk", ijpeg_axi_clk.c, "msm_iommu.5"),
4702 CLK_LOOKUP("iommu_clk", vfe_axi_clk.c, "msm_iommu.6"),
4703 CLK_LOOKUP("iommu_clk", vcodec_axi_a_clk.c, "msm_iommu.7"),
4704 CLK_LOOKUP("iommu_clk", vcodec_axi_b_clk.c, "msm_iommu.8"),
4705 CLK_LOOKUP("iommu_clk", gfx3d_clk.c, "msm_iommu.9"),
4706 CLK_LOOKUP("iommu_clk", gfx2d0_clk.c, "msm_iommu.10"),
4707 CLK_LOOKUP("iommu_clk", gfx2d1_clk.c, "msm_iommu.11"),
4708 CLK_LOOKUP("dfab_dsps_clk", dfab_dsps_clk.c, NULL),
4709 CLK_LOOKUP("dfab_usb_hs_clk", dfab_usb_hs_clk.c, NULL),
Matt Wagantall37ce3842011-08-17 16:00:36 -07004710 CLK_LOOKUP("bus_clk", dfab_sdc1_clk.c, "msm_sdcc.1"),
4711 CLK_LOOKUP("bus_clk", dfab_sdc2_clk.c, "msm_sdcc.2"),
4712 CLK_LOOKUP("bus_clk", dfab_sdc3_clk.c, "msm_sdcc.3"),
4713 CLK_LOOKUP("bus_clk", dfab_sdc4_clk.c, "msm_sdcc.4"),
4714 CLK_LOOKUP("bus_clk", dfab_sdc5_clk.c, "msm_sdcc.5"),
Yan He160633e2011-06-30 12:18:56 -07004715 CLK_LOOKUP("dfab_clk", dfab_sps_clk.c, "msm_sps"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004716
4717 CLK_LOOKUP("ebi1_msmbus_clk", ebi1_msmbus_clk.c, NULL),
Matt Wagantalle1a86062011-08-18 17:46:10 -07004718 CLK_LOOKUP("mem_clk", ebi1_adm_clk.c, "msm_dmov"),
Matt Wagantall8b38f942011-08-02 18:23:18 -07004719
4720 CLK_LOOKUP("l2_mclk", l2_m_clk, NULL),
4721 CLK_LOOKUP("krait0_mclk", krait0_m_clk, NULL),
4722 CLK_LOOKUP("krait1_mclk", krait1_m_clk, NULL),
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004723 CLK_LOOKUP("q6sw_clk", q6sw_clk, NULL),
4724 CLK_LOOKUP("q6fw_clk", q6fw_clk, NULL),
4725 CLK_LOOKUP("q6_func_clk", q6_func_clk, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004726};
4727
Stephen Boyd94625ef2011-07-12 17:06:01 -07004728static struct clk_lookup msm_clocks_8960_v2[] __initdata = {
4729 CLK_LOOKUP("cam_clk", cam2_clk.c, NULL),
4730 CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, NULL),
4731 CLK_LOOKUP("csi_clk", csi2_clk.c, NULL),
4732 CLK_LOOKUP("csi_pix1_clk", csi_pix1_clk.c, NULL),
4733 CLK_LOOKUP("csi_rdi1_clk", csi_rdi1_clk.c, NULL),
4734 CLK_LOOKUP("csi_rdi2_clk", csi_rdi2_clk.c, NULL),
4735 CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, NULL),
4736 CLK_LOOKUP("csi2phy_timer_clk", csi2phy_timer_clk.c, NULL),
4737 CLK_LOOKUP("usb_hsic_xcvr_fs_clk", usb_hsic_xcvr_fs_clk.c, NULL),
4738 CLK_LOOKUP("usb_hsic_hsic_clk", usb_hsic_hsic_clk.c, NULL),
4739 CLK_LOOKUP("usb_hsic_hsio_cal_clk", usb_hsic_hsio_cal_clk.c, NULL),
4740 CLK_LOOKUP("usb_hsic_system_clk", usb_hsic_system_clk.c, NULL),
4741 CLK_LOOKUP("usb_hsic_p_clk", usb_hsic_p_clk.c, NULL),
4742};
4743
4744/* Add v2 clocks dynamically at runtime */
4745static struct clk_lookup msm_clocks_8960[ARRAY_SIZE(msm_clocks_8960_v1) +
4746 ARRAY_SIZE(msm_clocks_8960_v2)];
4747
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004748/*
4749 * Miscellaneous clock register initializations
4750 */
4751
4752/* Read, modify, then write-back a register. */
4753static void __init rmwreg(uint32_t val, void *reg, uint32_t mask)
4754{
4755 uint32_t regval = readl_relaxed(reg);
4756 regval &= ~mask;
4757 regval |= val;
4758 writel_relaxed(regval, reg);
4759}
4760
4761static void __init reg_init(void)
4762{
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004763 /* Deassert MM SW_RESET_ALL signal. */
4764 writel_relaxed(0, SW_RESET_ALL_REG);
4765
4766 /* Initialize MM AHB registers: Enable the FPB clock and disable HW
4767 * gating for all clocks. Also set VFE_AHB's FORCE_CORE_ON bit to
4768 * prevent its memory from being collapsed when the clock is halted.
4769 * The sleep and wake-up delays are set to safe values. */
Matt Wagantall53d968f2011-07-19 13:22:53 -07004770 rmwreg(0x00000003, AHB_EN_REG, 0x6C000103);
4771 writel_relaxed(0x000007F9, AHB_EN2_REG);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004772
4773 /* Deassert all locally-owned MM AHB resets. */
4774 rmwreg(0, SW_RESET_AHB_REG, 0xFFF7DFFF);
4775
4776 /* Initialize MM AXI registers: Enable HW gating for all clocks that
4777 * support it. Also set FORCE_CORE_ON bits, and any sleep and wake-up
4778 * delays to safe values. */
4779 /* TODO: Enable HW Gating */
Matt Wagantall53d968f2011-07-19 13:22:53 -07004780 rmwreg(0x000007F9, MAXI_EN_REG, 0x0803FFFF);
4781 rmwreg(0x3027FCFF, MAXI_EN2_REG, 0x3A3FFFFF);
4782 rmwreg(0x0027FCFF, MAXI_EN3_REG, 0x003FFFFF);
4783 rmwreg(0x0027FCFF, MAXI_EN4_REG, 0x017FFFFF);
4784 rmwreg(0x000003C7, SAXI_EN_REG, 0x00003FFF);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004785
4786 /* Initialize MM CC registers: Set MM FORCE_CORE_ON bits so that core
4787 * memories retain state even when not clocked. Also, set sleep and
4788 * wake-up delays to safe values. */
Matt Wagantall53d968f2011-07-19 13:22:53 -07004789 rmwreg(0x00000000, CSI0_CC_REG, 0x00000410);
4790 rmwreg(0x00000000, CSI1_CC_REG, 0x00000410);
4791 rmwreg(0x80FF0000, DSI1_BYTE_CC_REG, 0xE0FF0010);
4792 rmwreg(0x80FF0000, DSI2_BYTE_CC_REG, 0xE0FF0010);
4793 rmwreg(0x80FF0000, DSI_PIXEL_CC_REG, 0xE0FF0010);
4794 rmwreg(0x80FF0000, DSI2_PIXEL_CC_REG, 0xE0FF0010);
4795 rmwreg(0x80FF0000, GFX2D0_CC_REG, 0xE0FF0010);
4796 rmwreg(0x80FF0000, GFX2D1_CC_REG, 0xE0FF0010);
4797 rmwreg(0x80FF0000, GFX3D_CC_REG, 0xE0FF0010);
4798 rmwreg(0x80FF0000, IJPEG_CC_REG, 0xE0FF0010);
4799 rmwreg(0x80FF0000, JPEGD_CC_REG, 0xE0FF0010);
4800 rmwreg(0x80FF0000, MDP_CC_REG, 0xE1FF0010);
4801 rmwreg(0x80FF0000, MDP_LUT_CC_REG, 0xE0FF0010);
4802 rmwreg(0x80FF0000, ROT_CC_REG, 0xE0FF0010);
4803 rmwreg(0x80FF0000, TV_CC_REG, 0xE1FFC010);
4804 rmwreg(0x000004FF, TV_CC2_REG, 0x000007FF);
4805 rmwreg(0xC0FF0000, VCODEC_CC_REG, 0xE0FF0010);
4806 rmwreg(0x80FF0000, VFE_CC_REG, 0xE0FF4010);
Stephen Boyd94625ef2011-07-12 17:06:01 -07004807 rmwreg(0x800000FF, VFE_CC2_REG, 0xE00000FF);
Matt Wagantall53d968f2011-07-19 13:22:53 -07004808 rmwreg(0x80FF0000, VPE_CC_REG, 0xE0FF0010);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004809
4810 /* De-assert MM AXI resets to all hardware blocks. */
4811 writel_relaxed(0, SW_RESET_AXI_REG);
4812
4813 /* Deassert all MM core resets. */
4814 writel_relaxed(0, SW_RESET_CORE_REG);
4815
4816 /* Reset 3D core once more, with its clock enabled. This can
4817 * eventually be done as part of the GDFS footswitch driver. */
4818 clk_set_rate(&gfx3d_clk.c, 27000000);
4819 clk_enable(&gfx3d_clk.c);
4820 writel_relaxed(BIT(12), SW_RESET_CORE_REG);
4821 mb();
4822 udelay(5);
4823 writel_relaxed(0, SW_RESET_CORE_REG);
4824 /* Make sure reset is de-asserted before clock is disabled. */
4825 mb();
4826 clk_disable(&gfx3d_clk.c);
4827
4828 /* Enable TSSC and PDM PXO sources. */
4829 writel_relaxed(BIT(11), TSSC_CLK_CTL_REG);
4830 writel_relaxed(BIT(15), PDM_CLK_NS_REG);
4831
4832 /* Source SLIMBus xo src from slimbus reference clock */
4833 writel_relaxed(0x3, SLIMBUS_XO_SRC_CLK_CTL_REG);
4834
4835 /* Source the dsi_byte_clks from the DSI PHY PLLs */
4836 rmwreg(0x1, DSI1_BYTE_NS_REG, 0x7);
4837 rmwreg(0x2, DSI2_BYTE_NS_REG, 0x7);
4838}
4839
Stephen Boyd94625ef2011-07-12 17:06:01 -07004840struct clock_init_data msm8960_clock_init_data __initdata;
4841
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004842/* Local clock driver initialization. */
Stephen Boydbb600ae2011-08-02 20:11:40 -07004843static void __init msm8960_clock_init(void)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004844{
Stephen Boyd94625ef2011-07-12 17:06:01 -07004845 size_t num_lookups = ARRAY_SIZE(msm_clocks_8960_v1);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004846 xo_pxo = msm_xo_get(MSM_XO_PXO, "clock-8960");
4847 if (IS_ERR(xo_pxo)) {
4848 pr_err("%s: msm_xo_get(PXO) failed.\n", __func__);
4849 BUG();
4850 }
4851 xo_cxo = msm_xo_get(MSM_XO_TCXO_D0, "clock-8960");
4852 if (IS_ERR(xo_cxo)) {
4853 pr_err("%s: msm_xo_get(CXO) failed.\n", __func__);
4854 BUG();
4855 }
4856
Stephen Boyd94625ef2011-07-12 17:06:01 -07004857 memcpy(msm_clocks_8960, msm_clocks_8960_v1, sizeof(msm_clocks_8960_v1));
4858 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) >= 2) {
Tianyi Goubaf6d342011-08-30 21:49:02 -07004859 gfx3d_clk.freq_tbl = clk_tbl_gfx3d_v2;
Stephen Boyd94625ef2011-07-12 17:06:01 -07004860 memcpy(msm_clocks_8960 + ARRAY_SIZE(msm_clocks_8960_v1),
4861 msm_clocks_8960_v2, sizeof(msm_clocks_8960_v2));
4862 num_lookups = ARRAY_SIZE(msm_clocks_8960);
4863 }
4864 msm8960_clock_init_data.size = num_lookups;
4865
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004866 soc_update_sys_vdd = msm8960_update_sys_vdd;
4867 local_vote_sys_vdd(HIGH);
4868
Vikram Mulukutla489e39e2011-08-31 18:04:05 -07004869 clk_ops_pll.enable = sr_pll_clk_enable;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004870
4871 /* Initialize clock registers. */
4872 reg_init();
4873
4874 /* Initialize rates for clocks that only support one. */
4875 clk_set_rate(&pdm_clk.c, 27000000);
4876 clk_set_rate(&prng_clk.c, 64000000);
4877 clk_set_rate(&mdp_vsync_clk.c, 27000000);
4878 clk_set_rate(&tsif_ref_clk.c, 105000);
4879 clk_set_rate(&tssc_clk.c, 27000000);
4880 clk_set_rate(&usb_hs1_xcvr_clk.c, 60000000);
4881 clk_set_rate(&usb_fs1_src_clk.c, 60000000);
4882 clk_set_rate(&usb_fs2_src_clk.c, 60000000);
Stephen Boyd94625ef2011-07-12 17:06:01 -07004883 clk_set_rate(&usb_hsic_xcvr_fs_clk.c, 60000000);
4884 clk_set_rate(&usb_hsic_hsic_src_clk.c, 480000000);
4885 clk_set_rate(&usb_hsic_hsio_cal_clk.c, 9000000);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004886
4887 /*
4888 * The halt status bits for PDM and TSSC may be incorrect at boot.
4889 * Toggle these clocks on and off to refresh them.
4890 */
Matt Wagantall0625ea02011-07-13 18:51:56 -07004891 rcg_clk_enable(&pdm_clk.c);
4892 rcg_clk_disable(&pdm_clk.c);
4893 rcg_clk_enable(&tssc_clk.c);
4894 rcg_clk_disable(&tssc_clk.c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004895
4896 if (machine_is_msm8960_sim()) {
4897 clk_set_rate(&sdc1_clk.c, 48000000);
4898 clk_enable(&sdc1_clk.c);
4899 clk_enable(&sdc1_p_clk.c);
4900 clk_set_rate(&sdc3_clk.c, 48000000);
4901 clk_enable(&sdc3_clk.c);
4902 clk_enable(&sdc3_p_clk.c);
4903 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004904}
4905
Stephen Boydbb600ae2011-08-02 20:11:40 -07004906static int __init msm8960_clock_late_init(void)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004907{
4908 return local_unvote_sys_vdd(HIGH);
4909}
Stephen Boydbb600ae2011-08-02 20:11:40 -07004910
4911struct clock_init_data msm8960_clock_init_data __initdata = {
4912 .table = msm_clocks_8960,
4913 .size = ARRAY_SIZE(msm_clocks_8960),
4914 .init = msm8960_clock_init,
4915 .late_init = msm8960_clock_late_init,
4916};