Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1 | /* |
Amy Maloche | 4c994c9 | 2012-02-15 09:56:15 -0800 | [diff] [blame] | 2 | * Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
| 14 | #define pr_fmt(fmt) "%s: " fmt, __func__ |
| 15 | |
| 16 | #include <linux/kernel.h> |
| 17 | #include <linux/slab.h> |
| 18 | #include <linux/spinlock.h> |
Anirudh Ghayal | 8b8f189 | 2011-11-11 10:48:41 +0530 | [diff] [blame] | 19 | #include <linux/interrupt.h> |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 20 | #include <linux/platform_device.h> |
Anirudh Ghayal | 1fd48c6 | 2011-12-13 12:39:43 +0530 | [diff] [blame] | 21 | #include <linux/delay.h> |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 22 | #include <linux/mfd/pm8xxx/core.h> |
| 23 | #include <linux/mfd/pm8xxx/misc.h> |
| 24 | |
| 25 | /* PON CTRL 1 register */ |
Anirudh Ghayal | a23c1ca | 2011-11-01 14:36:24 +0530 | [diff] [blame] | 26 | #define REG_PM8XXX_PON_CTRL_1 0x01C |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 27 | |
| 28 | #define PON_CTRL_1_PULL_UP_MASK 0xE0 |
| 29 | #define PON_CTRL_1_USB_PWR_EN 0x10 |
| 30 | |
| 31 | #define PON_CTRL_1_WD_EN_MASK 0x08 |
| 32 | #define PON_CTRL_1_WD_EN_RESET 0x08 |
| 33 | #define PON_CTRL_1_WD_EN_PWR_OFF 0x00 |
| 34 | |
Anirudh Ghayal | a4262a3 | 2011-11-10 00:02:18 +0530 | [diff] [blame] | 35 | /* PON CNTL registers */ |
| 36 | #define REG_PM8058_PON_CNTL_4 0x098 |
| 37 | #define REG_PM8901_PON_CNTL_4 0x099 |
| 38 | #define REG_PM8018_PON_CNTL_4 0x01E |
| 39 | #define REG_PM8921_PON_CNTL_4 0x01E |
| 40 | #define REG_PM8058_PON_CNTL_5 0x07B |
| 41 | #define REG_PM8901_PON_CNTL_5 0x09A |
| 42 | #define REG_PM8018_PON_CNTL_5 0x01F |
| 43 | #define REG_PM8921_PON_CNTL_5 0x01F |
| 44 | |
| 45 | #define PON_CTRL_4_RESET_EN_MASK 0x01 |
| 46 | #define PON_CTRL_4_SHUTDOWN_ON_RESET 0x0 |
| 47 | #define PON_CTRL_4_RESTART_ON_RESET 0x1 |
| 48 | #define PON_CTRL_5_HARD_RESET_EN_MASK 0x08 |
| 49 | #define PON_CTRL_5_HARD_RESET_EN 0x08 |
| 50 | #define PON_CTRL_5_HARD_RESET_DIS 0x00 |
| 51 | |
Anirudh Ghayal | 9e1bd64 | 2011-11-01 13:57:40 +0530 | [diff] [blame] | 52 | /* Regulator master enable addresses */ |
| 53 | #define REG_PM8058_VREG_EN_MSM 0x018 |
| 54 | #define REG_PM8058_VREG_EN_GRP_5_4 0x1C8 |
| 55 | |
| 56 | /* Regulator control registers for shutdown/reset */ |
| 57 | #define REG_PM8058_S0_CTRL 0x004 |
| 58 | #define REG_PM8058_S1_CTRL 0x005 |
| 59 | #define REG_PM8058_S3_CTRL 0x111 |
| 60 | #define REG_PM8058_L21_CTRL 0x120 |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 61 | #define REG_PM8058_L22_CTRL 0x121 |
| 62 | |
Anirudh Ghayal | 9e1bd64 | 2011-11-01 13:57:40 +0530 | [diff] [blame] | 63 | #define PM8058_REGULATOR_ENABLE_MASK 0x80 |
| 64 | #define PM8058_REGULATOR_ENABLE 0x80 |
| 65 | #define PM8058_REGULATOR_DISABLE 0x00 |
| 66 | #define PM8058_REGULATOR_PULL_DOWN_MASK 0x40 |
| 67 | #define PM8058_REGULATOR_PULL_DOWN_EN 0x40 |
| 68 | |
| 69 | /* Buck CTRL register */ |
| 70 | #define PM8058_SMPS_LEGACY_VREF_SEL 0x20 |
| 71 | #define PM8058_SMPS_LEGACY_VPROG_MASK 0x1F |
| 72 | #define PM8058_SMPS_ADVANCED_BAND_MASK 0xC0 |
| 73 | #define PM8058_SMPS_ADVANCED_BAND_SHIFT 6 |
| 74 | #define PM8058_SMPS_ADVANCED_VPROG_MASK 0x3F |
| 75 | |
| 76 | /* Buck TEST2 registers for shutdown/reset */ |
| 77 | #define REG_PM8058_S0_TEST2 0x084 |
| 78 | #define REG_PM8058_S1_TEST2 0x085 |
| 79 | #define REG_PM8058_S3_TEST2 0x11A |
| 80 | |
| 81 | #define PM8058_REGULATOR_BANK_WRITE 0x80 |
| 82 | #define PM8058_REGULATOR_BANK_MASK 0x70 |
| 83 | #define PM8058_REGULATOR_BANK_SHIFT 4 |
| 84 | #define PM8058_REGULATOR_BANK_SEL(n) ((n) << PM8058_REGULATOR_BANK_SHIFT) |
| 85 | |
| 86 | /* Buck TEST2 register bank 1 */ |
| 87 | #define PM8058_SMPS_LEGACY_VLOW_SEL 0x01 |
| 88 | |
| 89 | /* Buck TEST2 register bank 7 */ |
| 90 | #define PM8058_SMPS_ADVANCED_MODE_MASK 0x02 |
| 91 | #define PM8058_SMPS_ADVANCED_MODE 0x02 |
| 92 | #define PM8058_SMPS_LEGACY_MODE 0x00 |
| 93 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 94 | /* SLEEP CTRL register */ |
| 95 | #define REG_PM8058_SLEEP_CTRL 0x02B |
| 96 | #define REG_PM8921_SLEEP_CTRL 0x10A |
Jay Chokshi | 86580f2 | 2011-10-17 12:27:52 -0700 | [diff] [blame] | 97 | #define REG_PM8018_SLEEP_CTRL 0x10A |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 98 | |
| 99 | #define SLEEP_CTRL_SMPL_EN_MASK 0x04 |
| 100 | #define SLEEP_CTRL_SMPL_EN_RESET 0x04 |
| 101 | #define SLEEP_CTRL_SMPL_EN_PWR_OFF 0x00 |
| 102 | |
Anirudh Ghayal | bfbaf82 | 2011-11-01 14:28:34 +0530 | [diff] [blame] | 103 | #define SLEEP_CTRL_SMPL_SEL_MASK 0x03 |
| 104 | #define SLEEP_CTRL_SMPL_SEL_MIN 0 |
| 105 | #define SLEEP_CTRL_SMPL_SEL_MAX 3 |
| 106 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 107 | /* FTS regulator PMR registers */ |
| 108 | #define REG_PM8901_REGULATOR_S1_PMR 0xA7 |
| 109 | #define REG_PM8901_REGULATOR_S2_PMR 0xA8 |
| 110 | #define REG_PM8901_REGULATOR_S3_PMR 0xA9 |
| 111 | #define REG_PM8901_REGULATOR_S4_PMR 0xAA |
| 112 | |
| 113 | #define PM8901_REGULATOR_PMR_STATE_MASK 0x60 |
| 114 | #define PM8901_REGULATOR_PMR_STATE_OFF 0x20 |
| 115 | |
Anirudh Ghayal | 7b38229 | 2011-11-01 14:08:34 +0530 | [diff] [blame] | 116 | /* COINCELL CHG registers */ |
| 117 | #define REG_PM8058_COIN_CHG 0x02F |
| 118 | #define REG_PM8921_COIN_CHG 0x09C |
| 119 | #define REG_PM8018_COIN_CHG 0x09C |
| 120 | |
| 121 | #define COINCELL_RESISTOR_SHIFT 0x2 |
| 122 | |
Anirudh Ghayal | 51e947f | 2011-11-01 14:49:45 +0530 | [diff] [blame] | 123 | /* GP TEST register */ |
| 124 | #define REG_PM8XXX_GP_TEST_1 0x07A |
| 125 | |
| 126 | /* Stay on configuration */ |
| 127 | #define PM8XXX_STAY_ON_CFG 0x92 |
| 128 | |
Anirudh Ghayal | 5213eb8 | 2011-10-24 14:44:58 +0530 | [diff] [blame] | 129 | /* GPIO UART MUX CTRL registers */ |
| 130 | #define REG_PM8XXX_GPIO_MUX_CTRL 0x1CC |
| 131 | |
| 132 | #define UART_PATH_SEL_MASK 0x60 |
| 133 | #define UART_PATH_SEL_SHIFT 0x5 |
| 134 | |
Willie Ruan | 5db1f24 | 2012-01-30 22:08:04 -0800 | [diff] [blame] | 135 | #define USB_ID_PU_EN_MASK 0x10 /* PM8921 family only */ |
| 136 | #define USB_ID_PU_EN_SHIFT 4 |
| 137 | |
Anirudh Ghayal | 1fd48c6 | 2011-12-13 12:39:43 +0530 | [diff] [blame] | 138 | /* Shutdown/restart delays to allow for LDO 7/dVdd regulator load settling. */ |
| 139 | #define PM8901_DELAY_AFTER_REG_DISABLE_MS 4 |
| 140 | #define PM8901_DELAY_BEFORE_SHUTDOWN_MS 8 |
| 141 | |
Amy Maloche | 4c994c9 | 2012-02-15 09:56:15 -0800 | [diff] [blame] | 142 | #define REG_PM8XXX_XO_CNTRL_2 0x114 |
| 143 | #define MP3_1_MASK 0xE0 |
| 144 | #define MP3_2_MASK 0x1C |
| 145 | #define MP3_1_SHIFT 5 |
| 146 | #define MP3_2_SHIFT 2 |
| 147 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 148 | struct pm8xxx_misc_chip { |
| 149 | struct list_head link; |
| 150 | struct pm8xxx_misc_platform_data pdata; |
| 151 | struct device *dev; |
| 152 | enum pm8xxx_version version; |
Anirudh Ghayal | 8b8f189 | 2011-11-11 10:48:41 +0530 | [diff] [blame] | 153 | u64 osc_halt_count; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 154 | }; |
| 155 | |
| 156 | static LIST_HEAD(pm8xxx_misc_chips); |
| 157 | static DEFINE_SPINLOCK(pm8xxx_misc_chips_lock); |
| 158 | |
| 159 | static int pm8xxx_misc_masked_write(struct pm8xxx_misc_chip *chip, u16 addr, |
| 160 | u8 mask, u8 val) |
| 161 | { |
| 162 | int rc; |
| 163 | u8 reg; |
| 164 | |
| 165 | rc = pm8xxx_readb(chip->dev->parent, addr, ®); |
| 166 | if (rc) { |
| 167 | pr_err("pm8xxx_readb(0x%03X) failed, rc=%d\n", addr, rc); |
| 168 | return rc; |
| 169 | } |
| 170 | reg &= ~mask; |
| 171 | reg |= val & mask; |
| 172 | rc = pm8xxx_writeb(chip->dev->parent, addr, reg); |
| 173 | if (rc) |
| 174 | pr_err("pm8xxx_writeb(0x%03X)=0x%02X failed, rc=%d\n", addr, |
| 175 | reg, rc); |
| 176 | return rc; |
| 177 | } |
| 178 | |
Anirudh Ghayal | 9e1bd64 | 2011-11-01 13:57:40 +0530 | [diff] [blame] | 179 | /* |
| 180 | * Set an SMPS regulator to be disabled in its CTRL register, but enabled |
| 181 | * in the master enable register. Also set it's pull down enable bit. |
| 182 | * Take care to make sure that the output voltage doesn't change if switching |
| 183 | * from advanced mode to legacy mode. |
| 184 | */ |
| 185 | static int |
| 186 | __pm8058_disable_smps_locally_set_pull_down(struct pm8xxx_misc_chip *chip, |
| 187 | u16 ctrl_addr, u16 test2_addr, u16 master_enable_addr, |
| 188 | u8 master_enable_bit) |
| 189 | { |
| 190 | int rc = 0; |
| 191 | u8 vref_sel, vlow_sel, band, vprog, bank, reg; |
| 192 | |
| 193 | bank = PM8058_REGULATOR_BANK_SEL(7); |
| 194 | rc = pm8xxx_writeb(chip->dev->parent, test2_addr, bank); |
| 195 | if (rc) { |
| 196 | pr_err("%s: pm8xxx_writeb(0x%03X) failed: rc=%d\n", __func__, |
| 197 | test2_addr, rc); |
| 198 | goto done; |
| 199 | } |
| 200 | |
| 201 | rc = pm8xxx_readb(chip->dev->parent, test2_addr, ®); |
| 202 | if (rc) { |
| 203 | pr_err("%s: FAIL pm8xxx_readb(0x%03X): rc=%d\n", |
| 204 | __func__, test2_addr, rc); |
| 205 | goto done; |
| 206 | } |
| 207 | |
| 208 | /* Check if in advanced mode. */ |
| 209 | if ((reg & PM8058_SMPS_ADVANCED_MODE_MASK) == |
| 210 | PM8058_SMPS_ADVANCED_MODE) { |
| 211 | /* Determine current output voltage. */ |
| 212 | rc = pm8xxx_readb(chip->dev->parent, ctrl_addr, ®); |
| 213 | if (rc) { |
| 214 | pr_err("%s: FAIL pm8xxx_readb(0x%03X): rc=%d\n", |
| 215 | __func__, ctrl_addr, rc); |
| 216 | goto done; |
| 217 | } |
| 218 | |
| 219 | band = (reg & PM8058_SMPS_ADVANCED_BAND_MASK) |
| 220 | >> PM8058_SMPS_ADVANCED_BAND_SHIFT; |
| 221 | switch (band) { |
| 222 | case 3: |
| 223 | vref_sel = 0; |
| 224 | vlow_sel = 0; |
| 225 | break; |
| 226 | case 2: |
| 227 | vref_sel = PM8058_SMPS_LEGACY_VREF_SEL; |
| 228 | vlow_sel = 0; |
| 229 | break; |
| 230 | case 1: |
| 231 | vref_sel = PM8058_SMPS_LEGACY_VREF_SEL; |
| 232 | vlow_sel = PM8058_SMPS_LEGACY_VLOW_SEL; |
| 233 | break; |
| 234 | default: |
| 235 | pr_err("%s: regulator already disabled\n", __func__); |
| 236 | return -EPERM; |
| 237 | } |
| 238 | vprog = (reg & PM8058_SMPS_ADVANCED_VPROG_MASK); |
| 239 | /* Round up if fine step is in use. */ |
| 240 | vprog = (vprog + 1) >> 1; |
| 241 | if (vprog > PM8058_SMPS_LEGACY_VPROG_MASK) |
| 242 | vprog = PM8058_SMPS_LEGACY_VPROG_MASK; |
| 243 | |
| 244 | /* Set VLOW_SEL bit. */ |
| 245 | bank = PM8058_REGULATOR_BANK_SEL(1); |
| 246 | rc = pm8xxx_writeb(chip->dev->parent, test2_addr, bank); |
| 247 | if (rc) { |
| 248 | pr_err("%s: FAIL pm8xxx_writeb(0x%03X): rc=%d\n", |
| 249 | __func__, test2_addr, rc); |
| 250 | goto done; |
| 251 | } |
| 252 | |
| 253 | rc = pm8xxx_misc_masked_write(chip, test2_addr, |
| 254 | PM8058_REGULATOR_BANK_WRITE | PM8058_REGULATOR_BANK_MASK |
| 255 | | PM8058_SMPS_LEGACY_VLOW_SEL, |
| 256 | PM8058_REGULATOR_BANK_WRITE | |
| 257 | PM8058_REGULATOR_BANK_SEL(1) | vlow_sel); |
| 258 | if (rc) |
| 259 | goto done; |
| 260 | |
| 261 | /* Switch to legacy mode */ |
| 262 | bank = PM8058_REGULATOR_BANK_SEL(7); |
| 263 | rc = pm8xxx_writeb(chip->dev->parent, test2_addr, bank); |
| 264 | if (rc) { |
| 265 | pr_err("%s: FAIL pm8xxx_writeb(0x%03X): rc=%d\n", |
| 266 | __func__, test2_addr, rc); |
| 267 | goto done; |
| 268 | } |
| 269 | rc = pm8xxx_misc_masked_write(chip, test2_addr, |
| 270 | PM8058_REGULATOR_BANK_WRITE | |
| 271 | PM8058_REGULATOR_BANK_MASK | |
| 272 | PM8058_SMPS_ADVANCED_MODE_MASK, |
| 273 | PM8058_REGULATOR_BANK_WRITE | |
| 274 | PM8058_REGULATOR_BANK_SEL(7) | |
| 275 | PM8058_SMPS_LEGACY_MODE); |
| 276 | if (rc) |
| 277 | goto done; |
| 278 | |
| 279 | /* Enable locally, enable pull down, keep voltage the same. */ |
| 280 | rc = pm8xxx_misc_masked_write(chip, ctrl_addr, |
| 281 | PM8058_REGULATOR_ENABLE_MASK | |
| 282 | PM8058_REGULATOR_PULL_DOWN_MASK | |
| 283 | PM8058_SMPS_LEGACY_VREF_SEL | |
| 284 | PM8058_SMPS_LEGACY_VPROG_MASK, |
| 285 | PM8058_REGULATOR_ENABLE | PM8058_REGULATOR_PULL_DOWN_EN |
| 286 | | vref_sel | vprog); |
| 287 | if (rc) |
| 288 | goto done; |
| 289 | } |
| 290 | |
| 291 | /* Enable in master control register. */ |
| 292 | rc = pm8xxx_misc_masked_write(chip, master_enable_addr, |
| 293 | master_enable_bit, master_enable_bit); |
| 294 | if (rc) |
| 295 | goto done; |
| 296 | |
| 297 | /* Disable locally and enable pull down. */ |
| 298 | rc = pm8xxx_misc_masked_write(chip, ctrl_addr, |
| 299 | PM8058_REGULATOR_ENABLE_MASK | PM8058_REGULATOR_PULL_DOWN_MASK, |
| 300 | PM8058_REGULATOR_DISABLE | PM8058_REGULATOR_PULL_DOWN_EN); |
| 301 | |
| 302 | done: |
| 303 | return rc; |
| 304 | } |
| 305 | |
| 306 | static int |
| 307 | __pm8058_disable_ldo_locally_set_pull_down(struct pm8xxx_misc_chip *chip, |
| 308 | u16 ctrl_addr, u16 master_enable_addr, u8 master_enable_bit) |
| 309 | { |
| 310 | int rc; |
| 311 | |
| 312 | /* Enable LDO in master control register. */ |
| 313 | rc = pm8xxx_misc_masked_write(chip, master_enable_addr, |
| 314 | master_enable_bit, master_enable_bit); |
| 315 | if (rc) |
| 316 | goto done; |
| 317 | |
| 318 | /* Disable LDO in CTRL register and set pull down */ |
| 319 | rc = pm8xxx_misc_masked_write(chip, ctrl_addr, |
| 320 | PM8058_REGULATOR_ENABLE_MASK | PM8058_REGULATOR_PULL_DOWN_MASK, |
| 321 | PM8058_REGULATOR_DISABLE | PM8058_REGULATOR_PULL_DOWN_EN); |
| 322 | |
| 323 | done: |
| 324 | return rc; |
| 325 | } |
| 326 | |
Jay Chokshi | 86580f2 | 2011-10-17 12:27:52 -0700 | [diff] [blame] | 327 | static int __pm8018_reset_pwr_off(struct pm8xxx_misc_chip *chip, int reset) |
| 328 | { |
| 329 | int rc; |
| 330 | |
| 331 | /* Enable SMPL if resetting is desired. */ |
| 332 | rc = pm8xxx_misc_masked_write(chip, REG_PM8018_SLEEP_CTRL, |
| 333 | SLEEP_CTRL_SMPL_EN_MASK, |
| 334 | (reset ? SLEEP_CTRL_SMPL_EN_RESET : SLEEP_CTRL_SMPL_EN_PWR_OFF)); |
| 335 | if (rc) { |
| 336 | pr_err("pm8xxx_misc_masked_write failed, rc=%d\n", rc); |
| 337 | return rc; |
| 338 | } |
| 339 | |
| 340 | /* |
| 341 | * Select action to perform (reset or shutdown) when PS_HOLD goes low. |
| 342 | * Also ensure that KPD, CBL0, and CBL1 pull ups are enabled and that |
| 343 | * USB charging is enabled. |
| 344 | */ |
Anirudh Ghayal | a23c1ca | 2011-11-01 14:36:24 +0530 | [diff] [blame] | 345 | rc = pm8xxx_misc_masked_write(chip, REG_PM8XXX_PON_CTRL_1, |
Jay Chokshi | 86580f2 | 2011-10-17 12:27:52 -0700 | [diff] [blame] | 346 | PON_CTRL_1_PULL_UP_MASK | PON_CTRL_1_USB_PWR_EN |
| 347 | | PON_CTRL_1_WD_EN_MASK, |
| 348 | PON_CTRL_1_PULL_UP_MASK | PON_CTRL_1_USB_PWR_EN |
| 349 | | (reset ? PON_CTRL_1_WD_EN_RESET : PON_CTRL_1_WD_EN_PWR_OFF)); |
| 350 | if (rc) |
| 351 | pr_err("pm8xxx_misc_masked_write failed, rc=%d\n", rc); |
| 352 | |
| 353 | return rc; |
| 354 | } |
| 355 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 356 | static int __pm8058_reset_pwr_off(struct pm8xxx_misc_chip *chip, int reset) |
| 357 | { |
| 358 | int rc; |
| 359 | |
Anirudh Ghayal | 9e1bd64 | 2011-11-01 13:57:40 +0530 | [diff] [blame] | 360 | /* When shutting down, enable active pulldowns on important rails. */ |
| 361 | if (!reset) { |
| 362 | /* Disable SMPS's 0,1,3 locally and set pulldown enable bits. */ |
| 363 | __pm8058_disable_smps_locally_set_pull_down(chip, |
| 364 | REG_PM8058_S0_CTRL, REG_PM8058_S0_TEST2, |
| 365 | REG_PM8058_VREG_EN_MSM, BIT(7)); |
| 366 | __pm8058_disable_smps_locally_set_pull_down(chip, |
| 367 | REG_PM8058_S1_CTRL, REG_PM8058_S1_TEST2, |
| 368 | REG_PM8058_VREG_EN_MSM, BIT(6)); |
| 369 | __pm8058_disable_smps_locally_set_pull_down(chip, |
| 370 | REG_PM8058_S3_CTRL, REG_PM8058_S3_TEST2, |
| 371 | REG_PM8058_VREG_EN_GRP_5_4, BIT(7) | BIT(4)); |
| 372 | /* Disable LDO 21 locally and set pulldown enable bit. */ |
| 373 | __pm8058_disable_ldo_locally_set_pull_down(chip, |
| 374 | REG_PM8058_L21_CTRL, REG_PM8058_VREG_EN_GRP_5_4, |
| 375 | BIT(1)); |
| 376 | } |
| 377 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 378 | /* |
| 379 | * Fix-up: Set regulator LDO22 to 1.225 V in high power mode. Leave its |
| 380 | * pull-down state intact. This ensures a safe shutdown. |
| 381 | */ |
| 382 | rc = pm8xxx_misc_masked_write(chip, REG_PM8058_L22_CTRL, 0xBF, 0x93); |
| 383 | if (rc) { |
| 384 | pr_err("pm8xxx_misc_masked_write failed, rc=%d\n", rc); |
| 385 | goto read_write_err; |
| 386 | } |
| 387 | |
| 388 | /* Enable SMPL if resetting is desired. */ |
| 389 | rc = pm8xxx_misc_masked_write(chip, REG_PM8058_SLEEP_CTRL, |
| 390 | SLEEP_CTRL_SMPL_EN_MASK, |
| 391 | (reset ? SLEEP_CTRL_SMPL_EN_RESET : SLEEP_CTRL_SMPL_EN_PWR_OFF)); |
| 392 | if (rc) { |
| 393 | pr_err("pm8xxx_misc_masked_write failed, rc=%d\n", rc); |
| 394 | goto read_write_err; |
| 395 | } |
| 396 | |
| 397 | /* |
| 398 | * Select action to perform (reset or shutdown) when PS_HOLD goes low. |
| 399 | * Also ensure that KPD, CBL0, and CBL1 pull ups are enabled and that |
| 400 | * USB charging is enabled. |
| 401 | */ |
Anirudh Ghayal | a23c1ca | 2011-11-01 14:36:24 +0530 | [diff] [blame] | 402 | rc = pm8xxx_misc_masked_write(chip, REG_PM8XXX_PON_CTRL_1, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 403 | PON_CTRL_1_PULL_UP_MASK | PON_CTRL_1_USB_PWR_EN |
| 404 | | PON_CTRL_1_WD_EN_MASK, |
| 405 | PON_CTRL_1_PULL_UP_MASK | PON_CTRL_1_USB_PWR_EN |
| 406 | | (reset ? PON_CTRL_1_WD_EN_RESET : PON_CTRL_1_WD_EN_PWR_OFF)); |
| 407 | if (rc) { |
| 408 | pr_err("pm8xxx_misc_masked_write failed, rc=%d\n", rc); |
| 409 | goto read_write_err; |
| 410 | } |
| 411 | |
| 412 | read_write_err: |
| 413 | return rc; |
| 414 | } |
| 415 | |
| 416 | static int __pm8901_reset_pwr_off(struct pm8xxx_misc_chip *chip, int reset) |
| 417 | { |
| 418 | int rc = 0, i; |
| 419 | u8 pmr_addr[4] = { |
| 420 | REG_PM8901_REGULATOR_S2_PMR, |
| 421 | REG_PM8901_REGULATOR_S3_PMR, |
| 422 | REG_PM8901_REGULATOR_S4_PMR, |
| 423 | REG_PM8901_REGULATOR_S1_PMR, |
| 424 | }; |
| 425 | |
| 426 | /* Fix-up: Turn off regulators S1, S2, S3, S4 when shutting down. */ |
| 427 | if (!reset) { |
| 428 | for (i = 0; i < 4; i++) { |
| 429 | rc = pm8xxx_misc_masked_write(chip, pmr_addr[i], |
| 430 | PM8901_REGULATOR_PMR_STATE_MASK, |
| 431 | PM8901_REGULATOR_PMR_STATE_OFF); |
| 432 | if (rc) { |
| 433 | pr_err("pm8xxx_misc_masked_write failed, " |
| 434 | "rc=%d\n", rc); |
| 435 | goto read_write_err; |
| 436 | } |
Anirudh Ghayal | 1fd48c6 | 2011-12-13 12:39:43 +0530 | [diff] [blame] | 437 | mdelay(PM8901_DELAY_AFTER_REG_DISABLE_MS); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 438 | } |
| 439 | } |
| 440 | |
| 441 | read_write_err: |
Anirudh Ghayal | 1fd48c6 | 2011-12-13 12:39:43 +0530 | [diff] [blame] | 442 | mdelay(PM8901_DELAY_BEFORE_SHUTDOWN_MS); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 443 | return rc; |
| 444 | } |
| 445 | |
| 446 | static int __pm8921_reset_pwr_off(struct pm8xxx_misc_chip *chip, int reset) |
| 447 | { |
| 448 | int rc; |
| 449 | |
| 450 | /* Enable SMPL if resetting is desired. */ |
| 451 | rc = pm8xxx_misc_masked_write(chip, REG_PM8921_SLEEP_CTRL, |
| 452 | SLEEP_CTRL_SMPL_EN_MASK, |
| 453 | (reset ? SLEEP_CTRL_SMPL_EN_RESET : SLEEP_CTRL_SMPL_EN_PWR_OFF)); |
| 454 | if (rc) { |
| 455 | pr_err("pm8xxx_misc_masked_write failed, rc=%d\n", rc); |
| 456 | goto read_write_err; |
| 457 | } |
| 458 | |
| 459 | /* |
| 460 | * Select action to perform (reset or shutdown) when PS_HOLD goes low. |
| 461 | * Also ensure that KPD, CBL0, and CBL1 pull ups are enabled and that |
| 462 | * USB charging is enabled. |
| 463 | */ |
Anirudh Ghayal | a23c1ca | 2011-11-01 14:36:24 +0530 | [diff] [blame] | 464 | rc = pm8xxx_misc_masked_write(chip, REG_PM8XXX_PON_CTRL_1, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 465 | PON_CTRL_1_PULL_UP_MASK | PON_CTRL_1_USB_PWR_EN |
| 466 | | PON_CTRL_1_WD_EN_MASK, |
| 467 | PON_CTRL_1_PULL_UP_MASK | PON_CTRL_1_USB_PWR_EN |
| 468 | | (reset ? PON_CTRL_1_WD_EN_RESET : PON_CTRL_1_WD_EN_PWR_OFF)); |
| 469 | if (rc) { |
| 470 | pr_err("pm8xxx_misc_masked_write failed, rc=%d\n", rc); |
| 471 | goto read_write_err; |
| 472 | } |
| 473 | |
| 474 | read_write_err: |
| 475 | return rc; |
| 476 | } |
| 477 | |
| 478 | /** |
| 479 | * pm8xxx_reset_pwr_off - switch all PM8XXX PMIC chips attached to the system to |
| 480 | * either reset or shutdown when they are turned off |
| 481 | * @reset: 0 = shudown the PMICs, 1 = shutdown and then restart the PMICs |
| 482 | * |
| 483 | * RETURNS: an appropriate -ERRNO error value on error, or zero for success. |
| 484 | */ |
| 485 | int pm8xxx_reset_pwr_off(int reset) |
| 486 | { |
| 487 | struct pm8xxx_misc_chip *chip; |
| 488 | unsigned long flags; |
| 489 | int rc = 0; |
| 490 | |
| 491 | spin_lock_irqsave(&pm8xxx_misc_chips_lock, flags); |
| 492 | |
| 493 | /* Loop over all attached PMICs and call specific functions for them. */ |
| 494 | list_for_each_entry(chip, &pm8xxx_misc_chips, link) { |
| 495 | switch (chip->version) { |
Jay Chokshi | 86580f2 | 2011-10-17 12:27:52 -0700 | [diff] [blame] | 496 | case PM8XXX_VERSION_8018: |
| 497 | rc = __pm8018_reset_pwr_off(chip, reset); |
| 498 | break; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 499 | case PM8XXX_VERSION_8058: |
| 500 | rc = __pm8058_reset_pwr_off(chip, reset); |
| 501 | break; |
| 502 | case PM8XXX_VERSION_8901: |
| 503 | rc = __pm8901_reset_pwr_off(chip, reset); |
| 504 | break; |
David Keitel | 4256483 | 2012-05-02 13:58:02 -0700 | [diff] [blame] | 505 | case PM8XXX_VERSION_8038: |
| 506 | case PM8XXX_VERSION_8917: |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 507 | case PM8XXX_VERSION_8921: |
| 508 | rc = __pm8921_reset_pwr_off(chip, reset); |
| 509 | break; |
| 510 | default: |
| 511 | /* PMIC doesn't have reset_pwr_off; do nothing. */ |
| 512 | break; |
| 513 | } |
| 514 | if (rc) { |
| 515 | pr_err("reset_pwr_off failed, rc=%d\n", rc); |
| 516 | break; |
| 517 | } |
| 518 | } |
| 519 | |
| 520 | spin_unlock_irqrestore(&pm8xxx_misc_chips_lock, flags); |
| 521 | |
| 522 | return rc; |
| 523 | } |
| 524 | EXPORT_SYMBOL_GPL(pm8xxx_reset_pwr_off); |
| 525 | |
Anirudh Ghayal | 7b38229 | 2011-11-01 14:08:34 +0530 | [diff] [blame] | 526 | /** |
Anirudh Ghayal | bfbaf82 | 2011-11-01 14:28:34 +0530 | [diff] [blame] | 527 | * pm8xxx_smpl_control - enables/disables SMPL detection |
| 528 | * @enable: 0 = shutdown PMIC on power loss, 1 = reset PMIC on power loss |
| 529 | * |
| 530 | * This function enables or disables the Sudden Momentary Power Loss detection |
| 531 | * module. If SMPL detection is enabled, then when a sufficiently long power |
| 532 | * loss event occurs, the PMIC will automatically reset itself. If SMPL |
| 533 | * detection is disabled, then the PMIC will shutdown when power loss occurs. |
| 534 | * |
| 535 | * RETURNS: an appropriate -ERRNO error value on error, or zero for success. |
| 536 | */ |
| 537 | int pm8xxx_smpl_control(int enable) |
| 538 | { |
| 539 | struct pm8xxx_misc_chip *chip; |
| 540 | unsigned long flags; |
| 541 | int rc = 0; |
| 542 | |
| 543 | spin_lock_irqsave(&pm8xxx_misc_chips_lock, flags); |
| 544 | |
| 545 | /* Loop over all attached PMICs and call specific functions for them. */ |
| 546 | list_for_each_entry(chip, &pm8xxx_misc_chips, link) { |
| 547 | switch (chip->version) { |
| 548 | case PM8XXX_VERSION_8018: |
| 549 | rc = pm8xxx_misc_masked_write(chip, |
| 550 | REG_PM8018_SLEEP_CTRL, SLEEP_CTRL_SMPL_EN_MASK, |
David Collins | c06e0d6 | 2012-02-13 14:42:09 -0800 | [diff] [blame] | 551 | (enable ? SLEEP_CTRL_SMPL_EN_RESET |
Anirudh Ghayal | bfbaf82 | 2011-11-01 14:28:34 +0530 | [diff] [blame] | 552 | : SLEEP_CTRL_SMPL_EN_PWR_OFF)); |
| 553 | break; |
| 554 | case PM8XXX_VERSION_8058: |
| 555 | rc = pm8xxx_misc_masked_write(chip, |
| 556 | REG_PM8058_SLEEP_CTRL, SLEEP_CTRL_SMPL_EN_MASK, |
| 557 | (enable ? SLEEP_CTRL_SMPL_EN_RESET |
| 558 | : SLEEP_CTRL_SMPL_EN_PWR_OFF)); |
| 559 | break; |
| 560 | case PM8XXX_VERSION_8921: |
| 561 | rc = pm8xxx_misc_masked_write(chip, |
| 562 | REG_PM8921_SLEEP_CTRL, SLEEP_CTRL_SMPL_EN_MASK, |
David Collins | c06e0d6 | 2012-02-13 14:42:09 -0800 | [diff] [blame] | 563 | (enable ? SLEEP_CTRL_SMPL_EN_RESET |
Anirudh Ghayal | bfbaf82 | 2011-11-01 14:28:34 +0530 | [diff] [blame] | 564 | : SLEEP_CTRL_SMPL_EN_PWR_OFF)); |
| 565 | break; |
| 566 | default: |
| 567 | /* PMIC doesn't have reset_pwr_off; do nothing. */ |
| 568 | break; |
| 569 | } |
| 570 | if (rc) { |
| 571 | pr_err("setting smpl control failed, rc=%d\n", rc); |
| 572 | break; |
| 573 | } |
| 574 | } |
| 575 | |
| 576 | spin_unlock_irqrestore(&pm8xxx_misc_chips_lock, flags); |
| 577 | |
| 578 | return rc; |
| 579 | } |
| 580 | EXPORT_SYMBOL(pm8xxx_smpl_control); |
| 581 | |
| 582 | |
| 583 | /** |
| 584 | * pm8xxx_smpl_set_delay - sets the SMPL detection time delay |
| 585 | * @delay: enum value corresponding to delay time |
| 586 | * |
| 587 | * This function sets the time delay of the SMPL detection module. If power |
| 588 | * is reapplied within this interval, then the PMIC reset automatically. The |
| 589 | * SMPL detection module must be enabled for this delay time to take effect. |
| 590 | * |
| 591 | * RETURNS: an appropriate -ERRNO error value on error, or zero for success. |
| 592 | */ |
| 593 | int pm8xxx_smpl_set_delay(enum pm8xxx_smpl_delay delay) |
| 594 | { |
| 595 | struct pm8xxx_misc_chip *chip; |
| 596 | unsigned long flags; |
| 597 | int rc = 0; |
| 598 | |
| 599 | if (delay < SLEEP_CTRL_SMPL_SEL_MIN |
| 600 | || delay > SLEEP_CTRL_SMPL_SEL_MAX) { |
| 601 | pr_err("%s: invalid delay specified: %d\n", __func__, delay); |
| 602 | return -EINVAL; |
| 603 | } |
| 604 | |
| 605 | spin_lock_irqsave(&pm8xxx_misc_chips_lock, flags); |
| 606 | |
| 607 | /* Loop over all attached PMICs and call specific functions for them. */ |
| 608 | list_for_each_entry(chip, &pm8xxx_misc_chips, link) { |
| 609 | switch (chip->version) { |
| 610 | case PM8XXX_VERSION_8018: |
| 611 | rc = pm8xxx_misc_masked_write(chip, |
| 612 | REG_PM8018_SLEEP_CTRL, SLEEP_CTRL_SMPL_SEL_MASK, |
| 613 | delay); |
| 614 | break; |
| 615 | case PM8XXX_VERSION_8058: |
| 616 | rc = pm8xxx_misc_masked_write(chip, |
| 617 | REG_PM8058_SLEEP_CTRL, SLEEP_CTRL_SMPL_SEL_MASK, |
| 618 | delay); |
| 619 | break; |
| 620 | case PM8XXX_VERSION_8921: |
| 621 | rc = pm8xxx_misc_masked_write(chip, |
| 622 | REG_PM8921_SLEEP_CTRL, SLEEP_CTRL_SMPL_SEL_MASK, |
| 623 | delay); |
| 624 | break; |
| 625 | default: |
| 626 | /* PMIC doesn't have reset_pwr_off; do nothing. */ |
| 627 | break; |
| 628 | } |
| 629 | if (rc) { |
| 630 | pr_err("setting smpl delay failed, rc=%d\n", rc); |
| 631 | break; |
| 632 | } |
| 633 | } |
| 634 | |
| 635 | spin_unlock_irqrestore(&pm8xxx_misc_chips_lock, flags); |
| 636 | |
| 637 | return rc; |
| 638 | } |
| 639 | EXPORT_SYMBOL(pm8xxx_smpl_set_delay); |
| 640 | |
| 641 | /** |
Anirudh Ghayal | 7b38229 | 2011-11-01 14:08:34 +0530 | [diff] [blame] | 642 | * pm8xxx_coincell_chg_config - Disables or enables the coincell charger, and |
| 643 | * configures its voltage and resistor settings. |
| 644 | * @chg_config: Holds both voltage and resistor values, and a |
| 645 | * switch to change the state of charger. |
| 646 | * If state is to disable the charger then |
| 647 | * both voltage and resistor are disregarded. |
| 648 | * |
| 649 | * RETURNS: an appropriate -ERRNO error value on error, or zero for success. |
| 650 | */ |
| 651 | int pm8xxx_coincell_chg_config(struct pm8xxx_coincell_chg *chg_config) |
| 652 | { |
| 653 | struct pm8xxx_misc_chip *chip; |
| 654 | unsigned long flags; |
| 655 | u8 reg = 0, voltage, resistor; |
| 656 | int rc = 0; |
| 657 | |
| 658 | if (chg_config == NULL) { |
| 659 | pr_err("chg_config is NULL\n"); |
| 660 | return -EINVAL; |
| 661 | } |
| 662 | |
| 663 | voltage = chg_config->voltage; |
| 664 | resistor = chg_config->resistor; |
| 665 | |
| 666 | if (resistor < PM8XXX_COINCELL_RESISTOR_2100_OHMS || |
| 667 | resistor > PM8XXX_COINCELL_RESISTOR_800_OHMS) { |
| 668 | pr_err("Invalid resistor value provided\n"); |
| 669 | return -EINVAL; |
| 670 | } |
| 671 | |
| 672 | if (voltage < PM8XXX_COINCELL_VOLTAGE_3p2V || |
| 673 | (voltage > PM8XXX_COINCELL_VOLTAGE_3p0V && |
| 674 | voltage != PM8XXX_COINCELL_VOLTAGE_2p5V)) { |
| 675 | pr_err("Invalid voltage value provided\n"); |
| 676 | return -EINVAL; |
| 677 | } |
| 678 | |
| 679 | if (chg_config->state == PM8XXX_COINCELL_CHG_DISABLE) { |
| 680 | reg = 0; |
| 681 | } else { |
| 682 | reg |= voltage; |
| 683 | reg |= (resistor << COINCELL_RESISTOR_SHIFT); |
| 684 | } |
| 685 | |
| 686 | spin_lock_irqsave(&pm8xxx_misc_chips_lock, flags); |
| 687 | |
| 688 | /* Loop over all attached PMICs and call specific functions for them. */ |
| 689 | list_for_each_entry(chip, &pm8xxx_misc_chips, link) { |
| 690 | switch (chip->version) { |
| 691 | case PM8XXX_VERSION_8018: |
| 692 | rc = pm8xxx_writeb(chip->dev->parent, |
| 693 | REG_PM8018_COIN_CHG, reg); |
| 694 | break; |
| 695 | case PM8XXX_VERSION_8058: |
| 696 | rc = pm8xxx_writeb(chip->dev->parent, |
| 697 | REG_PM8058_COIN_CHG, reg); |
| 698 | break; |
| 699 | case PM8XXX_VERSION_8921: |
| 700 | rc = pm8xxx_writeb(chip->dev->parent, |
| 701 | REG_PM8921_COIN_CHG, reg); |
| 702 | break; |
| 703 | default: |
| 704 | /* PMIC doesn't have reset_pwr_off; do nothing. */ |
| 705 | break; |
| 706 | } |
| 707 | if (rc) { |
| 708 | pr_err("coincell chg. config failed, rc=%d\n", rc); |
| 709 | break; |
| 710 | } |
| 711 | } |
| 712 | |
| 713 | spin_unlock_irqrestore(&pm8xxx_misc_chips_lock, flags); |
| 714 | |
| 715 | return rc; |
| 716 | } |
| 717 | EXPORT_SYMBOL(pm8xxx_coincell_chg_config); |
| 718 | |
Anirudh Ghayal | a23c1ca | 2011-11-01 14:36:24 +0530 | [diff] [blame] | 719 | /** |
| 720 | * pm8xxx_watchdog_reset_control - enables/disables watchdog reset detection |
| 721 | * @enable: 0 = shutdown when PS_HOLD goes low, 1 = reset when PS_HOLD goes low |
| 722 | * |
| 723 | * This function enables or disables the PMIC watchdog reset detection feature. |
| 724 | * If watchdog reset detection is enabled, then the PMIC will reset itself |
| 725 | * when PS_HOLD goes low. If it is not enabled, then the PMIC will shutdown |
| 726 | * when PS_HOLD goes low. |
| 727 | * |
| 728 | * RETURNS: an appropriate -ERRNO error value on error, or zero for success. |
| 729 | */ |
| 730 | int pm8xxx_watchdog_reset_control(int enable) |
| 731 | { |
| 732 | struct pm8xxx_misc_chip *chip; |
| 733 | unsigned long flags; |
| 734 | int rc = 0; |
| 735 | |
| 736 | spin_lock_irqsave(&pm8xxx_misc_chips_lock, flags); |
| 737 | |
| 738 | /* Loop over all attached PMICs and call specific functions for them. */ |
| 739 | list_for_each_entry(chip, &pm8xxx_misc_chips, link) { |
| 740 | switch (chip->version) { |
| 741 | case PM8XXX_VERSION_8018: |
| 742 | case PM8XXX_VERSION_8058: |
| 743 | case PM8XXX_VERSION_8921: |
| 744 | rc = pm8xxx_misc_masked_write(chip, |
| 745 | REG_PM8XXX_PON_CTRL_1, PON_CTRL_1_WD_EN_MASK, |
| 746 | (enable ? PON_CTRL_1_WD_EN_RESET |
| 747 | : PON_CTRL_1_WD_EN_PWR_OFF)); |
| 748 | break; |
| 749 | default: |
| 750 | /* WD reset control not supported */ |
| 751 | break; |
| 752 | } |
| 753 | if (rc) { |
| 754 | pr_err("setting WD reset control failed, rc=%d\n", rc); |
| 755 | break; |
| 756 | } |
| 757 | } |
| 758 | |
| 759 | spin_unlock_irqrestore(&pm8xxx_misc_chips_lock, flags); |
| 760 | |
| 761 | return rc; |
| 762 | } |
| 763 | EXPORT_SYMBOL(pm8xxx_watchdog_reset_control); |
| 764 | |
Anirudh Ghayal | 51e947f | 2011-11-01 14:49:45 +0530 | [diff] [blame] | 765 | /** |
| 766 | * pm8xxx_stay_on - enables stay_on feature |
| 767 | * |
| 768 | * PMIC stay-on feature allows PMIC to ignore MSM PS_HOLD=low |
| 769 | * signal so that some special functions like debugging could be |
| 770 | * performed. |
| 771 | * |
| 772 | * This feature should not be used in any product release. |
| 773 | * |
| 774 | * RETURNS: an appropriate -ERRNO error value on error, or zero for success. |
| 775 | */ |
| 776 | int pm8xxx_stay_on(void) |
| 777 | { |
| 778 | struct pm8xxx_misc_chip *chip; |
| 779 | unsigned long flags; |
| 780 | int rc = 0; |
| 781 | |
| 782 | spin_lock_irqsave(&pm8xxx_misc_chips_lock, flags); |
| 783 | |
| 784 | /* Loop over all attached PMICs and call specific functions for them. */ |
| 785 | list_for_each_entry(chip, &pm8xxx_misc_chips, link) { |
| 786 | switch (chip->version) { |
| 787 | case PM8XXX_VERSION_8018: |
| 788 | case PM8XXX_VERSION_8058: |
| 789 | case PM8XXX_VERSION_8921: |
| 790 | rc = pm8xxx_writeb(chip->dev->parent, |
| 791 | REG_PM8XXX_GP_TEST_1, PM8XXX_STAY_ON_CFG); |
| 792 | break; |
| 793 | default: |
| 794 | /* stay on not supported */ |
| 795 | break; |
| 796 | } |
| 797 | if (rc) { |
| 798 | pr_err("stay_on failed failed, rc=%d\n", rc); |
| 799 | break; |
| 800 | } |
| 801 | } |
| 802 | |
| 803 | spin_unlock_irqrestore(&pm8xxx_misc_chips_lock, flags); |
| 804 | |
| 805 | return rc; |
| 806 | } |
| 807 | EXPORT_SYMBOL(pm8xxx_stay_on); |
| 808 | |
Anirudh Ghayal | a4262a3 | 2011-11-10 00:02:18 +0530 | [diff] [blame] | 809 | static int |
| 810 | __pm8xxx_hard_reset_config(struct pm8xxx_misc_chip *chip, |
| 811 | enum pm8xxx_pon_config config, u16 pon4_addr, u16 pon5_addr) |
| 812 | { |
| 813 | int rc = 0; |
| 814 | |
| 815 | switch (config) { |
| 816 | case PM8XXX_DISABLE_HARD_RESET: |
| 817 | rc = pm8xxx_misc_masked_write(chip, pon5_addr, |
| 818 | PON_CTRL_5_HARD_RESET_EN_MASK, |
| 819 | PON_CTRL_5_HARD_RESET_DIS); |
| 820 | break; |
| 821 | case PM8XXX_SHUTDOWN_ON_HARD_RESET: |
| 822 | rc = pm8xxx_misc_masked_write(chip, pon5_addr, |
| 823 | PON_CTRL_5_HARD_RESET_EN_MASK, |
| 824 | PON_CTRL_5_HARD_RESET_EN); |
| 825 | if (!rc) { |
| 826 | rc = pm8xxx_misc_masked_write(chip, pon4_addr, |
| 827 | PON_CTRL_4_RESET_EN_MASK, |
| 828 | PON_CTRL_4_SHUTDOWN_ON_RESET); |
| 829 | } |
| 830 | break; |
| 831 | case PM8XXX_RESTART_ON_HARD_RESET: |
| 832 | rc = pm8xxx_misc_masked_write(chip, pon5_addr, |
| 833 | PON_CTRL_5_HARD_RESET_EN_MASK, |
| 834 | PON_CTRL_5_HARD_RESET_EN); |
| 835 | if (!rc) { |
| 836 | rc = pm8xxx_misc_masked_write(chip, pon4_addr, |
| 837 | PON_CTRL_4_RESET_EN_MASK, |
| 838 | PON_CTRL_4_RESTART_ON_RESET); |
| 839 | } |
| 840 | break; |
| 841 | default: |
| 842 | rc = -EINVAL; |
| 843 | break; |
| 844 | } |
| 845 | return rc; |
| 846 | } |
| 847 | |
| 848 | /** |
| 849 | * pm8xxx_hard_reset_config - Allows different reset configurations |
| 850 | * |
| 851 | * config = PM8XXX_DISABLE_HARD_RESET to disable hard reset |
| 852 | * = PM8XXX_SHUTDOWN_ON_HARD_RESET to turn off the system on hard reset |
| 853 | * = PM8XXX_RESTART_ON_HARD_RESET to restart the system on hard reset |
| 854 | * |
| 855 | * RETURNS: an appropriate -ERRNO error value on error, or zero for success. |
| 856 | */ |
| 857 | int pm8xxx_hard_reset_config(enum pm8xxx_pon_config config) |
| 858 | { |
| 859 | struct pm8xxx_misc_chip *chip; |
| 860 | unsigned long flags; |
| 861 | int rc = 0; |
| 862 | |
| 863 | spin_lock_irqsave(&pm8xxx_misc_chips_lock, flags); |
| 864 | |
| 865 | /* Loop over all attached PMICs and call specific functions for them. */ |
| 866 | list_for_each_entry(chip, &pm8xxx_misc_chips, link) { |
| 867 | switch (chip->version) { |
| 868 | case PM8XXX_VERSION_8018: |
| 869 | __pm8xxx_hard_reset_config(chip, config, |
| 870 | REG_PM8018_PON_CNTL_4, REG_PM8018_PON_CNTL_5); |
| 871 | break; |
| 872 | case PM8XXX_VERSION_8058: |
| 873 | __pm8xxx_hard_reset_config(chip, config, |
| 874 | REG_PM8058_PON_CNTL_4, REG_PM8058_PON_CNTL_5); |
| 875 | break; |
| 876 | case PM8XXX_VERSION_8901: |
| 877 | __pm8xxx_hard_reset_config(chip, config, |
| 878 | REG_PM8901_PON_CNTL_4, REG_PM8901_PON_CNTL_5); |
| 879 | break; |
| 880 | case PM8XXX_VERSION_8921: |
| 881 | __pm8xxx_hard_reset_config(chip, config, |
| 882 | REG_PM8921_PON_CNTL_4, REG_PM8921_PON_CNTL_5); |
| 883 | break; |
| 884 | default: |
| 885 | /* hard reset config. no supported */ |
| 886 | break; |
| 887 | } |
| 888 | if (rc) { |
| 889 | pr_err("hard reset config. failed, rc=%d\n", rc); |
| 890 | break; |
| 891 | } |
| 892 | } |
| 893 | |
| 894 | spin_unlock_irqrestore(&pm8xxx_misc_chips_lock, flags); |
| 895 | |
| 896 | return rc; |
| 897 | } |
| 898 | EXPORT_SYMBOL(pm8xxx_hard_reset_config); |
| 899 | |
Anirudh Ghayal | 8b8f189 | 2011-11-11 10:48:41 +0530 | [diff] [blame] | 900 | /* Handle the OSC_HALT interrupt: 32 kHz XTAL oscillator has stopped. */ |
| 901 | static irqreturn_t pm8xxx_osc_halt_isr(int irq, void *data) |
| 902 | { |
| 903 | struct pm8xxx_misc_chip *chip = data; |
| 904 | u64 count = 0; |
| 905 | |
| 906 | if (chip) { |
| 907 | chip->osc_halt_count++; |
| 908 | count = chip->osc_halt_count; |
| 909 | } |
| 910 | |
| 911 | pr_crit("%s: OSC_HALT interrupt has triggered, 32 kHz XTAL oscillator" |
| 912 | " has halted (%llu)!\n", __func__, count); |
| 913 | |
| 914 | return IRQ_HANDLED; |
| 915 | } |
| 916 | |
Anirudh Ghayal | 5213eb8 | 2011-10-24 14:44:58 +0530 | [diff] [blame] | 917 | /** |
| 918 | * pm8xxx_uart_gpio_mux_ctrl - Mux configuration to select the UART |
| 919 | * |
| 920 | * @uart_path_sel: Input argument to select either UART1/2/3 |
| 921 | * |
| 922 | * RETURNS: an appropriate -ERRNO error value on error, or zero for success. |
| 923 | */ |
| 924 | int pm8xxx_uart_gpio_mux_ctrl(enum pm8xxx_uart_path_sel uart_path_sel) |
| 925 | { |
| 926 | struct pm8xxx_misc_chip *chip; |
| 927 | unsigned long flags; |
| 928 | int rc = 0; |
| 929 | |
| 930 | spin_lock_irqsave(&pm8xxx_misc_chips_lock, flags); |
| 931 | |
| 932 | /* Loop over all attached PMICs and call specific functions for them. */ |
| 933 | list_for_each_entry(chip, &pm8xxx_misc_chips, link) { |
| 934 | switch (chip->version) { |
| 935 | case PM8XXX_VERSION_8018: |
| 936 | case PM8XXX_VERSION_8058: |
| 937 | case PM8XXX_VERSION_8921: |
| 938 | rc = pm8xxx_misc_masked_write(chip, |
| 939 | REG_PM8XXX_GPIO_MUX_CTRL, UART_PATH_SEL_MASK, |
| 940 | uart_path_sel << UART_PATH_SEL_SHIFT); |
| 941 | break; |
| 942 | default: |
| 943 | /* Functionality not supported */ |
| 944 | break; |
| 945 | } |
| 946 | if (rc) { |
| 947 | pr_err("uart_gpio_mux_ctrl failed, rc=%d\n", rc); |
| 948 | break; |
| 949 | } |
| 950 | } |
| 951 | |
| 952 | spin_unlock_irqrestore(&pm8xxx_misc_chips_lock, flags); |
| 953 | |
| 954 | return rc; |
| 955 | } |
| 956 | EXPORT_SYMBOL(pm8xxx_uart_gpio_mux_ctrl); |
| 957 | |
Willie Ruan | 5db1f24 | 2012-01-30 22:08:04 -0800 | [diff] [blame] | 958 | /** |
| 959 | * pm8xxx_usb_id_pullup - Control a pullup for USB ID |
| 960 | * |
| 961 | * @enable: enable (1) or disable (0) the pullup |
| 962 | * |
| 963 | * RETURNS: an appropriate -ERRNO error value on error, or zero for success. |
| 964 | */ |
| 965 | int pm8xxx_usb_id_pullup(int enable) |
| 966 | { |
| 967 | struct pm8xxx_misc_chip *chip; |
| 968 | unsigned long flags; |
| 969 | int rc = -ENXIO; |
| 970 | |
| 971 | spin_lock_irqsave(&pm8xxx_misc_chips_lock, flags); |
| 972 | |
| 973 | /* Loop over all attached PMICs and call specific functions for them. */ |
| 974 | list_for_each_entry(chip, &pm8xxx_misc_chips, link) { |
| 975 | switch (chip->version) { |
| 976 | case PM8XXX_VERSION_8921: |
| 977 | case PM8XXX_VERSION_8922: |
| 978 | case PM8XXX_VERSION_8917: |
| 979 | case PM8XXX_VERSION_8038: |
| 980 | rc = pm8xxx_misc_masked_write(chip, |
| 981 | REG_PM8XXX_GPIO_MUX_CTRL, USB_ID_PU_EN_MASK, |
| 982 | enable << USB_ID_PU_EN_SHIFT); |
| 983 | |
| 984 | if (rc) |
| 985 | pr_err("Fail: reg=%x, rc=%d\n", |
| 986 | REG_PM8XXX_GPIO_MUX_CTRL, rc); |
| 987 | break; |
| 988 | default: |
| 989 | /* Functionality not supported */ |
| 990 | break; |
| 991 | } |
| 992 | } |
| 993 | |
| 994 | spin_unlock_irqrestore(&pm8xxx_misc_chips_lock, flags); |
| 995 | |
| 996 | return rc; |
| 997 | } |
| 998 | EXPORT_SYMBOL(pm8xxx_usb_id_pullup); |
| 999 | |
David Collins | 4724272 | 2012-01-20 11:34:58 -0800 | [diff] [blame] | 1000 | static int __pm8901_preload_dVdd(struct pm8xxx_misc_chip *chip) |
| 1001 | { |
| 1002 | int rc; |
| 1003 | |
David Collins | 135f3e0 | 2012-04-05 10:15:23 -0700 | [diff] [blame] | 1004 | /* dVdd preloading is not needed for PMIC PM8901 rev 2.3 and beyond. */ |
| 1005 | if (pm8xxx_get_revision(chip->dev->parent) >= PM8XXX_REVISION_8901_2p3) |
| 1006 | return 0; |
| 1007 | |
David Collins | 4724272 | 2012-01-20 11:34:58 -0800 | [diff] [blame] | 1008 | rc = pm8xxx_writeb(chip->dev->parent, 0x0BD, 0x0F); |
| 1009 | if (rc) |
| 1010 | pr_err("pm8xxx_writeb failed for 0x0BD, rc=%d\n", rc); |
| 1011 | |
| 1012 | rc = pm8xxx_writeb(chip->dev->parent, 0x001, 0xB4); |
| 1013 | if (rc) |
| 1014 | pr_err("pm8xxx_writeb failed for 0x001, rc=%d\n", rc); |
| 1015 | |
| 1016 | pr_info("dVdd preloaded\n"); |
| 1017 | |
| 1018 | return rc; |
| 1019 | } |
| 1020 | |
| 1021 | /** |
| 1022 | * pm8xxx_preload_dVdd - preload the dVdd regulator during off state. |
| 1023 | * |
| 1024 | * This can help to reduce fluctuations in the dVdd voltage during startup |
| 1025 | * at the cost of additional off state current draw. |
| 1026 | * |
| 1027 | * This API should only be called if dVdd startup issues are suspected. |
| 1028 | * |
| 1029 | * RETURNS: an appropriate -ERRNO error value on error, or zero for success. |
| 1030 | */ |
| 1031 | int pm8xxx_preload_dVdd(void) |
| 1032 | { |
| 1033 | struct pm8xxx_misc_chip *chip; |
| 1034 | unsigned long flags; |
| 1035 | int rc = 0; |
| 1036 | |
| 1037 | spin_lock_irqsave(&pm8xxx_misc_chips_lock, flags); |
| 1038 | |
| 1039 | /* Loop over all attached PMICs and call specific functions for them. */ |
| 1040 | list_for_each_entry(chip, &pm8xxx_misc_chips, link) { |
| 1041 | switch (chip->version) { |
| 1042 | case PM8XXX_VERSION_8901: |
| 1043 | rc = __pm8901_preload_dVdd(chip); |
| 1044 | break; |
| 1045 | default: |
| 1046 | /* PMIC doesn't have preload_dVdd; do nothing. */ |
| 1047 | break; |
| 1048 | } |
| 1049 | if (rc) { |
| 1050 | pr_err("preload_dVdd failed, rc=%d\n", rc); |
| 1051 | break; |
| 1052 | } |
| 1053 | } |
| 1054 | |
| 1055 | spin_unlock_irqrestore(&pm8xxx_misc_chips_lock, flags); |
| 1056 | |
| 1057 | return rc; |
| 1058 | } |
| 1059 | EXPORT_SYMBOL_GPL(pm8xxx_preload_dVdd); |
| 1060 | |
Amy Maloche | 4c994c9 | 2012-02-15 09:56:15 -0800 | [diff] [blame] | 1061 | int pm8xxx_aux_clk_control(enum pm8xxx_aux_clk_id clk_id, |
| 1062 | enum pm8xxx_aux_clk_div divider, bool enable) |
| 1063 | { |
| 1064 | struct pm8xxx_misc_chip *chip; |
| 1065 | unsigned long flags; |
| 1066 | u8 clk_mask = 0, value = 0; |
| 1067 | |
| 1068 | if (clk_id == CLK_MP3_1) { |
| 1069 | clk_mask = MP3_1_MASK; |
| 1070 | value = divider << MP3_1_SHIFT; |
| 1071 | } else if (clk_id == CLK_MP3_2) { |
| 1072 | clk_mask = MP3_2_MASK; |
| 1073 | value = divider << MP3_2_SHIFT; |
| 1074 | } else { |
| 1075 | pr_err("Invalid clock id of %d\n", clk_id); |
| 1076 | return -EINVAL; |
| 1077 | } |
| 1078 | if (!enable) |
| 1079 | value = 0; |
| 1080 | |
| 1081 | spin_lock_irqsave(&pm8xxx_misc_chips_lock, flags); |
| 1082 | |
| 1083 | /* Loop over all attached PMICs and call specific functions for them. */ |
| 1084 | list_for_each_entry(chip, &pm8xxx_misc_chips, link) { |
| 1085 | switch (chip->version) { |
| 1086 | case PM8XXX_VERSION_8038: |
| 1087 | case PM8XXX_VERSION_8921: |
| 1088 | pm8xxx_misc_masked_write(chip, |
| 1089 | REG_PM8XXX_XO_CNTRL_2, clk_mask, value); |
| 1090 | break; |
| 1091 | default: |
| 1092 | /* Functionality not supported */ |
| 1093 | break; |
| 1094 | } |
| 1095 | } |
| 1096 | |
| 1097 | spin_unlock_irqrestore(&pm8xxx_misc_chips_lock, flags); |
| 1098 | |
| 1099 | return 0; |
| 1100 | } |
| 1101 | EXPORT_SYMBOL_GPL(pm8xxx_aux_clk_control); |
| 1102 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1103 | static int __devinit pm8xxx_misc_probe(struct platform_device *pdev) |
| 1104 | { |
| 1105 | const struct pm8xxx_misc_platform_data *pdata = pdev->dev.platform_data; |
| 1106 | struct pm8xxx_misc_chip *chip; |
| 1107 | struct pm8xxx_misc_chip *sibling; |
| 1108 | struct list_head *prev; |
| 1109 | unsigned long flags; |
Anirudh Ghayal | 8b8f189 | 2011-11-11 10:48:41 +0530 | [diff] [blame] | 1110 | int rc = 0, irq; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1111 | |
| 1112 | if (!pdata) { |
| 1113 | pr_err("missing platform data\n"); |
| 1114 | return -EINVAL; |
| 1115 | } |
| 1116 | |
| 1117 | chip = kzalloc(sizeof(struct pm8xxx_misc_chip), GFP_KERNEL); |
| 1118 | if (!chip) { |
| 1119 | pr_err("Cannot allocate %d bytes\n", |
| 1120 | sizeof(struct pm8xxx_misc_chip)); |
| 1121 | return -ENOMEM; |
| 1122 | } |
| 1123 | |
| 1124 | chip->dev = &pdev->dev; |
| 1125 | chip->version = pm8xxx_get_version(chip->dev->parent); |
| 1126 | memcpy(&(chip->pdata), pdata, sizeof(struct pm8xxx_misc_platform_data)); |
| 1127 | |
Anirudh Ghayal | 8b8f189 | 2011-11-11 10:48:41 +0530 | [diff] [blame] | 1128 | irq = platform_get_irq_byname(pdev, "pm8xxx_osc_halt_irq"); |
| 1129 | if (irq > 0) { |
| 1130 | rc = request_any_context_irq(irq, pm8xxx_osc_halt_isr, |
| 1131 | IRQF_TRIGGER_RISING | IRQF_DISABLED, |
| 1132 | "pm8xxx_osc_halt_irq", chip); |
| 1133 | if (rc < 0) { |
| 1134 | pr_err("%s: request_any_context_irq(%d) FAIL: %d\n", |
| 1135 | __func__, irq, rc); |
| 1136 | goto fail_irq; |
| 1137 | } |
| 1138 | } |
| 1139 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1140 | /* Insert PMICs in priority order (lowest value first). */ |
| 1141 | spin_lock_irqsave(&pm8xxx_misc_chips_lock, flags); |
| 1142 | prev = &pm8xxx_misc_chips; |
| 1143 | list_for_each_entry(sibling, &pm8xxx_misc_chips, link) { |
| 1144 | if (chip->pdata.priority < sibling->pdata.priority) |
| 1145 | break; |
| 1146 | else |
| 1147 | prev = &sibling->link; |
| 1148 | } |
| 1149 | list_add(&chip->link, prev); |
| 1150 | spin_unlock_irqrestore(&pm8xxx_misc_chips_lock, flags); |
| 1151 | |
| 1152 | platform_set_drvdata(pdev, chip); |
| 1153 | |
| 1154 | return rc; |
Anirudh Ghayal | 8b8f189 | 2011-11-11 10:48:41 +0530 | [diff] [blame] | 1155 | |
| 1156 | fail_irq: |
| 1157 | platform_set_drvdata(pdev, NULL); |
| 1158 | kfree(chip); |
| 1159 | return rc; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1160 | } |
| 1161 | |
| 1162 | static int __devexit pm8xxx_misc_remove(struct platform_device *pdev) |
| 1163 | { |
| 1164 | struct pm8xxx_misc_chip *chip = platform_get_drvdata(pdev); |
| 1165 | unsigned long flags; |
Anirudh Ghayal | 8b8f189 | 2011-11-11 10:48:41 +0530 | [diff] [blame] | 1166 | int irq = platform_get_irq_byname(pdev, "pm8xxx_osc_halt_irq"); |
| 1167 | if (irq > 0) |
| 1168 | free_irq(irq, chip); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1169 | |
| 1170 | spin_lock_irqsave(&pm8xxx_misc_chips_lock, flags); |
| 1171 | list_del(&chip->link); |
| 1172 | spin_unlock_irqrestore(&pm8xxx_misc_chips_lock, flags); |
| 1173 | |
| 1174 | platform_set_drvdata(pdev, NULL); |
| 1175 | kfree(chip); |
| 1176 | |
| 1177 | return 0; |
| 1178 | } |
| 1179 | |
| 1180 | static struct platform_driver pm8xxx_misc_driver = { |
| 1181 | .probe = pm8xxx_misc_probe, |
| 1182 | .remove = __devexit_p(pm8xxx_misc_remove), |
| 1183 | .driver = { |
| 1184 | .name = PM8XXX_MISC_DEV_NAME, |
| 1185 | .owner = THIS_MODULE, |
| 1186 | }, |
| 1187 | }; |
| 1188 | |
| 1189 | static int __init pm8xxx_misc_init(void) |
| 1190 | { |
| 1191 | return platform_driver_register(&pm8xxx_misc_driver); |
| 1192 | } |
| 1193 | postcore_initcall(pm8xxx_misc_init); |
| 1194 | |
| 1195 | static void __exit pm8xxx_misc_exit(void) |
| 1196 | { |
| 1197 | platform_driver_unregister(&pm8xxx_misc_driver); |
| 1198 | } |
| 1199 | module_exit(pm8xxx_misc_exit); |
| 1200 | |
| 1201 | MODULE_LICENSE("GPL v2"); |
| 1202 | MODULE_DESCRIPTION("PMIC 8XXX misc driver"); |
| 1203 | MODULE_VERSION("1.0"); |
| 1204 | MODULE_ALIAS("platform:" PM8XXX_MISC_DEV_NAME); |