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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/arch/arm/mach-pxa/irq.c
3 *
eric miaoe3630db2008-03-04 11:42:26 +08004 * Generic PXA IRQ handling
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 *
6 * Author: Nicolas Pitre
7 * Created: Jun 15, 2001
8 * Copyright: MontaVista Software Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/interrupt.h>
eric miaoc01655042008-01-28 23:00:02 +000018#include <linux/sysdev.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070019
Russell Kinga09e64f2008-08-05 16:14:15 +010020#include <mach/hardware.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070021#include <asm/irq.h>
22#include <asm/mach/irq.h>
Eric Miaoa58fbcd2009-01-06 17:37:37 +080023#include <mach/gpio.h>
Eric Miao5bf3df32009-01-20 11:04:16 +080024#include <mach/regs-intc.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070025
26#include "generic.h"
27
Haojian Zhuangc482ae42009-11-02 14:02:21 -050028#define MAX_INTERNAL_IRQS 128
29
eric miaof6fb7af2008-03-04 13:53:05 +080030#define IRQ_BIT(n) (((n) - PXA_IRQ(0)) & 0x1f)
31#define _ICMR(n) (*((((n) - PXA_IRQ(0)) & ~0x1f) ? &ICMR2 : &ICMR))
32#define _ICLR(n) (*((((n) - PXA_IRQ(0)) & ~0x1f) ? &ICLR2 : &ICLR))
Linus Torvalds1da177e2005-04-16 15:20:36 -070033
34/*
35 * This is for peripheral IRQs internal to the PXA chip.
36 */
37
eric miaof6fb7af2008-03-04 13:53:05 +080038static int pxa_internal_irq_nr;
39
Haojian Zhuangbb71bdd2010-11-17 19:03:36 +080040static inline int cpu_has_ipr(void)
41{
42 return !cpu_is_pxa25x();
43}
44
eric miaof6fb7af2008-03-04 13:53:05 +080045static void pxa_mask_irq(unsigned int irq)
Linus Torvalds1da177e2005-04-16 15:20:36 -070046{
eric miaof6fb7af2008-03-04 13:53:05 +080047 _ICMR(irq) &= ~(1 << IRQ_BIT(irq));
Linus Torvalds1da177e2005-04-16 15:20:36 -070048}
49
eric miaof6fb7af2008-03-04 13:53:05 +080050static void pxa_unmask_irq(unsigned int irq)
Linus Torvalds1da177e2005-04-16 15:20:36 -070051{
eric miaof6fb7af2008-03-04 13:53:05 +080052 _ICMR(irq) |= 1 << IRQ_BIT(irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -070053}
54
eric miaof6fb7af2008-03-04 13:53:05 +080055static struct irq_chip pxa_internal_irq_chip = {
David Brownell38c677c2006-08-01 22:26:25 +010056 .name = "SC",
eric miaof6fb7af2008-03-04 13:53:05 +080057 .ack = pxa_mask_irq,
58 .mask = pxa_mask_irq,
59 .unmask = pxa_unmask_irq,
Linus Torvalds1da177e2005-04-16 15:20:36 -070060};
61
Eric Miaoa58fbcd2009-01-06 17:37:37 +080062/*
63 * GPIO IRQs for GPIO 0 and 1
64 */
65static int pxa_set_low_gpio_type(unsigned int irq, unsigned int type)
66{
67 int gpio = irq - IRQ_GPIO0;
68
69 if (__gpio_is_occupied(gpio)) {
70 pr_err("%s failed: GPIO is configured\n", __func__);
71 return -EINVAL;
72 }
73
74 if (type & IRQ_TYPE_EDGE_RISING)
75 GRER0 |= GPIO_bit(gpio);
76 else
77 GRER0 &= ~GPIO_bit(gpio);
78
79 if (type & IRQ_TYPE_EDGE_FALLING)
80 GFER0 |= GPIO_bit(gpio);
81 else
82 GFER0 &= ~GPIO_bit(gpio);
83
84 return 0;
85}
86
87static void pxa_ack_low_gpio(unsigned int irq)
88{
89 GEDR0 = (1 << (irq - IRQ_GPIO0));
90}
91
92static void pxa_mask_low_gpio(unsigned int irq)
93{
94 ICMR &= ~(1 << (irq - PXA_IRQ(0)));
95}
96
97static void pxa_unmask_low_gpio(unsigned int irq)
98{
99 ICMR |= 1 << (irq - PXA_IRQ(0));
100}
101
102static struct irq_chip pxa_low_gpio_chip = {
103 .name = "GPIO-l",
104 .ack = pxa_ack_low_gpio,
105 .mask = pxa_mask_low_gpio,
106 .unmask = pxa_unmask_low_gpio,
107 .set_type = pxa_set_low_gpio_type,
108};
109
110static void __init pxa_init_low_gpio_irq(set_wake_t fn)
111{
112 int irq;
113
114 /* clear edge detection on GPIO 0 and 1 */
115 GFER0 &= ~0x3;
116 GRER0 &= ~0x3;
117 GEDR0 = 0x3;
118
119 for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
120 set_irq_chip(irq, &pxa_low_gpio_chip);
121 set_irq_handler(irq, handle_edge_irq);
122 set_irq_flags(irq, IRQF_VALID);
123 }
124
125 pxa_low_gpio_chip.set_wake = fn;
126}
127
eric miaob9e25ac2008-03-04 14:19:58 +0800128void __init pxa_init_irq(int irq_nr, set_wake_t fn)
Eric Miao53665a52007-06-06 06:36:04 +0100129{
Haojian Zhuangd2c37062009-08-19 19:49:31 +0800130 int irq, i;
Eric Miao53665a52007-06-06 06:36:04 +0100131
Haojian Zhuangc482ae42009-11-02 14:02:21 -0500132 BUG_ON(irq_nr > MAX_INTERNAL_IRQS);
133
eric miaof6fb7af2008-03-04 13:53:05 +0800134 pxa_internal_irq_nr = irq_nr;
Eric Miao53665a52007-06-06 06:36:04 +0100135
Marc Zyngier57a7a622008-09-01 13:03:32 +0100136 for (irq = PXA_IRQ(0); irq < PXA_IRQ(irq_nr); irq += 32) {
eric miaof6fb7af2008-03-04 13:53:05 +0800137 _ICMR(irq) = 0; /* disable all IRQs */
138 _ICLR(irq) = 0; /* all IRQs are IRQ, not FIQ */
139 }
Eric Miao53665a52007-06-06 06:36:04 +0100140
Haojian Zhuangd2c37062009-08-19 19:49:31 +0800141 /* initialize interrupt priority */
Haojian Zhuangbb71bdd2010-11-17 19:03:36 +0800142 if (cpu_has_ipr()) {
Haojian Zhuangd2c37062009-08-19 19:49:31 +0800143 for (i = 0; i < irq_nr; i++)
144 IPR(i) = i | (1 << 31);
145 }
146
Eric Miao53665a52007-06-06 06:36:04 +0100147 /* only unmasked interrupts kick us out of idle */
148 ICCR = 1;
149
eric miaof6fb7af2008-03-04 13:53:05 +0800150 for (irq = PXA_IRQ(0); irq < PXA_IRQ(irq_nr); irq++) {
151 set_irq_chip(irq, &pxa_internal_irq_chip);
Eric Miao53665a52007-06-06 06:36:04 +0100152 set_irq_handler(irq, handle_level_irq);
153 set_irq_flags(irq, IRQF_VALID);
154 }
Eric Miao53665a52007-06-06 06:36:04 +0100155
eric miaob9e25ac2008-03-04 14:19:58 +0800156 pxa_internal_irq_chip.set_wake = fn;
Eric Miaoa58fbcd2009-01-06 17:37:37 +0800157 pxa_init_low_gpio_irq(fn);
eric miaoc95530c2007-08-29 10:22:17 +0100158}
eric miaoc01655042008-01-28 23:00:02 +0000159
160#ifdef CONFIG_PM
Haojian Zhuangc482ae42009-11-02 14:02:21 -0500161static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32];
162static unsigned long saved_ipr[MAX_INTERNAL_IRQS];
eric miaoc01655042008-01-28 23:00:02 +0000163
164static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state)
165{
eric miaof6fb7af2008-03-04 13:53:05 +0800166 int i, irq = PXA_IRQ(0);
167
168 for (i = 0; irq < PXA_IRQ(pxa_internal_irq_nr); i++, irq += 32) {
169 saved_icmr[i] = _ICMR(irq);
170 _ICMR(irq) = 0;
eric miaoc01655042008-01-28 23:00:02 +0000171 }
Eric Miaoc70f5a62010-01-11 20:39:37 +0800172
Haojian Zhuangbb71bdd2010-11-17 19:03:36 +0800173 if (cpu_has_ipr()) {
Eric Miaoc70f5a62010-01-11 20:39:37 +0800174 for (i = 0; i < pxa_internal_irq_nr; i++)
175 saved_ipr[i] = IPR(i);
176 }
eric miaoc01655042008-01-28 23:00:02 +0000177
178 return 0;
179}
180
181static int pxa_irq_resume(struct sys_device *dev)
182{
eric miaof6fb7af2008-03-04 13:53:05 +0800183 int i, irq = PXA_IRQ(0);
184
Haojian Zhuangbb71bdd2010-11-17 19:03:36 +0800185 if (cpu_has_ipr()) {
Eric Miaoc70f5a62010-01-11 20:39:37 +0800186 for (i = 0; i < pxa_internal_irq_nr; i++)
187 IPR(i) = saved_ipr[i];
188 }
189
eric miaof6fb7af2008-03-04 13:53:05 +0800190 for (i = 0; irq < PXA_IRQ(pxa_internal_irq_nr); i++, irq += 32) {
191 _ICMR(irq) = saved_icmr[i];
192 _ICLR(irq) = 0;
eric miaoc01655042008-01-28 23:00:02 +0000193 }
194
eric miaof6fb7af2008-03-04 13:53:05 +0800195 ICCR = 1;
eric miaoc01655042008-01-28 23:00:02 +0000196 return 0;
197}
198#else
199#define pxa_irq_suspend NULL
200#define pxa_irq_resume NULL
201#endif
202
203struct sysdev_class pxa_irq_sysclass = {
204 .name = "irq",
205 .suspend = pxa_irq_suspend,
206 .resume = pxa_irq_resume,
207};
208
209static int __init pxa_irq_init(void)
210{
211 return sysdev_class_register(&pxa_irq_sysclass);
212}
213
214core_initcall(pxa_irq_init);