Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
Jeff Garzik | af36d7f | 2005-08-28 20:18:39 -0400 | [diff] [blame] | 2 | * ata_piix.c - Intel PATA/SATA controllers |
| 3 | * |
| 4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> |
| 5 | * Please ALWAYS copy linux-ide@vger.kernel.org |
| 6 | * on emails. |
| 7 | * |
| 8 | * |
| 9 | * Copyright 2003-2005 Red Hat Inc |
| 10 | * Copyright 2003-2005 Jeff Garzik |
| 11 | * |
| 12 | * |
| 13 | * Copyright header from piix.c: |
| 14 | * |
| 15 | * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer |
| 16 | * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> |
| 17 | * Copyright (C) 2003 Red Hat Inc <alan@redhat.com> |
| 18 | * |
| 19 | * |
| 20 | * This program is free software; you can redistribute it and/or modify |
| 21 | * it under the terms of the GNU General Public License as published by |
| 22 | * the Free Software Foundation; either version 2, or (at your option) |
| 23 | * any later version. |
| 24 | * |
| 25 | * This program is distributed in the hope that it will be useful, |
| 26 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 27 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 28 | * GNU General Public License for more details. |
| 29 | * |
| 30 | * You should have received a copy of the GNU General Public License |
| 31 | * along with this program; see the file COPYING. If not, write to |
| 32 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. |
| 33 | * |
| 34 | * |
| 35 | * libata documentation is available via 'make {ps|pdf}docs', |
| 36 | * as Documentation/DocBook/libata.* |
| 37 | * |
| 38 | * Hardware documentation available at http://developer.intel.com/ |
| 39 | * |
Alan Cox | d96212e | 2005-12-08 19:19:50 +0000 | [diff] [blame] | 40 | * Documentation |
| 41 | * Publically available from Intel web site. Errata documentation |
| 42 | * is also publically available. As an aide to anyone hacking on this |
Alan | 2c5ff67 | 2006-12-04 16:33:20 +0000 | [diff] [blame] | 43 | * driver the list of errata that are relevant is below, going back to |
Alan Cox | d96212e | 2005-12-08 19:19:50 +0000 | [diff] [blame] | 44 | * PIIX4. Older device documentation is now a bit tricky to find. |
| 45 | * |
| 46 | * The chipsets all follow very much the same design. The orginal Triton |
| 47 | * series chipsets do _not_ support independant device timings, but this |
| 48 | * is fixed in Triton II. With the odd mobile exception the chips then |
| 49 | * change little except in gaining more modes until SATA arrives. This |
| 50 | * driver supports only the chips with independant timing (that is those |
| 51 | * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix |
| 52 | * for the early chip drivers. |
| 53 | * |
| 54 | * Errata of note: |
| 55 | * |
| 56 | * Unfixable |
| 57 | * PIIX4 errata #9 - Only on ultra obscure hw |
| 58 | * ICH3 errata #13 - Not observed to affect real hw |
| 59 | * by Intel |
| 60 | * |
| 61 | * Things we must deal with |
| 62 | * PIIX4 errata #10 - BM IDE hang with non UDMA |
| 63 | * (must stop/start dma to recover) |
| 64 | * 440MX errata #15 - As PIIX4 errata #10 |
| 65 | * PIIX4 errata #15 - Must not read control registers |
| 66 | * during a PIO transfer |
| 67 | * 440MX errata #13 - As PIIX4 errata #15 |
| 68 | * ICH2 errata #21 - DMA mode 0 doesn't work right |
| 69 | * ICH0/1 errata #55 - As ICH2 errata #21 |
| 70 | * ICH2 spec c #9 - Extra operations needed to handle |
| 71 | * drive hotswap [NOT YET SUPPORTED] |
| 72 | * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary |
| 73 | * and must be dword aligned |
| 74 | * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3 |
| 75 | * |
| 76 | * Should have been BIOS fixed: |
| 77 | * 450NX: errata #19 - DMA hangs on old 450NX |
| 78 | * 450NX: errata #20 - DMA hangs on old 450NX |
| 79 | * 450NX: errata #25 - Corruption with DMA on old 450NX |
| 80 | * ICH3 errata #15 - IDE deadlock under high load |
| 81 | * (BIOS must set dev 31 fn 0 bit 23) |
| 82 | * ICH3 errata #18 - Don't use native mode |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 83 | */ |
| 84 | |
| 85 | #include <linux/kernel.h> |
| 86 | #include <linux/module.h> |
| 87 | #include <linux/pci.h> |
| 88 | #include <linux/init.h> |
| 89 | #include <linux/blkdev.h> |
| 90 | #include <linux/delay.h> |
Jeff Garzik | 6248e64 | 2005-10-30 06:42:18 -0500 | [diff] [blame] | 91 | #include <linux/device.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 92 | #include <scsi/scsi_host.h> |
| 93 | #include <linux/libata.h> |
| 94 | |
| 95 | #define DRV_NAME "ata_piix" |
Alan Cox | eb4a2c7 | 2007-04-11 00:04:20 +0100 | [diff] [blame] | 96 | #define DRV_VERSION "2.11" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 97 | |
| 98 | enum { |
| 99 | PIIX_IOCFG = 0x54, /* IDE I/O configuration register */ |
| 100 | ICH5_PMR = 0x90, /* port mapping register */ |
| 101 | ICH5_PCS = 0x92, /* port control and status */ |
Greg Felix | 7b6dbd6 | 2005-07-28 15:54:15 -0400 | [diff] [blame] | 102 | PIIX_SCC = 0x0A, /* sub-class code register */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 103 | |
Tejun Heo | d435804 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 104 | PIIX_FLAG_SCR = (1 << 26), /* SCR available */ |
Tejun Heo | ff0fc14 | 2005-12-18 17:17:07 +0900 | [diff] [blame] | 105 | PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */ |
| 106 | PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 107 | |
Tejun Heo | 800b399 | 2006-12-03 21:34:13 +0900 | [diff] [blame] | 108 | PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS, |
| 109 | PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR, |
Tejun Heo | b3362f8 | 2006-11-10 18:08:10 +0900 | [diff] [blame] | 110 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 111 | /* combined mode. if set, PATA is channel 0. |
| 112 | * if clear, PATA is channel 1. |
| 113 | */ |
Hannes Reinecke | 6a690df | 2005-06-28 17:30:38 -0700 | [diff] [blame] | 114 | PIIX_PORT_ENABLED = (1 << 0), |
| 115 | PIIX_PORT_PRESENT = (1 << 4), |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 116 | |
| 117 | PIIX_80C_PRI = (1 << 5) | (1 << 4), |
| 118 | PIIX_80C_SEC = (1 << 7) | (1 << 6), |
| 119 | |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 120 | /* controller IDs */ |
Alan | d2cdfc0 | 2007-01-10 17:13:38 +0000 | [diff] [blame] | 121 | piix_pata_33 = 0, /* PIIX4 at 33Mhz */ |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 122 | ich_pata_33 = 1, /* ICH up to UDMA 33 only */ |
| 123 | ich_pata_66 = 2, /* ICH up to 66 Mhz */ |
| 124 | ich_pata_100 = 3, /* ICH up to UDMA 100 */ |
| 125 | ich_pata_133 = 4, /* ICH up to UDMA 133 */ |
| 126 | ich5_sata = 5, |
Tejun Heo | 5e56a37 | 2006-11-10 18:08:10 +0900 | [diff] [blame] | 127 | ich6_sata = 6, |
| 128 | ich6_sata_ahci = 7, |
| 129 | ich6m_sata_ahci = 8, |
| 130 | ich8_sata_ahci = 9, |
Alan | d2cdfc0 | 2007-01-10 17:13:38 +0000 | [diff] [blame] | 131 | piix_pata_mwdma = 10, /* PIIX3 MWDMA only */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 132 | |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 133 | /* constants for mapping table */ |
| 134 | P0 = 0, /* port 0 */ |
| 135 | P1 = 1, /* port 1 */ |
| 136 | P2 = 2, /* port 2 */ |
| 137 | P3 = 3, /* port 3 */ |
| 138 | IDE = -1, /* IDE */ |
| 139 | NA = -2, /* not avaliable */ |
| 140 | RV = -3, /* reserved */ |
| 141 | |
Greg Felix | 7b6dbd6 | 2005-07-28 15:54:15 -0400 | [diff] [blame] | 142 | PIIX_AHCI_DEVICE = 6, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 143 | }; |
| 144 | |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 145 | struct piix_map_db { |
| 146 | const u32 mask; |
Jeff Garzik | 73291a1 | 2006-07-11 13:11:17 -0400 | [diff] [blame] | 147 | const u16 port_enable; |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 148 | const int map[][4]; |
| 149 | }; |
| 150 | |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 151 | struct piix_host_priv { |
| 152 | const int *map; |
| 153 | }; |
| 154 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 155 | static int piix_init_one (struct pci_dev *pdev, |
| 156 | const struct pci_device_id *ent); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 157 | static void piix_pata_error_handler(struct ata_port *ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 158 | static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev); |
| 159 | static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 160 | static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev); |
Alan Cox | eb4a2c7 | 2007-04-11 00:04:20 +0100 | [diff] [blame] | 161 | static int ich_pata_cable_detect(struct ata_port *ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 162 | |
| 163 | static unsigned int in_module_init = 1; |
| 164 | |
Jeff Garzik | 3b7d697 | 2005-11-10 11:04:11 -0500 | [diff] [blame] | 165 | static const struct pci_device_id piix_pci_tbl[] = { |
Alan | d2cdfc0 | 2007-01-10 17:13:38 +0000 | [diff] [blame] | 166 | /* Intel PIIX3 for the 430HX etc */ |
| 167 | { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma }, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 168 | /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */ |
| 169 | /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */ |
| 170 | { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 171 | /* Intel PIIX4 */ |
| 172 | { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, |
| 173 | /* Intel PIIX4 */ |
| 174 | { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, |
| 175 | /* Intel PIIX */ |
| 176 | { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, |
| 177 | /* Intel ICH (i810, i815, i840) UDMA 66*/ |
| 178 | { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 }, |
| 179 | /* Intel ICH0 : UDMA 33*/ |
| 180 | { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 }, |
| 181 | /* Intel ICH2M */ |
| 182 | { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
| 183 | /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */ |
| 184 | { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
| 185 | /* Intel ICH3M */ |
| 186 | { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
| 187 | /* Intel ICH3 (E7500/1) UDMA 100 */ |
| 188 | { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
| 189 | /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */ |
| 190 | { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
| 191 | { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
| 192 | /* Intel ICH5 */ |
| 193 | { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 }, |
| 194 | /* C-ICH (i810E2) */ |
| 195 | { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 196 | /* ESB (855GME/875P + 6300ESB) UDMA 100 */ |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 197 | { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
| 198 | /* ICH6 (and 6) (i915) UDMA 100 */ |
| 199 | { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
| 200 | /* ICH7/7-R (i945, i975) UDMA 100*/ |
| 201 | { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 }, |
| 202 | { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
Christian Lamparter | c1e6f28 | 2007-07-03 10:19:20 -0400 | [diff] [blame^] | 203 | /* ICH8 Mobile PATA Controller */ |
| 204 | { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 205 | |
| 206 | /* NOTE: The following PCI ids must be kept in sync with the |
| 207 | * list in drivers/pci/quirks.c. |
| 208 | */ |
| 209 | |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 210 | /* 82801EB (ICH5) */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 211 | { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 212 | /* 82801EB (ICH5) */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 213 | { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 214 | /* 6300ESB (ICH5 variant with broken PCS present bits) */ |
Tejun Heo | 5e56a37 | 2006-11-10 18:08:10 +0900 | [diff] [blame] | 215 | { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 216 | /* 6300ESB pretending RAID */ |
Tejun Heo | 5e56a37 | 2006-11-10 18:08:10 +0900 | [diff] [blame] | 217 | { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 218 | /* 82801FB/FW (ICH6/ICH6W) */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 219 | { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 220 | /* 82801FR/FRW (ICH6R/ICH6RW) */ |
Jeff Garzik | 1c24a41 | 2005-11-14 18:20:23 -0500 | [diff] [blame] | 221 | { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 222 | /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */ |
| 223 | { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci }, |
| 224 | /* 82801GB/GR/GH (ICH7, identical to ICH6) */ |
Jeff Garzik | 1c24a41 | 2005-11-14 18:20:23 -0500 | [diff] [blame] | 225 | { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 226 | /* 2801GBM/GHM (ICH7M, identical to ICH6M) */ |
Tejun Heo | c6446a4 | 2006-10-09 13:23:58 +0900 | [diff] [blame] | 227 | { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci }, |
Jason Gaston | f98b657 | 2006-12-07 08:57:32 -0800 | [diff] [blame] | 228 | /* Enterprise Southbridge 2 (631xESB/632xESB) */ |
Jeff Garzik | 1c24a41 | 2005-11-14 18:20:23 -0500 | [diff] [blame] | 229 | { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, |
Jason Gaston | f98b657 | 2006-12-07 08:57:32 -0800 | [diff] [blame] | 230 | /* SATA Controller 1 IDE (ICH8) */ |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 231 | { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, |
Jason Gaston | f98b657 | 2006-12-07 08:57:32 -0800 | [diff] [blame] | 232 | /* SATA Controller 2 IDE (ICH8) */ |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 233 | { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, |
Jason Gaston | f98b657 | 2006-12-07 08:57:32 -0800 | [diff] [blame] | 234 | /* Mobile SATA Controller IDE (ICH8M) */ |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 235 | { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, |
Jason Gaston | f98b657 | 2006-12-07 08:57:32 -0800 | [diff] [blame] | 236 | /* SATA Controller IDE (ICH9) */ |
| 237 | { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, |
| 238 | /* SATA Controller IDE (ICH9) */ |
| 239 | { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, |
| 240 | /* SATA Controller IDE (ICH9) */ |
| 241 | { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, |
| 242 | /* SATA Controller IDE (ICH9M) */ |
| 243 | { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, |
| 244 | /* SATA Controller IDE (ICH9M) */ |
| 245 | { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, |
| 246 | /* SATA Controller IDE (ICH9M) */ |
| 247 | { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 248 | |
| 249 | { } /* terminate list */ |
| 250 | }; |
| 251 | |
| 252 | static struct pci_driver piix_pci_driver = { |
| 253 | .name = DRV_NAME, |
| 254 | .id_table = piix_pci_tbl, |
| 255 | .probe = piix_init_one, |
| 256 | .remove = ata_pci_remove_one, |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 257 | #ifdef CONFIG_PM |
Jens Axboe | 9b84754 | 2006-01-06 09:28:07 +0100 | [diff] [blame] | 258 | .suspend = ata_pci_device_suspend, |
| 259 | .resume = ata_pci_device_resume, |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 260 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 261 | }; |
| 262 | |
Jeff Garzik | 193515d | 2005-11-07 00:59:37 -0500 | [diff] [blame] | 263 | static struct scsi_host_template piix_sht = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 264 | .module = THIS_MODULE, |
| 265 | .name = DRV_NAME, |
| 266 | .ioctl = ata_scsi_ioctl, |
| 267 | .queuecommand = ata_scsi_queuecmd, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 268 | .can_queue = ATA_DEF_QUEUE, |
| 269 | .this_id = ATA_SHT_THIS_ID, |
| 270 | .sg_tablesize = LIBATA_MAX_PRD, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 271 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
| 272 | .emulated = ATA_SHT_EMULATED, |
| 273 | .use_clustering = ATA_SHT_USE_CLUSTERING, |
| 274 | .proc_name = DRV_NAME, |
| 275 | .dma_boundary = ATA_DMA_BOUNDARY, |
| 276 | .slave_configure = ata_scsi_slave_config, |
Tejun Heo | ccf68c3 | 2006-05-31 18:28:09 +0900 | [diff] [blame] | 277 | .slave_destroy = ata_scsi_slave_destroy, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 278 | .bios_param = ata_std_bios_param, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 279 | }; |
| 280 | |
Jeff Garzik | 057ace5 | 2005-10-22 14:27:05 -0400 | [diff] [blame] | 281 | static const struct ata_port_operations piix_pata_ops = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 282 | .port_disable = ata_port_disable, |
| 283 | .set_piomode = piix_set_piomode, |
| 284 | .set_dmamode = piix_set_dmamode, |
Albert Lee | 89bad58 | 2006-05-26 13:49:18 +0800 | [diff] [blame] | 285 | .mode_filter = ata_pci_default_filter, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 286 | |
| 287 | .tf_load = ata_tf_load, |
| 288 | .tf_read = ata_tf_read, |
| 289 | .check_status = ata_check_status, |
| 290 | .exec_command = ata_exec_command, |
| 291 | .dev_select = ata_std_dev_select, |
| 292 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 293 | .bmdma_setup = ata_bmdma_setup, |
| 294 | .bmdma_start = ata_bmdma_start, |
| 295 | .bmdma_stop = ata_bmdma_stop, |
| 296 | .bmdma_status = ata_bmdma_status, |
| 297 | .qc_prep = ata_qc_prep, |
| 298 | .qc_issue = ata_qc_issue_prot, |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 299 | .data_xfer = ata_data_xfer, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 300 | |
Tejun Heo | 3f037db | 2006-05-15 20:58:25 +0900 | [diff] [blame] | 301 | .freeze = ata_bmdma_freeze, |
| 302 | .thaw = ata_bmdma_thaw, |
Tejun Heo | ccc4672 | 2006-05-31 18:28:14 +0900 | [diff] [blame] | 303 | .error_handler = piix_pata_error_handler, |
Tejun Heo | 3f037db | 2006-05-15 20:58:25 +0900 | [diff] [blame] | 304 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
Alan Cox | eb4a2c7 | 2007-04-11 00:04:20 +0100 | [diff] [blame] | 305 | .cable_detect = ata_cable_40wire, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 306 | |
| 307 | .irq_handler = ata_interrupt, |
| 308 | .irq_clear = ata_bmdma_irq_clear, |
Akira Iguchi | 246ce3b | 2007-01-26 16:27:58 +0900 | [diff] [blame] | 309 | .irq_on = ata_irq_on, |
| 310 | .irq_ack = ata_irq_ack, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 311 | |
| 312 | .port_start = ata_port_start, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 313 | }; |
| 314 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 315 | static const struct ata_port_operations ich_pata_ops = { |
| 316 | .port_disable = ata_port_disable, |
| 317 | .set_piomode = piix_set_piomode, |
| 318 | .set_dmamode = ich_set_dmamode, |
| 319 | .mode_filter = ata_pci_default_filter, |
| 320 | |
| 321 | .tf_load = ata_tf_load, |
| 322 | .tf_read = ata_tf_read, |
| 323 | .check_status = ata_check_status, |
| 324 | .exec_command = ata_exec_command, |
| 325 | .dev_select = ata_std_dev_select, |
| 326 | |
| 327 | .bmdma_setup = ata_bmdma_setup, |
| 328 | .bmdma_start = ata_bmdma_start, |
| 329 | .bmdma_stop = ata_bmdma_stop, |
| 330 | .bmdma_status = ata_bmdma_status, |
| 331 | .qc_prep = ata_qc_prep, |
| 332 | .qc_issue = ata_qc_issue_prot, |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 333 | .data_xfer = ata_data_xfer, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 334 | |
| 335 | .freeze = ata_bmdma_freeze, |
| 336 | .thaw = ata_bmdma_thaw, |
Alan Cox | eb4a2c7 | 2007-04-11 00:04:20 +0100 | [diff] [blame] | 337 | .error_handler = piix_pata_error_handler, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 338 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
Alan Cox | eb4a2c7 | 2007-04-11 00:04:20 +0100 | [diff] [blame] | 339 | .cable_detect = ich_pata_cable_detect, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 340 | |
| 341 | .irq_handler = ata_interrupt, |
| 342 | .irq_clear = ata_bmdma_irq_clear, |
Akira Iguchi | 246ce3b | 2007-01-26 16:27:58 +0900 | [diff] [blame] | 343 | .irq_on = ata_irq_on, |
| 344 | .irq_ack = ata_irq_ack, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 345 | |
| 346 | .port_start = ata_port_start, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 347 | }; |
| 348 | |
Jeff Garzik | 057ace5 | 2005-10-22 14:27:05 -0400 | [diff] [blame] | 349 | static const struct ata_port_operations piix_sata_ops = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 350 | .port_disable = ata_port_disable, |
| 351 | |
| 352 | .tf_load = ata_tf_load, |
| 353 | .tf_read = ata_tf_read, |
| 354 | .check_status = ata_check_status, |
| 355 | .exec_command = ata_exec_command, |
| 356 | .dev_select = ata_std_dev_select, |
| 357 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 358 | .bmdma_setup = ata_bmdma_setup, |
| 359 | .bmdma_start = ata_bmdma_start, |
| 360 | .bmdma_stop = ata_bmdma_stop, |
| 361 | .bmdma_status = ata_bmdma_status, |
| 362 | .qc_prep = ata_qc_prep, |
| 363 | .qc_issue = ata_qc_issue_prot, |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 364 | .data_xfer = ata_data_xfer, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 365 | |
Tejun Heo | 3f037db | 2006-05-15 20:58:25 +0900 | [diff] [blame] | 366 | .freeze = ata_bmdma_freeze, |
| 367 | .thaw = ata_bmdma_thaw, |
Alan Cox | 2f91d81 | 2007-05-21 15:15:51 +0100 | [diff] [blame] | 368 | .error_handler = ata_bmdma_error_handler, |
Tejun Heo | 3f037db | 2006-05-15 20:58:25 +0900 | [diff] [blame] | 369 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 370 | |
| 371 | .irq_handler = ata_interrupt, |
| 372 | .irq_clear = ata_bmdma_irq_clear, |
Akira Iguchi | 246ce3b | 2007-01-26 16:27:58 +0900 | [diff] [blame] | 373 | .irq_on = ata_irq_on, |
| 374 | .irq_ack = ata_irq_ack, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 375 | |
| 376 | .port_start = ata_port_start, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 377 | }; |
| 378 | |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 379 | static const struct piix_map_db ich5_map_db = { |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 380 | .mask = 0x7, |
Jeff Garzik | ea35d29 | 2006-07-11 11:48:50 -0400 | [diff] [blame] | 381 | .port_enable = 0x3, |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 382 | .map = { |
| 383 | /* PM PS SM SS MAP */ |
| 384 | { P0, NA, P1, NA }, /* 000b */ |
| 385 | { P1, NA, P0, NA }, /* 001b */ |
| 386 | { RV, RV, RV, RV }, |
| 387 | { RV, RV, RV, RV }, |
| 388 | { P0, P1, IDE, IDE }, /* 100b */ |
| 389 | { P1, P0, IDE, IDE }, /* 101b */ |
| 390 | { IDE, IDE, P0, P1 }, /* 110b */ |
| 391 | { IDE, IDE, P1, P0 }, /* 111b */ |
| 392 | }, |
| 393 | }; |
| 394 | |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 395 | static const struct piix_map_db ich6_map_db = { |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 396 | .mask = 0x3, |
Jeff Garzik | ea35d29 | 2006-07-11 11:48:50 -0400 | [diff] [blame] | 397 | .port_enable = 0xf, |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 398 | .map = { |
| 399 | /* PM PS SM SS MAP */ |
Tejun Heo | 79ea24e | 2006-03-31 20:01:50 +0900 | [diff] [blame] | 400 | { P0, P2, P1, P3 }, /* 00b */ |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 401 | { IDE, IDE, P1, P3 }, /* 01b */ |
| 402 | { P0, P2, IDE, IDE }, /* 10b */ |
| 403 | { RV, RV, RV, RV }, |
| 404 | }, |
| 405 | }; |
| 406 | |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 407 | static const struct piix_map_db ich6m_map_db = { |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 408 | .mask = 0x3, |
Jeff Garzik | ea35d29 | 2006-07-11 11:48:50 -0400 | [diff] [blame] | 409 | .port_enable = 0x5, |
Tejun Heo | 6708374 | 2006-09-11 06:29:03 +0900 | [diff] [blame] | 410 | |
| 411 | /* Map 01b isn't specified in the doc but some notebooks use |
Tejun Heo | c6446a4 | 2006-10-09 13:23:58 +0900 | [diff] [blame] | 412 | * it anyway. MAP 01b have been spotted on both ICH6M and |
| 413 | * ICH7M. |
Tejun Heo | 6708374 | 2006-09-11 06:29:03 +0900 | [diff] [blame] | 414 | */ |
| 415 | .map = { |
| 416 | /* PM PS SM SS MAP */ |
| 417 | { P0, P2, RV, RV }, /* 00b */ |
| 418 | { IDE, IDE, P1, P3 }, /* 01b */ |
| 419 | { P0, P2, IDE, IDE }, /* 10b */ |
| 420 | { RV, RV, RV, RV }, |
| 421 | }, |
| 422 | }; |
| 423 | |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 424 | static const struct piix_map_db ich8_map_db = { |
| 425 | .mask = 0x3, |
| 426 | .port_enable = 0x3, |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 427 | .map = { |
| 428 | /* PM PS SM SS MAP */ |
Kristen Carlson Accardi | 158f30c8 | 2006-10-19 13:27:39 -0700 | [diff] [blame] | 429 | { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */ |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 430 | { RV, RV, RV, RV }, |
Kristen Carlson Accardi | 158f30c8 | 2006-10-19 13:27:39 -0700 | [diff] [blame] | 431 | { IDE, IDE, NA, NA }, /* 10b (IDE mode) */ |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 432 | { RV, RV, RV, RV }, |
| 433 | }, |
| 434 | }; |
| 435 | |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 436 | static const struct piix_map_db *piix_map_db_table[] = { |
| 437 | [ich5_sata] = &ich5_map_db, |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 438 | [ich6_sata] = &ich6_map_db, |
| 439 | [ich6_sata_ahci] = &ich6_map_db, |
| 440 | [ich6m_sata_ahci] = &ich6m_map_db, |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 441 | [ich8_sata_ahci] = &ich8_map_db, |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 442 | }; |
| 443 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 444 | static struct ata_port_info piix_port_info[] = { |
Alan | d2cdfc0 | 2007-01-10 17:13:38 +0000 | [diff] [blame] | 445 | /* piix_pata_33: 0: PIIX4 at 33MHz */ |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 446 | { |
| 447 | .sht = &piix_sht, |
Tejun Heo | b3362f8 | 2006-11-10 18:08:10 +0900 | [diff] [blame] | 448 | .flags = PIIX_PATA_FLAGS, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 449 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 450 | .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 451 | .udma_mask = ATA_UDMA_MASK_40C, |
| 452 | .port_ops = &piix_pata_ops, |
| 453 | }, |
| 454 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 455 | /* ich_pata_33: 1 ICH0 - ICH at 33Mhz*/ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 456 | { |
| 457 | .sht = &piix_sht, |
Tejun Heo | b3362f8 | 2006-11-10 18:08:10 +0900 | [diff] [blame] | 458 | .flags = PIIX_PATA_FLAGS, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 459 | .pio_mask = 0x1f, /* pio 0-4 */ |
| 460 | .mwdma_mask = 0x06, /* Check: maybe 0x07 */ |
| 461 | .udma_mask = ATA_UDMA2, /* UDMA33 */ |
| 462 | .port_ops = &ich_pata_ops, |
| 463 | }, |
| 464 | /* ich_pata_66: 2 ICH controllers up to 66MHz */ |
| 465 | { |
| 466 | .sht = &piix_sht, |
Tejun Heo | b3362f8 | 2006-11-10 18:08:10 +0900 | [diff] [blame] | 467 | .flags = PIIX_PATA_FLAGS, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 468 | .pio_mask = 0x1f, /* pio 0-4 */ |
| 469 | .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */ |
| 470 | .udma_mask = ATA_UDMA4, |
| 471 | .port_ops = &ich_pata_ops, |
| 472 | }, |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 473 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 474 | /* ich_pata_100: 3 */ |
| 475 | { |
| 476 | .sht = &piix_sht, |
Tejun Heo | b3362f8 | 2006-11-10 18:08:10 +0900 | [diff] [blame] | 477 | .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 478 | .pio_mask = 0x1f, /* pio0-4 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 479 | .mwdma_mask = 0x06, /* mwdma1-2 */ |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 480 | .udma_mask = ATA_UDMA5, /* udma0-5 */ |
| 481 | .port_ops = &ich_pata_ops, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 482 | }, |
| 483 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 484 | /* ich_pata_133: 4 ICH with full UDMA6 */ |
| 485 | { |
| 486 | .sht = &piix_sht, |
Tejun Heo | b3362f8 | 2006-11-10 18:08:10 +0900 | [diff] [blame] | 487 | .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 488 | .pio_mask = 0x1f, /* pio 0-4 */ |
| 489 | .mwdma_mask = 0x06, /* Check: maybe 0x07 */ |
| 490 | .udma_mask = ATA_UDMA6, /* UDMA133 */ |
| 491 | .port_ops = &ich_pata_ops, |
| 492 | }, |
| 493 | |
| 494 | /* ich5_sata: 5 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 495 | { |
| 496 | .sht = &piix_sht, |
Tejun Heo | 228c159 | 2006-11-10 18:08:10 +0900 | [diff] [blame] | 497 | .flags = PIIX_SATA_FLAGS, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 498 | .pio_mask = 0x1f, /* pio0-4 */ |
| 499 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
| 500 | .udma_mask = 0x7f, /* udma0-6 */ |
| 501 | .port_ops = &piix_sata_ops, |
| 502 | }, |
| 503 | |
Tejun Heo | 5e56a37 | 2006-11-10 18:08:10 +0900 | [diff] [blame] | 504 | /* ich6_sata: 6 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 505 | { |
| 506 | .sht = &piix_sht, |
Tejun Heo | b3362f8 | 2006-11-10 18:08:10 +0900 | [diff] [blame] | 507 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 508 | .pio_mask = 0x1f, /* pio0-4 */ |
| 509 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
| 510 | .udma_mask = 0x7f, /* udma0-6 */ |
| 511 | .port_ops = &piix_sata_ops, |
| 512 | }, |
| 513 | |
Tejun Heo | 5e56a37 | 2006-11-10 18:08:10 +0900 | [diff] [blame] | 514 | /* ich6_sata_ahci: 7 */ |
Jason Gaston | c368ca4 | 2005-04-16 15:24:44 -0700 | [diff] [blame] | 515 | { |
| 516 | .sht = &piix_sht, |
Tejun Heo | b3362f8 | 2006-11-10 18:08:10 +0900 | [diff] [blame] | 517 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR | |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 518 | PIIX_FLAG_AHCI, |
Jason Gaston | c368ca4 | 2005-04-16 15:24:44 -0700 | [diff] [blame] | 519 | .pio_mask = 0x1f, /* pio0-4 */ |
| 520 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
| 521 | .udma_mask = 0x7f, /* udma0-6 */ |
| 522 | .port_ops = &piix_sata_ops, |
| 523 | }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 524 | |
Tejun Heo | 5e56a37 | 2006-11-10 18:08:10 +0900 | [diff] [blame] | 525 | /* ich6m_sata_ahci: 8 */ |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 526 | { |
| 527 | .sht = &piix_sht, |
Tejun Heo | b3362f8 | 2006-11-10 18:08:10 +0900 | [diff] [blame] | 528 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR | |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 529 | PIIX_FLAG_AHCI, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 530 | .pio_mask = 0x1f, /* pio0-4 */ |
| 531 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
| 532 | .udma_mask = 0x7f, /* udma0-6 */ |
| 533 | .port_ops = &piix_sata_ops, |
| 534 | }, |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 535 | |
Tejun Heo | 5e56a37 | 2006-11-10 18:08:10 +0900 | [diff] [blame] | 536 | /* ich8_sata_ahci: 9 */ |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 537 | { |
| 538 | .sht = &piix_sht, |
Tejun Heo | b3362f8 | 2006-11-10 18:08:10 +0900 | [diff] [blame] | 539 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR | |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 540 | PIIX_FLAG_AHCI, |
| 541 | .pio_mask = 0x1f, /* pio0-4 */ |
| 542 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
| 543 | .udma_mask = 0x7f, /* udma0-6 */ |
| 544 | .port_ops = &piix_sata_ops, |
| 545 | }, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 546 | |
Alan | d2cdfc0 | 2007-01-10 17:13:38 +0000 | [diff] [blame] | 547 | /* piix_pata_mwdma: 10: PIIX3 MWDMA only */ |
| 548 | { |
| 549 | .sht = &piix_sht, |
| 550 | .flags = PIIX_PATA_FLAGS, |
| 551 | .pio_mask = 0x1f, /* pio0-4 */ |
| 552 | .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ |
| 553 | .port_ops = &piix_pata_ops, |
| 554 | }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 555 | }; |
| 556 | |
| 557 | static struct pci_bits piix_enable_bits[] = { |
| 558 | { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */ |
| 559 | { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */ |
| 560 | }; |
| 561 | |
| 562 | MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik"); |
| 563 | MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers"); |
| 564 | MODULE_LICENSE("GPL"); |
| 565 | MODULE_DEVICE_TABLE(pci, piix_pci_tbl); |
| 566 | MODULE_VERSION(DRV_VERSION); |
| 567 | |
Alan Cox | fc08515 | 2006-10-10 14:28:11 -0700 | [diff] [blame] | 568 | struct ich_laptop { |
| 569 | u16 device; |
| 570 | u16 subvendor; |
| 571 | u16 subdevice; |
| 572 | }; |
| 573 | |
| 574 | /* |
| 575 | * List of laptops that use short cables rather than 80 wire |
| 576 | */ |
| 577 | |
| 578 | static const struct ich_laptop ich_laptop[] = { |
| 579 | /* devid, subvendor, subdev */ |
| 580 | { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */ |
J J | babfb68 | 2007-01-09 02:26:30 +0900 | [diff] [blame] | 581 | { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */ |
Robin H\. Johnson | 1234010 | 2007-03-28 18:02:07 -0700 | [diff] [blame] | 582 | { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */ |
Tejun Heo | b33620f | 2007-05-22 11:34:22 +0200 | [diff] [blame] | 583 | { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */ |
Alan Cox | fc08515 | 2006-10-10 14:28:11 -0700 | [diff] [blame] | 584 | /* end marker */ |
| 585 | { 0, } |
| 586 | }; |
| 587 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 588 | /** |
Alan Cox | eb4a2c7 | 2007-04-11 00:04:20 +0100 | [diff] [blame] | 589 | * ich_pata_cable_detect - Probe host controller cable detect info |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 590 | * @ap: Port for which cable detect info is desired |
| 591 | * |
| 592 | * Read 80c cable indicator from ATA PCI device's PCI config |
| 593 | * register. This register is normally set by firmware (BIOS). |
| 594 | * |
| 595 | * LOCKING: |
| 596 | * None (inherited from caller). |
| 597 | */ |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 598 | |
Alan Cox | eb4a2c7 | 2007-04-11 00:04:20 +0100 | [diff] [blame] | 599 | static int ich_pata_cable_detect(struct ata_port *ap) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 600 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 601 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
Alan Cox | fc08515 | 2006-10-10 14:28:11 -0700 | [diff] [blame] | 602 | const struct ich_laptop *lap = &ich_laptop[0]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 603 | u8 tmp, mask; |
| 604 | |
Alan Cox | fc08515 | 2006-10-10 14:28:11 -0700 | [diff] [blame] | 605 | /* Check for specials - Acer Aspire 5602WLMi */ |
| 606 | while (lap->device) { |
| 607 | if (lap->device == pdev->device && |
| 608 | lap->subvendor == pdev->subsystem_vendor && |
| 609 | lap->subdevice == pdev->subsystem_device) { |
Alan Cox | eb4a2c7 | 2007-04-11 00:04:20 +0100 | [diff] [blame] | 610 | return ATA_CBL_PATA40_SHORT; |
Alan Cox | fc08515 | 2006-10-10 14:28:11 -0700 | [diff] [blame] | 611 | } |
| 612 | lap++; |
| 613 | } |
| 614 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 615 | /* check BIOS cable detect results */ |
Tejun Heo | 2a88d1a | 2006-08-10 16:59:16 +0900 | [diff] [blame] | 616 | mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 617 | pci_read_config_byte(pdev, PIIX_IOCFG, &tmp); |
| 618 | if ((tmp & mask) == 0) |
Alan Cox | eb4a2c7 | 2007-04-11 00:04:20 +0100 | [diff] [blame] | 619 | return ATA_CBL_PATA40; |
| 620 | return ATA_CBL_PATA80; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 621 | } |
| 622 | |
| 623 | /** |
Tejun Heo | ccc4672 | 2006-05-31 18:28:14 +0900 | [diff] [blame] | 624 | * piix_pata_prereset - prereset for PATA host controller |
Tejun Heo | 573db6b | 2006-02-15 15:01:42 +0900 | [diff] [blame] | 625 | * @ap: Target port |
Tejun Heo | d4b2bab | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 626 | * @deadline: deadline jiffies for the operation |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 627 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 628 | * LOCKING: |
| 629 | * None (inherited from caller). |
| 630 | */ |
Tejun Heo | d4b2bab | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 631 | static int piix_pata_prereset(struct ata_port *ap, unsigned long deadline) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 632 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 633 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 634 | |
Alan Cox | c961922 | 2006-09-26 17:53:38 +0100 | [diff] [blame] | 635 | if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no])) |
| 636 | return -ENOENT; |
Tejun Heo | d4b2bab | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 637 | return ata_std_prereset(ap, deadline); |
Tejun Heo | ccc4672 | 2006-05-31 18:28:14 +0900 | [diff] [blame] | 638 | } |
| 639 | |
| 640 | static void piix_pata_error_handler(struct ata_port *ap) |
| 641 | { |
| 642 | ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL, |
| 643 | ata_std_postreset); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 644 | } |
| 645 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 646 | /** |
| 647 | * piix_set_piomode - Initialize host controller PATA PIO timings |
| 648 | * @ap: Port whose timings we are configuring |
| 649 | * @adev: um |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 650 | * |
| 651 | * Set PIO mode for device, in host controller PCI config space. |
| 652 | * |
| 653 | * LOCKING: |
| 654 | * None (inherited from caller). |
| 655 | */ |
| 656 | |
| 657 | static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev) |
| 658 | { |
| 659 | unsigned int pio = adev->pio_mode - XFER_PIO_0; |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 660 | struct pci_dev *dev = to_pci_dev(ap->host->dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 661 | unsigned int is_slave = (adev->devno != 0); |
Tejun Heo | 2a88d1a | 2006-08-10 16:59:16 +0900 | [diff] [blame] | 662 | unsigned int master_port= ap->port_no ? 0x42 : 0x40; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 663 | unsigned int slave_port = 0x44; |
| 664 | u16 master_data; |
| 665 | u8 slave_data; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 666 | u8 udma_enable; |
| 667 | int control = 0; |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 668 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 669 | /* |
| 670 | * See Intel Document 298600-004 for the timing programing rules |
| 671 | * for ICH controllers. |
| 672 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 673 | |
| 674 | static const /* ISP RTC */ |
| 675 | u8 timings[][2] = { { 0, 0 }, |
| 676 | { 0, 0 }, |
| 677 | { 1, 0 }, |
| 678 | { 2, 1 }, |
| 679 | { 2, 3 }, }; |
| 680 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 681 | if (pio >= 2) |
| 682 | control |= 1; /* TIME1 enable */ |
| 683 | if (ata_pio_need_iordy(adev)) |
| 684 | control |= 2; /* IE enable */ |
| 685 | |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 686 | /* Intel specifies that the PPE functionality is for disk only */ |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 687 | if (adev->class == ATA_DEV_ATA) |
| 688 | control |= 4; /* PPE enable */ |
| 689 | |
Tejun Heo | a5bf5f5 | 2007-05-25 19:16:58 +0200 | [diff] [blame] | 690 | /* PIO configuration clears DTE unconditionally. It will be |
| 691 | * programmed in set_dmamode which is guaranteed to be called |
| 692 | * after set_piomode if any DMA mode is available. |
| 693 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 694 | pci_read_config_word(dev, master_port, &master_data); |
| 695 | if (is_slave) { |
Tejun Heo | a5bf5f5 | 2007-05-25 19:16:58 +0200 | [diff] [blame] | 696 | /* clear TIME1|IE1|PPE1|DTE1 */ |
| 697 | master_data &= 0xff0f; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 698 | /* Enable SITRE (seperate slave timing register) */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 699 | master_data |= 0x4000; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 700 | /* enable PPE1, IE1 and TIME1 as needed */ |
| 701 | master_data |= (control << 4); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 702 | pci_read_config_byte(dev, slave_port, &slave_data); |
Tejun Heo | 2a88d1a | 2006-08-10 16:59:16 +0900 | [diff] [blame] | 703 | slave_data &= (ap->port_no ? 0x0f : 0xf0); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 704 | /* Load the timing nibble for this slave */ |
Tejun Heo | a5bf5f5 | 2007-05-25 19:16:58 +0200 | [diff] [blame] | 705 | slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) |
| 706 | << (ap->port_no ? 4 : 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 707 | } else { |
Tejun Heo | a5bf5f5 | 2007-05-25 19:16:58 +0200 | [diff] [blame] | 708 | /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */ |
| 709 | master_data &= 0xccf0; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 710 | /* Enable PPE, IE and TIME as appropriate */ |
| 711 | master_data |= control; |
Tejun Heo | a5bf5f5 | 2007-05-25 19:16:58 +0200 | [diff] [blame] | 712 | /* load ISP and RCT */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 713 | master_data |= |
| 714 | (timings[pio][0] << 12) | |
| 715 | (timings[pio][1] << 8); |
| 716 | } |
| 717 | pci_write_config_word(dev, master_port, master_data); |
| 718 | if (is_slave) |
| 719 | pci_write_config_byte(dev, slave_port, slave_data); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 720 | |
| 721 | /* Ensure the UDMA bit is off - it will be turned back on if |
| 722 | UDMA is selected */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 723 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 724 | if (ap->udma_mask) { |
| 725 | pci_read_config_byte(dev, 0x48, &udma_enable); |
| 726 | udma_enable &= ~(1 << (2 * ap->port_no + adev->devno)); |
| 727 | pci_write_config_byte(dev, 0x48, udma_enable); |
| 728 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 729 | } |
| 730 | |
| 731 | /** |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 732 | * do_pata_set_dmamode - Initialize host controller PATA PIO timings |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 733 | * @ap: Port whose timings we are configuring |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 734 | * @adev: Drive in question |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 735 | * @udma: udma mode, 0 - 6 |
Henne | c32a8fd | 2006-09-25 22:00:46 +0200 | [diff] [blame] | 736 | * @isich: set if the chip is an ICH device |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 737 | * |
| 738 | * Set UDMA mode for device, in host controller PCI config space. |
| 739 | * |
| 740 | * LOCKING: |
| 741 | * None (inherited from caller). |
| 742 | */ |
| 743 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 744 | static void do_pata_set_dmamode (struct ata_port *ap, struct ata_device *adev, int isich) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 745 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 746 | struct pci_dev *dev = to_pci_dev(ap->host->dev); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 747 | u8 master_port = ap->port_no ? 0x42 : 0x40; |
| 748 | u16 master_data; |
| 749 | u8 speed = adev->dma_mode; |
| 750 | int devid = adev->devno + 2 * ap->port_no; |
Andrew Morton | dedf61d | 2007-01-10 17:20:34 -0800 | [diff] [blame] | 751 | u8 udma_enable = 0; |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 752 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 753 | static const /* ISP RTC */ |
| 754 | u8 timings[][2] = { { 0, 0 }, |
| 755 | { 0, 0 }, |
| 756 | { 1, 0 }, |
| 757 | { 2, 1 }, |
| 758 | { 2, 3 }, }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 759 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 760 | pci_read_config_word(dev, master_port, &master_data); |
Alan | d2cdfc0 | 2007-01-10 17:13:38 +0000 | [diff] [blame] | 761 | if (ap->udma_mask) |
| 762 | pci_read_config_byte(dev, 0x48, &udma_enable); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 763 | |
| 764 | if (speed >= XFER_UDMA_0) { |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 765 | unsigned int udma = adev->dma_mode - XFER_UDMA_0; |
| 766 | u16 udma_timing; |
| 767 | u16 ideconf; |
| 768 | int u_clock, u_speed; |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 769 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 770 | /* |
| 771 | * UDMA is handled by a combination of clock switching and |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 772 | * selection of dividers |
| 773 | * |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 774 | * Handy rule: Odd modes are UDMATIMx 01, even are 02 |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 775 | * except UDMA0 which is 00 |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 776 | */ |
| 777 | u_speed = min(2 - (udma & 1), udma); |
| 778 | if (udma == 5) |
| 779 | u_clock = 0x1000; /* 100Mhz */ |
| 780 | else if (udma > 2) |
| 781 | u_clock = 1; /* 66Mhz */ |
| 782 | else |
| 783 | u_clock = 0; /* 33Mhz */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 784 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 785 | udma_enable |= (1 << devid); |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 786 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 787 | /* Load the CT/RP selection */ |
| 788 | pci_read_config_word(dev, 0x4A, &udma_timing); |
| 789 | udma_timing &= ~(3 << (4 * devid)); |
| 790 | udma_timing |= u_speed << (4 * devid); |
| 791 | pci_write_config_word(dev, 0x4A, udma_timing); |
| 792 | |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 793 | if (isich) { |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 794 | /* Select a 33/66/100Mhz clock */ |
| 795 | pci_read_config_word(dev, 0x54, &ideconf); |
| 796 | ideconf &= ~(0x1001 << devid); |
| 797 | ideconf |= u_clock << devid; |
| 798 | /* For ICH or later we should set bit 10 for better |
| 799 | performance (WR_PingPong_En) */ |
| 800 | pci_write_config_word(dev, 0x54, ideconf); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 801 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 802 | } else { |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 803 | /* |
| 804 | * MWDMA is driven by the PIO timings. We must also enable |
| 805 | * IORDY unconditionally along with TIME1. PPE has already |
| 806 | * been set when the PIO timing was set. |
| 807 | */ |
| 808 | unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0; |
| 809 | unsigned int control; |
| 810 | u8 slave_data; |
| 811 | const unsigned int needed_pio[3] = { |
| 812 | XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 |
| 813 | }; |
| 814 | int pio = needed_pio[mwdma] - XFER_PIO_0; |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 815 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 816 | control = 3; /* IORDY|TIME1 */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 817 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 818 | /* If the drive MWDMA is faster than it can do PIO then |
| 819 | we must force PIO into PIO0 */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 820 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 821 | if (adev->pio_mode < needed_pio[mwdma]) |
| 822 | /* Enable DMA timing only */ |
| 823 | control |= 8; /* PIO cycles in PIO0 */ |
| 824 | |
| 825 | if (adev->devno) { /* Slave */ |
| 826 | master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */ |
| 827 | master_data |= control << 4; |
| 828 | pci_read_config_byte(dev, 0x44, &slave_data); |
Tejun Heo | a5bf5f5 | 2007-05-25 19:16:58 +0200 | [diff] [blame] | 829 | slave_data &= (ap->port_no ? 0x0f : 0xf0); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 830 | /* Load the matching timing */ |
| 831 | slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0); |
| 832 | pci_write_config_byte(dev, 0x44, slave_data); |
| 833 | } else { /* Master */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 834 | master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 835 | and master timing bits */ |
| 836 | master_data |= control; |
| 837 | master_data |= |
| 838 | (timings[pio][0] << 12) | |
| 839 | (timings[pio][1] << 8); |
| 840 | } |
Tejun Heo | a5bf5f5 | 2007-05-25 19:16:58 +0200 | [diff] [blame] | 841 | |
| 842 | if (ap->udma_mask) { |
| 843 | udma_enable &= ~(1 << devid); |
| 844 | pci_write_config_word(dev, master_port, master_data); |
| 845 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 846 | } |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 847 | /* Don't scribble on 0x48 if the controller does not support UDMA */ |
| 848 | if (ap->udma_mask) |
| 849 | pci_write_config_byte(dev, 0x48, udma_enable); |
| 850 | } |
| 851 | |
| 852 | /** |
| 853 | * piix_set_dmamode - Initialize host controller PATA DMA timings |
| 854 | * @ap: Port whose timings we are configuring |
| 855 | * @adev: um |
| 856 | * |
| 857 | * Set MW/UDMA mode for device, in host controller PCI config space. |
| 858 | * |
| 859 | * LOCKING: |
| 860 | * None (inherited from caller). |
| 861 | */ |
| 862 | |
| 863 | static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev) |
| 864 | { |
| 865 | do_pata_set_dmamode(ap, adev, 0); |
| 866 | } |
| 867 | |
| 868 | /** |
| 869 | * ich_set_dmamode - Initialize host controller PATA DMA timings |
| 870 | * @ap: Port whose timings we are configuring |
| 871 | * @adev: um |
| 872 | * |
| 873 | * Set MW/UDMA mode for device, in host controller PCI config space. |
| 874 | * |
| 875 | * LOCKING: |
| 876 | * None (inherited from caller). |
| 877 | */ |
| 878 | |
| 879 | static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev) |
| 880 | { |
| 881 | do_pata_set_dmamode(ap, adev, 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 882 | } |
| 883 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 884 | #define AHCI_PCI_BAR 5 |
| 885 | #define AHCI_GLOBAL_CTL 0x04 |
| 886 | #define AHCI_ENABLE (1 << 31) |
| 887 | static int piix_disable_ahci(struct pci_dev *pdev) |
| 888 | { |
Jeff Garzik | ea6ba10 | 2005-08-30 05:18:18 -0400 | [diff] [blame] | 889 | void __iomem *mmio; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 890 | u32 tmp; |
| 891 | int rc = 0; |
| 892 | |
| 893 | /* BUG: pci_enable_device has not yet been called. This |
| 894 | * works because this device is usually set up by BIOS. |
| 895 | */ |
| 896 | |
Jeff Garzik | 374b187 | 2005-08-30 05:42:52 -0400 | [diff] [blame] | 897 | if (!pci_resource_start(pdev, AHCI_PCI_BAR) || |
| 898 | !pci_resource_len(pdev, AHCI_PCI_BAR)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 899 | return 0; |
Greg Felix | 7b6dbd6 | 2005-07-28 15:54:15 -0400 | [diff] [blame] | 900 | |
Jeff Garzik | 374b187 | 2005-08-30 05:42:52 -0400 | [diff] [blame] | 901 | mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 902 | if (!mmio) |
| 903 | return -ENOMEM; |
Greg Felix | 7b6dbd6 | 2005-07-28 15:54:15 -0400 | [diff] [blame] | 904 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 905 | tmp = readl(mmio + AHCI_GLOBAL_CTL); |
| 906 | if (tmp & AHCI_ENABLE) { |
| 907 | tmp &= ~AHCI_ENABLE; |
| 908 | writel(tmp, mmio + AHCI_GLOBAL_CTL); |
| 909 | |
| 910 | tmp = readl(mmio + AHCI_GLOBAL_CTL); |
| 911 | if (tmp & AHCI_ENABLE) |
| 912 | rc = -EIO; |
| 913 | } |
Greg Felix | 7b6dbd6 | 2005-07-28 15:54:15 -0400 | [diff] [blame] | 914 | |
Jeff Garzik | 374b187 | 2005-08-30 05:42:52 -0400 | [diff] [blame] | 915 | pci_iounmap(pdev, mmio); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 916 | return rc; |
| 917 | } |
| 918 | |
| 919 | /** |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 920 | * piix_check_450nx_errata - Check for problem 450NX setup |
Randy Dunlap | c893a3a | 2006-01-28 13:15:32 -0500 | [diff] [blame] | 921 | * @ata_dev: the PCI device to check |
Jeff Garzik | 2e9edbf | 2006-03-24 09:56:57 -0500 | [diff] [blame] | 922 | * |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 923 | * Check for the present of 450NX errata #19 and errata #25. If |
| 924 | * they are found return an error code so we can turn off DMA |
| 925 | */ |
| 926 | |
| 927 | static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev) |
| 928 | { |
| 929 | struct pci_dev *pdev = NULL; |
| 930 | u16 cfg; |
| 931 | u8 rev; |
| 932 | int no_piix_dma = 0; |
Jeff Garzik | 2e9edbf | 2006-03-24 09:56:57 -0500 | [diff] [blame] | 933 | |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 934 | while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) |
| 935 | { |
| 936 | /* Look for 450NX PXB. Check for problem configurations |
| 937 | A PCI quirk checks bit 6 already */ |
| 938 | pci_read_config_byte(pdev, PCI_REVISION_ID, &rev); |
| 939 | pci_read_config_word(pdev, 0x41, &cfg); |
| 940 | /* Only on the original revision: IDE DMA can hang */ |
Alan Cox | 31a34fe | 2006-05-22 22:58:14 +0100 | [diff] [blame] | 941 | if (rev == 0x00) |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 942 | no_piix_dma = 1; |
| 943 | /* On all revisions below 5 PXB bus lock must be disabled for IDE */ |
Alan Cox | 31a34fe | 2006-05-22 22:58:14 +0100 | [diff] [blame] | 944 | else if (cfg & (1<<14) && rev < 5) |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 945 | no_piix_dma = 2; |
| 946 | } |
Alan Cox | 31a34fe | 2006-05-22 22:58:14 +0100 | [diff] [blame] | 947 | if (no_piix_dma) |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 948 | dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n"); |
Alan Cox | 31a34fe | 2006-05-22 22:58:14 +0100 | [diff] [blame] | 949 | if (no_piix_dma == 2) |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 950 | dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n"); |
| 951 | return no_piix_dma; |
Jeff Garzik | 2e9edbf | 2006-03-24 09:56:57 -0500 | [diff] [blame] | 952 | } |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 953 | |
Jeff Garzik | ea35d29 | 2006-07-11 11:48:50 -0400 | [diff] [blame] | 954 | static void __devinit piix_init_pcs(struct pci_dev *pdev, |
Tejun Heo | 9dd9c16 | 2006-08-22 21:15:58 +0900 | [diff] [blame] | 955 | struct ata_port_info *pinfo, |
Jeff Garzik | ea35d29 | 2006-07-11 11:48:50 -0400 | [diff] [blame] | 956 | const struct piix_map_db *map_db) |
| 957 | { |
| 958 | u16 pcs, new_pcs; |
| 959 | |
| 960 | pci_read_config_word(pdev, ICH5_PCS, &pcs); |
| 961 | |
| 962 | new_pcs = pcs | map_db->port_enable; |
| 963 | |
| 964 | if (new_pcs != pcs) { |
| 965 | DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs); |
| 966 | pci_write_config_word(pdev, ICH5_PCS, new_pcs); |
| 967 | msleep(150); |
| 968 | } |
| 969 | } |
| 970 | |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 971 | static void __devinit piix_init_sata_map(struct pci_dev *pdev, |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 972 | struct ata_port_info *pinfo, |
| 973 | const struct piix_map_db *map_db) |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 974 | { |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 975 | struct piix_host_priv *hpriv = pinfo[0].private_data; |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 976 | const unsigned int *map; |
| 977 | int i, invalid_map = 0; |
| 978 | u8 map_value; |
| 979 | |
| 980 | pci_read_config_byte(pdev, ICH5_PMR, &map_value); |
| 981 | |
| 982 | map = map_db->map[map_value & map_db->mask]; |
| 983 | |
| 984 | dev_printk(KERN_INFO, &pdev->dev, "MAP ["); |
| 985 | for (i = 0; i < 4; i++) { |
| 986 | switch (map[i]) { |
| 987 | case RV: |
| 988 | invalid_map = 1; |
| 989 | printk(" XX"); |
| 990 | break; |
| 991 | |
| 992 | case NA: |
| 993 | printk(" --"); |
| 994 | break; |
| 995 | |
| 996 | case IDE: |
| 997 | WARN_ON((i & 1) || map[i + 1] != IDE); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 998 | pinfo[i / 2] = piix_port_info[ich_pata_100]; |
Tejun Heo | f814b75 | 2006-08-05 03:59:13 +0900 | [diff] [blame] | 999 | pinfo[i / 2].private_data = hpriv; |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 1000 | i++; |
| 1001 | printk(" IDE IDE"); |
| 1002 | break; |
| 1003 | |
| 1004 | default: |
| 1005 | printk(" P%d", map[i]); |
| 1006 | if (i & 1) |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1007 | pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS; |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 1008 | break; |
| 1009 | } |
| 1010 | } |
| 1011 | printk(" ]\n"); |
| 1012 | |
| 1013 | if (invalid_map) |
| 1014 | dev_printk(KERN_ERR, &pdev->dev, |
| 1015 | "invalid MAP value %u\n", map_value); |
| 1016 | |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 1017 | hpriv->map = map; |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 1018 | } |
| 1019 | |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 1020 | /** |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1021 | * piix_init_one - Register PIIX ATA PCI device with kernel services |
| 1022 | * @pdev: PCI device to register |
| 1023 | * @ent: Entry in piix_pci_tbl matching with @pdev |
| 1024 | * |
| 1025 | * Called from kernel PCI layer. We probe for combined mode (sigh), |
| 1026 | * and then hand over control to libata, for it to do the rest. |
| 1027 | * |
| 1028 | * LOCKING: |
| 1029 | * Inherited from PCI layer (may sleep). |
| 1030 | * |
| 1031 | * RETURNS: |
| 1032 | * Zero on success, or -ERRNO value. |
| 1033 | */ |
| 1034 | |
| 1035 | static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) |
| 1036 | { |
| 1037 | static int printed_version; |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1038 | struct device *dev = &pdev->dev; |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 1039 | struct ata_port_info port_info[2]; |
Tejun Heo | 1626aeb | 2007-05-04 12:43:58 +0200 | [diff] [blame] | 1040 | const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] }; |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 1041 | struct piix_host_priv *hpriv; |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1042 | unsigned long port_flags; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1043 | |
| 1044 | if (!printed_version++) |
Jeff Garzik | 6248e64 | 2005-10-30 06:42:18 -0500 | [diff] [blame] | 1045 | dev_printk(KERN_DEBUG, &pdev->dev, |
| 1046 | "version " DRV_VERSION "\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1047 | |
| 1048 | /* no hotplugging support (FIXME) */ |
| 1049 | if (!in_module_init) |
| 1050 | return -ENODEV; |
| 1051 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1052 | hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 1053 | if (!hpriv) |
| 1054 | return -ENOMEM; |
| 1055 | |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 1056 | port_info[0] = piix_port_info[ent->driver_data]; |
| 1057 | port_info[1] = piix_port_info[ent->driver_data]; |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 1058 | port_info[0].private_data = hpriv; |
| 1059 | port_info[1].private_data = hpriv; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1060 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1061 | port_flags = port_info[0].flags; |
Tejun Heo | ff0fc14 | 2005-12-18 17:17:07 +0900 | [diff] [blame] | 1062 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1063 | if (port_flags & PIIX_FLAG_AHCI) { |
Jeff Garzik | 8a60a07 | 2005-07-31 13:13:24 -0400 | [diff] [blame] | 1064 | u8 tmp; |
| 1065 | pci_read_config_byte(pdev, PIIX_SCC, &tmp); |
| 1066 | if (tmp == PIIX_AHCI_DEVICE) { |
| 1067 | int rc = piix_disable_ahci(pdev); |
| 1068 | if (rc) |
| 1069 | return rc; |
| 1070 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1071 | } |
| 1072 | |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 1073 | /* Initialize SATA map */ |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1074 | if (port_flags & ATA_FLAG_SATA) { |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 1075 | piix_init_sata_map(pdev, port_info, |
| 1076 | piix_map_db_table[ent->driver_data]); |
Tejun Heo | 9dd9c16 | 2006-08-22 21:15:58 +0900 | [diff] [blame] | 1077 | piix_init_pcs(pdev, port_info, |
| 1078 | piix_map_db_table[ent->driver_data]); |
Jeff Garzik | ea35d29 | 2006-07-11 11:48:50 -0400 | [diff] [blame] | 1079 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1080 | |
| 1081 | /* On ICH5, some BIOSen disable the interrupt using the |
| 1082 | * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3. |
| 1083 | * On ICH6, this bit has the same effect, but only when |
| 1084 | * MSI is disabled (and it is disabled, as we don't use |
| 1085 | * message-signalled interrupts currently). |
| 1086 | */ |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1087 | if (port_flags & PIIX_FLAG_CHECKINTR) |
Brett M Russ | a04ce0f | 2005-08-15 15:23:41 -0400 | [diff] [blame] | 1088 | pci_intx(pdev, 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1089 | |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 1090 | if (piix_check_450nx_errata(pdev)) { |
| 1091 | /* This writes into the master table but it does not |
| 1092 | really matter for this errata as we will apply it to |
| 1093 | all the PIIX devices on the board */ |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 1094 | port_info[0].mwdma_mask = 0; |
| 1095 | port_info[0].udma_mask = 0; |
| 1096 | port_info[1].mwdma_mask = 0; |
| 1097 | port_info[1].udma_mask = 0; |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 1098 | } |
Tejun Heo | 1626aeb | 2007-05-04 12:43:58 +0200 | [diff] [blame] | 1099 | return ata_pci_init_one(pdev, ppi); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1100 | } |
| 1101 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1102 | static int __init piix_init(void) |
| 1103 | { |
| 1104 | int rc; |
| 1105 | |
Pavel Roskin | b788719 | 2006-08-10 18:13:18 +0900 | [diff] [blame] | 1106 | DPRINTK("pci_register_driver\n"); |
| 1107 | rc = pci_register_driver(&piix_pci_driver); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1108 | if (rc) |
| 1109 | return rc; |
| 1110 | |
| 1111 | in_module_init = 0; |
| 1112 | |
| 1113 | DPRINTK("done\n"); |
| 1114 | return 0; |
| 1115 | } |
| 1116 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1117 | static void __exit piix_exit(void) |
| 1118 | { |
| 1119 | pci_unregister_driver(&piix_pci_driver); |
| 1120 | } |
| 1121 | |
| 1122 | module_init(piix_init); |
| 1123 | module_exit(piix_exit); |