Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 1 | /* |
| 2 | * xHCI host controller driver |
| 3 | * |
| 4 | * Copyright (C) 2008 Intel Corp. |
| 5 | * |
| 6 | * Author: Sarah Sharp |
| 7 | * Some code borrowed from the Linux EHCI driver. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License version 2 as |
| 11 | * published by the Free Software Foundation. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, but |
| 14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
| 15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 16 | * for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software Foundation, |
| 20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 21 | */ |
| 22 | |
| 23 | /* |
| 24 | * Ring initialization rules: |
| 25 | * 1. Each segment is initialized to zero, except for link TRBs. |
| 26 | * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or |
| 27 | * Consumer Cycle State (CCS), depending on ring function. |
| 28 | * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment. |
| 29 | * |
| 30 | * Ring behavior rules: |
| 31 | * 1. A ring is empty if enqueue == dequeue. This means there will always be at |
| 32 | * least one free TRB in the ring. This is useful if you want to turn that |
| 33 | * into a link TRB and expand the ring. |
| 34 | * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a |
| 35 | * link TRB, then load the pointer with the address in the link TRB. If the |
| 36 | * link TRB had its toggle bit set, you may need to update the ring cycle |
| 37 | * state (see cycle bit rules). You may have to do this multiple times |
| 38 | * until you reach a non-link TRB. |
| 39 | * 3. A ring is full if enqueue++ (for the definition of increment above) |
| 40 | * equals the dequeue pointer. |
| 41 | * |
| 42 | * Cycle bit rules: |
| 43 | * 1. When a consumer increments a dequeue pointer and encounters a toggle bit |
| 44 | * in a link TRB, it must toggle the ring cycle state. |
| 45 | * 2. When a producer increments an enqueue pointer and encounters a toggle bit |
| 46 | * in a link TRB, it must toggle the ring cycle state. |
| 47 | * |
| 48 | * Producer rules: |
| 49 | * 1. Check if ring is full before you enqueue. |
| 50 | * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing. |
| 51 | * Update enqueue pointer between each write (which may update the ring |
| 52 | * cycle state). |
| 53 | * 3. Notify consumer. If SW is producer, it rings the doorbell for command |
| 54 | * and endpoint rings. If HC is the producer for the event ring, |
| 55 | * and it generates an interrupt according to interrupt modulation rules. |
| 56 | * |
| 57 | * Consumer rules: |
| 58 | * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state, |
| 59 | * the TRB is owned by the consumer. |
| 60 | * 2. Update dequeue pointer (which may update the ring cycle state) and |
| 61 | * continue processing TRBs until you reach a TRB which is not owned by you. |
| 62 | * 3. Notify the producer. SW is the consumer for the event ring, and it |
| 63 | * updates event ring dequeue pointer. HC is the consumer for the command and |
| 64 | * endpoint rings; it generates events on the event ring for these. |
| 65 | */ |
| 66 | |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 67 | #include <linux/scatterlist.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 68 | #include <linux/slab.h> |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 69 | #include "xhci.h" |
| 70 | |
| 71 | /* |
| 72 | * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA |
| 73 | * address of the TRB. |
| 74 | */ |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 75 | dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 76 | union xhci_trb *trb) |
| 77 | { |
Sarah Sharp | 6071d83 | 2009-05-14 11:44:14 -0700 | [diff] [blame] | 78 | unsigned long segment_offset; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 79 | |
Sarah Sharp | 6071d83 | 2009-05-14 11:44:14 -0700 | [diff] [blame] | 80 | if (!seg || !trb || trb < seg->trbs) |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 81 | return 0; |
Sarah Sharp | 6071d83 | 2009-05-14 11:44:14 -0700 | [diff] [blame] | 82 | /* offset in TRBs */ |
| 83 | segment_offset = trb - seg->trbs; |
| 84 | if (segment_offset > TRBS_PER_SEGMENT) |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 85 | return 0; |
Sarah Sharp | 6071d83 | 2009-05-14 11:44:14 -0700 | [diff] [blame] | 86 | return seg->dma + (segment_offset * sizeof(*trb)); |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 87 | } |
| 88 | |
| 89 | /* Does this link TRB point to the first segment in a ring, |
| 90 | * or was the previous TRB the last TRB on the last segment in the ERST? |
| 91 | */ |
| 92 | static inline bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring, |
| 93 | struct xhci_segment *seg, union xhci_trb *trb) |
| 94 | { |
| 95 | if (ring == xhci->event_ring) |
| 96 | return (trb == &seg->trbs[TRBS_PER_SEGMENT]) && |
| 97 | (seg->next == xhci->event_ring->first_seg); |
| 98 | else |
| 99 | return trb->link.control & LINK_TOGGLE; |
| 100 | } |
| 101 | |
| 102 | /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring |
| 103 | * segment? I.e. would the updated event TRB pointer step off the end of the |
| 104 | * event seg? |
| 105 | */ |
| 106 | static inline int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring, |
| 107 | struct xhci_segment *seg, union xhci_trb *trb) |
| 108 | { |
| 109 | if (ring == xhci->event_ring) |
| 110 | return trb == &seg->trbs[TRBS_PER_SEGMENT]; |
| 111 | else |
| 112 | return (trb->link.control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK); |
| 113 | } |
| 114 | |
John Youn | 6c12db9 | 2010-05-10 15:33:00 -0700 | [diff] [blame] | 115 | static inline int enqueue_is_link_trb(struct xhci_ring *ring) |
| 116 | { |
| 117 | struct xhci_link_trb *link = &ring->enqueue->link; |
| 118 | return ((link->control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK)); |
| 119 | } |
| 120 | |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 121 | /* Updates trb to point to the next TRB in the ring, and updates seg if the next |
| 122 | * TRB is in a new segment. This does not skip over link TRBs, and it does not |
| 123 | * effect the ring dequeue or enqueue pointers. |
| 124 | */ |
| 125 | static void next_trb(struct xhci_hcd *xhci, |
| 126 | struct xhci_ring *ring, |
| 127 | struct xhci_segment **seg, |
| 128 | union xhci_trb **trb) |
| 129 | { |
| 130 | if (last_trb(xhci, ring, *seg, *trb)) { |
| 131 | *seg = (*seg)->next; |
| 132 | *trb = ((*seg)->trbs); |
| 133 | } else { |
| 134 | *trb = (*trb)++; |
| 135 | } |
| 136 | } |
| 137 | |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 138 | /* |
| 139 | * See Cycle bit rules. SW is the consumer for the event ring only. |
| 140 | * Don't make a ring full of link TRBs. That would be dumb and this would loop. |
| 141 | */ |
| 142 | static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer) |
| 143 | { |
| 144 | union xhci_trb *next = ++(ring->dequeue); |
Sarah Sharp | 66e49d8 | 2009-07-27 12:03:46 -0700 | [diff] [blame] | 145 | unsigned long long addr; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 146 | |
| 147 | ring->deq_updates++; |
| 148 | /* Update the dequeue pointer further if that was a link TRB or we're at |
| 149 | * the end of an event ring segment (which doesn't have link TRBS) |
| 150 | */ |
| 151 | while (last_trb(xhci, ring, ring->deq_seg, next)) { |
| 152 | if (consumer && last_trb_on_last_seg(xhci, ring, ring->deq_seg, next)) { |
| 153 | ring->cycle_state = (ring->cycle_state ? 0 : 1); |
| 154 | if (!in_interrupt()) |
Greg Kroah-Hartman | 700e205 | 2009-04-29 19:14:08 -0700 | [diff] [blame] | 155 | xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n", |
| 156 | ring, |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 157 | (unsigned int) ring->cycle_state); |
| 158 | } |
| 159 | ring->deq_seg = ring->deq_seg->next; |
| 160 | ring->dequeue = ring->deq_seg->trbs; |
| 161 | next = ring->dequeue; |
| 162 | } |
Sarah Sharp | 66e49d8 | 2009-07-27 12:03:46 -0700 | [diff] [blame] | 163 | addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue); |
| 164 | if (ring == xhci->event_ring) |
| 165 | xhci_dbg(xhci, "Event ring deq = 0x%llx (DMA)\n", addr); |
| 166 | else if (ring == xhci->cmd_ring) |
| 167 | xhci_dbg(xhci, "Command ring deq = 0x%llx (DMA)\n", addr); |
| 168 | else |
| 169 | xhci_dbg(xhci, "Ring deq = 0x%llx (DMA)\n", addr); |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 170 | } |
| 171 | |
| 172 | /* |
| 173 | * See Cycle bit rules. SW is the consumer for the event ring only. |
| 174 | * Don't make a ring full of link TRBs. That would be dumb and this would loop. |
| 175 | * |
| 176 | * If we've just enqueued a TRB that is in the middle of a TD (meaning the |
| 177 | * chain bit is set), then set the chain bit in all the following link TRBs. |
| 178 | * If we've enqueued the last TRB in a TD, make sure the following link TRBs |
| 179 | * have their chain bit cleared (so that each Link TRB is a separate TD). |
| 180 | * |
| 181 | * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit |
Sarah Sharp | b0567b3 | 2009-08-07 14:04:36 -0700 | [diff] [blame] | 182 | * set, but other sections talk about dealing with the chain bit set. This was |
| 183 | * fixed in the 0.96 specification errata, but we have to assume that all 0.95 |
| 184 | * xHCI hardware can't handle the chain bit being cleared on a link TRB. |
Sarah Sharp | 6cc30d8 | 2010-06-10 12:25:28 -0700 | [diff] [blame] | 185 | * |
| 186 | * @more_trbs_coming: Will you enqueue more TRBs before calling |
| 187 | * prepare_transfer()? |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 188 | */ |
Sarah Sharp | 6cc30d8 | 2010-06-10 12:25:28 -0700 | [diff] [blame] | 189 | static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, |
| 190 | bool consumer, bool more_trbs_coming) |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 191 | { |
| 192 | u32 chain; |
| 193 | union xhci_trb *next; |
Sarah Sharp | 66e49d8 | 2009-07-27 12:03:46 -0700 | [diff] [blame] | 194 | unsigned long long addr; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 195 | |
| 196 | chain = ring->enqueue->generic.field[3] & TRB_CHAIN; |
| 197 | next = ++(ring->enqueue); |
| 198 | |
| 199 | ring->enq_updates++; |
| 200 | /* Update the dequeue pointer further if that was a link TRB or we're at |
| 201 | * the end of an event ring segment (which doesn't have link TRBS) |
| 202 | */ |
| 203 | while (last_trb(xhci, ring, ring->enq_seg, next)) { |
| 204 | if (!consumer) { |
| 205 | if (ring != xhci->event_ring) { |
Sarah Sharp | 6cc30d8 | 2010-06-10 12:25:28 -0700 | [diff] [blame] | 206 | /* |
| 207 | * If the caller doesn't plan on enqueueing more |
| 208 | * TDs before ringing the doorbell, then we |
| 209 | * don't want to give the link TRB to the |
| 210 | * hardware just yet. We'll give the link TRB |
| 211 | * back in prepare_ring() just before we enqueue |
| 212 | * the TD at the top of the ring. |
| 213 | */ |
| 214 | if (!chain && !more_trbs_coming) |
John Youn | 6c12db9 | 2010-05-10 15:33:00 -0700 | [diff] [blame] | 215 | break; |
Sarah Sharp | 6cc30d8 | 2010-06-10 12:25:28 -0700 | [diff] [blame] | 216 | |
| 217 | /* If we're not dealing with 0.95 hardware, |
| 218 | * carry over the chain bit of the previous TRB |
| 219 | * (which may mean the chain bit is cleared). |
| 220 | */ |
| 221 | if (!xhci_link_trb_quirk(xhci)) { |
| 222 | next->link.control &= ~TRB_CHAIN; |
| 223 | next->link.control |= chain; |
Sarah Sharp | b0567b3 | 2009-08-07 14:04:36 -0700 | [diff] [blame] | 224 | } |
Sarah Sharp | 6cc30d8 | 2010-06-10 12:25:28 -0700 | [diff] [blame] | 225 | /* Give this link TRB to the hardware */ |
| 226 | wmb(); |
| 227 | next->link.control ^= TRB_CYCLE; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 228 | } |
| 229 | /* Toggle the cycle bit after the last ring segment. */ |
| 230 | if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) { |
| 231 | ring->cycle_state = (ring->cycle_state ? 0 : 1); |
| 232 | if (!in_interrupt()) |
Greg Kroah-Hartman | 700e205 | 2009-04-29 19:14:08 -0700 | [diff] [blame] | 233 | xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n", |
| 234 | ring, |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 235 | (unsigned int) ring->cycle_state); |
| 236 | } |
| 237 | } |
| 238 | ring->enq_seg = ring->enq_seg->next; |
| 239 | ring->enqueue = ring->enq_seg->trbs; |
| 240 | next = ring->enqueue; |
| 241 | } |
Sarah Sharp | 66e49d8 | 2009-07-27 12:03:46 -0700 | [diff] [blame] | 242 | addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue); |
| 243 | if (ring == xhci->event_ring) |
| 244 | xhci_dbg(xhci, "Event ring enq = 0x%llx (DMA)\n", addr); |
| 245 | else if (ring == xhci->cmd_ring) |
| 246 | xhci_dbg(xhci, "Command ring enq = 0x%llx (DMA)\n", addr); |
| 247 | else |
| 248 | xhci_dbg(xhci, "Ring enq = 0x%llx (DMA)\n", addr); |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 249 | } |
| 250 | |
| 251 | /* |
| 252 | * Check to see if there's room to enqueue num_trbs on the ring. See rules |
| 253 | * above. |
| 254 | * FIXME: this would be simpler and faster if we just kept track of the number |
| 255 | * of free TRBs in a ring. |
| 256 | */ |
| 257 | static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring, |
| 258 | unsigned int num_trbs) |
| 259 | { |
| 260 | int i; |
| 261 | union xhci_trb *enq = ring->enqueue; |
| 262 | struct xhci_segment *enq_seg = ring->enq_seg; |
Sarah Sharp | 44ebd03 | 2010-05-18 16:05:26 -0700 | [diff] [blame] | 263 | struct xhci_segment *cur_seg; |
| 264 | unsigned int left_on_ring; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 265 | |
John Youn | 6c12db9 | 2010-05-10 15:33:00 -0700 | [diff] [blame] | 266 | /* If we are currently pointing to a link TRB, advance the |
| 267 | * enqueue pointer before checking for space */ |
| 268 | while (last_trb(xhci, ring, enq_seg, enq)) { |
| 269 | enq_seg = enq_seg->next; |
| 270 | enq = enq_seg->trbs; |
| 271 | } |
| 272 | |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 273 | /* Check if ring is empty */ |
Sarah Sharp | 44ebd03 | 2010-05-18 16:05:26 -0700 | [diff] [blame] | 274 | if (enq == ring->dequeue) { |
| 275 | /* Can't use link trbs */ |
| 276 | left_on_ring = TRBS_PER_SEGMENT - 1; |
| 277 | for (cur_seg = enq_seg->next; cur_seg != enq_seg; |
| 278 | cur_seg = cur_seg->next) |
| 279 | left_on_ring += TRBS_PER_SEGMENT - 1; |
| 280 | |
| 281 | /* Always need one TRB free in the ring. */ |
| 282 | left_on_ring -= 1; |
| 283 | if (num_trbs > left_on_ring) { |
| 284 | xhci_warn(xhci, "Not enough room on ring; " |
| 285 | "need %u TRBs, %u TRBs left\n", |
| 286 | num_trbs, left_on_ring); |
| 287 | return 0; |
| 288 | } |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 289 | return 1; |
Sarah Sharp | 44ebd03 | 2010-05-18 16:05:26 -0700 | [diff] [blame] | 290 | } |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 291 | /* Make sure there's an extra empty TRB available */ |
| 292 | for (i = 0; i <= num_trbs; ++i) { |
| 293 | if (enq == ring->dequeue) |
| 294 | return 0; |
| 295 | enq++; |
| 296 | while (last_trb(xhci, ring, enq_seg, enq)) { |
| 297 | enq_seg = enq_seg->next; |
| 298 | enq = enq_seg->trbs; |
| 299 | } |
| 300 | } |
| 301 | return 1; |
| 302 | } |
| 303 | |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 304 | /* Ring the host controller doorbell after placing a command on the ring */ |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 305 | void xhci_ring_cmd_db(struct xhci_hcd *xhci) |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 306 | { |
| 307 | u32 temp; |
| 308 | |
| 309 | xhci_dbg(xhci, "// Ding dong!\n"); |
| 310 | temp = xhci_readl(xhci, &xhci->dba->doorbell[0]) & DB_MASK; |
| 311 | xhci_writel(xhci, temp | DB_TARGET_HOST, &xhci->dba->doorbell[0]); |
| 312 | /* Flush PCI posted writes */ |
| 313 | xhci_readl(xhci, &xhci->dba->doorbell[0]); |
| 314 | } |
| 315 | |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 316 | static void ring_ep_doorbell(struct xhci_hcd *xhci, |
| 317 | unsigned int slot_id, |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 318 | unsigned int ep_index, |
| 319 | unsigned int stream_id) |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 320 | { |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 321 | struct xhci_virt_ep *ep; |
| 322 | unsigned int ep_state; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 323 | u32 field; |
| 324 | __u32 __iomem *db_addr = &xhci->dba->doorbell[slot_id]; |
| 325 | |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 326 | ep = &xhci->devs[slot_id]->eps[ep_index]; |
| 327 | ep_state = ep->ep_state; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 328 | /* Don't ring the doorbell for this endpoint if there are pending |
| 329 | * cancellations because the we don't want to interrupt processing. |
Sarah Sharp | 8df75f4 | 2010-04-02 15:34:16 -0700 | [diff] [blame] | 330 | * We don't want to restart any stream rings if there's a set dequeue |
| 331 | * pointer command pending because the device can choose to start any |
| 332 | * stream once the endpoint is on the HW schedule. |
| 333 | * FIXME - check all the stream rings for pending cancellations. |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 334 | */ |
Sarah Sharp | 678539c | 2009-10-27 10:55:52 -0700 | [diff] [blame] | 335 | if (!(ep_state & EP_HALT_PENDING) && !(ep_state & SET_DEQ_PENDING) |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 336 | && !(ep_state & EP_HALTED)) { |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 337 | field = xhci_readl(xhci, db_addr) & DB_MASK; |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 338 | field |= EPI_TO_DB(ep_index) | STREAM_ID_TO_DB(stream_id); |
| 339 | xhci_writel(xhci, field, db_addr); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 340 | /* Flush PCI posted writes - FIXME Matthew Wilcox says this |
| 341 | * isn't time-critical and we shouldn't make the CPU wait for |
| 342 | * the flush. |
| 343 | */ |
| 344 | xhci_readl(xhci, db_addr); |
| 345 | } |
| 346 | } |
| 347 | |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 348 | /* Ring the doorbell for any rings with pending URBs */ |
| 349 | static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci, |
| 350 | unsigned int slot_id, |
| 351 | unsigned int ep_index) |
| 352 | { |
| 353 | unsigned int stream_id; |
| 354 | struct xhci_virt_ep *ep; |
| 355 | |
| 356 | ep = &xhci->devs[slot_id]->eps[ep_index]; |
| 357 | |
| 358 | /* A ring has pending URBs if its TD list is not empty */ |
| 359 | if (!(ep->ep_state & EP_HAS_STREAMS)) { |
| 360 | if (!(list_empty(&ep->ring->td_list))) |
| 361 | ring_ep_doorbell(xhci, slot_id, ep_index, 0); |
| 362 | return; |
| 363 | } |
| 364 | |
| 365 | for (stream_id = 1; stream_id < ep->stream_info->num_streams; |
| 366 | stream_id++) { |
| 367 | struct xhci_stream_info *stream_info = ep->stream_info; |
| 368 | if (!list_empty(&stream_info->stream_rings[stream_id]->td_list)) |
| 369 | ring_ep_doorbell(xhci, slot_id, ep_index, stream_id); |
| 370 | } |
| 371 | } |
| 372 | |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 373 | /* |
| 374 | * Find the segment that trb is in. Start searching in start_seg. |
| 375 | * If we must move past a segment that has a link TRB with a toggle cycle state |
| 376 | * bit set, then we will toggle the value pointed at by cycle_state. |
| 377 | */ |
| 378 | static struct xhci_segment *find_trb_seg( |
| 379 | struct xhci_segment *start_seg, |
| 380 | union xhci_trb *trb, int *cycle_state) |
| 381 | { |
| 382 | struct xhci_segment *cur_seg = start_seg; |
| 383 | struct xhci_generic_trb *generic_trb; |
| 384 | |
| 385 | while (cur_seg->trbs > trb || |
| 386 | &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) { |
| 387 | generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic; |
Andiry Xu | 54b5acf | 2010-05-10 19:57:17 -0700 | [diff] [blame] | 388 | if ((generic_trb->field[3] & TRB_TYPE_BITMASK) == |
| 389 | TRB_TYPE(TRB_LINK) && |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 390 | (generic_trb->field[3] & LINK_TOGGLE)) |
| 391 | *cycle_state = ~(*cycle_state) & 0x1; |
| 392 | cur_seg = cur_seg->next; |
| 393 | if (cur_seg == start_seg) |
| 394 | /* Looped over the entire list. Oops! */ |
Randy Dunlap | 326b481 | 2010-04-19 08:53:50 -0700 | [diff] [blame] | 395 | return NULL; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 396 | } |
| 397 | return cur_seg; |
| 398 | } |
| 399 | |
Sarah Sharp | 021bff9 | 2010-07-29 22:12:20 -0700 | [diff] [blame] | 400 | |
| 401 | static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci, |
| 402 | unsigned int slot_id, unsigned int ep_index, |
| 403 | unsigned int stream_id) |
| 404 | { |
| 405 | struct xhci_virt_ep *ep; |
| 406 | |
| 407 | ep = &xhci->devs[slot_id]->eps[ep_index]; |
| 408 | /* Common case: no streams */ |
| 409 | if (!(ep->ep_state & EP_HAS_STREAMS)) |
| 410 | return ep->ring; |
| 411 | |
| 412 | if (stream_id == 0) { |
| 413 | xhci_warn(xhci, |
| 414 | "WARN: Slot ID %u, ep index %u has streams, " |
| 415 | "but URB has no stream ID.\n", |
| 416 | slot_id, ep_index); |
| 417 | return NULL; |
| 418 | } |
| 419 | |
| 420 | if (stream_id < ep->stream_info->num_streams) |
| 421 | return ep->stream_info->stream_rings[stream_id]; |
| 422 | |
| 423 | xhci_warn(xhci, |
| 424 | "WARN: Slot ID %u, ep index %u has " |
| 425 | "stream IDs 1 to %u allocated, " |
| 426 | "but stream ID %u is requested.\n", |
| 427 | slot_id, ep_index, |
| 428 | ep->stream_info->num_streams - 1, |
| 429 | stream_id); |
| 430 | return NULL; |
| 431 | } |
| 432 | |
| 433 | /* Get the right ring for the given URB. |
| 434 | * If the endpoint supports streams, boundary check the URB's stream ID. |
| 435 | * If the endpoint doesn't support streams, return the singular endpoint ring. |
| 436 | */ |
| 437 | static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci, |
| 438 | struct urb *urb) |
| 439 | { |
| 440 | return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id, |
| 441 | xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id); |
| 442 | } |
| 443 | |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 444 | /* |
| 445 | * Move the xHC's endpoint ring dequeue pointer past cur_td. |
| 446 | * Record the new state of the xHC's endpoint ring dequeue segment, |
| 447 | * dequeue pointer, and new consumer cycle state in state. |
| 448 | * Update our internal representation of the ring's dequeue pointer. |
| 449 | * |
| 450 | * We do this in three jumps: |
| 451 | * - First we update our new ring state to be the same as when the xHC stopped. |
| 452 | * - Then we traverse the ring to find the segment that contains |
| 453 | * the last TRB in the TD. We toggle the xHC's new cycle state when we pass |
| 454 | * any link TRBs with the toggle cycle bit set. |
| 455 | * - Finally we move the dequeue state one TRB further, toggling the cycle bit |
| 456 | * if we've moved it past a link TRB with the toggle cycle bit set. |
| 457 | */ |
Sarah Sharp | c92bcfa | 2009-07-27 12:05:21 -0700 | [diff] [blame] | 458 | void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 459 | unsigned int slot_id, unsigned int ep_index, |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 460 | unsigned int stream_id, struct xhci_td *cur_td, |
| 461 | struct xhci_dequeue_state *state) |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 462 | { |
| 463 | struct xhci_virt_device *dev = xhci->devs[slot_id]; |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 464 | struct xhci_ring *ep_ring; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 465 | struct xhci_generic_trb *trb; |
John Youn | d115b04 | 2009-07-27 12:05:15 -0700 | [diff] [blame] | 466 | struct xhci_ep_ctx *ep_ctx; |
Sarah Sharp | c92bcfa | 2009-07-27 12:05:21 -0700 | [diff] [blame] | 467 | dma_addr_t addr; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 468 | |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 469 | ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id, |
| 470 | ep_index, stream_id); |
| 471 | if (!ep_ring) { |
| 472 | xhci_warn(xhci, "WARN can't find new dequeue state " |
| 473 | "for invalid stream ID %u.\n", |
| 474 | stream_id); |
| 475 | return; |
| 476 | } |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 477 | state->new_cycle_state = 0; |
Sarah Sharp | c92bcfa | 2009-07-27 12:05:21 -0700 | [diff] [blame] | 478 | xhci_dbg(xhci, "Finding segment containing stopped TRB.\n"); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 479 | state->new_deq_seg = find_trb_seg(cur_td->start_seg, |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 480 | dev->eps[ep_index].stopped_trb, |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 481 | &state->new_cycle_state); |
| 482 | if (!state->new_deq_seg) |
| 483 | BUG(); |
| 484 | /* Dig out the cycle state saved by the xHC during the stop ep cmd */ |
Sarah Sharp | c92bcfa | 2009-07-27 12:05:21 -0700 | [diff] [blame] | 485 | xhci_dbg(xhci, "Finding endpoint context\n"); |
John Youn | d115b04 | 2009-07-27 12:05:15 -0700 | [diff] [blame] | 486 | ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); |
| 487 | state->new_cycle_state = 0x1 & ep_ctx->deq; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 488 | |
| 489 | state->new_deq_ptr = cur_td->last_trb; |
Sarah Sharp | c92bcfa | 2009-07-27 12:05:21 -0700 | [diff] [blame] | 490 | xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n"); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 491 | state->new_deq_seg = find_trb_seg(state->new_deq_seg, |
| 492 | state->new_deq_ptr, |
| 493 | &state->new_cycle_state); |
| 494 | if (!state->new_deq_seg) |
| 495 | BUG(); |
| 496 | |
| 497 | trb = &state->new_deq_ptr->generic; |
Andiry Xu | 54b5acf | 2010-05-10 19:57:17 -0700 | [diff] [blame] | 498 | if ((trb->field[3] & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK) && |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 499 | (trb->field[3] & LINK_TOGGLE)) |
| 500 | state->new_cycle_state = ~(state->new_cycle_state) & 0x1; |
| 501 | next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr); |
| 502 | |
| 503 | /* Don't update the ring cycle state for the producer (us). */ |
Sarah Sharp | c92bcfa | 2009-07-27 12:05:21 -0700 | [diff] [blame] | 504 | xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n", |
| 505 | state->new_deq_seg); |
| 506 | addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr); |
| 507 | xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n", |
| 508 | (unsigned long long) addr); |
| 509 | xhci_dbg(xhci, "Setting dequeue pointer in internal ring state.\n"); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 510 | ep_ring->dequeue = state->new_deq_ptr; |
| 511 | ep_ring->deq_seg = state->new_deq_seg; |
| 512 | } |
| 513 | |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 514 | static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 515 | struct xhci_td *cur_td) |
| 516 | { |
| 517 | struct xhci_segment *cur_seg; |
| 518 | union xhci_trb *cur_trb; |
| 519 | |
| 520 | for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb; |
| 521 | true; |
| 522 | next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { |
| 523 | if ((cur_trb->generic.field[3] & TRB_TYPE_BITMASK) == |
| 524 | TRB_TYPE(TRB_LINK)) { |
| 525 | /* Unchain any chained Link TRBs, but |
| 526 | * leave the pointers intact. |
| 527 | */ |
| 528 | cur_trb->generic.field[3] &= ~TRB_CHAIN; |
| 529 | xhci_dbg(xhci, "Cancel (unchain) link TRB\n"); |
Greg Kroah-Hartman | 700e205 | 2009-04-29 19:14:08 -0700 | [diff] [blame] | 530 | xhci_dbg(xhci, "Address = %p (0x%llx dma); " |
| 531 | "in seg %p (0x%llx dma)\n", |
| 532 | cur_trb, |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 533 | (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb), |
Greg Kroah-Hartman | 700e205 | 2009-04-29 19:14:08 -0700 | [diff] [blame] | 534 | cur_seg, |
| 535 | (unsigned long long)cur_seg->dma); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 536 | } else { |
| 537 | cur_trb->generic.field[0] = 0; |
| 538 | cur_trb->generic.field[1] = 0; |
| 539 | cur_trb->generic.field[2] = 0; |
| 540 | /* Preserve only the cycle bit of this TRB */ |
| 541 | cur_trb->generic.field[3] &= TRB_CYCLE; |
| 542 | cur_trb->generic.field[3] |= TRB_TYPE(TRB_TR_NOOP); |
Greg Kroah-Hartman | 700e205 | 2009-04-29 19:14:08 -0700 | [diff] [blame] | 543 | xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) " |
| 544 | "in seg %p (0x%llx dma)\n", |
| 545 | cur_trb, |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 546 | (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb), |
Greg Kroah-Hartman | 700e205 | 2009-04-29 19:14:08 -0700 | [diff] [blame] | 547 | cur_seg, |
| 548 | (unsigned long long)cur_seg->dma); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 549 | } |
| 550 | if (cur_trb == cur_td->last_trb) |
| 551 | break; |
| 552 | } |
| 553 | } |
| 554 | |
| 555 | static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id, |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 556 | unsigned int ep_index, unsigned int stream_id, |
| 557 | struct xhci_segment *deq_seg, |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 558 | union xhci_trb *deq_ptr, u32 cycle_state); |
| 559 | |
Sarah Sharp | c92bcfa | 2009-07-27 12:05:21 -0700 | [diff] [blame] | 560 | void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 561 | unsigned int slot_id, unsigned int ep_index, |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 562 | unsigned int stream_id, |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 563 | struct xhci_dequeue_state *deq_state) |
Sarah Sharp | c92bcfa | 2009-07-27 12:05:21 -0700 | [diff] [blame] | 564 | { |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 565 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; |
| 566 | |
Sarah Sharp | c92bcfa | 2009-07-27 12:05:21 -0700 | [diff] [blame] | 567 | xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), " |
| 568 | "new deq ptr = %p (0x%llx dma), new cycle = %u\n", |
| 569 | deq_state->new_deq_seg, |
| 570 | (unsigned long long)deq_state->new_deq_seg->dma, |
| 571 | deq_state->new_deq_ptr, |
| 572 | (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr), |
| 573 | deq_state->new_cycle_state); |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 574 | queue_set_tr_deq(xhci, slot_id, ep_index, stream_id, |
Sarah Sharp | c92bcfa | 2009-07-27 12:05:21 -0700 | [diff] [blame] | 575 | deq_state->new_deq_seg, |
| 576 | deq_state->new_deq_ptr, |
| 577 | (u32) deq_state->new_cycle_state); |
| 578 | /* Stop the TD queueing code from ringing the doorbell until |
| 579 | * this command completes. The HC won't set the dequeue pointer |
| 580 | * if the ring is running, and ringing the doorbell starts the |
| 581 | * ring running. |
| 582 | */ |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 583 | ep->ep_state |= SET_DEQ_PENDING; |
Sarah Sharp | c92bcfa | 2009-07-27 12:05:21 -0700 | [diff] [blame] | 584 | } |
| 585 | |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 586 | static inline void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci, |
| 587 | struct xhci_virt_ep *ep) |
| 588 | { |
| 589 | ep->ep_state &= ~EP_HALT_PENDING; |
| 590 | /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the |
| 591 | * timer is running on another CPU, we don't decrement stop_cmds_pending |
| 592 | * (since we didn't successfully stop the watchdog timer). |
| 593 | */ |
| 594 | if (del_timer(&ep->stop_cmd_timer)) |
| 595 | ep->stop_cmds_pending--; |
| 596 | } |
| 597 | |
| 598 | /* Must be called with xhci->lock held in interrupt context */ |
| 599 | static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci, |
| 600 | struct xhci_td *cur_td, int status, char *adjective) |
| 601 | { |
| 602 | struct usb_hcd *hcd = xhci_to_hcd(xhci); |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 603 | struct urb *urb; |
| 604 | struct urb_priv *urb_priv; |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 605 | |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 606 | urb = cur_td->urb; |
| 607 | urb_priv = urb->hcpriv; |
| 608 | urb_priv->td_cnt++; |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 609 | |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 610 | /* Only giveback urb when this is the last td in urb */ |
| 611 | if (urb_priv->td_cnt == urb_priv->length) { |
| 612 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
| 613 | xhci_dbg(xhci, "Giveback %s URB %p\n", adjective, urb); |
| 614 | |
| 615 | spin_unlock(&xhci->lock); |
| 616 | usb_hcd_giveback_urb(hcd, urb, status); |
| 617 | xhci_urb_free_priv(xhci, urb_priv); |
| 618 | spin_lock(&xhci->lock); |
| 619 | xhci_dbg(xhci, "%s URB given back\n", adjective); |
| 620 | } |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 621 | } |
| 622 | |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 623 | /* |
| 624 | * When we get a command completion for a Stop Endpoint Command, we need to |
| 625 | * unlink any cancelled TDs from the ring. There are two ways to do that: |
| 626 | * |
| 627 | * 1. If the HW was in the middle of processing the TD that needs to be |
| 628 | * cancelled, then we must move the ring's dequeue pointer past the last TRB |
| 629 | * in the TD with a Set Dequeue Pointer Command. |
| 630 | * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain |
| 631 | * bit cleared) so that the HW will skip over them. |
| 632 | */ |
| 633 | static void handle_stopped_endpoint(struct xhci_hcd *xhci, |
| 634 | union xhci_trb *trb) |
| 635 | { |
| 636 | unsigned int slot_id; |
| 637 | unsigned int ep_index; |
| 638 | struct xhci_ring *ep_ring; |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 639 | struct xhci_virt_ep *ep; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 640 | struct list_head *entry; |
Randy Dunlap | 326b481 | 2010-04-19 08:53:50 -0700 | [diff] [blame] | 641 | struct xhci_td *cur_td = NULL; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 642 | struct xhci_td *last_unlinked_td; |
| 643 | |
Sarah Sharp | c92bcfa | 2009-07-27 12:05:21 -0700 | [diff] [blame] | 644 | struct xhci_dequeue_state deq_state; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 645 | |
| 646 | memset(&deq_state, 0, sizeof(deq_state)); |
| 647 | slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]); |
| 648 | ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]); |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 649 | ep = &xhci->devs[slot_id]->eps[ep_index]; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 650 | |
Sarah Sharp | 678539c | 2009-10-27 10:55:52 -0700 | [diff] [blame] | 651 | if (list_empty(&ep->cancelled_td_list)) { |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 652 | xhci_stop_watchdog_timer_in_irq(xhci, ep); |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 653 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 654 | return; |
Sarah Sharp | 678539c | 2009-10-27 10:55:52 -0700 | [diff] [blame] | 655 | } |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 656 | |
| 657 | /* Fix up the ep ring first, so HW stops executing cancelled TDs. |
| 658 | * We have the xHCI lock, so nothing can modify this list until we drop |
| 659 | * it. We're also in the event handler, so we can't get re-interrupted |
| 660 | * if another Stop Endpoint command completes |
| 661 | */ |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 662 | list_for_each(entry, &ep->cancelled_td_list) { |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 663 | cur_td = list_entry(entry, struct xhci_td, cancelled_td_list); |
Greg Kroah-Hartman | 700e205 | 2009-04-29 19:14:08 -0700 | [diff] [blame] | 664 | xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n", |
| 665 | cur_td->first_trb, |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 666 | (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb)); |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 667 | ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb); |
| 668 | if (!ep_ring) { |
| 669 | /* This shouldn't happen unless a driver is mucking |
| 670 | * with the stream ID after submission. This will |
| 671 | * leave the TD on the hardware ring, and the hardware |
| 672 | * will try to execute it, and may access a buffer |
| 673 | * that has already been freed. In the best case, the |
| 674 | * hardware will execute it, and the event handler will |
| 675 | * ignore the completion event for that TD, since it was |
| 676 | * removed from the td_list for that endpoint. In |
| 677 | * short, don't muck with the stream ID after |
| 678 | * submission. |
| 679 | */ |
| 680 | xhci_warn(xhci, "WARN Cancelled URB %p " |
| 681 | "has invalid stream ID %u.\n", |
| 682 | cur_td->urb, |
| 683 | cur_td->urb->stream_id); |
| 684 | goto remove_finished_td; |
| 685 | } |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 686 | /* |
| 687 | * If we stopped on the TD we need to cancel, then we have to |
| 688 | * move the xHC endpoint ring dequeue pointer past this TD. |
| 689 | */ |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 690 | if (cur_td == ep->stopped_td) |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 691 | xhci_find_new_dequeue_state(xhci, slot_id, ep_index, |
| 692 | cur_td->urb->stream_id, |
| 693 | cur_td, &deq_state); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 694 | else |
| 695 | td_to_noop(xhci, ep_ring, cur_td); |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 696 | remove_finished_td: |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 697 | /* |
| 698 | * The event handler won't see a completion for this TD anymore, |
| 699 | * so remove it from the endpoint ring's TD list. Keep it in |
| 700 | * the cancelled TD list for URB completion later. |
| 701 | */ |
| 702 | list_del(&cur_td->td_list); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 703 | } |
| 704 | last_unlinked_td = cur_td; |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 705 | xhci_stop_watchdog_timer_in_irq(xhci, ep); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 706 | |
| 707 | /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */ |
| 708 | if (deq_state.new_deq_ptr && deq_state.new_deq_seg) { |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 709 | xhci_queue_new_dequeue_state(xhci, |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 710 | slot_id, ep_index, |
| 711 | ep->stopped_td->urb->stream_id, |
| 712 | &deq_state); |
Sarah Sharp | ac9d8fe | 2009-08-07 14:04:55 -0700 | [diff] [blame] | 713 | xhci_ring_cmd_db(xhci); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 714 | } else { |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 715 | /* Otherwise ring the doorbell(s) to restart queued transfers */ |
| 716 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 717 | } |
Sarah Sharp | 1624ae1 | 2010-05-06 13:40:08 -0700 | [diff] [blame] | 718 | ep->stopped_td = NULL; |
| 719 | ep->stopped_trb = NULL; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 720 | |
| 721 | /* |
| 722 | * Drop the lock and complete the URBs in the cancelled TD list. |
| 723 | * New TDs to be cancelled might be added to the end of the list before |
| 724 | * we can complete all the URBs for the TDs we already unlinked. |
| 725 | * So stop when we've completed the URB for the last TD we unlinked. |
| 726 | */ |
| 727 | do { |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 728 | cur_td = list_entry(ep->cancelled_td_list.next, |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 729 | struct xhci_td, cancelled_td_list); |
| 730 | list_del(&cur_td->cancelled_td_list); |
| 731 | |
| 732 | /* Clean up the cancelled URB */ |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 733 | /* Doesn't matter what we pass for status, since the core will |
| 734 | * just overwrite it (because the URB has been unlinked). |
| 735 | */ |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 736 | xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled"); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 737 | |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 738 | /* Stop processing the cancelled list if the watchdog timer is |
| 739 | * running. |
| 740 | */ |
| 741 | if (xhci->xhc_state & XHCI_STATE_DYING) |
| 742 | return; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 743 | } while (cur_td != last_unlinked_td); |
| 744 | |
| 745 | /* Return to the event handler with xhci->lock re-acquired */ |
| 746 | } |
| 747 | |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 748 | /* Watchdog timer function for when a stop endpoint command fails to complete. |
| 749 | * In this case, we assume the host controller is broken or dying or dead. The |
| 750 | * host may still be completing some other events, so we have to be careful to |
| 751 | * let the event ring handler and the URB dequeueing/enqueueing functions know |
| 752 | * through xhci->state. |
| 753 | * |
| 754 | * The timer may also fire if the host takes a very long time to respond to the |
| 755 | * command, and the stop endpoint command completion handler cannot delete the |
| 756 | * timer before the timer function is called. Another endpoint cancellation may |
| 757 | * sneak in before the timer function can grab the lock, and that may queue |
| 758 | * another stop endpoint command and add the timer back. So we cannot use a |
| 759 | * simple flag to say whether there is a pending stop endpoint command for a |
| 760 | * particular endpoint. |
| 761 | * |
| 762 | * Instead we use a combination of that flag and a counter for the number of |
| 763 | * pending stop endpoint commands. If the timer is the tail end of the last |
| 764 | * stop endpoint command, and the endpoint's command is still pending, we assume |
| 765 | * the host is dying. |
| 766 | */ |
| 767 | void xhci_stop_endpoint_command_watchdog(unsigned long arg) |
| 768 | { |
| 769 | struct xhci_hcd *xhci; |
| 770 | struct xhci_virt_ep *ep; |
| 771 | struct xhci_virt_ep *temp_ep; |
| 772 | struct xhci_ring *ring; |
| 773 | struct xhci_td *cur_td; |
| 774 | int ret, i, j; |
| 775 | |
| 776 | ep = (struct xhci_virt_ep *) arg; |
| 777 | xhci = ep->xhci; |
| 778 | |
| 779 | spin_lock(&xhci->lock); |
| 780 | |
| 781 | ep->stop_cmds_pending--; |
| 782 | if (xhci->xhc_state & XHCI_STATE_DYING) { |
| 783 | xhci_dbg(xhci, "Stop EP timer ran, but another timer marked " |
| 784 | "xHCI as DYING, exiting.\n"); |
| 785 | spin_unlock(&xhci->lock); |
| 786 | return; |
| 787 | } |
| 788 | if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) { |
| 789 | xhci_dbg(xhci, "Stop EP timer ran, but no command pending, " |
| 790 | "exiting.\n"); |
| 791 | spin_unlock(&xhci->lock); |
| 792 | return; |
| 793 | } |
| 794 | |
| 795 | xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n"); |
| 796 | xhci_warn(xhci, "Assuming host is dying, halting host.\n"); |
| 797 | /* Oops, HC is dead or dying or at least not responding to the stop |
| 798 | * endpoint command. |
| 799 | */ |
| 800 | xhci->xhc_state |= XHCI_STATE_DYING; |
| 801 | /* Disable interrupts from the host controller and start halting it */ |
| 802 | xhci_quiesce(xhci); |
| 803 | spin_unlock(&xhci->lock); |
| 804 | |
| 805 | ret = xhci_halt(xhci); |
| 806 | |
| 807 | spin_lock(&xhci->lock); |
| 808 | if (ret < 0) { |
| 809 | /* This is bad; the host is not responding to commands and it's |
| 810 | * not allowing itself to be halted. At least interrupts are |
| 811 | * disabled, so we can set HC_STATE_HALT and notify the |
| 812 | * USB core. But if we call usb_hc_died(), it will attempt to |
| 813 | * disconnect all device drivers under this host. Those |
| 814 | * disconnect() methods will wait for all URBs to be unlinked, |
| 815 | * so we must complete them. |
| 816 | */ |
| 817 | xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n"); |
| 818 | xhci_warn(xhci, "Completing active URBs anyway.\n"); |
| 819 | /* We could turn all TDs on the rings to no-ops. This won't |
| 820 | * help if the host has cached part of the ring, and is slow if |
| 821 | * we want to preserve the cycle bit. Skip it and hope the host |
| 822 | * doesn't touch the memory. |
| 823 | */ |
| 824 | } |
| 825 | for (i = 0; i < MAX_HC_SLOTS; i++) { |
| 826 | if (!xhci->devs[i]) |
| 827 | continue; |
| 828 | for (j = 0; j < 31; j++) { |
| 829 | temp_ep = &xhci->devs[i]->eps[j]; |
| 830 | ring = temp_ep->ring; |
| 831 | if (!ring) |
| 832 | continue; |
| 833 | xhci_dbg(xhci, "Killing URBs for slot ID %u, " |
| 834 | "ep index %u\n", i, j); |
| 835 | while (!list_empty(&ring->td_list)) { |
| 836 | cur_td = list_first_entry(&ring->td_list, |
| 837 | struct xhci_td, |
| 838 | td_list); |
| 839 | list_del(&cur_td->td_list); |
| 840 | if (!list_empty(&cur_td->cancelled_td_list)) |
| 841 | list_del(&cur_td->cancelled_td_list); |
| 842 | xhci_giveback_urb_in_irq(xhci, cur_td, |
| 843 | -ESHUTDOWN, "killed"); |
| 844 | } |
| 845 | while (!list_empty(&temp_ep->cancelled_td_list)) { |
| 846 | cur_td = list_first_entry( |
| 847 | &temp_ep->cancelled_td_list, |
| 848 | struct xhci_td, |
| 849 | cancelled_td_list); |
| 850 | list_del(&cur_td->cancelled_td_list); |
| 851 | xhci_giveback_urb_in_irq(xhci, cur_td, |
| 852 | -ESHUTDOWN, "killed"); |
| 853 | } |
| 854 | } |
| 855 | } |
| 856 | spin_unlock(&xhci->lock); |
| 857 | xhci_to_hcd(xhci)->state = HC_STATE_HALT; |
| 858 | xhci_dbg(xhci, "Calling usb_hc_died()\n"); |
| 859 | usb_hc_died(xhci_to_hcd(xhci)); |
| 860 | xhci_dbg(xhci, "xHCI host controller is dead.\n"); |
| 861 | } |
| 862 | |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 863 | /* |
| 864 | * When we get a completion for a Set Transfer Ring Dequeue Pointer command, |
| 865 | * we need to clear the set deq pending flag in the endpoint ring state, so that |
| 866 | * the TD queueing code can ring the doorbell again. We also need to ring the |
| 867 | * endpoint doorbell to restart the ring, but only if there aren't more |
| 868 | * cancellations pending. |
| 869 | */ |
| 870 | static void handle_set_deq_completion(struct xhci_hcd *xhci, |
| 871 | struct xhci_event_cmd *event, |
| 872 | union xhci_trb *trb) |
| 873 | { |
| 874 | unsigned int slot_id; |
| 875 | unsigned int ep_index; |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 876 | unsigned int stream_id; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 877 | struct xhci_ring *ep_ring; |
| 878 | struct xhci_virt_device *dev; |
John Youn | d115b04 | 2009-07-27 12:05:15 -0700 | [diff] [blame] | 879 | struct xhci_ep_ctx *ep_ctx; |
| 880 | struct xhci_slot_ctx *slot_ctx; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 881 | |
| 882 | slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]); |
| 883 | ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]); |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 884 | stream_id = TRB_TO_STREAM_ID(trb->generic.field[2]); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 885 | dev = xhci->devs[slot_id]; |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 886 | |
| 887 | ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id); |
| 888 | if (!ep_ring) { |
| 889 | xhci_warn(xhci, "WARN Set TR deq ptr command for " |
| 890 | "freed stream ID %u\n", |
| 891 | stream_id); |
| 892 | /* XXX: Harmless??? */ |
| 893 | dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING; |
| 894 | return; |
| 895 | } |
| 896 | |
John Youn | d115b04 | 2009-07-27 12:05:15 -0700 | [diff] [blame] | 897 | ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); |
| 898 | slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 899 | |
| 900 | if (GET_COMP_CODE(event->status) != COMP_SUCCESS) { |
| 901 | unsigned int ep_state; |
| 902 | unsigned int slot_state; |
| 903 | |
| 904 | switch (GET_COMP_CODE(event->status)) { |
| 905 | case COMP_TRB_ERR: |
| 906 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because " |
| 907 | "of stream ID configuration\n"); |
| 908 | break; |
| 909 | case COMP_CTX_STATE: |
| 910 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due " |
| 911 | "to incorrect slot or ep state.\n"); |
John Youn | d115b04 | 2009-07-27 12:05:15 -0700 | [diff] [blame] | 912 | ep_state = ep_ctx->ep_info; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 913 | ep_state &= EP_STATE_MASK; |
John Youn | d115b04 | 2009-07-27 12:05:15 -0700 | [diff] [blame] | 914 | slot_state = slot_ctx->dev_state; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 915 | slot_state = GET_SLOT_STATE(slot_state); |
| 916 | xhci_dbg(xhci, "Slot state = %u, EP state = %u\n", |
| 917 | slot_state, ep_state); |
| 918 | break; |
| 919 | case COMP_EBADSLT: |
| 920 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because " |
| 921 | "slot %u was not enabled.\n", slot_id); |
| 922 | break; |
| 923 | default: |
| 924 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown " |
| 925 | "completion code of %u.\n", |
| 926 | GET_COMP_CODE(event->status)); |
| 927 | break; |
| 928 | } |
| 929 | /* OK what do we do now? The endpoint state is hosed, and we |
| 930 | * should never get to this point if the synchronization between |
| 931 | * queueing, and endpoint state are correct. This might happen |
| 932 | * if the device gets disconnected after we've finished |
| 933 | * cancelling URBs, which might not be an error... |
| 934 | */ |
| 935 | } else { |
Sarah Sharp | 8e595a5 | 2009-07-27 12:03:31 -0700 | [diff] [blame] | 936 | xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n", |
John Youn | d115b04 | 2009-07-27 12:05:15 -0700 | [diff] [blame] | 937 | ep_ctx->deq); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 938 | } |
| 939 | |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 940 | dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING; |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 941 | /* Restart any rings with pending URBs */ |
| 942 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 943 | } |
| 944 | |
Sarah Sharp | a1587d9 | 2009-07-27 12:03:15 -0700 | [diff] [blame] | 945 | static void handle_reset_ep_completion(struct xhci_hcd *xhci, |
| 946 | struct xhci_event_cmd *event, |
| 947 | union xhci_trb *trb) |
| 948 | { |
| 949 | int slot_id; |
| 950 | unsigned int ep_index; |
| 951 | |
| 952 | slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]); |
| 953 | ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]); |
| 954 | /* This command will only fail if the endpoint wasn't halted, |
| 955 | * but we don't care. |
| 956 | */ |
| 957 | xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n", |
| 958 | (unsigned int) GET_COMP_CODE(event->status)); |
| 959 | |
Sarah Sharp | ac9d8fe | 2009-08-07 14:04:55 -0700 | [diff] [blame] | 960 | /* HW with the reset endpoint quirk needs to have a configure endpoint |
| 961 | * command complete before the endpoint can be used. Queue that here |
| 962 | * because the HW can't handle two commands being queued in a row. |
| 963 | */ |
| 964 | if (xhci->quirks & XHCI_RESET_EP_QUIRK) { |
| 965 | xhci_dbg(xhci, "Queueing configure endpoint command\n"); |
| 966 | xhci_queue_configure_endpoint(xhci, |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 967 | xhci->devs[slot_id]->in_ctx->dma, slot_id, |
| 968 | false); |
Sarah Sharp | ac9d8fe | 2009-08-07 14:04:55 -0700 | [diff] [blame] | 969 | xhci_ring_cmd_db(xhci); |
| 970 | } else { |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 971 | /* Clear our internal halted state and restart the ring(s) */ |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 972 | xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED; |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 973 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); |
Sarah Sharp | ac9d8fe | 2009-08-07 14:04:55 -0700 | [diff] [blame] | 974 | } |
Sarah Sharp | a1587d9 | 2009-07-27 12:03:15 -0700 | [diff] [blame] | 975 | } |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 976 | |
Sarah Sharp | a50c8aa | 2009-09-04 10:53:15 -0700 | [diff] [blame] | 977 | /* Check to see if a command in the device's command queue matches this one. |
| 978 | * Signal the completion or free the command, and return 1. Return 0 if the |
| 979 | * completed command isn't at the head of the command list. |
| 980 | */ |
| 981 | static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci, |
| 982 | struct xhci_virt_device *virt_dev, |
| 983 | struct xhci_event_cmd *event) |
| 984 | { |
| 985 | struct xhci_command *command; |
| 986 | |
| 987 | if (list_empty(&virt_dev->cmd_list)) |
| 988 | return 0; |
| 989 | |
| 990 | command = list_entry(virt_dev->cmd_list.next, |
| 991 | struct xhci_command, cmd_list); |
| 992 | if (xhci->cmd_ring->dequeue != command->command_trb) |
| 993 | return 0; |
| 994 | |
| 995 | command->status = |
| 996 | GET_COMP_CODE(event->status); |
| 997 | list_del(&command->cmd_list); |
| 998 | if (command->completion) |
| 999 | complete(command->completion); |
| 1000 | else |
| 1001 | xhci_free_command(xhci, command); |
| 1002 | return 1; |
| 1003 | } |
| 1004 | |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 1005 | static void handle_cmd_completion(struct xhci_hcd *xhci, |
| 1006 | struct xhci_event_cmd *event) |
| 1007 | { |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 1008 | int slot_id = TRB_TO_SLOT_ID(event->flags); |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 1009 | u64 cmd_dma; |
| 1010 | dma_addr_t cmd_dequeue_dma; |
Sarah Sharp | ac9d8fe | 2009-08-07 14:04:55 -0700 | [diff] [blame] | 1011 | struct xhci_input_control_ctx *ctrl_ctx; |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 1012 | struct xhci_virt_device *virt_dev; |
Sarah Sharp | ac9d8fe | 2009-08-07 14:04:55 -0700 | [diff] [blame] | 1013 | unsigned int ep_index; |
| 1014 | struct xhci_ring *ep_ring; |
| 1015 | unsigned int ep_state; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 1016 | |
Sarah Sharp | 8e595a5 | 2009-07-27 12:03:31 -0700 | [diff] [blame] | 1017 | cmd_dma = event->cmd_trb; |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 1018 | cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg, |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 1019 | xhci->cmd_ring->dequeue); |
| 1020 | /* Is the command ring deq ptr out of sync with the deq seg ptr? */ |
| 1021 | if (cmd_dequeue_dma == 0) { |
| 1022 | xhci->error_bitmask |= 1 << 4; |
| 1023 | return; |
| 1024 | } |
| 1025 | /* Does the DMA address match our internal dequeue pointer address? */ |
| 1026 | if (cmd_dma != (u64) cmd_dequeue_dma) { |
| 1027 | xhci->error_bitmask |= 1 << 5; |
| 1028 | return; |
| 1029 | } |
| 1030 | switch (xhci->cmd_ring->dequeue->generic.field[3] & TRB_TYPE_BITMASK) { |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 1031 | case TRB_TYPE(TRB_ENABLE_SLOT): |
| 1032 | if (GET_COMP_CODE(event->status) == COMP_SUCCESS) |
| 1033 | xhci->slot_id = slot_id; |
| 1034 | else |
| 1035 | xhci->slot_id = 0; |
| 1036 | complete(&xhci->addr_dev); |
| 1037 | break; |
| 1038 | case TRB_TYPE(TRB_DISABLE_SLOT): |
| 1039 | if (xhci->devs[slot_id]) |
| 1040 | xhci_free_virt_device(xhci, slot_id); |
| 1041 | break; |
Sarah Sharp | f94e0186 | 2009-04-27 19:58:38 -0700 | [diff] [blame] | 1042 | case TRB_TYPE(TRB_CONFIG_EP): |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 1043 | virt_dev = xhci->devs[slot_id]; |
Sarah Sharp | a50c8aa | 2009-09-04 10:53:15 -0700 | [diff] [blame] | 1044 | if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event)) |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 1045 | break; |
Sarah Sharp | ac9d8fe | 2009-08-07 14:04:55 -0700 | [diff] [blame] | 1046 | /* |
| 1047 | * Configure endpoint commands can come from the USB core |
| 1048 | * configuration or alt setting changes, or because the HW |
| 1049 | * needed an extra configure endpoint command after a reset |
Sarah Sharp | 8df75f4 | 2010-04-02 15:34:16 -0700 | [diff] [blame] | 1050 | * endpoint command or streams were being configured. |
| 1051 | * If the command was for a halted endpoint, the xHCI driver |
| 1052 | * is not waiting on the configure endpoint command. |
Sarah Sharp | ac9d8fe | 2009-08-07 14:04:55 -0700 | [diff] [blame] | 1053 | */ |
| 1054 | ctrl_ctx = xhci_get_input_control_ctx(xhci, |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 1055 | virt_dev->in_ctx); |
Sarah Sharp | ac9d8fe | 2009-08-07 14:04:55 -0700 | [diff] [blame] | 1056 | /* Input ctx add_flags are the endpoint index plus one */ |
| 1057 | ep_index = xhci_last_valid_endpoint(ctrl_ctx->add_flags) - 1; |
Sarah Sharp | 06df572 | 2009-12-03 09:44:31 -0800 | [diff] [blame] | 1058 | /* A usb_set_interface() call directly after clearing a halted |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 1059 | * condition may race on this quirky hardware. Not worth |
| 1060 | * worrying about, since this is prototype hardware. Not sure |
| 1061 | * if this will work for streams, but streams support was |
| 1062 | * untested on this prototype. |
Sarah Sharp | 06df572 | 2009-12-03 09:44:31 -0800 | [diff] [blame] | 1063 | */ |
Sarah Sharp | ac9d8fe | 2009-08-07 14:04:55 -0700 | [diff] [blame] | 1064 | if (xhci->quirks & XHCI_RESET_EP_QUIRK && |
Sarah Sharp | 06df572 | 2009-12-03 09:44:31 -0800 | [diff] [blame] | 1065 | ep_index != (unsigned int) -1 && |
| 1066 | ctrl_ctx->add_flags - SLOT_FLAG == |
| 1067 | ctrl_ctx->drop_flags) { |
| 1068 | ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; |
| 1069 | ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state; |
| 1070 | if (!(ep_state & EP_HALTED)) |
| 1071 | goto bandwidth_change; |
| 1072 | xhci_dbg(xhci, "Completed config ep cmd - " |
| 1073 | "last ep index = %d, state = %d\n", |
| 1074 | ep_index, ep_state); |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 1075 | /* Clear internal halted state and restart ring(s) */ |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 1076 | xhci->devs[slot_id]->eps[ep_index].ep_state &= |
Sarah Sharp | ac9d8fe | 2009-08-07 14:04:55 -0700 | [diff] [blame] | 1077 | ~EP_HALTED; |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 1078 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); |
Sarah Sharp | 06df572 | 2009-12-03 09:44:31 -0800 | [diff] [blame] | 1079 | break; |
Sarah Sharp | ac9d8fe | 2009-08-07 14:04:55 -0700 | [diff] [blame] | 1080 | } |
Sarah Sharp | 06df572 | 2009-12-03 09:44:31 -0800 | [diff] [blame] | 1081 | bandwidth_change: |
| 1082 | xhci_dbg(xhci, "Completed config ep cmd\n"); |
| 1083 | xhci->devs[slot_id]->cmd_status = |
| 1084 | GET_COMP_CODE(event->status); |
| 1085 | complete(&xhci->devs[slot_id]->cmd_completion); |
Sarah Sharp | f94e0186 | 2009-04-27 19:58:38 -0700 | [diff] [blame] | 1086 | break; |
Sarah Sharp | 2d3f1fa | 2009-08-07 14:04:49 -0700 | [diff] [blame] | 1087 | case TRB_TYPE(TRB_EVAL_CONTEXT): |
Sarah Sharp | ac1c1b7 | 2009-09-04 10:53:20 -0700 | [diff] [blame] | 1088 | virt_dev = xhci->devs[slot_id]; |
| 1089 | if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event)) |
| 1090 | break; |
Sarah Sharp | 2d3f1fa | 2009-08-07 14:04:49 -0700 | [diff] [blame] | 1091 | xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status); |
| 1092 | complete(&xhci->devs[slot_id]->cmd_completion); |
| 1093 | break; |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 1094 | case TRB_TYPE(TRB_ADDR_DEV): |
| 1095 | xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status); |
| 1096 | complete(&xhci->addr_dev); |
| 1097 | break; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 1098 | case TRB_TYPE(TRB_STOP_RING): |
| 1099 | handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue); |
| 1100 | break; |
| 1101 | case TRB_TYPE(TRB_SET_DEQ): |
| 1102 | handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue); |
| 1103 | break; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 1104 | case TRB_TYPE(TRB_CMD_NOOP): |
| 1105 | ++xhci->noops_handled; |
| 1106 | break; |
Sarah Sharp | a1587d9 | 2009-07-27 12:03:15 -0700 | [diff] [blame] | 1107 | case TRB_TYPE(TRB_RESET_EP): |
| 1108 | handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue); |
| 1109 | break; |
Sarah Sharp | 2a8f82c | 2009-12-09 15:59:13 -0800 | [diff] [blame] | 1110 | case TRB_TYPE(TRB_RESET_DEV): |
| 1111 | xhci_dbg(xhci, "Completed reset device command.\n"); |
| 1112 | slot_id = TRB_TO_SLOT_ID( |
| 1113 | xhci->cmd_ring->dequeue->generic.field[3]); |
| 1114 | virt_dev = xhci->devs[slot_id]; |
| 1115 | if (virt_dev) |
| 1116 | handle_cmd_in_cmd_wait_list(xhci, virt_dev, event); |
| 1117 | else |
| 1118 | xhci_warn(xhci, "Reset device command completion " |
| 1119 | "for disabled slot %u\n", slot_id); |
| 1120 | break; |
Sarah Sharp | 0238634 | 2010-05-24 13:25:28 -0700 | [diff] [blame] | 1121 | case TRB_TYPE(TRB_NEC_GET_FW): |
| 1122 | if (!(xhci->quirks & XHCI_NEC_HOST)) { |
| 1123 | xhci->error_bitmask |= 1 << 6; |
| 1124 | break; |
| 1125 | } |
| 1126 | xhci_dbg(xhci, "NEC firmware version %2x.%02x\n", |
| 1127 | NEC_FW_MAJOR(event->status), |
| 1128 | NEC_FW_MINOR(event->status)); |
| 1129 | break; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 1130 | default: |
| 1131 | /* Skip over unknown commands on the event ring */ |
| 1132 | xhci->error_bitmask |= 1 << 6; |
| 1133 | break; |
| 1134 | } |
| 1135 | inc_deq(xhci, xhci->cmd_ring, false); |
| 1136 | } |
| 1137 | |
Sarah Sharp | 0238634 | 2010-05-24 13:25:28 -0700 | [diff] [blame] | 1138 | static void handle_vendor_event(struct xhci_hcd *xhci, |
| 1139 | union xhci_trb *event) |
| 1140 | { |
| 1141 | u32 trb_type; |
| 1142 | |
| 1143 | trb_type = TRB_FIELD_TO_TYPE(event->generic.field[3]); |
| 1144 | xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type); |
| 1145 | if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST)) |
| 1146 | handle_cmd_completion(xhci, &event->event_cmd); |
| 1147 | } |
| 1148 | |
Sarah Sharp | 0f2a793 | 2009-04-27 19:57:12 -0700 | [diff] [blame] | 1149 | static void handle_port_status(struct xhci_hcd *xhci, |
| 1150 | union xhci_trb *event) |
| 1151 | { |
| 1152 | u32 port_id; |
| 1153 | |
| 1154 | /* Port status change events always have a successful completion code */ |
| 1155 | if (GET_COMP_CODE(event->generic.field[2]) != COMP_SUCCESS) { |
| 1156 | xhci_warn(xhci, "WARN: xHC returned failed port status event\n"); |
| 1157 | xhci->error_bitmask |= 1 << 8; |
| 1158 | } |
| 1159 | /* FIXME: core doesn't care about all port link state changes yet */ |
| 1160 | port_id = GET_PORT_ID(event->generic.field[0]); |
| 1161 | xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id); |
| 1162 | |
| 1163 | /* Update event ring dequeue pointer before dropping the lock */ |
| 1164 | inc_deq(xhci, xhci->event_ring, true); |
Sarah Sharp | 0f2a793 | 2009-04-27 19:57:12 -0700 | [diff] [blame] | 1165 | |
| 1166 | spin_unlock(&xhci->lock); |
| 1167 | /* Pass this up to the core */ |
| 1168 | usb_hcd_poll_rh_status(xhci_to_hcd(xhci)); |
| 1169 | spin_lock(&xhci->lock); |
| 1170 | } |
| 1171 | |
| 1172 | /* |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1173 | * This TD is defined by the TRBs starting at start_trb in start_seg and ending |
| 1174 | * at end_trb, which may be in another segment. If the suspect DMA address is a |
| 1175 | * TRB in this TD, this function returns that TRB's segment. Otherwise it |
| 1176 | * returns 0. |
| 1177 | */ |
Sarah Sharp | 6648f29 | 2009-11-09 13:35:23 -0800 | [diff] [blame] | 1178 | struct xhci_segment *trb_in_td(struct xhci_segment *start_seg, |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1179 | union xhci_trb *start_trb, |
| 1180 | union xhci_trb *end_trb, |
| 1181 | dma_addr_t suspect_dma) |
| 1182 | { |
| 1183 | dma_addr_t start_dma; |
| 1184 | dma_addr_t end_seg_dma; |
| 1185 | dma_addr_t end_trb_dma; |
| 1186 | struct xhci_segment *cur_seg; |
| 1187 | |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 1188 | start_dma = xhci_trb_virt_to_dma(start_seg, start_trb); |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1189 | cur_seg = start_seg; |
| 1190 | |
| 1191 | do { |
Sarah Sharp | 2fa88da | 2009-11-03 22:02:24 -0800 | [diff] [blame] | 1192 | if (start_dma == 0) |
Randy Dunlap | 326b481 | 2010-04-19 08:53:50 -0700 | [diff] [blame] | 1193 | return NULL; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 1194 | /* We may get an event for a Link TRB in the middle of a TD */ |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 1195 | end_seg_dma = xhci_trb_virt_to_dma(cur_seg, |
Sarah Sharp | 2fa88da | 2009-11-03 22:02:24 -0800 | [diff] [blame] | 1196 | &cur_seg->trbs[TRBS_PER_SEGMENT - 1]); |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1197 | /* If the end TRB isn't in this segment, this is set to 0 */ |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 1198 | end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb); |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1199 | |
| 1200 | if (end_trb_dma > 0) { |
| 1201 | /* The end TRB is in this segment, so suspect should be here */ |
| 1202 | if (start_dma <= end_trb_dma) { |
| 1203 | if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma) |
| 1204 | return cur_seg; |
| 1205 | } else { |
| 1206 | /* Case for one segment with |
| 1207 | * a TD wrapped around to the top |
| 1208 | */ |
| 1209 | if ((suspect_dma >= start_dma && |
| 1210 | suspect_dma <= end_seg_dma) || |
| 1211 | (suspect_dma >= cur_seg->dma && |
| 1212 | suspect_dma <= end_trb_dma)) |
| 1213 | return cur_seg; |
| 1214 | } |
Randy Dunlap | 326b481 | 2010-04-19 08:53:50 -0700 | [diff] [blame] | 1215 | return NULL; |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1216 | } else { |
| 1217 | /* Might still be somewhere in this segment */ |
| 1218 | if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma) |
| 1219 | return cur_seg; |
| 1220 | } |
| 1221 | cur_seg = cur_seg->next; |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 1222 | start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]); |
Sarah Sharp | 2fa88da | 2009-11-03 22:02:24 -0800 | [diff] [blame] | 1223 | } while (cur_seg != start_seg); |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1224 | |
Randy Dunlap | 326b481 | 2010-04-19 08:53:50 -0700 | [diff] [blame] | 1225 | return NULL; |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1226 | } |
| 1227 | |
Sarah Sharp | bcef3fd | 2009-11-11 10:28:44 -0800 | [diff] [blame] | 1228 | static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci, |
| 1229 | unsigned int slot_id, unsigned int ep_index, |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 1230 | unsigned int stream_id, |
Sarah Sharp | bcef3fd | 2009-11-11 10:28:44 -0800 | [diff] [blame] | 1231 | struct xhci_td *td, union xhci_trb *event_trb) |
| 1232 | { |
| 1233 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; |
| 1234 | ep->ep_state |= EP_HALTED; |
| 1235 | ep->stopped_td = td; |
| 1236 | ep->stopped_trb = event_trb; |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 1237 | ep->stopped_stream = stream_id; |
Sarah Sharp | 1624ae1 | 2010-05-06 13:40:08 -0700 | [diff] [blame] | 1238 | |
Sarah Sharp | bcef3fd | 2009-11-11 10:28:44 -0800 | [diff] [blame] | 1239 | xhci_queue_reset_ep(xhci, slot_id, ep_index); |
| 1240 | xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index); |
Sarah Sharp | 1624ae1 | 2010-05-06 13:40:08 -0700 | [diff] [blame] | 1241 | |
| 1242 | ep->stopped_td = NULL; |
| 1243 | ep->stopped_trb = NULL; |
Sarah Sharp | 5e5cf6f | 2010-05-06 13:40:18 -0700 | [diff] [blame] | 1244 | ep->stopped_stream = 0; |
Sarah Sharp | 1624ae1 | 2010-05-06 13:40:08 -0700 | [diff] [blame] | 1245 | |
Sarah Sharp | bcef3fd | 2009-11-11 10:28:44 -0800 | [diff] [blame] | 1246 | xhci_ring_cmd_db(xhci); |
| 1247 | } |
| 1248 | |
| 1249 | /* Check if an error has halted the endpoint ring. The class driver will |
| 1250 | * cleanup the halt for a non-default control endpoint if we indicate a stall. |
| 1251 | * However, a babble and other errors also halt the endpoint ring, and the class |
| 1252 | * driver won't clear the halt in that case, so we need to issue a Set Transfer |
| 1253 | * Ring Dequeue Pointer command manually. |
| 1254 | */ |
| 1255 | static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci, |
| 1256 | struct xhci_ep_ctx *ep_ctx, |
| 1257 | unsigned int trb_comp_code) |
| 1258 | { |
| 1259 | /* TRB completion codes that may require a manual halt cleanup */ |
| 1260 | if (trb_comp_code == COMP_TX_ERR || |
| 1261 | trb_comp_code == COMP_BABBLE || |
| 1262 | trb_comp_code == COMP_SPLIT_ERR) |
| 1263 | /* The 0.96 spec says a babbling control endpoint |
| 1264 | * is not halted. The 0.96 spec says it is. Some HW |
| 1265 | * claims to be 0.95 compliant, but it halts the control |
| 1266 | * endpoint anyway. Check if a babble halted the |
| 1267 | * endpoint. |
| 1268 | */ |
| 1269 | if ((ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_HALTED) |
| 1270 | return 1; |
| 1271 | |
| 1272 | return 0; |
| 1273 | } |
| 1274 | |
Sarah Sharp | b45b506 | 2009-12-09 15:59:06 -0800 | [diff] [blame] | 1275 | int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code) |
| 1276 | { |
| 1277 | if (trb_comp_code >= 224 && trb_comp_code <= 255) { |
| 1278 | /* Vendor defined "informational" completion code, |
| 1279 | * treat as not-an-error. |
| 1280 | */ |
| 1281 | xhci_dbg(xhci, "Vendor defined info completion code %u\n", |
| 1282 | trb_comp_code); |
| 1283 | xhci_dbg(xhci, "Treating code as success.\n"); |
| 1284 | return 1; |
| 1285 | } |
| 1286 | return 0; |
| 1287 | } |
| 1288 | |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1289 | /* |
Andiry Xu | 4422da6 | 2010-07-22 15:22:55 -0700 | [diff] [blame] | 1290 | * Finish the td processing, remove the td from td list; |
| 1291 | * Return 1 if the urb can be given back. |
| 1292 | */ |
| 1293 | static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td, |
| 1294 | union xhci_trb *event_trb, struct xhci_transfer_event *event, |
| 1295 | struct xhci_virt_ep *ep, int *status, bool skip) |
| 1296 | { |
| 1297 | struct xhci_virt_device *xdev; |
| 1298 | struct xhci_ring *ep_ring; |
| 1299 | unsigned int slot_id; |
| 1300 | int ep_index; |
| 1301 | struct urb *urb = NULL; |
| 1302 | struct xhci_ep_ctx *ep_ctx; |
| 1303 | int ret = 0; |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 1304 | struct urb_priv *urb_priv; |
Andiry Xu | 4422da6 | 2010-07-22 15:22:55 -0700 | [diff] [blame] | 1305 | u32 trb_comp_code; |
| 1306 | |
| 1307 | slot_id = TRB_TO_SLOT_ID(event->flags); |
| 1308 | xdev = xhci->devs[slot_id]; |
| 1309 | ep_index = TRB_TO_EP_ID(event->flags) - 1; |
| 1310 | ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer); |
| 1311 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
| 1312 | trb_comp_code = GET_COMP_CODE(event->transfer_len); |
| 1313 | |
| 1314 | if (skip) |
| 1315 | goto td_cleanup; |
| 1316 | |
| 1317 | if (trb_comp_code == COMP_STOP_INVAL || |
| 1318 | trb_comp_code == COMP_STOP) { |
| 1319 | /* The Endpoint Stop Command completion will take care of any |
| 1320 | * stopped TDs. A stopped TD may be restarted, so don't update |
| 1321 | * the ring dequeue pointer or take this TD off any lists yet. |
| 1322 | */ |
| 1323 | ep->stopped_td = td; |
| 1324 | ep->stopped_trb = event_trb; |
| 1325 | return 0; |
| 1326 | } else { |
| 1327 | if (trb_comp_code == COMP_STALL) { |
| 1328 | /* The transfer is completed from the driver's |
| 1329 | * perspective, but we need to issue a set dequeue |
| 1330 | * command for this stalled endpoint to move the dequeue |
| 1331 | * pointer past the TD. We can't do that here because |
| 1332 | * the halt condition must be cleared first. Let the |
| 1333 | * USB class driver clear the stall later. |
| 1334 | */ |
| 1335 | ep->stopped_td = td; |
| 1336 | ep->stopped_trb = event_trb; |
| 1337 | ep->stopped_stream = ep_ring->stream_id; |
| 1338 | } else if (xhci_requires_manual_halt_cleanup(xhci, |
| 1339 | ep_ctx, trb_comp_code)) { |
| 1340 | /* Other types of errors halt the endpoint, but the |
| 1341 | * class driver doesn't call usb_reset_endpoint() unless |
| 1342 | * the error is -EPIPE. Clear the halted status in the |
| 1343 | * xHCI hardware manually. |
| 1344 | */ |
| 1345 | xhci_cleanup_halted_endpoint(xhci, |
| 1346 | slot_id, ep_index, ep_ring->stream_id, |
| 1347 | td, event_trb); |
| 1348 | } else { |
| 1349 | /* Update ring dequeue pointer */ |
| 1350 | while (ep_ring->dequeue != td->last_trb) |
| 1351 | inc_deq(xhci, ep_ring, false); |
| 1352 | inc_deq(xhci, ep_ring, false); |
| 1353 | } |
| 1354 | |
| 1355 | td_cleanup: |
| 1356 | /* Clean up the endpoint's TD list */ |
| 1357 | urb = td->urb; |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 1358 | urb_priv = urb->hcpriv; |
Andiry Xu | 4422da6 | 2010-07-22 15:22:55 -0700 | [diff] [blame] | 1359 | |
| 1360 | /* Do one last check of the actual transfer length. |
| 1361 | * If the host controller said we transferred more data than |
| 1362 | * the buffer length, urb->actual_length will be a very big |
| 1363 | * number (since it's unsigned). Play it safe and say we didn't |
| 1364 | * transfer anything. |
| 1365 | */ |
| 1366 | if (urb->actual_length > urb->transfer_buffer_length) { |
| 1367 | xhci_warn(xhci, "URB transfer length is wrong, " |
| 1368 | "xHC issue? req. len = %u, " |
| 1369 | "act. len = %u\n", |
| 1370 | urb->transfer_buffer_length, |
| 1371 | urb->actual_length); |
| 1372 | urb->actual_length = 0; |
| 1373 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) |
| 1374 | *status = -EREMOTEIO; |
| 1375 | else |
| 1376 | *status = 0; |
| 1377 | } |
| 1378 | list_del(&td->td_list); |
| 1379 | /* Was this TD slated to be cancelled but completed anyway? */ |
| 1380 | if (!list_empty(&td->cancelled_td_list)) |
| 1381 | list_del(&td->cancelled_td_list); |
| 1382 | |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 1383 | urb_priv->td_cnt++; |
| 1384 | /* Giveback the urb when all the tds are completed */ |
| 1385 | if (urb_priv->td_cnt == urb_priv->length) |
| 1386 | ret = 1; |
Andiry Xu | 4422da6 | 2010-07-22 15:22:55 -0700 | [diff] [blame] | 1387 | } |
| 1388 | |
| 1389 | return ret; |
| 1390 | } |
| 1391 | |
| 1392 | /* |
Andiry Xu | 8af56be | 2010-07-22 15:23:03 -0700 | [diff] [blame] | 1393 | * Process control tds, update urb status and actual_length. |
| 1394 | */ |
| 1395 | static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td, |
| 1396 | union xhci_trb *event_trb, struct xhci_transfer_event *event, |
| 1397 | struct xhci_virt_ep *ep, int *status) |
| 1398 | { |
| 1399 | struct xhci_virt_device *xdev; |
| 1400 | struct xhci_ring *ep_ring; |
| 1401 | unsigned int slot_id; |
| 1402 | int ep_index; |
| 1403 | struct xhci_ep_ctx *ep_ctx; |
| 1404 | u32 trb_comp_code; |
| 1405 | |
| 1406 | slot_id = TRB_TO_SLOT_ID(event->flags); |
| 1407 | xdev = xhci->devs[slot_id]; |
| 1408 | ep_index = TRB_TO_EP_ID(event->flags) - 1; |
| 1409 | ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer); |
| 1410 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
| 1411 | trb_comp_code = GET_COMP_CODE(event->transfer_len); |
| 1412 | |
| 1413 | xhci_debug_trb(xhci, xhci->event_ring->dequeue); |
| 1414 | switch (trb_comp_code) { |
| 1415 | case COMP_SUCCESS: |
| 1416 | if (event_trb == ep_ring->dequeue) { |
| 1417 | xhci_warn(xhci, "WARN: Success on ctrl setup TRB " |
| 1418 | "without IOC set??\n"); |
| 1419 | *status = -ESHUTDOWN; |
| 1420 | } else if (event_trb != td->last_trb) { |
| 1421 | xhci_warn(xhci, "WARN: Success on ctrl data TRB " |
| 1422 | "without IOC set??\n"); |
| 1423 | *status = -ESHUTDOWN; |
| 1424 | } else { |
| 1425 | xhci_dbg(xhci, "Successful control transfer!\n"); |
| 1426 | *status = 0; |
| 1427 | } |
| 1428 | break; |
| 1429 | case COMP_SHORT_TX: |
| 1430 | xhci_warn(xhci, "WARN: short transfer on control ep\n"); |
| 1431 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) |
| 1432 | *status = -EREMOTEIO; |
| 1433 | else |
| 1434 | *status = 0; |
| 1435 | break; |
| 1436 | default: |
| 1437 | if (!xhci_requires_manual_halt_cleanup(xhci, |
| 1438 | ep_ctx, trb_comp_code)) |
| 1439 | break; |
| 1440 | xhci_dbg(xhci, "TRB error code %u, " |
| 1441 | "halted endpoint index = %u\n", |
| 1442 | trb_comp_code, ep_index); |
| 1443 | /* else fall through */ |
| 1444 | case COMP_STALL: |
| 1445 | /* Did we transfer part of the data (middle) phase? */ |
| 1446 | if (event_trb != ep_ring->dequeue && |
| 1447 | event_trb != td->last_trb) |
| 1448 | td->urb->actual_length = |
| 1449 | td->urb->transfer_buffer_length |
| 1450 | - TRB_LEN(event->transfer_len); |
| 1451 | else |
| 1452 | td->urb->actual_length = 0; |
| 1453 | |
| 1454 | xhci_cleanup_halted_endpoint(xhci, |
| 1455 | slot_id, ep_index, 0, td, event_trb); |
| 1456 | return finish_td(xhci, td, event_trb, event, ep, status, true); |
| 1457 | } |
| 1458 | /* |
| 1459 | * Did we transfer any data, despite the errors that might have |
| 1460 | * happened? I.e. did we get past the setup stage? |
| 1461 | */ |
| 1462 | if (event_trb != ep_ring->dequeue) { |
| 1463 | /* The event was for the status stage */ |
| 1464 | if (event_trb == td->last_trb) { |
| 1465 | if (td->urb->actual_length != 0) { |
| 1466 | /* Don't overwrite a previously set error code |
| 1467 | */ |
| 1468 | if ((*status == -EINPROGRESS || *status == 0) && |
| 1469 | (td->urb->transfer_flags |
| 1470 | & URB_SHORT_NOT_OK)) |
| 1471 | /* Did we already see a short data |
| 1472 | * stage? */ |
| 1473 | *status = -EREMOTEIO; |
| 1474 | } else { |
| 1475 | td->urb->actual_length = |
| 1476 | td->urb->transfer_buffer_length; |
| 1477 | } |
| 1478 | } else { |
| 1479 | /* Maybe the event was for the data stage? */ |
| 1480 | if (trb_comp_code != COMP_STOP_INVAL) { |
| 1481 | /* We didn't stop on a link TRB in the middle */ |
| 1482 | td->urb->actual_length = |
| 1483 | td->urb->transfer_buffer_length - |
| 1484 | TRB_LEN(event->transfer_len); |
| 1485 | xhci_dbg(xhci, "Waiting for status " |
| 1486 | "stage event\n"); |
| 1487 | return 0; |
| 1488 | } |
| 1489 | } |
| 1490 | } |
| 1491 | |
| 1492 | return finish_td(xhci, td, event_trb, event, ep, status, false); |
| 1493 | } |
| 1494 | |
| 1495 | /* |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 1496 | * Process isochronous tds, update urb packet status and actual_length. |
| 1497 | */ |
| 1498 | static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td, |
| 1499 | union xhci_trb *event_trb, struct xhci_transfer_event *event, |
| 1500 | struct xhci_virt_ep *ep, int *status) |
| 1501 | { |
| 1502 | struct xhci_ring *ep_ring; |
| 1503 | struct urb_priv *urb_priv; |
| 1504 | int idx; |
| 1505 | int len = 0; |
| 1506 | int skip_td = 0; |
| 1507 | union xhci_trb *cur_trb; |
| 1508 | struct xhci_segment *cur_seg; |
| 1509 | u32 trb_comp_code; |
| 1510 | |
| 1511 | ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer); |
| 1512 | trb_comp_code = GET_COMP_CODE(event->transfer_len); |
| 1513 | urb_priv = td->urb->hcpriv; |
| 1514 | idx = urb_priv->td_cnt; |
| 1515 | |
| 1516 | if (ep->skip) { |
| 1517 | /* The transfer is partly done */ |
| 1518 | *status = -EXDEV; |
| 1519 | td->urb->iso_frame_desc[idx].status = -EXDEV; |
| 1520 | } else { |
| 1521 | /* handle completion code */ |
| 1522 | switch (trb_comp_code) { |
| 1523 | case COMP_SUCCESS: |
| 1524 | td->urb->iso_frame_desc[idx].status = 0; |
| 1525 | xhci_dbg(xhci, "Successful isoc transfer!\n"); |
| 1526 | break; |
| 1527 | case COMP_SHORT_TX: |
| 1528 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) |
| 1529 | td->urb->iso_frame_desc[idx].status = |
| 1530 | -EREMOTEIO; |
| 1531 | else |
| 1532 | td->urb->iso_frame_desc[idx].status = 0; |
| 1533 | break; |
| 1534 | case COMP_BW_OVER: |
| 1535 | td->urb->iso_frame_desc[idx].status = -ECOMM; |
| 1536 | skip_td = 1; |
| 1537 | break; |
| 1538 | case COMP_BUFF_OVER: |
| 1539 | case COMP_BABBLE: |
| 1540 | td->urb->iso_frame_desc[idx].status = -EOVERFLOW; |
| 1541 | skip_td = 1; |
| 1542 | break; |
| 1543 | case COMP_STALL: |
| 1544 | td->urb->iso_frame_desc[idx].status = -EPROTO; |
| 1545 | skip_td = 1; |
| 1546 | break; |
| 1547 | case COMP_STOP: |
| 1548 | case COMP_STOP_INVAL: |
| 1549 | break; |
| 1550 | default: |
| 1551 | td->urb->iso_frame_desc[idx].status = -1; |
| 1552 | break; |
| 1553 | } |
| 1554 | } |
| 1555 | |
| 1556 | /* calc actual length */ |
| 1557 | if (ep->skip) { |
| 1558 | td->urb->iso_frame_desc[idx].actual_length = 0; |
| 1559 | return finish_td(xhci, td, event_trb, event, ep, status, true); |
| 1560 | } |
| 1561 | |
| 1562 | if (trb_comp_code == COMP_SUCCESS || skip_td == 1) { |
| 1563 | td->urb->iso_frame_desc[idx].actual_length = |
| 1564 | td->urb->iso_frame_desc[idx].length; |
| 1565 | td->urb->actual_length += |
| 1566 | td->urb->iso_frame_desc[idx].length; |
| 1567 | } else { |
| 1568 | for (cur_trb = ep_ring->dequeue, |
| 1569 | cur_seg = ep_ring->deq_seg; cur_trb != event_trb; |
| 1570 | next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { |
| 1571 | if ((cur_trb->generic.field[3] & |
| 1572 | TRB_TYPE_BITMASK) != TRB_TYPE(TRB_TR_NOOP) && |
| 1573 | (cur_trb->generic.field[3] & |
| 1574 | TRB_TYPE_BITMASK) != TRB_TYPE(TRB_LINK)) |
| 1575 | len += |
| 1576 | TRB_LEN(cur_trb->generic.field[2]); |
| 1577 | } |
| 1578 | len += TRB_LEN(cur_trb->generic.field[2]) - |
| 1579 | TRB_LEN(event->transfer_len); |
| 1580 | |
| 1581 | if (trb_comp_code != COMP_STOP_INVAL) { |
| 1582 | td->urb->iso_frame_desc[idx].actual_length = len; |
| 1583 | td->urb->actual_length += len; |
| 1584 | } |
| 1585 | } |
| 1586 | |
| 1587 | if ((idx == urb_priv->length - 1) && *status == -EINPROGRESS) |
| 1588 | *status = 0; |
| 1589 | |
| 1590 | return finish_td(xhci, td, event_trb, event, ep, status, false); |
| 1591 | } |
| 1592 | |
| 1593 | /* |
Andiry Xu | 22405ed | 2010-07-22 15:23:08 -0700 | [diff] [blame] | 1594 | * Process bulk and interrupt tds, update urb status and actual_length. |
| 1595 | */ |
| 1596 | static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td, |
| 1597 | union xhci_trb *event_trb, struct xhci_transfer_event *event, |
| 1598 | struct xhci_virt_ep *ep, int *status) |
| 1599 | { |
| 1600 | struct xhci_ring *ep_ring; |
| 1601 | union xhci_trb *cur_trb; |
| 1602 | struct xhci_segment *cur_seg; |
| 1603 | u32 trb_comp_code; |
| 1604 | |
| 1605 | ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer); |
| 1606 | trb_comp_code = GET_COMP_CODE(event->transfer_len); |
| 1607 | |
| 1608 | switch (trb_comp_code) { |
| 1609 | case COMP_SUCCESS: |
| 1610 | /* Double check that the HW transferred everything. */ |
| 1611 | if (event_trb != td->last_trb) { |
| 1612 | xhci_warn(xhci, "WARN Successful completion " |
| 1613 | "on short TX\n"); |
| 1614 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) |
| 1615 | *status = -EREMOTEIO; |
| 1616 | else |
| 1617 | *status = 0; |
| 1618 | } else { |
| 1619 | if (usb_endpoint_xfer_bulk(&td->urb->ep->desc)) |
| 1620 | xhci_dbg(xhci, "Successful bulk " |
| 1621 | "transfer!\n"); |
| 1622 | else |
| 1623 | xhci_dbg(xhci, "Successful interrupt " |
| 1624 | "transfer!\n"); |
| 1625 | *status = 0; |
| 1626 | } |
| 1627 | break; |
| 1628 | case COMP_SHORT_TX: |
| 1629 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) |
| 1630 | *status = -EREMOTEIO; |
| 1631 | else |
| 1632 | *status = 0; |
| 1633 | break; |
| 1634 | default: |
| 1635 | /* Others already handled above */ |
| 1636 | break; |
| 1637 | } |
| 1638 | dev_dbg(&td->urb->dev->dev, |
| 1639 | "ep %#x - asked for %d bytes, " |
| 1640 | "%d bytes untransferred\n", |
| 1641 | td->urb->ep->desc.bEndpointAddress, |
| 1642 | td->urb->transfer_buffer_length, |
| 1643 | TRB_LEN(event->transfer_len)); |
| 1644 | /* Fast path - was this the last TRB in the TD for this URB? */ |
| 1645 | if (event_trb == td->last_trb) { |
| 1646 | if (TRB_LEN(event->transfer_len) != 0) { |
| 1647 | td->urb->actual_length = |
| 1648 | td->urb->transfer_buffer_length - |
| 1649 | TRB_LEN(event->transfer_len); |
| 1650 | if (td->urb->transfer_buffer_length < |
| 1651 | td->urb->actual_length) { |
| 1652 | xhci_warn(xhci, "HC gave bad length " |
| 1653 | "of %d bytes left\n", |
| 1654 | TRB_LEN(event->transfer_len)); |
| 1655 | td->urb->actual_length = 0; |
| 1656 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) |
| 1657 | *status = -EREMOTEIO; |
| 1658 | else |
| 1659 | *status = 0; |
| 1660 | } |
| 1661 | /* Don't overwrite a previously set error code */ |
| 1662 | if (*status == -EINPROGRESS) { |
| 1663 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) |
| 1664 | *status = -EREMOTEIO; |
| 1665 | else |
| 1666 | *status = 0; |
| 1667 | } |
| 1668 | } else { |
| 1669 | td->urb->actual_length = |
| 1670 | td->urb->transfer_buffer_length; |
| 1671 | /* Ignore a short packet completion if the |
| 1672 | * untransferred length was zero. |
| 1673 | */ |
| 1674 | if (*status == -EREMOTEIO) |
| 1675 | *status = 0; |
| 1676 | } |
| 1677 | } else { |
| 1678 | /* Slow path - walk the list, starting from the dequeue |
| 1679 | * pointer, to get the actual length transferred. |
| 1680 | */ |
| 1681 | td->urb->actual_length = 0; |
| 1682 | for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg; |
| 1683 | cur_trb != event_trb; |
| 1684 | next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { |
| 1685 | if ((cur_trb->generic.field[3] & |
| 1686 | TRB_TYPE_BITMASK) != TRB_TYPE(TRB_TR_NOOP) && |
| 1687 | (cur_trb->generic.field[3] & |
| 1688 | TRB_TYPE_BITMASK) != TRB_TYPE(TRB_LINK)) |
| 1689 | td->urb->actual_length += |
| 1690 | TRB_LEN(cur_trb->generic.field[2]); |
| 1691 | } |
| 1692 | /* If the ring didn't stop on a Link or No-op TRB, add |
| 1693 | * in the actual bytes transferred from the Normal TRB |
| 1694 | */ |
| 1695 | if (trb_comp_code != COMP_STOP_INVAL) |
| 1696 | td->urb->actual_length += |
| 1697 | TRB_LEN(cur_trb->generic.field[2]) - |
| 1698 | TRB_LEN(event->transfer_len); |
| 1699 | } |
| 1700 | |
| 1701 | return finish_td(xhci, td, event_trb, event, ep, status, false); |
| 1702 | } |
| 1703 | |
| 1704 | /* |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1705 | * If this function returns an error condition, it means it got a Transfer |
| 1706 | * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address. |
| 1707 | * At this point, the host controller is probably hosed and should be reset. |
| 1708 | */ |
| 1709 | static int handle_tx_event(struct xhci_hcd *xhci, |
| 1710 | struct xhci_transfer_event *event) |
| 1711 | { |
| 1712 | struct xhci_virt_device *xdev; |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 1713 | struct xhci_virt_ep *ep; |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1714 | struct xhci_ring *ep_ring; |
Sarah Sharp | 82d1009 | 2009-08-07 14:04:52 -0700 | [diff] [blame] | 1715 | unsigned int slot_id; |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1716 | int ep_index; |
Randy Dunlap | 326b481 | 2010-04-19 08:53:50 -0700 | [diff] [blame] | 1717 | struct xhci_td *td = NULL; |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1718 | dma_addr_t event_dma; |
| 1719 | struct xhci_segment *event_seg; |
| 1720 | union xhci_trb *event_trb; |
Randy Dunlap | 326b481 | 2010-04-19 08:53:50 -0700 | [diff] [blame] | 1721 | struct urb *urb = NULL; |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1722 | int status = -EINPROGRESS; |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 1723 | struct urb_priv *urb_priv; |
John Youn | d115b04 | 2009-07-27 12:05:15 -0700 | [diff] [blame] | 1724 | struct xhci_ep_ctx *ep_ctx; |
Sarah Sharp | 66d1eeb | 2009-08-27 14:35:53 -0700 | [diff] [blame] | 1725 | u32 trb_comp_code; |
Andiry Xu | 4422da6 | 2010-07-22 15:22:55 -0700 | [diff] [blame] | 1726 | int ret = 0; |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1727 | |
Sarah Sharp | 82d1009 | 2009-08-07 14:04:52 -0700 | [diff] [blame] | 1728 | slot_id = TRB_TO_SLOT_ID(event->flags); |
| 1729 | xdev = xhci->devs[slot_id]; |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1730 | if (!xdev) { |
| 1731 | xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n"); |
| 1732 | return -ENODEV; |
| 1733 | } |
| 1734 | |
| 1735 | /* Endpoint ID is 1 based, our index is zero based */ |
| 1736 | ep_index = TRB_TO_EP_ID(event->flags) - 1; |
Sarah Sharp | 66e49d8 | 2009-07-27 12:03:46 -0700 | [diff] [blame] | 1737 | xhci_dbg(xhci, "%s - ep index = %d\n", __func__, ep_index); |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 1738 | ep = &xdev->eps[ep_index]; |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 1739 | ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer); |
John Youn | d115b04 | 2009-07-27 12:05:15 -0700 | [diff] [blame] | 1740 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
Andiry Xu | 986a92d | 2010-07-22 15:23:20 -0700 | [diff] [blame] | 1741 | if (!ep_ring || |
| 1742 | (ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_DISABLED) { |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 1743 | xhci_err(xhci, "ERROR Transfer event for disabled endpoint " |
| 1744 | "or incorrect stream ring\n"); |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1745 | return -ENODEV; |
| 1746 | } |
| 1747 | |
Sarah Sharp | 8e595a5 | 2009-07-27 12:03:31 -0700 | [diff] [blame] | 1748 | event_dma = event->buffer; |
Sarah Sharp | 66d1eeb | 2009-08-27 14:35:53 -0700 | [diff] [blame] | 1749 | trb_comp_code = GET_COMP_CODE(event->transfer_len); |
Andiry Xu | 986a92d | 2010-07-22 15:23:20 -0700 | [diff] [blame] | 1750 | /* Look for common error cases */ |
Sarah Sharp | 66d1eeb | 2009-08-27 14:35:53 -0700 | [diff] [blame] | 1751 | switch (trb_comp_code) { |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 1752 | /* Skip codes that require special handling depending on |
| 1753 | * transfer type |
| 1754 | */ |
| 1755 | case COMP_SUCCESS: |
| 1756 | case COMP_SHORT_TX: |
| 1757 | break; |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 1758 | case COMP_STOP: |
| 1759 | xhci_dbg(xhci, "Stopped on Transfer TRB\n"); |
| 1760 | break; |
| 1761 | case COMP_STOP_INVAL: |
| 1762 | xhci_dbg(xhci, "Stopped on No-op or Link TRB\n"); |
| 1763 | break; |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 1764 | case COMP_STALL: |
| 1765 | xhci_warn(xhci, "WARN: Stalled endpoint\n"); |
Sarah Sharp | 63a0d9a | 2009-09-04 10:53:09 -0700 | [diff] [blame] | 1766 | ep->ep_state |= EP_HALTED; |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 1767 | status = -EPIPE; |
| 1768 | break; |
| 1769 | case COMP_TRB_ERR: |
| 1770 | xhci_warn(xhci, "WARN: TRB error on endpoint\n"); |
| 1771 | status = -EILSEQ; |
| 1772 | break; |
Sarah Sharp | ec74e40 | 2009-11-11 10:28:36 -0800 | [diff] [blame] | 1773 | case COMP_SPLIT_ERR: |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 1774 | case COMP_TX_ERR: |
| 1775 | xhci_warn(xhci, "WARN: transfer error on endpoint\n"); |
| 1776 | status = -EPROTO; |
| 1777 | break; |
Sarah Sharp | 4a73143 | 2009-07-27 12:04:32 -0700 | [diff] [blame] | 1778 | case COMP_BABBLE: |
| 1779 | xhci_warn(xhci, "WARN: babble error on endpoint\n"); |
| 1780 | status = -EOVERFLOW; |
| 1781 | break; |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 1782 | case COMP_DB_ERR: |
| 1783 | xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n"); |
| 1784 | status = -ENOSR; |
| 1785 | break; |
Andiry Xu | 986a92d | 2010-07-22 15:23:20 -0700 | [diff] [blame] | 1786 | case COMP_BW_OVER: |
| 1787 | xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n"); |
| 1788 | break; |
| 1789 | case COMP_BUFF_OVER: |
| 1790 | xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n"); |
| 1791 | break; |
| 1792 | case COMP_UNDERRUN: |
| 1793 | /* |
| 1794 | * When the Isoch ring is empty, the xHC will generate |
| 1795 | * a Ring Overrun Event for IN Isoch endpoint or Ring |
| 1796 | * Underrun Event for OUT Isoch endpoint. |
| 1797 | */ |
| 1798 | xhci_dbg(xhci, "underrun event on endpoint\n"); |
| 1799 | if (!list_empty(&ep_ring->td_list)) |
| 1800 | xhci_dbg(xhci, "Underrun Event for slot %d ep %d " |
| 1801 | "still with TDs queued?\n", |
| 1802 | TRB_TO_SLOT_ID(event->flags), ep_index); |
| 1803 | goto cleanup; |
| 1804 | case COMP_OVERRUN: |
| 1805 | xhci_dbg(xhci, "overrun event on endpoint\n"); |
| 1806 | if (!list_empty(&ep_ring->td_list)) |
| 1807 | xhci_dbg(xhci, "Overrun Event for slot %d ep %d " |
| 1808 | "still with TDs queued?\n", |
| 1809 | TRB_TO_SLOT_ID(event->flags), ep_index); |
| 1810 | goto cleanup; |
Andiry Xu | d18240d | 2010-07-22 15:23:25 -0700 | [diff] [blame] | 1811 | case COMP_MISSED_INT: |
| 1812 | /* |
| 1813 | * When encounter missed service error, one or more isoc tds |
| 1814 | * may be missed by xHC. |
| 1815 | * Set skip flag of the ep_ring; Complete the missed tds as |
| 1816 | * short transfer when process the ep_ring next time. |
| 1817 | */ |
| 1818 | ep->skip = true; |
| 1819 | xhci_dbg(xhci, "Miss service interval error, set skip flag\n"); |
| 1820 | goto cleanup; |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 1821 | default: |
Sarah Sharp | b45b506 | 2009-12-09 15:59:06 -0800 | [diff] [blame] | 1822 | if (xhci_is_vendor_info_code(xhci, trb_comp_code)) { |
Sarah Sharp | 5ad6a52 | 2009-11-11 10:28:40 -0800 | [diff] [blame] | 1823 | status = 0; |
| 1824 | break; |
| 1825 | } |
Andiry Xu | 986a92d | 2010-07-22 15:23:20 -0700 | [diff] [blame] | 1826 | xhci_warn(xhci, "ERROR Unknown event condition, HC probably " |
| 1827 | "busted\n"); |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 1828 | goto cleanup; |
| 1829 | } |
Andiry Xu | 986a92d | 2010-07-22 15:23:20 -0700 | [diff] [blame] | 1830 | |
Andiry Xu | d18240d | 2010-07-22 15:23:25 -0700 | [diff] [blame] | 1831 | do { |
| 1832 | /* This TRB should be in the TD at the head of this ring's |
| 1833 | * TD list. |
| 1834 | */ |
| 1835 | if (list_empty(&ep_ring->td_list)) { |
| 1836 | xhci_warn(xhci, "WARN Event TRB for slot %d ep %d " |
| 1837 | "with no TDs queued?\n", |
| 1838 | TRB_TO_SLOT_ID(event->flags), ep_index); |
| 1839 | xhci_dbg(xhci, "Event TRB with TRB type ID %u\n", |
| 1840 | (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10); |
| 1841 | xhci_print_trb_offsets(xhci, (union xhci_trb *) event); |
| 1842 | if (ep->skip) { |
| 1843 | ep->skip = false; |
| 1844 | xhci_dbg(xhci, "td_list is empty while skip " |
| 1845 | "flag set. Clear skip flag.\n"); |
| 1846 | } |
| 1847 | ret = 0; |
| 1848 | goto cleanup; |
| 1849 | } |
Andiry Xu | 986a92d | 2010-07-22 15:23:20 -0700 | [diff] [blame] | 1850 | |
Andiry Xu | d18240d | 2010-07-22 15:23:25 -0700 | [diff] [blame] | 1851 | td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list); |
| 1852 | /* Is this a TRB in the currently executing TD? */ |
| 1853 | event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue, |
| 1854 | td->last_trb, event_dma); |
| 1855 | if (event_seg && ep->skip) { |
| 1856 | xhci_dbg(xhci, "Found td. Clear skip flag.\n"); |
| 1857 | ep->skip = false; |
| 1858 | } |
| 1859 | if (!event_seg && |
| 1860 | (!ep->skip || !usb_endpoint_xfer_isoc(&td->urb->ep->desc))) { |
| 1861 | /* HC is busted, give up! */ |
| 1862 | xhci_err(xhci, "ERROR Transfer event TRB DMA ptr not " |
| 1863 | "part of current TD\n"); |
| 1864 | return -ESHUTDOWN; |
| 1865 | } |
Andiry Xu | 986a92d | 2010-07-22 15:23:20 -0700 | [diff] [blame] | 1866 | |
Andiry Xu | d18240d | 2010-07-22 15:23:25 -0700 | [diff] [blame] | 1867 | if (event_seg) { |
| 1868 | event_trb = &event_seg->trbs[(event_dma - |
| 1869 | event_seg->dma) / sizeof(*event_trb)]; |
| 1870 | /* |
| 1871 | * No-op TRB should not trigger interrupts. |
| 1872 | * If event_trb is a no-op TRB, it means the |
| 1873 | * corresponding TD has been cancelled. Just ignore |
| 1874 | * the TD. |
| 1875 | */ |
| 1876 | if ((event_trb->generic.field[3] & TRB_TYPE_BITMASK) |
| 1877 | == TRB_TYPE(TRB_TR_NOOP)) { |
| 1878 | xhci_dbg(xhci, "event_trb is a no-op TRB. " |
| 1879 | "Skip it\n"); |
| 1880 | goto cleanup; |
| 1881 | } |
| 1882 | } |
| 1883 | |
| 1884 | /* Now update the urb's actual_length and give back to |
| 1885 | * the core |
| 1886 | */ |
| 1887 | if (usb_endpoint_xfer_control(&td->urb->ep->desc)) |
| 1888 | ret = process_ctrl_td(xhci, td, event_trb, event, ep, |
| 1889 | &status); |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 1890 | else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc)) |
| 1891 | ret = process_isoc_td(xhci, td, event_trb, event, ep, |
| 1892 | &status); |
Andiry Xu | d18240d | 2010-07-22 15:23:25 -0700 | [diff] [blame] | 1893 | else |
| 1894 | ret = process_bulk_intr_td(xhci, td, event_trb, event, |
| 1895 | ep, &status); |
Andiry Xu | 4422da6 | 2010-07-22 15:22:55 -0700 | [diff] [blame] | 1896 | |
| 1897 | cleanup: |
Andiry Xu | d18240d | 2010-07-22 15:23:25 -0700 | [diff] [blame] | 1898 | /* |
| 1899 | * Do not update event ring dequeue pointer if ep->skip is set. |
| 1900 | * Will roll back to continue process missed tds. |
Sarah Sharp | 82d1009 | 2009-08-07 14:04:52 -0700 | [diff] [blame] | 1901 | */ |
Andiry Xu | d18240d | 2010-07-22 15:23:25 -0700 | [diff] [blame] | 1902 | if (trb_comp_code == COMP_MISSED_INT || !ep->skip) { |
| 1903 | inc_deq(xhci, xhci->event_ring, true); |
Andiry Xu | d18240d | 2010-07-22 15:23:25 -0700 | [diff] [blame] | 1904 | } |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1905 | |
Andiry Xu | d18240d | 2010-07-22 15:23:25 -0700 | [diff] [blame] | 1906 | if (ret) { |
| 1907 | urb = td->urb; |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 1908 | urb_priv = urb->hcpriv; |
Andiry Xu | d18240d | 2010-07-22 15:23:25 -0700 | [diff] [blame] | 1909 | /* Leave the TD around for the reset endpoint function |
| 1910 | * to use(but only if it's not a control endpoint, |
| 1911 | * since we already queued the Set TR dequeue pointer |
| 1912 | * command for stalled control endpoints). |
| 1913 | */ |
| 1914 | if (usb_endpoint_xfer_control(&urb->ep->desc) || |
| 1915 | (trb_comp_code != COMP_STALL && |
| 1916 | trb_comp_code != COMP_BABBLE)) |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 1917 | xhci_urb_free_priv(xhci, urb_priv); |
Andiry Xu | d18240d | 2010-07-22 15:23:25 -0700 | [diff] [blame] | 1918 | |
| 1919 | usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci), urb); |
| 1920 | xhci_dbg(xhci, "Giveback URB %p, len = %d, " |
| 1921 | "status = %d\n", |
| 1922 | urb, urb->actual_length, status); |
| 1923 | spin_unlock(&xhci->lock); |
| 1924 | usb_hcd_giveback_urb(xhci_to_hcd(xhci), urb, status); |
| 1925 | spin_lock(&xhci->lock); |
| 1926 | } |
| 1927 | |
| 1928 | /* |
| 1929 | * If ep->skip is set, it means there are missed tds on the |
| 1930 | * endpoint ring need to take care of. |
| 1931 | * Process them as short transfer until reach the td pointed by |
| 1932 | * the event. |
| 1933 | */ |
| 1934 | } while (ep->skip && trb_comp_code != COMP_MISSED_INT); |
| 1935 | |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1936 | return 0; |
| 1937 | } |
| 1938 | |
| 1939 | /* |
Sarah Sharp | 0f2a793 | 2009-04-27 19:57:12 -0700 | [diff] [blame] | 1940 | * This function handles all OS-owned events on the event ring. It may drop |
| 1941 | * xhci->lock between event processing (e.g. to pass up port status changes). |
| 1942 | */ |
Sarah Sharp | d6d98a4 | 2010-07-29 22:12:46 -0700 | [diff] [blame] | 1943 | static void xhci_handle_event(struct xhci_hcd *xhci) |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 1944 | { |
| 1945 | union xhci_trb *event; |
Sarah Sharp | 0f2a793 | 2009-04-27 19:57:12 -0700 | [diff] [blame] | 1946 | int update_ptrs = 1; |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1947 | int ret; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 1948 | |
Sarah Sharp | 66e49d8 | 2009-07-27 12:03:46 -0700 | [diff] [blame] | 1949 | xhci_dbg(xhci, "In %s\n", __func__); |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 1950 | if (!xhci->event_ring || !xhci->event_ring->dequeue) { |
| 1951 | xhci->error_bitmask |= 1 << 1; |
| 1952 | return; |
| 1953 | } |
| 1954 | |
| 1955 | event = xhci->event_ring->dequeue; |
| 1956 | /* Does the HC or OS own the TRB? */ |
| 1957 | if ((event->event_cmd.flags & TRB_CYCLE) != |
| 1958 | xhci->event_ring->cycle_state) { |
| 1959 | xhci->error_bitmask |= 1 << 2; |
| 1960 | return; |
| 1961 | } |
Sarah Sharp | 66e49d8 | 2009-07-27 12:03:46 -0700 | [diff] [blame] | 1962 | xhci_dbg(xhci, "%s - OS owns TRB\n", __func__); |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 1963 | |
Sarah Sharp | 0f2a793 | 2009-04-27 19:57:12 -0700 | [diff] [blame] | 1964 | /* FIXME: Handle more event types. */ |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 1965 | switch ((event->event_cmd.flags & TRB_TYPE_BITMASK)) { |
| 1966 | case TRB_TYPE(TRB_COMPLETION): |
Sarah Sharp | 66e49d8 | 2009-07-27 12:03:46 -0700 | [diff] [blame] | 1967 | xhci_dbg(xhci, "%s - calling handle_cmd_completion\n", __func__); |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 1968 | handle_cmd_completion(xhci, &event->event_cmd); |
Sarah Sharp | 66e49d8 | 2009-07-27 12:03:46 -0700 | [diff] [blame] | 1969 | xhci_dbg(xhci, "%s - returned from handle_cmd_completion\n", __func__); |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 1970 | break; |
Sarah Sharp | 0f2a793 | 2009-04-27 19:57:12 -0700 | [diff] [blame] | 1971 | case TRB_TYPE(TRB_PORT_STATUS): |
Sarah Sharp | 66e49d8 | 2009-07-27 12:03:46 -0700 | [diff] [blame] | 1972 | xhci_dbg(xhci, "%s - calling handle_port_status\n", __func__); |
Sarah Sharp | 0f2a793 | 2009-04-27 19:57:12 -0700 | [diff] [blame] | 1973 | handle_port_status(xhci, event); |
Sarah Sharp | 66e49d8 | 2009-07-27 12:03:46 -0700 | [diff] [blame] | 1974 | xhci_dbg(xhci, "%s - returned from handle_port_status\n", __func__); |
Sarah Sharp | 0f2a793 | 2009-04-27 19:57:12 -0700 | [diff] [blame] | 1975 | update_ptrs = 0; |
| 1976 | break; |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1977 | case TRB_TYPE(TRB_TRANSFER): |
Sarah Sharp | 66e49d8 | 2009-07-27 12:03:46 -0700 | [diff] [blame] | 1978 | xhci_dbg(xhci, "%s - calling handle_tx_event\n", __func__); |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1979 | ret = handle_tx_event(xhci, &event->trans_event); |
Sarah Sharp | 66e49d8 | 2009-07-27 12:03:46 -0700 | [diff] [blame] | 1980 | xhci_dbg(xhci, "%s - returned from handle_tx_event\n", __func__); |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 1981 | if (ret < 0) |
| 1982 | xhci->error_bitmask |= 1 << 9; |
| 1983 | else |
| 1984 | update_ptrs = 0; |
| 1985 | break; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 1986 | default: |
Sarah Sharp | 0238634 | 2010-05-24 13:25:28 -0700 | [diff] [blame] | 1987 | if ((event->event_cmd.flags & TRB_TYPE_BITMASK) >= TRB_TYPE(48)) |
| 1988 | handle_vendor_event(xhci, event); |
| 1989 | else |
| 1990 | xhci->error_bitmask |= 1 << 3; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 1991 | } |
Sarah Sharp | 6f5165c | 2009-10-27 10:57:01 -0700 | [diff] [blame] | 1992 | /* Any of the above functions may drop and re-acquire the lock, so check |
| 1993 | * to make sure a watchdog timer didn't mark the host as non-responsive. |
| 1994 | */ |
| 1995 | if (xhci->xhc_state & XHCI_STATE_DYING) { |
| 1996 | xhci_dbg(xhci, "xHCI host dying, returning from " |
| 1997 | "event handler.\n"); |
| 1998 | return; |
| 1999 | } |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 2000 | |
Sarah Sharp | c06d68b | 2010-07-29 22:12:49 -0700 | [diff] [blame] | 2001 | if (update_ptrs) |
| 2002 | /* Update SW event ring dequeue pointer */ |
Sarah Sharp | 0f2a793 | 2009-04-27 19:57:12 -0700 | [diff] [blame] | 2003 | inc_deq(xhci, xhci->event_ring, true); |
Sarah Sharp | c06d68b | 2010-07-29 22:12:49 -0700 | [diff] [blame] | 2004 | |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 2005 | /* Are there more items on the event ring? */ |
Stephen Rothwell | b7258a4 | 2009-04-29 19:02:47 -0700 | [diff] [blame] | 2006 | xhci_handle_event(xhci); |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 2007 | } |
Sarah Sharp | 9032cd5 | 2010-07-29 22:12:29 -0700 | [diff] [blame] | 2008 | |
| 2009 | /* |
| 2010 | * xHCI spec says we can get an interrupt, and if the HC has an error condition, |
| 2011 | * we might get bad data out of the event ring. Section 4.10.2.7 has a list of |
| 2012 | * indicators of an event TRB error, but we check the status *first* to be safe. |
| 2013 | */ |
| 2014 | irqreturn_t xhci_irq(struct usb_hcd *hcd) |
| 2015 | { |
| 2016 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
Sarah Sharp | c21599a | 2010-07-29 22:13:00 -0700 | [diff] [blame^] | 2017 | u32 status; |
Sarah Sharp | 9032cd5 | 2010-07-29 22:12:29 -0700 | [diff] [blame] | 2018 | union xhci_trb *trb; |
Sarah Sharp | bda5314 | 2010-07-29 22:12:38 -0700 | [diff] [blame] | 2019 | u64 temp_64; |
Sarah Sharp | c06d68b | 2010-07-29 22:12:49 -0700 | [diff] [blame] | 2020 | union xhci_trb *event_ring_deq; |
| 2021 | dma_addr_t deq; |
Sarah Sharp | 9032cd5 | 2010-07-29 22:12:29 -0700 | [diff] [blame] | 2022 | |
| 2023 | spin_lock(&xhci->lock); |
| 2024 | trb = xhci->event_ring->dequeue; |
| 2025 | /* Check if the xHC generated the interrupt, or the irq is shared */ |
Sarah Sharp | 27e0dd4 | 2010-07-29 22:12:43 -0700 | [diff] [blame] | 2026 | status = xhci_readl(xhci, &xhci->op_regs->status); |
Sarah Sharp | c21599a | 2010-07-29 22:13:00 -0700 | [diff] [blame^] | 2027 | if (status == 0xffffffff) |
Sarah Sharp | 9032cd5 | 2010-07-29 22:12:29 -0700 | [diff] [blame] | 2028 | goto hw_died; |
| 2029 | |
Sarah Sharp | c21599a | 2010-07-29 22:13:00 -0700 | [diff] [blame^] | 2030 | if (!(status & STS_EINT)) { |
Sarah Sharp | 9032cd5 | 2010-07-29 22:12:29 -0700 | [diff] [blame] | 2031 | spin_unlock(&xhci->lock); |
| 2032 | xhci_warn(xhci, "Spurious interrupt.\n"); |
| 2033 | return IRQ_NONE; |
| 2034 | } |
Sarah Sharp | 27e0dd4 | 2010-07-29 22:12:43 -0700 | [diff] [blame] | 2035 | xhci_dbg(xhci, "op reg status = %08x\n", status); |
Sarah Sharp | 9032cd5 | 2010-07-29 22:12:29 -0700 | [diff] [blame] | 2036 | xhci_dbg(xhci, "Event ring dequeue ptr:\n"); |
| 2037 | xhci_dbg(xhci, "@%llx %08x %08x %08x %08x\n", |
| 2038 | (unsigned long long) |
| 2039 | xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, trb), |
| 2040 | lower_32_bits(trb->link.segment_ptr), |
| 2041 | upper_32_bits(trb->link.segment_ptr), |
| 2042 | (unsigned int) trb->link.intr_target, |
| 2043 | (unsigned int) trb->link.control); |
| 2044 | |
Sarah Sharp | 27e0dd4 | 2010-07-29 22:12:43 -0700 | [diff] [blame] | 2045 | if (status & STS_FATAL) { |
Sarah Sharp | 9032cd5 | 2010-07-29 22:12:29 -0700 | [diff] [blame] | 2046 | xhci_warn(xhci, "WARNING: Host System Error\n"); |
| 2047 | xhci_halt(xhci); |
| 2048 | hw_died: |
| 2049 | xhci_to_hcd(xhci)->state = HC_STATE_HALT; |
| 2050 | spin_unlock(&xhci->lock); |
| 2051 | return -ESHUTDOWN; |
| 2052 | } |
| 2053 | |
Sarah Sharp | bda5314 | 2010-07-29 22:12:38 -0700 | [diff] [blame] | 2054 | /* |
| 2055 | * Clear the op reg interrupt status first, |
| 2056 | * so we can receive interrupts from other MSI-X interrupters. |
| 2057 | * Write 1 to clear the interrupt status. |
| 2058 | */ |
Sarah Sharp | 27e0dd4 | 2010-07-29 22:12:43 -0700 | [diff] [blame] | 2059 | status |= STS_EINT; |
| 2060 | xhci_writel(xhci, status, &xhci->op_regs->status); |
Sarah Sharp | bda5314 | 2010-07-29 22:12:38 -0700 | [diff] [blame] | 2061 | /* FIXME when MSI-X is supported and there are multiple vectors */ |
| 2062 | /* Clear the MSI-X event interrupt status */ |
| 2063 | |
Sarah Sharp | c21599a | 2010-07-29 22:13:00 -0700 | [diff] [blame^] | 2064 | if (hcd->irq != -1) { |
| 2065 | u32 irq_pending; |
| 2066 | /* Acknowledge the PCI interrupt */ |
| 2067 | irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending); |
| 2068 | irq_pending |= 0x3; |
| 2069 | xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending); |
| 2070 | } |
Sarah Sharp | bda5314 | 2010-07-29 22:12:38 -0700 | [diff] [blame] | 2071 | |
Sarah Sharp | c06d68b | 2010-07-29 22:12:49 -0700 | [diff] [blame] | 2072 | if (xhci->xhc_state & XHCI_STATE_DYING) { |
Sarah Sharp | bda5314 | 2010-07-29 22:12:38 -0700 | [diff] [blame] | 2073 | xhci_dbg(xhci, "xHCI dying, ignoring interrupt. " |
| 2074 | "Shouldn't IRQs be disabled?\n"); |
Sarah Sharp | c06d68b | 2010-07-29 22:12:49 -0700 | [diff] [blame] | 2075 | /* Clear the event handler busy flag (RW1C); |
| 2076 | * the event ring should be empty. |
Sarah Sharp | bda5314 | 2010-07-29 22:12:38 -0700 | [diff] [blame] | 2077 | */ |
Sarah Sharp | c06d68b | 2010-07-29 22:12:49 -0700 | [diff] [blame] | 2078 | temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
| 2079 | xhci_write_64(xhci, temp_64 | ERST_EHB, |
| 2080 | &xhci->ir_set->erst_dequeue); |
| 2081 | spin_unlock(&xhci->lock); |
| 2082 | |
| 2083 | return IRQ_HANDLED; |
| 2084 | } |
| 2085 | |
| 2086 | event_ring_deq = xhci->event_ring->dequeue; |
| 2087 | /* FIXME this should be a delayed service routine |
| 2088 | * that clears the EHB. |
| 2089 | */ |
| 2090 | xhci_handle_event(xhci); |
| 2091 | |
| 2092 | temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
| 2093 | /* If necessary, update the HW's version of the event ring deq ptr. */ |
| 2094 | if (event_ring_deq != xhci->event_ring->dequeue) { |
| 2095 | deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, |
| 2096 | xhci->event_ring->dequeue); |
| 2097 | if (deq == 0) |
| 2098 | xhci_warn(xhci, "WARN something wrong with SW event " |
| 2099 | "ring dequeue ptr.\n"); |
| 2100 | /* Update HC event ring dequeue pointer */ |
| 2101 | temp_64 &= ERST_PTR_MASK; |
| 2102 | temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK); |
| 2103 | } |
Sarah Sharp | bda5314 | 2010-07-29 22:12:38 -0700 | [diff] [blame] | 2104 | |
| 2105 | /* Clear the event handler busy flag (RW1C); event ring is empty. */ |
Sarah Sharp | c06d68b | 2010-07-29 22:12:49 -0700 | [diff] [blame] | 2106 | temp_64 |= ERST_EHB; |
| 2107 | xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue); |
| 2108 | |
Sarah Sharp | 9032cd5 | 2010-07-29 22:12:29 -0700 | [diff] [blame] | 2109 | spin_unlock(&xhci->lock); |
| 2110 | |
| 2111 | return IRQ_HANDLED; |
| 2112 | } |
| 2113 | |
| 2114 | irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd) |
| 2115 | { |
| 2116 | irqreturn_t ret; |
| 2117 | |
| 2118 | set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags); |
| 2119 | |
| 2120 | ret = xhci_irq(hcd); |
| 2121 | |
| 2122 | return ret; |
| 2123 | } |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 2124 | |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2125 | /**** Endpoint Ring Operations ****/ |
| 2126 | |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 2127 | /* |
| 2128 | * Generic function for queueing a TRB on a ring. |
| 2129 | * The caller must have checked to make sure there's room on the ring. |
Sarah Sharp | 6cc30d8 | 2010-06-10 12:25:28 -0700 | [diff] [blame] | 2130 | * |
| 2131 | * @more_trbs_coming: Will you enqueue more TRBs before calling |
| 2132 | * prepare_transfer()? |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 2133 | */ |
| 2134 | static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring, |
Sarah Sharp | 6cc30d8 | 2010-06-10 12:25:28 -0700 | [diff] [blame] | 2135 | bool consumer, bool more_trbs_coming, |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 2136 | u32 field1, u32 field2, u32 field3, u32 field4) |
| 2137 | { |
| 2138 | struct xhci_generic_trb *trb; |
| 2139 | |
| 2140 | trb = &ring->enqueue->generic; |
| 2141 | trb->field[0] = field1; |
| 2142 | trb->field[1] = field2; |
| 2143 | trb->field[2] = field3; |
| 2144 | trb->field[3] = field4; |
Sarah Sharp | 6cc30d8 | 2010-06-10 12:25:28 -0700 | [diff] [blame] | 2145 | inc_enq(xhci, ring, consumer, more_trbs_coming); |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 2146 | } |
| 2147 | |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2148 | /* |
| 2149 | * Does various checks on the endpoint ring, and makes it ready to queue num_trbs. |
| 2150 | * FIXME allocate segments if the ring is full. |
| 2151 | */ |
| 2152 | static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, |
| 2153 | u32 ep_state, unsigned int num_trbs, gfp_t mem_flags) |
| 2154 | { |
| 2155 | /* Make sure the endpoint has been added to xHC schedule */ |
| 2156 | xhci_dbg(xhci, "Endpoint state = 0x%x\n", ep_state); |
| 2157 | switch (ep_state) { |
| 2158 | case EP_STATE_DISABLED: |
| 2159 | /* |
| 2160 | * USB core changed config/interfaces without notifying us, |
| 2161 | * or hardware is reporting the wrong state. |
| 2162 | */ |
| 2163 | xhci_warn(xhci, "WARN urb submitted to disabled ep\n"); |
| 2164 | return -ENOENT; |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2165 | case EP_STATE_ERROR: |
Sarah Sharp | c92bcfa | 2009-07-27 12:05:21 -0700 | [diff] [blame] | 2166 | xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n"); |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2167 | /* FIXME event handling code for error needs to clear it */ |
| 2168 | /* XXX not sure if this should be -ENOENT or not */ |
| 2169 | return -EINVAL; |
Sarah Sharp | c92bcfa | 2009-07-27 12:05:21 -0700 | [diff] [blame] | 2170 | case EP_STATE_HALTED: |
| 2171 | xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n"); |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2172 | case EP_STATE_STOPPED: |
| 2173 | case EP_STATE_RUNNING: |
| 2174 | break; |
| 2175 | default: |
| 2176 | xhci_err(xhci, "ERROR unknown endpoint state for ep\n"); |
| 2177 | /* |
| 2178 | * FIXME issue Configure Endpoint command to try to get the HC |
| 2179 | * back into a known state. |
| 2180 | */ |
| 2181 | return -EINVAL; |
| 2182 | } |
| 2183 | if (!room_on_ring(xhci, ep_ring, num_trbs)) { |
| 2184 | /* FIXME allocate more room */ |
| 2185 | xhci_err(xhci, "ERROR no room on ep ring\n"); |
| 2186 | return -ENOMEM; |
| 2187 | } |
John Youn | 6c12db9 | 2010-05-10 15:33:00 -0700 | [diff] [blame] | 2188 | |
| 2189 | if (enqueue_is_link_trb(ep_ring)) { |
| 2190 | struct xhci_ring *ring = ep_ring; |
| 2191 | union xhci_trb *next; |
John Youn | 6c12db9 | 2010-05-10 15:33:00 -0700 | [diff] [blame] | 2192 | |
| 2193 | xhci_dbg(xhci, "prepare_ring: pointing to link trb\n"); |
| 2194 | next = ring->enqueue; |
| 2195 | |
| 2196 | while (last_trb(xhci, ring, ring->enq_seg, next)) { |
| 2197 | |
| 2198 | /* If we're not dealing with 0.95 hardware, |
| 2199 | * clear the chain bit. |
| 2200 | */ |
| 2201 | if (!xhci_link_trb_quirk(xhci)) |
| 2202 | next->link.control &= ~TRB_CHAIN; |
| 2203 | else |
| 2204 | next->link.control |= TRB_CHAIN; |
| 2205 | |
| 2206 | wmb(); |
| 2207 | next->link.control ^= (u32) TRB_CYCLE; |
| 2208 | |
| 2209 | /* Toggle the cycle bit after the last ring segment. */ |
| 2210 | if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) { |
| 2211 | ring->cycle_state = (ring->cycle_state ? 0 : 1); |
| 2212 | if (!in_interrupt()) { |
| 2213 | xhci_dbg(xhci, "queue_trb: Toggle cycle " |
| 2214 | "state for ring %p = %i\n", |
| 2215 | ring, (unsigned int)ring->cycle_state); |
| 2216 | } |
| 2217 | } |
| 2218 | ring->enq_seg = ring->enq_seg->next; |
| 2219 | ring->enqueue = ring->enq_seg->trbs; |
| 2220 | next = ring->enqueue; |
| 2221 | } |
| 2222 | } |
| 2223 | |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2224 | return 0; |
| 2225 | } |
| 2226 | |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 2227 | static int prepare_transfer(struct xhci_hcd *xhci, |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2228 | struct xhci_virt_device *xdev, |
| 2229 | unsigned int ep_index, |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 2230 | unsigned int stream_id, |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2231 | unsigned int num_trbs, |
| 2232 | struct urb *urb, |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 2233 | unsigned int td_index, |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2234 | gfp_t mem_flags) |
| 2235 | { |
| 2236 | int ret; |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 2237 | struct urb_priv *urb_priv; |
| 2238 | struct xhci_td *td; |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 2239 | struct xhci_ring *ep_ring; |
John Youn | d115b04 | 2009-07-27 12:05:15 -0700 | [diff] [blame] | 2240 | struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 2241 | |
| 2242 | ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id); |
| 2243 | if (!ep_ring) { |
| 2244 | xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n", |
| 2245 | stream_id); |
| 2246 | return -EINVAL; |
| 2247 | } |
| 2248 | |
| 2249 | ret = prepare_ring(xhci, ep_ring, |
John Youn | d115b04 | 2009-07-27 12:05:15 -0700 | [diff] [blame] | 2250 | ep_ctx->ep_info & EP_STATE_MASK, |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2251 | num_trbs, mem_flags); |
| 2252 | if (ret) |
| 2253 | return ret; |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2254 | |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 2255 | urb_priv = urb->hcpriv; |
| 2256 | td = urb_priv->td[td_index]; |
| 2257 | |
| 2258 | INIT_LIST_HEAD(&td->td_list); |
| 2259 | INIT_LIST_HEAD(&td->cancelled_td_list); |
| 2260 | |
| 2261 | if (td_index == 0) { |
| 2262 | ret = usb_hcd_link_urb_to_ep(xhci_to_hcd(xhci), urb); |
| 2263 | if (unlikely(ret)) { |
| 2264 | xhci_urb_free_priv(xhci, urb_priv); |
| 2265 | urb->hcpriv = NULL; |
| 2266 | return ret; |
| 2267 | } |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2268 | } |
| 2269 | |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 2270 | td->urb = urb; |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2271 | /* Add this TD to the tail of the endpoint ring's TD list */ |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 2272 | list_add_tail(&td->td_list, &ep_ring->td_list); |
| 2273 | td->start_seg = ep_ring->enq_seg; |
| 2274 | td->first_trb = ep_ring->enqueue; |
| 2275 | |
| 2276 | urb_priv->td[td_index] = td; |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2277 | |
| 2278 | return 0; |
| 2279 | } |
| 2280 | |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 2281 | static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb) |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2282 | { |
| 2283 | int num_sgs, num_trbs, running_total, temp, i; |
| 2284 | struct scatterlist *sg; |
| 2285 | |
| 2286 | sg = NULL; |
| 2287 | num_sgs = urb->num_sgs; |
| 2288 | temp = urb->transfer_buffer_length; |
| 2289 | |
| 2290 | xhci_dbg(xhci, "count sg list trbs: \n"); |
| 2291 | num_trbs = 0; |
Matthew Wilcox | 910f8d0 | 2010-05-01 12:20:01 -0600 | [diff] [blame] | 2292 | for_each_sg(urb->sg, sg, num_sgs, i) { |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2293 | unsigned int previous_total_trbs = num_trbs; |
| 2294 | unsigned int len = sg_dma_len(sg); |
| 2295 | |
| 2296 | /* Scatter gather list entries may cross 64KB boundaries */ |
| 2297 | running_total = TRB_MAX_BUFF_SIZE - |
| 2298 | (sg_dma_address(sg) & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); |
| 2299 | if (running_total != 0) |
| 2300 | num_trbs++; |
| 2301 | |
| 2302 | /* How many more 64KB chunks to transfer, how many more TRBs? */ |
| 2303 | while (running_total < sg_dma_len(sg)) { |
| 2304 | num_trbs++; |
| 2305 | running_total += TRB_MAX_BUFF_SIZE; |
| 2306 | } |
Greg Kroah-Hartman | 700e205 | 2009-04-29 19:14:08 -0700 | [diff] [blame] | 2307 | xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n", |
| 2308 | i, (unsigned long long)sg_dma_address(sg), |
| 2309 | len, len, num_trbs - previous_total_trbs); |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2310 | |
| 2311 | len = min_t(int, len, temp); |
| 2312 | temp -= len; |
| 2313 | if (temp == 0) |
| 2314 | break; |
| 2315 | } |
| 2316 | xhci_dbg(xhci, "\n"); |
| 2317 | if (!in_interrupt()) |
| 2318 | dev_dbg(&urb->dev->dev, "ep %#x - urb len = %d, sglist used, num_trbs = %d\n", |
| 2319 | urb->ep->desc.bEndpointAddress, |
| 2320 | urb->transfer_buffer_length, |
| 2321 | num_trbs); |
| 2322 | return num_trbs; |
| 2323 | } |
| 2324 | |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 2325 | static void check_trb_math(struct urb *urb, int num_trbs, int running_total) |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2326 | { |
| 2327 | if (num_trbs != 0) |
| 2328 | dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated number of " |
| 2329 | "TRBs, %d left\n", __func__, |
| 2330 | urb->ep->desc.bEndpointAddress, num_trbs); |
| 2331 | if (running_total != urb->transfer_buffer_length) |
| 2332 | dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, " |
| 2333 | "queued %#x (%d), asked for %#x (%d)\n", |
| 2334 | __func__, |
| 2335 | urb->ep->desc.bEndpointAddress, |
| 2336 | running_total, running_total, |
| 2337 | urb->transfer_buffer_length, |
| 2338 | urb->transfer_buffer_length); |
| 2339 | } |
| 2340 | |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 2341 | static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id, |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 2342 | unsigned int ep_index, unsigned int stream_id, int start_cycle, |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2343 | struct xhci_generic_trb *start_trb, struct xhci_td *td) |
| 2344 | { |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2345 | /* |
| 2346 | * Pass all the TRBs to the hardware at once and make sure this write |
| 2347 | * isn't reordered. |
| 2348 | */ |
| 2349 | wmb(); |
| 2350 | start_trb->field[3] |= start_cycle; |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 2351 | ring_ep_doorbell(xhci, slot_id, ep_index, stream_id); |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2352 | } |
| 2353 | |
Sarah Sharp | 624defa | 2009-09-02 12:14:28 -0700 | [diff] [blame] | 2354 | /* |
| 2355 | * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt |
| 2356 | * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD |
| 2357 | * (comprised of sg list entries) can take several service intervals to |
| 2358 | * transmit. |
| 2359 | */ |
| 2360 | int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
| 2361 | struct urb *urb, int slot_id, unsigned int ep_index) |
| 2362 | { |
| 2363 | struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, |
| 2364 | xhci->devs[slot_id]->out_ctx, ep_index); |
| 2365 | int xhci_interval; |
| 2366 | int ep_interval; |
| 2367 | |
| 2368 | xhci_interval = EP_INTERVAL_TO_UFRAMES(ep_ctx->ep_info); |
| 2369 | ep_interval = urb->interval; |
| 2370 | /* Convert to microframes */ |
| 2371 | if (urb->dev->speed == USB_SPEED_LOW || |
| 2372 | urb->dev->speed == USB_SPEED_FULL) |
| 2373 | ep_interval *= 8; |
| 2374 | /* FIXME change this to a warning and a suggestion to use the new API |
| 2375 | * to set the polling interval (once the API is added). |
| 2376 | */ |
| 2377 | if (xhci_interval != ep_interval) { |
| 2378 | if (!printk_ratelimit()) |
| 2379 | dev_dbg(&urb->dev->dev, "Driver uses different interval" |
| 2380 | " (%d microframe%s) than xHCI " |
| 2381 | "(%d microframe%s)\n", |
| 2382 | ep_interval, |
| 2383 | ep_interval == 1 ? "" : "s", |
| 2384 | xhci_interval, |
| 2385 | xhci_interval == 1 ? "" : "s"); |
| 2386 | urb->interval = xhci_interval; |
| 2387 | /* Convert back to frames for LS/FS devices */ |
| 2388 | if (urb->dev->speed == USB_SPEED_LOW || |
| 2389 | urb->dev->speed == USB_SPEED_FULL) |
| 2390 | urb->interval /= 8; |
| 2391 | } |
| 2392 | return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index); |
| 2393 | } |
| 2394 | |
Sarah Sharp | 04dd950 | 2009-11-11 10:28:30 -0800 | [diff] [blame] | 2395 | /* |
| 2396 | * The TD size is the number of bytes remaining in the TD (including this TRB), |
| 2397 | * right shifted by 10. |
| 2398 | * It must fit in bits 21:17, so it can't be bigger than 31. |
| 2399 | */ |
| 2400 | static u32 xhci_td_remainder(unsigned int remainder) |
| 2401 | { |
| 2402 | u32 max = (1 << (21 - 17 + 1)) - 1; |
| 2403 | |
| 2404 | if ((remainder >> 10) >= max) |
| 2405 | return max << 17; |
| 2406 | else |
| 2407 | return (remainder >> 10) << 17; |
| 2408 | } |
| 2409 | |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 2410 | static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2411 | struct urb *urb, int slot_id, unsigned int ep_index) |
| 2412 | { |
| 2413 | struct xhci_ring *ep_ring; |
| 2414 | unsigned int num_trbs; |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 2415 | struct urb_priv *urb_priv; |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2416 | struct xhci_td *td; |
| 2417 | struct scatterlist *sg; |
| 2418 | int num_sgs; |
| 2419 | int trb_buff_len, this_sg_len, running_total; |
| 2420 | bool first_trb; |
| 2421 | u64 addr; |
Sarah Sharp | 6cc30d8 | 2010-06-10 12:25:28 -0700 | [diff] [blame] | 2422 | bool more_trbs_coming; |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2423 | |
| 2424 | struct xhci_generic_trb *start_trb; |
| 2425 | int start_cycle; |
| 2426 | |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 2427 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); |
| 2428 | if (!ep_ring) |
| 2429 | return -EINVAL; |
| 2430 | |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2431 | num_trbs = count_sg_trbs_needed(xhci, urb); |
| 2432 | num_sgs = urb->num_sgs; |
| 2433 | |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 2434 | trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id], |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 2435 | ep_index, urb->stream_id, |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 2436 | num_trbs, urb, 0, mem_flags); |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2437 | if (trb_buff_len < 0) |
| 2438 | return trb_buff_len; |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 2439 | |
| 2440 | urb_priv = urb->hcpriv; |
| 2441 | td = urb_priv->td[0]; |
| 2442 | |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2443 | /* |
| 2444 | * Don't give the first TRB to the hardware (by toggling the cycle bit) |
| 2445 | * until we've finished creating all the other TRBs. The ring's cycle |
| 2446 | * state may change as we enqueue the other TRBs, so save it too. |
| 2447 | */ |
| 2448 | start_trb = &ep_ring->enqueue->generic; |
| 2449 | start_cycle = ep_ring->cycle_state; |
| 2450 | |
| 2451 | running_total = 0; |
| 2452 | /* |
| 2453 | * How much data is in the first TRB? |
| 2454 | * |
| 2455 | * There are three forces at work for TRB buffer pointers and lengths: |
| 2456 | * 1. We don't want to walk off the end of this sg-list entry buffer. |
| 2457 | * 2. The transfer length that the driver requested may be smaller than |
| 2458 | * the amount of memory allocated for this scatter-gather list. |
| 2459 | * 3. TRBs buffers can't cross 64KB boundaries. |
| 2460 | */ |
Matthew Wilcox | 910f8d0 | 2010-05-01 12:20:01 -0600 | [diff] [blame] | 2461 | sg = urb->sg; |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2462 | addr = (u64) sg_dma_address(sg); |
| 2463 | this_sg_len = sg_dma_len(sg); |
| 2464 | trb_buff_len = TRB_MAX_BUFF_SIZE - |
| 2465 | (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); |
| 2466 | trb_buff_len = min_t(int, trb_buff_len, this_sg_len); |
| 2467 | if (trb_buff_len > urb->transfer_buffer_length) |
| 2468 | trb_buff_len = urb->transfer_buffer_length; |
| 2469 | xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n", |
| 2470 | trb_buff_len); |
| 2471 | |
| 2472 | first_trb = true; |
| 2473 | /* Queue the first TRB, even if it's zero-length */ |
| 2474 | do { |
| 2475 | u32 field = 0; |
Sarah Sharp | f9dc68f | 2009-07-27 12:03:07 -0700 | [diff] [blame] | 2476 | u32 length_field = 0; |
Sarah Sharp | 04dd950 | 2009-11-11 10:28:30 -0800 | [diff] [blame] | 2477 | u32 remainder = 0; |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2478 | |
| 2479 | /* Don't change the cycle bit of the first TRB until later */ |
| 2480 | if (first_trb) |
| 2481 | first_trb = false; |
| 2482 | else |
| 2483 | field |= ep_ring->cycle_state; |
| 2484 | |
| 2485 | /* Chain all the TRBs together; clear the chain bit in the last |
| 2486 | * TRB to indicate it's the last TRB in the chain. |
| 2487 | */ |
| 2488 | if (num_trbs > 1) { |
| 2489 | field |= TRB_CHAIN; |
| 2490 | } else { |
| 2491 | /* FIXME - add check for ZERO_PACKET flag before this */ |
| 2492 | td->last_trb = ep_ring->enqueue; |
| 2493 | field |= TRB_IOC; |
| 2494 | } |
| 2495 | xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), " |
| 2496 | "64KB boundary at %#x, end dma = %#x\n", |
| 2497 | (unsigned int) addr, trb_buff_len, trb_buff_len, |
| 2498 | (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1), |
| 2499 | (unsigned int) addr + trb_buff_len); |
| 2500 | if (TRB_MAX_BUFF_SIZE - |
| 2501 | (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)) < trb_buff_len) { |
| 2502 | xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n"); |
| 2503 | xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n", |
| 2504 | (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1), |
| 2505 | (unsigned int) addr + trb_buff_len); |
| 2506 | } |
Sarah Sharp | 04dd950 | 2009-11-11 10:28:30 -0800 | [diff] [blame] | 2507 | remainder = xhci_td_remainder(urb->transfer_buffer_length - |
| 2508 | running_total) ; |
Sarah Sharp | f9dc68f | 2009-07-27 12:03:07 -0700 | [diff] [blame] | 2509 | length_field = TRB_LEN(trb_buff_len) | |
Sarah Sharp | 04dd950 | 2009-11-11 10:28:30 -0800 | [diff] [blame] | 2510 | remainder | |
Sarah Sharp | f9dc68f | 2009-07-27 12:03:07 -0700 | [diff] [blame] | 2511 | TRB_INTR_TARGET(0); |
Sarah Sharp | 6cc30d8 | 2010-06-10 12:25:28 -0700 | [diff] [blame] | 2512 | if (num_trbs > 1) |
| 2513 | more_trbs_coming = true; |
| 2514 | else |
| 2515 | more_trbs_coming = false; |
| 2516 | queue_trb(xhci, ep_ring, false, more_trbs_coming, |
Sarah Sharp | 8e595a5 | 2009-07-27 12:03:31 -0700 | [diff] [blame] | 2517 | lower_32_bits(addr), |
| 2518 | upper_32_bits(addr), |
Sarah Sharp | f9dc68f | 2009-07-27 12:03:07 -0700 | [diff] [blame] | 2519 | length_field, |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2520 | /* We always want to know if the TRB was short, |
| 2521 | * or we won't get an event when it completes. |
| 2522 | * (Unless we use event data TRBs, which are a |
| 2523 | * waste of space and HC resources.) |
| 2524 | */ |
| 2525 | field | TRB_ISP | TRB_TYPE(TRB_NORMAL)); |
| 2526 | --num_trbs; |
| 2527 | running_total += trb_buff_len; |
| 2528 | |
| 2529 | /* Calculate length for next transfer -- |
| 2530 | * Are we done queueing all the TRBs for this sg entry? |
| 2531 | */ |
| 2532 | this_sg_len -= trb_buff_len; |
| 2533 | if (this_sg_len == 0) { |
| 2534 | --num_sgs; |
| 2535 | if (num_sgs == 0) |
| 2536 | break; |
| 2537 | sg = sg_next(sg); |
| 2538 | addr = (u64) sg_dma_address(sg); |
| 2539 | this_sg_len = sg_dma_len(sg); |
| 2540 | } else { |
| 2541 | addr += trb_buff_len; |
| 2542 | } |
| 2543 | |
| 2544 | trb_buff_len = TRB_MAX_BUFF_SIZE - |
| 2545 | (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); |
| 2546 | trb_buff_len = min_t(int, trb_buff_len, this_sg_len); |
| 2547 | if (running_total + trb_buff_len > urb->transfer_buffer_length) |
| 2548 | trb_buff_len = |
| 2549 | urb->transfer_buffer_length - running_total; |
| 2550 | } while (running_total < urb->transfer_buffer_length); |
| 2551 | |
| 2552 | check_trb_math(urb, num_trbs, running_total); |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 2553 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
| 2554 | start_cycle, start_trb, td); |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2555 | return 0; |
| 2556 | } |
| 2557 | |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 2558 | /* This is very similar to what ehci-q.c qtd_fill() does */ |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 2559 | int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 2560 | struct urb *urb, int slot_id, unsigned int ep_index) |
| 2561 | { |
| 2562 | struct xhci_ring *ep_ring; |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 2563 | struct urb_priv *urb_priv; |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 2564 | struct xhci_td *td; |
| 2565 | int num_trbs; |
| 2566 | struct xhci_generic_trb *start_trb; |
| 2567 | bool first_trb; |
Sarah Sharp | 6cc30d8 | 2010-06-10 12:25:28 -0700 | [diff] [blame] | 2568 | bool more_trbs_coming; |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 2569 | int start_cycle; |
Sarah Sharp | f9dc68f | 2009-07-27 12:03:07 -0700 | [diff] [blame] | 2570 | u32 field, length_field; |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 2571 | |
| 2572 | int running_total, trb_buff_len, ret; |
| 2573 | u64 addr; |
| 2574 | |
Alan Stern | ff9c895 | 2010-04-02 13:27:28 -0400 | [diff] [blame] | 2575 | if (urb->num_sgs) |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2576 | return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index); |
| 2577 | |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 2578 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); |
| 2579 | if (!ep_ring) |
| 2580 | return -EINVAL; |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 2581 | |
| 2582 | num_trbs = 0; |
| 2583 | /* How much data is (potentially) left before the 64KB boundary? */ |
| 2584 | running_total = TRB_MAX_BUFF_SIZE - |
| 2585 | (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); |
| 2586 | |
| 2587 | /* If there's some data on this 64KB chunk, or we have to send a |
| 2588 | * zero-length transfer, we need at least one TRB |
| 2589 | */ |
| 2590 | if (running_total != 0 || urb->transfer_buffer_length == 0) |
| 2591 | num_trbs++; |
| 2592 | /* How many more 64KB chunks to transfer, how many more TRBs? */ |
| 2593 | while (running_total < urb->transfer_buffer_length) { |
| 2594 | num_trbs++; |
| 2595 | running_total += TRB_MAX_BUFF_SIZE; |
| 2596 | } |
| 2597 | /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */ |
| 2598 | |
| 2599 | if (!in_interrupt()) |
Greg Kroah-Hartman | 700e205 | 2009-04-29 19:14:08 -0700 | [diff] [blame] | 2600 | dev_dbg(&urb->dev->dev, "ep %#x - urb len = %#x (%d), addr = %#llx, num_trbs = %d\n", |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 2601 | urb->ep->desc.bEndpointAddress, |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2602 | urb->transfer_buffer_length, |
| 2603 | urb->transfer_buffer_length, |
Greg Kroah-Hartman | 700e205 | 2009-04-29 19:14:08 -0700 | [diff] [blame] | 2604 | (unsigned long long)urb->transfer_dma, |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 2605 | num_trbs); |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2606 | |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 2607 | ret = prepare_transfer(xhci, xhci->devs[slot_id], |
| 2608 | ep_index, urb->stream_id, |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 2609 | num_trbs, urb, 0, mem_flags); |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 2610 | if (ret < 0) |
| 2611 | return ret; |
| 2612 | |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 2613 | urb_priv = urb->hcpriv; |
| 2614 | td = urb_priv->td[0]; |
| 2615 | |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 2616 | /* |
| 2617 | * Don't give the first TRB to the hardware (by toggling the cycle bit) |
| 2618 | * until we've finished creating all the other TRBs. The ring's cycle |
| 2619 | * state may change as we enqueue the other TRBs, so save it too. |
| 2620 | */ |
| 2621 | start_trb = &ep_ring->enqueue->generic; |
| 2622 | start_cycle = ep_ring->cycle_state; |
| 2623 | |
| 2624 | running_total = 0; |
| 2625 | /* How much data is in the first TRB? */ |
| 2626 | addr = (u64) urb->transfer_dma; |
| 2627 | trb_buff_len = TRB_MAX_BUFF_SIZE - |
| 2628 | (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); |
| 2629 | if (urb->transfer_buffer_length < trb_buff_len) |
| 2630 | trb_buff_len = urb->transfer_buffer_length; |
| 2631 | |
| 2632 | first_trb = true; |
| 2633 | |
| 2634 | /* Queue the first TRB, even if it's zero-length */ |
| 2635 | do { |
Sarah Sharp | 04dd950 | 2009-11-11 10:28:30 -0800 | [diff] [blame] | 2636 | u32 remainder = 0; |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 2637 | field = 0; |
| 2638 | |
| 2639 | /* Don't change the cycle bit of the first TRB until later */ |
| 2640 | if (first_trb) |
| 2641 | first_trb = false; |
| 2642 | else |
| 2643 | field |= ep_ring->cycle_state; |
| 2644 | |
| 2645 | /* Chain all the TRBs together; clear the chain bit in the last |
| 2646 | * TRB to indicate it's the last TRB in the chain. |
| 2647 | */ |
| 2648 | if (num_trbs > 1) { |
| 2649 | field |= TRB_CHAIN; |
| 2650 | } else { |
| 2651 | /* FIXME - add check for ZERO_PACKET flag before this */ |
| 2652 | td->last_trb = ep_ring->enqueue; |
| 2653 | field |= TRB_IOC; |
| 2654 | } |
Sarah Sharp | 04dd950 | 2009-11-11 10:28:30 -0800 | [diff] [blame] | 2655 | remainder = xhci_td_remainder(urb->transfer_buffer_length - |
| 2656 | running_total); |
Sarah Sharp | f9dc68f | 2009-07-27 12:03:07 -0700 | [diff] [blame] | 2657 | length_field = TRB_LEN(trb_buff_len) | |
Sarah Sharp | 04dd950 | 2009-11-11 10:28:30 -0800 | [diff] [blame] | 2658 | remainder | |
Sarah Sharp | f9dc68f | 2009-07-27 12:03:07 -0700 | [diff] [blame] | 2659 | TRB_INTR_TARGET(0); |
Sarah Sharp | 6cc30d8 | 2010-06-10 12:25:28 -0700 | [diff] [blame] | 2660 | if (num_trbs > 1) |
| 2661 | more_trbs_coming = true; |
| 2662 | else |
| 2663 | more_trbs_coming = false; |
| 2664 | queue_trb(xhci, ep_ring, false, more_trbs_coming, |
Sarah Sharp | 8e595a5 | 2009-07-27 12:03:31 -0700 | [diff] [blame] | 2665 | lower_32_bits(addr), |
| 2666 | upper_32_bits(addr), |
Sarah Sharp | f9dc68f | 2009-07-27 12:03:07 -0700 | [diff] [blame] | 2667 | length_field, |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 2668 | /* We always want to know if the TRB was short, |
| 2669 | * or we won't get an event when it completes. |
| 2670 | * (Unless we use event data TRBs, which are a |
| 2671 | * waste of space and HC resources.) |
| 2672 | */ |
| 2673 | field | TRB_ISP | TRB_TYPE(TRB_NORMAL)); |
| 2674 | --num_trbs; |
| 2675 | running_total += trb_buff_len; |
| 2676 | |
| 2677 | /* Calculate length for next transfer */ |
| 2678 | addr += trb_buff_len; |
| 2679 | trb_buff_len = urb->transfer_buffer_length - running_total; |
| 2680 | if (trb_buff_len > TRB_MAX_BUFF_SIZE) |
| 2681 | trb_buff_len = TRB_MAX_BUFF_SIZE; |
| 2682 | } while (running_total < urb->transfer_buffer_length); |
| 2683 | |
Sarah Sharp | 8a96c05 | 2009-04-27 19:59:19 -0700 | [diff] [blame] | 2684 | check_trb_math(urb, num_trbs, running_total); |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 2685 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
| 2686 | start_cycle, start_trb, td); |
Sarah Sharp | b10de14 | 2009-04-27 19:58:50 -0700 | [diff] [blame] | 2687 | return 0; |
| 2688 | } |
| 2689 | |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2690 | /* Caller must have locked xhci->lock */ |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 2691 | int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2692 | struct urb *urb, int slot_id, unsigned int ep_index) |
| 2693 | { |
| 2694 | struct xhci_ring *ep_ring; |
| 2695 | int num_trbs; |
| 2696 | int ret; |
| 2697 | struct usb_ctrlrequest *setup; |
| 2698 | struct xhci_generic_trb *start_trb; |
| 2699 | int start_cycle; |
Sarah Sharp | f9dc68f | 2009-07-27 12:03:07 -0700 | [diff] [blame] | 2700 | u32 field, length_field; |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 2701 | struct urb_priv *urb_priv; |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2702 | struct xhci_td *td; |
| 2703 | |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 2704 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); |
| 2705 | if (!ep_ring) |
| 2706 | return -EINVAL; |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2707 | |
| 2708 | /* |
| 2709 | * Need to copy setup packet into setup TRB, so we can't use the setup |
| 2710 | * DMA address. |
| 2711 | */ |
| 2712 | if (!urb->setup_packet) |
| 2713 | return -EINVAL; |
| 2714 | |
| 2715 | if (!in_interrupt()) |
| 2716 | xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n", |
| 2717 | slot_id, ep_index); |
| 2718 | /* 1 TRB for setup, 1 for status */ |
| 2719 | num_trbs = 2; |
| 2720 | /* |
| 2721 | * Don't need to check if we need additional event data and normal TRBs, |
| 2722 | * since data in control transfers will never get bigger than 16MB |
| 2723 | * XXX: can we get a buffer that crosses 64KB boundaries? |
| 2724 | */ |
| 2725 | if (urb->transfer_buffer_length > 0) |
| 2726 | num_trbs++; |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 2727 | ret = prepare_transfer(xhci, xhci->devs[slot_id], |
| 2728 | ep_index, urb->stream_id, |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 2729 | num_trbs, urb, 0, mem_flags); |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2730 | if (ret < 0) |
| 2731 | return ret; |
| 2732 | |
Andiry Xu | 8e51adc | 2010-07-22 15:23:31 -0700 | [diff] [blame] | 2733 | urb_priv = urb->hcpriv; |
| 2734 | td = urb_priv->td[0]; |
| 2735 | |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2736 | /* |
| 2737 | * Don't give the first TRB to the hardware (by toggling the cycle bit) |
| 2738 | * until we've finished creating all the other TRBs. The ring's cycle |
| 2739 | * state may change as we enqueue the other TRBs, so save it too. |
| 2740 | */ |
| 2741 | start_trb = &ep_ring->enqueue->generic; |
| 2742 | start_cycle = ep_ring->cycle_state; |
| 2743 | |
| 2744 | /* Queue setup TRB - see section 6.4.1.2.1 */ |
| 2745 | /* FIXME better way to translate setup_packet into two u32 fields? */ |
| 2746 | setup = (struct usb_ctrlrequest *) urb->setup_packet; |
Sarah Sharp | 6cc30d8 | 2010-06-10 12:25:28 -0700 | [diff] [blame] | 2747 | queue_trb(xhci, ep_ring, false, true, |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2748 | /* FIXME endianness is probably going to bite my ass here. */ |
| 2749 | setup->bRequestType | setup->bRequest << 8 | setup->wValue << 16, |
| 2750 | setup->wIndex | setup->wLength << 16, |
| 2751 | TRB_LEN(8) | TRB_INTR_TARGET(0), |
| 2752 | /* Immediate data in pointer */ |
| 2753 | TRB_IDT | TRB_TYPE(TRB_SETUP)); |
| 2754 | |
| 2755 | /* If there's data, queue data TRBs */ |
| 2756 | field = 0; |
Sarah Sharp | f9dc68f | 2009-07-27 12:03:07 -0700 | [diff] [blame] | 2757 | length_field = TRB_LEN(urb->transfer_buffer_length) | |
Sarah Sharp | 04dd950 | 2009-11-11 10:28:30 -0800 | [diff] [blame] | 2758 | xhci_td_remainder(urb->transfer_buffer_length) | |
Sarah Sharp | f9dc68f | 2009-07-27 12:03:07 -0700 | [diff] [blame] | 2759 | TRB_INTR_TARGET(0); |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2760 | if (urb->transfer_buffer_length > 0) { |
| 2761 | if (setup->bRequestType & USB_DIR_IN) |
| 2762 | field |= TRB_DIR_IN; |
Sarah Sharp | 6cc30d8 | 2010-06-10 12:25:28 -0700 | [diff] [blame] | 2763 | queue_trb(xhci, ep_ring, false, true, |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2764 | lower_32_bits(urb->transfer_dma), |
| 2765 | upper_32_bits(urb->transfer_dma), |
Sarah Sharp | f9dc68f | 2009-07-27 12:03:07 -0700 | [diff] [blame] | 2766 | length_field, |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2767 | /* Event on short tx */ |
| 2768 | field | TRB_ISP | TRB_TYPE(TRB_DATA) | ep_ring->cycle_state); |
| 2769 | } |
| 2770 | |
| 2771 | /* Save the DMA address of the last TRB in the TD */ |
| 2772 | td->last_trb = ep_ring->enqueue; |
| 2773 | |
| 2774 | /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */ |
| 2775 | /* If the device sent data, the status stage is an OUT transfer */ |
| 2776 | if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN) |
| 2777 | field = 0; |
| 2778 | else |
| 2779 | field = TRB_DIR_IN; |
Sarah Sharp | 6cc30d8 | 2010-06-10 12:25:28 -0700 | [diff] [blame] | 2780 | queue_trb(xhci, ep_ring, false, false, |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2781 | 0, |
| 2782 | 0, |
| 2783 | TRB_INTR_TARGET(0), |
| 2784 | /* Event on completion */ |
| 2785 | field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state); |
| 2786 | |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 2787 | giveback_first_trb(xhci, slot_id, ep_index, 0, |
| 2788 | start_cycle, start_trb, td); |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 2789 | return 0; |
| 2790 | } |
| 2791 | |
Andiry Xu | 04e5190 | 2010-07-22 15:23:39 -0700 | [diff] [blame] | 2792 | static int count_isoc_trbs_needed(struct xhci_hcd *xhci, |
| 2793 | struct urb *urb, int i) |
| 2794 | { |
| 2795 | int num_trbs = 0; |
| 2796 | u64 addr, td_len, running_total; |
| 2797 | |
| 2798 | addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset); |
| 2799 | td_len = urb->iso_frame_desc[i].length; |
| 2800 | |
| 2801 | running_total = TRB_MAX_BUFF_SIZE - |
| 2802 | (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); |
| 2803 | if (running_total != 0) |
| 2804 | num_trbs++; |
| 2805 | |
| 2806 | while (running_total < td_len) { |
| 2807 | num_trbs++; |
| 2808 | running_total += TRB_MAX_BUFF_SIZE; |
| 2809 | } |
| 2810 | |
| 2811 | return num_trbs; |
| 2812 | } |
| 2813 | |
| 2814 | /* This is for isoc transfer */ |
| 2815 | static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
| 2816 | struct urb *urb, int slot_id, unsigned int ep_index) |
| 2817 | { |
| 2818 | struct xhci_ring *ep_ring; |
| 2819 | struct urb_priv *urb_priv; |
| 2820 | struct xhci_td *td; |
| 2821 | int num_tds, trbs_per_td; |
| 2822 | struct xhci_generic_trb *start_trb; |
| 2823 | bool first_trb; |
| 2824 | int start_cycle; |
| 2825 | u32 field, length_field; |
| 2826 | int running_total, trb_buff_len, td_len, td_remain_len, ret; |
| 2827 | u64 start_addr, addr; |
| 2828 | int i, j; |
| 2829 | |
| 2830 | ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; |
| 2831 | |
| 2832 | num_tds = urb->number_of_packets; |
| 2833 | if (num_tds < 1) { |
| 2834 | xhci_dbg(xhci, "Isoc URB with zero packets?\n"); |
| 2835 | return -EINVAL; |
| 2836 | } |
| 2837 | |
| 2838 | if (!in_interrupt()) |
| 2839 | dev_dbg(&urb->dev->dev, "ep %#x - urb len = %#x (%d)," |
| 2840 | " addr = %#llx, num_tds = %d\n", |
| 2841 | urb->ep->desc.bEndpointAddress, |
| 2842 | urb->transfer_buffer_length, |
| 2843 | urb->transfer_buffer_length, |
| 2844 | (unsigned long long)urb->transfer_dma, |
| 2845 | num_tds); |
| 2846 | |
| 2847 | start_addr = (u64) urb->transfer_dma; |
| 2848 | start_trb = &ep_ring->enqueue->generic; |
| 2849 | start_cycle = ep_ring->cycle_state; |
| 2850 | |
| 2851 | /* Queue the first TRB, even if it's zero-length */ |
| 2852 | for (i = 0; i < num_tds; i++) { |
| 2853 | first_trb = true; |
| 2854 | |
| 2855 | running_total = 0; |
| 2856 | addr = start_addr + urb->iso_frame_desc[i].offset; |
| 2857 | td_len = urb->iso_frame_desc[i].length; |
| 2858 | td_remain_len = td_len; |
| 2859 | |
| 2860 | trbs_per_td = count_isoc_trbs_needed(xhci, urb, i); |
| 2861 | |
| 2862 | ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index, |
| 2863 | urb->stream_id, trbs_per_td, urb, i, mem_flags); |
| 2864 | if (ret < 0) |
| 2865 | return ret; |
| 2866 | |
| 2867 | urb_priv = urb->hcpriv; |
| 2868 | td = urb_priv->td[i]; |
| 2869 | |
| 2870 | for (j = 0; j < trbs_per_td; j++) { |
| 2871 | u32 remainder = 0; |
| 2872 | field = 0; |
| 2873 | |
| 2874 | if (first_trb) { |
| 2875 | /* Queue the isoc TRB */ |
| 2876 | field |= TRB_TYPE(TRB_ISOC); |
| 2877 | /* Assume URB_ISO_ASAP is set */ |
| 2878 | field |= TRB_SIA; |
| 2879 | if (i > 0) |
| 2880 | field |= ep_ring->cycle_state; |
| 2881 | first_trb = false; |
| 2882 | } else { |
| 2883 | /* Queue other normal TRBs */ |
| 2884 | field |= TRB_TYPE(TRB_NORMAL); |
| 2885 | field |= ep_ring->cycle_state; |
| 2886 | } |
| 2887 | |
| 2888 | /* Chain all the TRBs together; clear the chain bit in |
| 2889 | * the last TRB to indicate it's the last TRB in the |
| 2890 | * chain. |
| 2891 | */ |
| 2892 | if (j < trbs_per_td - 1) { |
| 2893 | field |= TRB_CHAIN; |
| 2894 | } else { |
| 2895 | td->last_trb = ep_ring->enqueue; |
| 2896 | field |= TRB_IOC; |
| 2897 | } |
| 2898 | |
| 2899 | /* Calculate TRB length */ |
| 2900 | trb_buff_len = TRB_MAX_BUFF_SIZE - |
| 2901 | (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); |
| 2902 | if (trb_buff_len > td_remain_len) |
| 2903 | trb_buff_len = td_remain_len; |
| 2904 | |
| 2905 | remainder = xhci_td_remainder(td_len - running_total); |
| 2906 | length_field = TRB_LEN(trb_buff_len) | |
| 2907 | remainder | |
| 2908 | TRB_INTR_TARGET(0); |
| 2909 | queue_trb(xhci, ep_ring, false, false, |
| 2910 | lower_32_bits(addr), |
| 2911 | upper_32_bits(addr), |
| 2912 | length_field, |
| 2913 | /* We always want to know if the TRB was short, |
| 2914 | * or we won't get an event when it completes. |
| 2915 | * (Unless we use event data TRBs, which are a |
| 2916 | * waste of space and HC resources.) |
| 2917 | */ |
| 2918 | field | TRB_ISP); |
| 2919 | running_total += trb_buff_len; |
| 2920 | |
| 2921 | addr += trb_buff_len; |
| 2922 | td_remain_len -= trb_buff_len; |
| 2923 | } |
| 2924 | |
| 2925 | /* Check TD length */ |
| 2926 | if (running_total != td_len) { |
| 2927 | xhci_err(xhci, "ISOC TD length unmatch\n"); |
| 2928 | return -EINVAL; |
| 2929 | } |
| 2930 | } |
| 2931 | |
| 2932 | wmb(); |
| 2933 | start_trb->field[3] |= start_cycle; |
| 2934 | |
| 2935 | ring_ep_doorbell(xhci, slot_id, ep_index, urb->stream_id); |
| 2936 | return 0; |
| 2937 | } |
| 2938 | |
| 2939 | /* |
| 2940 | * Check transfer ring to guarantee there is enough room for the urb. |
| 2941 | * Update ISO URB start_frame and interval. |
| 2942 | * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to |
| 2943 | * update the urb->start_frame by now. |
| 2944 | * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input. |
| 2945 | */ |
| 2946 | int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, |
| 2947 | struct urb *urb, int slot_id, unsigned int ep_index) |
| 2948 | { |
| 2949 | struct xhci_virt_device *xdev; |
| 2950 | struct xhci_ring *ep_ring; |
| 2951 | struct xhci_ep_ctx *ep_ctx; |
| 2952 | int start_frame; |
| 2953 | int xhci_interval; |
| 2954 | int ep_interval; |
| 2955 | int num_tds, num_trbs, i; |
| 2956 | int ret; |
| 2957 | |
| 2958 | xdev = xhci->devs[slot_id]; |
| 2959 | ep_ring = xdev->eps[ep_index].ring; |
| 2960 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
| 2961 | |
| 2962 | num_trbs = 0; |
| 2963 | num_tds = urb->number_of_packets; |
| 2964 | for (i = 0; i < num_tds; i++) |
| 2965 | num_trbs += count_isoc_trbs_needed(xhci, urb, i); |
| 2966 | |
| 2967 | /* Check the ring to guarantee there is enough room for the whole urb. |
| 2968 | * Do not insert any td of the urb to the ring if the check failed. |
| 2969 | */ |
| 2970 | ret = prepare_ring(xhci, ep_ring, ep_ctx->ep_info & EP_STATE_MASK, |
| 2971 | num_trbs, mem_flags); |
| 2972 | if (ret) |
| 2973 | return ret; |
| 2974 | |
| 2975 | start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index); |
| 2976 | start_frame &= 0x3fff; |
| 2977 | |
| 2978 | urb->start_frame = start_frame; |
| 2979 | if (urb->dev->speed == USB_SPEED_LOW || |
| 2980 | urb->dev->speed == USB_SPEED_FULL) |
| 2981 | urb->start_frame >>= 3; |
| 2982 | |
| 2983 | xhci_interval = EP_INTERVAL_TO_UFRAMES(ep_ctx->ep_info); |
| 2984 | ep_interval = urb->interval; |
| 2985 | /* Convert to microframes */ |
| 2986 | if (urb->dev->speed == USB_SPEED_LOW || |
| 2987 | urb->dev->speed == USB_SPEED_FULL) |
| 2988 | ep_interval *= 8; |
| 2989 | /* FIXME change this to a warning and a suggestion to use the new API |
| 2990 | * to set the polling interval (once the API is added). |
| 2991 | */ |
| 2992 | if (xhci_interval != ep_interval) { |
| 2993 | if (!printk_ratelimit()) |
| 2994 | dev_dbg(&urb->dev->dev, "Driver uses different interval" |
| 2995 | " (%d microframe%s) than xHCI " |
| 2996 | "(%d microframe%s)\n", |
| 2997 | ep_interval, |
| 2998 | ep_interval == 1 ? "" : "s", |
| 2999 | xhci_interval, |
| 3000 | xhci_interval == 1 ? "" : "s"); |
| 3001 | urb->interval = xhci_interval; |
| 3002 | /* Convert back to frames for LS/FS devices */ |
| 3003 | if (urb->dev->speed == USB_SPEED_LOW || |
| 3004 | urb->dev->speed == USB_SPEED_FULL) |
| 3005 | urb->interval /= 8; |
| 3006 | } |
| 3007 | return xhci_queue_isoc_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index); |
| 3008 | } |
| 3009 | |
Sarah Sharp | d0e96f5 | 2009-04-27 19:58:01 -0700 | [diff] [blame] | 3010 | /**** Command Ring Operations ****/ |
| 3011 | |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 3012 | /* Generic function for queueing a command TRB on the command ring. |
| 3013 | * Check to make sure there's room on the command ring for one command TRB. |
| 3014 | * Also check that there's room reserved for commands that must not fail. |
| 3015 | * If this is a command that must not fail, meaning command_must_succeed = TRUE, |
| 3016 | * then only check for the number of reserved spots. |
| 3017 | * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB |
| 3018 | * because the command event handler may want to resubmit a failed command. |
| 3019 | */ |
| 3020 | static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2, |
| 3021 | u32 field3, u32 field4, bool command_must_succeed) |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 3022 | { |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 3023 | int reserved_trbs = xhci->cmd_ring_reserved_trbs; |
Sarah Sharp | d1dc908 | 2010-07-09 17:08:38 +0200 | [diff] [blame] | 3024 | int ret; |
| 3025 | |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 3026 | if (!command_must_succeed) |
| 3027 | reserved_trbs++; |
| 3028 | |
Sarah Sharp | d1dc908 | 2010-07-09 17:08:38 +0200 | [diff] [blame] | 3029 | ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING, |
| 3030 | reserved_trbs, GFP_ATOMIC); |
| 3031 | if (ret < 0) { |
| 3032 | xhci_err(xhci, "ERR: No room for command on command ring\n"); |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 3033 | if (command_must_succeed) |
| 3034 | xhci_err(xhci, "ERR: Reserved TRB counting for " |
| 3035 | "unfailable commands failed.\n"); |
Sarah Sharp | d1dc908 | 2010-07-09 17:08:38 +0200 | [diff] [blame] | 3036 | return ret; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 3037 | } |
Sarah Sharp | 6cc30d8 | 2010-06-10 12:25:28 -0700 | [diff] [blame] | 3038 | queue_trb(xhci, xhci->cmd_ring, false, false, field1, field2, field3, |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 3039 | field4 | xhci->cmd_ring->cycle_state); |
| 3040 | return 0; |
| 3041 | } |
| 3042 | |
| 3043 | /* Queue a no-op command on the command ring */ |
| 3044 | static int queue_cmd_noop(struct xhci_hcd *xhci) |
| 3045 | { |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 3046 | return queue_command(xhci, 0, 0, 0, TRB_TYPE(TRB_CMD_NOOP), false); |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 3047 | } |
| 3048 | |
| 3049 | /* |
| 3050 | * Place a no-op command on the command ring to test the command and |
| 3051 | * event ring. |
| 3052 | */ |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 3053 | void *xhci_setup_one_noop(struct xhci_hcd *xhci) |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 3054 | { |
| 3055 | if (queue_cmd_noop(xhci) < 0) |
| 3056 | return NULL; |
| 3057 | xhci->noops_submitted++; |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 3058 | return xhci_ring_cmd_db; |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame] | 3059 | } |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 3060 | |
| 3061 | /* Queue a slot enable or disable request on the command ring */ |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 3062 | int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id) |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 3063 | { |
| 3064 | return queue_command(xhci, 0, 0, 0, |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 3065 | TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false); |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 3066 | } |
| 3067 | |
| 3068 | /* Queue an address device command TRB */ |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 3069 | int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, |
| 3070 | u32 slot_id) |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 3071 | { |
Sarah Sharp | 8e595a5 | 2009-07-27 12:03:31 -0700 | [diff] [blame] | 3072 | return queue_command(xhci, lower_32_bits(in_ctx_ptr), |
| 3073 | upper_32_bits(in_ctx_ptr), 0, |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 3074 | TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id), |
| 3075 | false); |
Sarah Sharp | 3ffbba9 | 2009-04-27 19:57:38 -0700 | [diff] [blame] | 3076 | } |
Sarah Sharp | f94e0186 | 2009-04-27 19:58:38 -0700 | [diff] [blame] | 3077 | |
Sarah Sharp | 0238634 | 2010-05-24 13:25:28 -0700 | [diff] [blame] | 3078 | int xhci_queue_vendor_command(struct xhci_hcd *xhci, |
| 3079 | u32 field1, u32 field2, u32 field3, u32 field4) |
| 3080 | { |
| 3081 | return queue_command(xhci, field1, field2, field3, field4, false); |
| 3082 | } |
| 3083 | |
Sarah Sharp | 2a8f82c | 2009-12-09 15:59:13 -0800 | [diff] [blame] | 3084 | /* Queue a reset device command TRB */ |
| 3085 | int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id) |
| 3086 | { |
| 3087 | return queue_command(xhci, 0, 0, 0, |
| 3088 | TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id), |
| 3089 | false); |
| 3090 | } |
| 3091 | |
Sarah Sharp | f94e0186 | 2009-04-27 19:58:38 -0700 | [diff] [blame] | 3092 | /* Queue a configure endpoint command TRB */ |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 3093 | int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 3094 | u32 slot_id, bool command_must_succeed) |
Sarah Sharp | f94e0186 | 2009-04-27 19:58:38 -0700 | [diff] [blame] | 3095 | { |
Sarah Sharp | 8e595a5 | 2009-07-27 12:03:31 -0700 | [diff] [blame] | 3096 | return queue_command(xhci, lower_32_bits(in_ctx_ptr), |
| 3097 | upper_32_bits(in_ctx_ptr), 0, |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 3098 | TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id), |
| 3099 | command_must_succeed); |
Sarah Sharp | f94e0186 | 2009-04-27 19:58:38 -0700 | [diff] [blame] | 3100 | } |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 3101 | |
Sarah Sharp | f2217e8 | 2009-08-07 14:04:43 -0700 | [diff] [blame] | 3102 | /* Queue an evaluate context command TRB */ |
| 3103 | int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, |
| 3104 | u32 slot_id) |
| 3105 | { |
| 3106 | return queue_command(xhci, lower_32_bits(in_ctx_ptr), |
| 3107 | upper_32_bits(in_ctx_ptr), 0, |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 3108 | TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id), |
| 3109 | false); |
Sarah Sharp | f2217e8 | 2009-08-07 14:04:43 -0700 | [diff] [blame] | 3110 | } |
| 3111 | |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 3112 | int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id, |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 3113 | unsigned int ep_index) |
| 3114 | { |
| 3115 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); |
| 3116 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); |
| 3117 | u32 type = TRB_TYPE(TRB_STOP_RING); |
| 3118 | |
| 3119 | return queue_command(xhci, 0, 0, 0, |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 3120 | trb_slot_id | trb_ep_index | type, false); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 3121 | } |
| 3122 | |
| 3123 | /* Set Transfer Ring Dequeue Pointer command. |
| 3124 | * This should not be used for endpoints that have streams enabled. |
| 3125 | */ |
| 3126 | static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id, |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 3127 | unsigned int ep_index, unsigned int stream_id, |
| 3128 | struct xhci_segment *deq_seg, |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 3129 | union xhci_trb *deq_ptr, u32 cycle_state) |
| 3130 | { |
| 3131 | dma_addr_t addr; |
| 3132 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); |
| 3133 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 3134 | u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 3135 | u32 type = TRB_TYPE(TRB_SET_DEQ); |
| 3136 | |
Sarah Sharp | 23e3be1 | 2009-04-29 19:05:20 -0700 | [diff] [blame] | 3137 | addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr); |
Sarah Sharp | c92bcfa | 2009-07-27 12:05:21 -0700 | [diff] [blame] | 3138 | if (addr == 0) { |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 3139 | xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n"); |
Greg Kroah-Hartman | 700e205 | 2009-04-29 19:14:08 -0700 | [diff] [blame] | 3140 | xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n", |
| 3141 | deq_seg, deq_ptr); |
Sarah Sharp | c92bcfa | 2009-07-27 12:05:21 -0700 | [diff] [blame] | 3142 | return 0; |
| 3143 | } |
Sarah Sharp | 8e595a5 | 2009-07-27 12:03:31 -0700 | [diff] [blame] | 3144 | return queue_command(xhci, lower_32_bits(addr) | cycle_state, |
Sarah Sharp | e9df17e | 2010-04-02 15:34:43 -0700 | [diff] [blame] | 3145 | upper_32_bits(addr), trb_stream_id, |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 3146 | trb_slot_id | trb_ep_index | type, false); |
Sarah Sharp | ae63674 | 2009-04-29 19:02:31 -0700 | [diff] [blame] | 3147 | } |
Sarah Sharp | a1587d9 | 2009-07-27 12:03:15 -0700 | [diff] [blame] | 3148 | |
| 3149 | int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id, |
| 3150 | unsigned int ep_index) |
| 3151 | { |
| 3152 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); |
| 3153 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); |
| 3154 | u32 type = TRB_TYPE(TRB_RESET_EP); |
| 3155 | |
Sarah Sharp | 913a8a3 | 2009-09-04 10:53:13 -0700 | [diff] [blame] | 3156 | return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type, |
| 3157 | false); |
Sarah Sharp | a1587d9 | 2009-07-27 12:03:15 -0700 | [diff] [blame] | 3158 | } |