Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved. |
| 3 | * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved. |
| 4 | |
| 5 | * This program is free software; you can redistribute it and/or |
| 6 | * modify it under the terms of the GNU General Public |
| 7 | * License as published by the Free Software Foundation; |
| 8 | * either version 2, or (at your option) any later version. |
| 9 | |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even |
| 12 | * the implied warranty of MERCHANTABILITY or FITNESS FOR |
| 13 | * A PARTICULAR PURPOSE.See the GNU General Public License |
| 14 | * for more details. |
| 15 | |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., |
| 19 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| 20 | */ |
Jonathan Corbet | ec66841 | 2010-05-05 14:44:55 -0600 | [diff] [blame] | 21 | |
| 22 | #include <linux/via-core.h> |
Florian Tobias Schandinat | 32fab7b | 2011-04-23 22:06:18 +0000 | [diff] [blame] | 23 | #include <asm/olpc.h> |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 24 | #include "global.h" |
Florian Tobias Schandinat | 2c536f8 | 2011-03-24 13:30:09 +0000 | [diff] [blame] | 25 | #include "via_clock.h" |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 26 | |
Florian Tobias Schandinat | eb0536c | 2011-03-21 13:28:26 +0000 | [diff] [blame] | 27 | static struct pll_limit cle266_pll_limits[] = { |
| 28 | {19, 19, 4, 0}, |
| 29 | {26, 102, 5, 0}, |
| 30 | {53, 112, 6, 0}, |
| 31 | {41, 100, 7, 0}, |
| 32 | {83, 108, 8, 0}, |
| 33 | {87, 118, 9, 0}, |
| 34 | {95, 115, 12, 0}, |
| 35 | {108, 108, 13, 0}, |
| 36 | {83, 83, 17, 0}, |
| 37 | {67, 98, 20, 0}, |
| 38 | {121, 121, 24, 0}, |
| 39 | {99, 99, 29, 0}, |
| 40 | {33, 33, 3, 1}, |
| 41 | {15, 23, 4, 1}, |
| 42 | {37, 121, 5, 1}, |
| 43 | {82, 82, 6, 1}, |
| 44 | {31, 84, 7, 1}, |
| 45 | {83, 83, 8, 1}, |
| 46 | {76, 127, 9, 1}, |
| 47 | {33, 121, 4, 2}, |
| 48 | {91, 118, 5, 2}, |
| 49 | {83, 109, 6, 2}, |
| 50 | {90, 90, 7, 2}, |
| 51 | {93, 93, 2, 3}, |
| 52 | {53, 53, 3, 3}, |
| 53 | {73, 117, 4, 3}, |
| 54 | {101, 127, 5, 3}, |
| 55 | {99, 99, 7, 3} |
Florian Tobias Schandinat | e4fcaef | 2011-03-12 01:36:38 +0000 | [diff] [blame] | 56 | }; |
| 57 | |
Florian Tobias Schandinat | eb0536c | 2011-03-21 13:28:26 +0000 | [diff] [blame] | 58 | static struct pll_limit k800_pll_limits[] = { |
| 59 | {22, 22, 2, 0}, |
| 60 | {28, 28, 3, 0}, |
| 61 | {81, 112, 3, 1}, |
| 62 | {86, 166, 4, 1}, |
| 63 | {109, 153, 5, 1}, |
| 64 | {66, 116, 3, 2}, |
| 65 | {93, 137, 4, 2}, |
| 66 | {117, 208, 5, 2}, |
| 67 | {30, 30, 2, 3}, |
| 68 | {69, 125, 3, 3}, |
| 69 | {89, 161, 4, 3}, |
| 70 | {121, 208, 5, 3}, |
| 71 | {66, 66, 2, 4}, |
| 72 | {85, 85, 3, 4}, |
| 73 | {141, 161, 4, 4}, |
| 74 | {177, 177, 5, 4} |
Florian Tobias Schandinat | e4fcaef | 2011-03-12 01:36:38 +0000 | [diff] [blame] | 75 | }; |
| 76 | |
Florian Tobias Schandinat | eb0536c | 2011-03-21 13:28:26 +0000 | [diff] [blame] | 77 | static struct pll_limit cx700_pll_limits[] = { |
| 78 | {98, 98, 3, 1}, |
| 79 | {86, 86, 4, 1}, |
| 80 | {109, 208, 5, 1}, |
| 81 | {68, 68, 2, 2}, |
| 82 | {95, 116, 3, 2}, |
| 83 | {93, 166, 4, 2}, |
| 84 | {110, 206, 5, 2}, |
| 85 | {174, 174, 7, 2}, |
| 86 | {82, 109, 3, 3}, |
| 87 | {117, 161, 4, 3}, |
| 88 | {112, 208, 5, 3}, |
| 89 | {141, 202, 5, 4} |
Florian Tobias Schandinat | e4fcaef | 2011-03-12 01:36:38 +0000 | [diff] [blame] | 90 | }; |
| 91 | |
Florian Tobias Schandinat | eb0536c | 2011-03-21 13:28:26 +0000 | [diff] [blame] | 92 | static struct pll_limit vx855_pll_limits[] = { |
| 93 | {86, 86, 4, 1}, |
| 94 | {108, 208, 5, 1}, |
| 95 | {110, 208, 5, 2}, |
| 96 | {83, 112, 3, 3}, |
| 97 | {103, 161, 4, 3}, |
| 98 | {112, 209, 5, 3}, |
| 99 | {142, 161, 4, 4}, |
| 100 | {141, 176, 5, 4} |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 101 | }; |
| 102 | |
Florian Tobias Schandinat | bf5ea02 | 2011-01-05 10:36:05 +0000 | [diff] [blame] | 103 | /* according to VIA Technologies these values are based on experiment */ |
| 104 | static struct io_reg scaling_parameters[] = { |
| 105 | {VIACR, CR7A, 0xFF, 0x01}, /* LCD Scaling Parameter 1 */ |
| 106 | {VIACR, CR7B, 0xFF, 0x02}, /* LCD Scaling Parameter 2 */ |
| 107 | {VIACR, CR7C, 0xFF, 0x03}, /* LCD Scaling Parameter 3 */ |
| 108 | {VIACR, CR7D, 0xFF, 0x04}, /* LCD Scaling Parameter 4 */ |
| 109 | {VIACR, CR7E, 0xFF, 0x07}, /* LCD Scaling Parameter 5 */ |
| 110 | {VIACR, CR7F, 0xFF, 0x0A}, /* LCD Scaling Parameter 6 */ |
| 111 | {VIACR, CR80, 0xFF, 0x0D}, /* LCD Scaling Parameter 7 */ |
| 112 | {VIACR, CR81, 0xFF, 0x13}, /* LCD Scaling Parameter 8 */ |
| 113 | {VIACR, CR82, 0xFF, 0x16}, /* LCD Scaling Parameter 9 */ |
| 114 | {VIACR, CR83, 0xFF, 0x19}, /* LCD Scaling Parameter 10 */ |
| 115 | {VIACR, CR84, 0xFF, 0x1C}, /* LCD Scaling Parameter 11 */ |
| 116 | {VIACR, CR85, 0xFF, 0x1D}, /* LCD Scaling Parameter 12 */ |
| 117 | {VIACR, CR86, 0xFF, 0x1E}, /* LCD Scaling Parameter 13 */ |
| 118 | {VIACR, CR87, 0xFF, 0x1F}, /* LCD Scaling Parameter 14 */ |
| 119 | }; |
| 120 | |
Florian Tobias Schandinat | 95d517c | 2011-03-26 23:39:07 +0000 | [diff] [blame] | 121 | static struct io_reg common_vga[] = { |
| 122 | {VIACR, CR07, 0x10, 0x10}, /* [0] vertical total (bit 8) |
| 123 | [1] vertical display end (bit 8) |
| 124 | [2] vertical retrace start (bit 8) |
| 125 | [3] start vertical blanking (bit 8) |
| 126 | [4] line compare (bit 8) |
| 127 | [5] vertical total (bit 9) |
| 128 | [6] vertical display end (bit 9) |
| 129 | [7] vertical retrace start (bit 9) */ |
| 130 | {VIACR, CR08, 0xFF, 0x00}, /* [0-4] preset row scan |
| 131 | [5-6] byte panning */ |
| 132 | {VIACR, CR09, 0xDF, 0x40}, /* [0-4] max scan line |
| 133 | [5] start vertical blanking (bit 9) |
| 134 | [6] line compare (bit 9) |
| 135 | [7] scan doubling */ |
| 136 | {VIACR, CR0A, 0xFF, 0x1E}, /* [0-4] cursor start |
| 137 | [5] cursor disable */ |
| 138 | {VIACR, CR0B, 0xFF, 0x00}, /* [0-4] cursor end |
| 139 | [5-6] cursor skew */ |
| 140 | {VIACR, CR0E, 0xFF, 0x00}, /* [0-7] cursor location (high) */ |
| 141 | {VIACR, CR0F, 0xFF, 0x00}, /* [0-7] cursor location (low) */ |
| 142 | {VIACR, CR11, 0xF0, 0x80}, /* [0-3] vertical retrace end |
| 143 | [6] memory refresh bandwidth |
| 144 | [7] CRTC register protect enable */ |
| 145 | {VIACR, CR14, 0xFF, 0x00}, /* [0-4] underline location |
| 146 | [5] divide memory address clock by 4 |
| 147 | [6] double word addressing */ |
| 148 | {VIACR, CR17, 0xFF, 0x63}, /* [0-1] mapping of display address 13-14 |
| 149 | [2] divide scan line clock by 2 |
| 150 | [3] divide memory address clock by 2 |
| 151 | [5] address wrap |
| 152 | [6] byte mode select |
| 153 | [7] sync enable */ |
| 154 | {VIACR, CR18, 0xFF, 0xFF}, /* [0-7] line compare */ |
| 155 | }; |
| 156 | |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 157 | static struct fifo_depth_select display_fifo_depth_reg = { |
| 158 | /* IGA1 FIFO Depth_Select */ |
| 159 | {IGA1_FIFO_DEPTH_SELECT_REG_NUM, {{SR17, 0, 7} } }, |
| 160 | /* IGA2 FIFO Depth_Select */ |
| 161 | {IGA2_FIFO_DEPTH_SELECT_REG_NUM, |
| 162 | {{CR68, 4, 7}, {CR94, 7, 7}, {CR95, 7, 7} } } |
| 163 | }; |
| 164 | |
| 165 | static struct fifo_threshold_select fifo_threshold_select_reg = { |
| 166 | /* IGA1 FIFO Threshold Select */ |
| 167 | {IGA1_FIFO_THRESHOLD_REG_NUM, {{SR16, 0, 5}, {SR16, 7, 7} } }, |
| 168 | /* IGA2 FIFO Threshold Select */ |
| 169 | {IGA2_FIFO_THRESHOLD_REG_NUM, {{CR68, 0, 3}, {CR95, 4, 6} } } |
| 170 | }; |
| 171 | |
| 172 | static struct fifo_high_threshold_select fifo_high_threshold_select_reg = { |
| 173 | /* IGA1 FIFO High Threshold Select */ |
| 174 | {IGA1_FIFO_HIGH_THRESHOLD_REG_NUM, {{SR18, 0, 5}, {SR18, 7, 7} } }, |
| 175 | /* IGA2 FIFO High Threshold Select */ |
| 176 | {IGA2_FIFO_HIGH_THRESHOLD_REG_NUM, {{CR92, 0, 3}, {CR95, 0, 2} } } |
| 177 | }; |
| 178 | |
| 179 | static struct display_queue_expire_num display_queue_expire_num_reg = { |
| 180 | /* IGA1 Display Queue Expire Num */ |
| 181 | {IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{SR22, 0, 4} } }, |
| 182 | /* IGA2 Display Queue Expire Num */ |
| 183 | {IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{CR94, 0, 6} } } |
| 184 | }; |
| 185 | |
| 186 | /* Definition Fetch Count Registers*/ |
| 187 | static struct fetch_count fetch_count_reg = { |
| 188 | /* IGA1 Fetch Count Register */ |
| 189 | {IGA1_FETCH_COUNT_REG_NUM, {{SR1C, 0, 7}, {SR1D, 0, 1} } }, |
| 190 | /* IGA2 Fetch Count Register */ |
| 191 | {IGA2_FETCH_COUNT_REG_NUM, {{CR65, 0, 7}, {CR67, 2, 3} } } |
| 192 | }; |
| 193 | |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 194 | static struct rgbLUT palLUT_table[] = { |
| 195 | /* {R,G,B} */ |
| 196 | /* Index 0x00~0x03 */ |
| 197 | {0x00, 0x00, 0x00}, {0x00, 0x00, 0x2A}, {0x00, 0x2A, 0x00}, {0x00, |
| 198 | 0x2A, |
| 199 | 0x2A}, |
| 200 | /* Index 0x04~0x07 */ |
| 201 | {0x2A, 0x00, 0x00}, {0x2A, 0x00, 0x2A}, {0x2A, 0x15, 0x00}, {0x2A, |
| 202 | 0x2A, |
| 203 | 0x2A}, |
| 204 | /* Index 0x08~0x0B */ |
| 205 | {0x15, 0x15, 0x15}, {0x15, 0x15, 0x3F}, {0x15, 0x3F, 0x15}, {0x15, |
| 206 | 0x3F, |
| 207 | 0x3F}, |
| 208 | /* Index 0x0C~0x0F */ |
| 209 | {0x3F, 0x15, 0x15}, {0x3F, 0x15, 0x3F}, {0x3F, 0x3F, 0x15}, {0x3F, |
| 210 | 0x3F, |
| 211 | 0x3F}, |
| 212 | /* Index 0x10~0x13 */ |
| 213 | {0x00, 0x00, 0x00}, {0x05, 0x05, 0x05}, {0x08, 0x08, 0x08}, {0x0B, |
| 214 | 0x0B, |
| 215 | 0x0B}, |
| 216 | /* Index 0x14~0x17 */ |
| 217 | {0x0E, 0x0E, 0x0E}, {0x11, 0x11, 0x11}, {0x14, 0x14, 0x14}, {0x18, |
| 218 | 0x18, |
| 219 | 0x18}, |
| 220 | /* Index 0x18~0x1B */ |
| 221 | {0x1C, 0x1C, 0x1C}, {0x20, 0x20, 0x20}, {0x24, 0x24, 0x24}, {0x28, |
| 222 | 0x28, |
| 223 | 0x28}, |
| 224 | /* Index 0x1C~0x1F */ |
| 225 | {0x2D, 0x2D, 0x2D}, {0x32, 0x32, 0x32}, {0x38, 0x38, 0x38}, {0x3F, |
| 226 | 0x3F, |
| 227 | 0x3F}, |
| 228 | /* Index 0x20~0x23 */ |
| 229 | {0x00, 0x00, 0x3F}, {0x10, 0x00, 0x3F}, {0x1F, 0x00, 0x3F}, {0x2F, |
| 230 | 0x00, |
| 231 | 0x3F}, |
| 232 | /* Index 0x24~0x27 */ |
| 233 | {0x3F, 0x00, 0x3F}, {0x3F, 0x00, 0x2F}, {0x3F, 0x00, 0x1F}, {0x3F, |
| 234 | 0x00, |
| 235 | 0x10}, |
| 236 | /* Index 0x28~0x2B */ |
| 237 | {0x3F, 0x00, 0x00}, {0x3F, 0x10, 0x00}, {0x3F, 0x1F, 0x00}, {0x3F, |
| 238 | 0x2F, |
| 239 | 0x00}, |
| 240 | /* Index 0x2C~0x2F */ |
| 241 | {0x3F, 0x3F, 0x00}, {0x2F, 0x3F, 0x00}, {0x1F, 0x3F, 0x00}, {0x10, |
| 242 | 0x3F, |
| 243 | 0x00}, |
| 244 | /* Index 0x30~0x33 */ |
| 245 | {0x00, 0x3F, 0x00}, {0x00, 0x3F, 0x10}, {0x00, 0x3F, 0x1F}, {0x00, |
| 246 | 0x3F, |
| 247 | 0x2F}, |
| 248 | /* Index 0x34~0x37 */ |
| 249 | {0x00, 0x3F, 0x3F}, {0x00, 0x2F, 0x3F}, {0x00, 0x1F, 0x3F}, {0x00, |
| 250 | 0x10, |
| 251 | 0x3F}, |
| 252 | /* Index 0x38~0x3B */ |
| 253 | {0x1F, 0x1F, 0x3F}, {0x27, 0x1F, 0x3F}, {0x2F, 0x1F, 0x3F}, {0x37, |
| 254 | 0x1F, |
| 255 | 0x3F}, |
| 256 | /* Index 0x3C~0x3F */ |
| 257 | {0x3F, 0x1F, 0x3F}, {0x3F, 0x1F, 0x37}, {0x3F, 0x1F, 0x2F}, {0x3F, |
| 258 | 0x1F, |
| 259 | 0x27}, |
| 260 | /* Index 0x40~0x43 */ |
| 261 | {0x3F, 0x1F, 0x1F}, {0x3F, 0x27, 0x1F}, {0x3F, 0x2F, 0x1F}, {0x3F, |
| 262 | 0x3F, |
| 263 | 0x1F}, |
| 264 | /* Index 0x44~0x47 */ |
| 265 | {0x3F, 0x3F, 0x1F}, {0x37, 0x3F, 0x1F}, {0x2F, 0x3F, 0x1F}, {0x27, |
| 266 | 0x3F, |
| 267 | 0x1F}, |
| 268 | /* Index 0x48~0x4B */ |
| 269 | {0x1F, 0x3F, 0x1F}, {0x1F, 0x3F, 0x27}, {0x1F, 0x3F, 0x2F}, {0x1F, |
| 270 | 0x3F, |
| 271 | 0x37}, |
| 272 | /* Index 0x4C~0x4F */ |
| 273 | {0x1F, 0x3F, 0x3F}, {0x1F, 0x37, 0x3F}, {0x1F, 0x2F, 0x3F}, {0x1F, |
| 274 | 0x27, |
| 275 | 0x3F}, |
| 276 | /* Index 0x50~0x53 */ |
| 277 | {0x2D, 0x2D, 0x3F}, {0x31, 0x2D, 0x3F}, {0x36, 0x2D, 0x3F}, {0x3A, |
| 278 | 0x2D, |
| 279 | 0x3F}, |
| 280 | /* Index 0x54~0x57 */ |
| 281 | {0x3F, 0x2D, 0x3F}, {0x3F, 0x2D, 0x3A}, {0x3F, 0x2D, 0x36}, {0x3F, |
| 282 | 0x2D, |
| 283 | 0x31}, |
| 284 | /* Index 0x58~0x5B */ |
| 285 | {0x3F, 0x2D, 0x2D}, {0x3F, 0x31, 0x2D}, {0x3F, 0x36, 0x2D}, {0x3F, |
| 286 | 0x3A, |
| 287 | 0x2D}, |
| 288 | /* Index 0x5C~0x5F */ |
| 289 | {0x3F, 0x3F, 0x2D}, {0x3A, 0x3F, 0x2D}, {0x36, 0x3F, 0x2D}, {0x31, |
| 290 | 0x3F, |
| 291 | 0x2D}, |
| 292 | /* Index 0x60~0x63 */ |
| 293 | {0x2D, 0x3F, 0x2D}, {0x2D, 0x3F, 0x31}, {0x2D, 0x3F, 0x36}, {0x2D, |
| 294 | 0x3F, |
| 295 | 0x3A}, |
| 296 | /* Index 0x64~0x67 */ |
| 297 | {0x2D, 0x3F, 0x3F}, {0x2D, 0x3A, 0x3F}, {0x2D, 0x36, 0x3F}, {0x2D, |
| 298 | 0x31, |
| 299 | 0x3F}, |
| 300 | /* Index 0x68~0x6B */ |
| 301 | {0x00, 0x00, 0x1C}, {0x07, 0x00, 0x1C}, {0x0E, 0x00, 0x1C}, {0x15, |
| 302 | 0x00, |
| 303 | 0x1C}, |
| 304 | /* Index 0x6C~0x6F */ |
| 305 | {0x1C, 0x00, 0x1C}, {0x1C, 0x00, 0x15}, {0x1C, 0x00, 0x0E}, {0x1C, |
| 306 | 0x00, |
| 307 | 0x07}, |
| 308 | /* Index 0x70~0x73 */ |
| 309 | {0x1C, 0x00, 0x00}, {0x1C, 0x07, 0x00}, {0x1C, 0x0E, 0x00}, {0x1C, |
| 310 | 0x15, |
| 311 | 0x00}, |
| 312 | /* Index 0x74~0x77 */ |
| 313 | {0x1C, 0x1C, 0x00}, {0x15, 0x1C, 0x00}, {0x0E, 0x1C, 0x00}, {0x07, |
| 314 | 0x1C, |
| 315 | 0x00}, |
| 316 | /* Index 0x78~0x7B */ |
| 317 | {0x00, 0x1C, 0x00}, {0x00, 0x1C, 0x07}, {0x00, 0x1C, 0x0E}, {0x00, |
| 318 | 0x1C, |
| 319 | 0x15}, |
| 320 | /* Index 0x7C~0x7F */ |
| 321 | {0x00, 0x1C, 0x1C}, {0x00, 0x15, 0x1C}, {0x00, 0x0E, 0x1C}, {0x00, |
| 322 | 0x07, |
| 323 | 0x1C}, |
| 324 | /* Index 0x80~0x83 */ |
| 325 | {0x0E, 0x0E, 0x1C}, {0x11, 0x0E, 0x1C}, {0x15, 0x0E, 0x1C}, {0x18, |
| 326 | 0x0E, |
| 327 | 0x1C}, |
| 328 | /* Index 0x84~0x87 */ |
| 329 | {0x1C, 0x0E, 0x1C}, {0x1C, 0x0E, 0x18}, {0x1C, 0x0E, 0x15}, {0x1C, |
| 330 | 0x0E, |
| 331 | 0x11}, |
| 332 | /* Index 0x88~0x8B */ |
| 333 | {0x1C, 0x0E, 0x0E}, {0x1C, 0x11, 0x0E}, {0x1C, 0x15, 0x0E}, {0x1C, |
| 334 | 0x18, |
| 335 | 0x0E}, |
| 336 | /* Index 0x8C~0x8F */ |
| 337 | {0x1C, 0x1C, 0x0E}, {0x18, 0x1C, 0x0E}, {0x15, 0x1C, 0x0E}, {0x11, |
| 338 | 0x1C, |
| 339 | 0x0E}, |
| 340 | /* Index 0x90~0x93 */ |
| 341 | {0x0E, 0x1C, 0x0E}, {0x0E, 0x1C, 0x11}, {0x0E, 0x1C, 0x15}, {0x0E, |
| 342 | 0x1C, |
| 343 | 0x18}, |
| 344 | /* Index 0x94~0x97 */ |
| 345 | {0x0E, 0x1C, 0x1C}, {0x0E, 0x18, 0x1C}, {0x0E, 0x15, 0x1C}, {0x0E, |
| 346 | 0x11, |
| 347 | 0x1C}, |
| 348 | /* Index 0x98~0x9B */ |
| 349 | {0x14, 0x14, 0x1C}, {0x16, 0x14, 0x1C}, {0x18, 0x14, 0x1C}, {0x1A, |
| 350 | 0x14, |
| 351 | 0x1C}, |
| 352 | /* Index 0x9C~0x9F */ |
| 353 | {0x1C, 0x14, 0x1C}, {0x1C, 0x14, 0x1A}, {0x1C, 0x14, 0x18}, {0x1C, |
| 354 | 0x14, |
| 355 | 0x16}, |
| 356 | /* Index 0xA0~0xA3 */ |
| 357 | {0x1C, 0x14, 0x14}, {0x1C, 0x16, 0x14}, {0x1C, 0x18, 0x14}, {0x1C, |
| 358 | 0x1A, |
| 359 | 0x14}, |
| 360 | /* Index 0xA4~0xA7 */ |
| 361 | {0x1C, 0x1C, 0x14}, {0x1A, 0x1C, 0x14}, {0x18, 0x1C, 0x14}, {0x16, |
| 362 | 0x1C, |
| 363 | 0x14}, |
| 364 | /* Index 0xA8~0xAB */ |
| 365 | {0x14, 0x1C, 0x14}, {0x14, 0x1C, 0x16}, {0x14, 0x1C, 0x18}, {0x14, |
| 366 | 0x1C, |
| 367 | 0x1A}, |
| 368 | /* Index 0xAC~0xAF */ |
| 369 | {0x14, 0x1C, 0x1C}, {0x14, 0x1A, 0x1C}, {0x14, 0x18, 0x1C}, {0x14, |
| 370 | 0x16, |
| 371 | 0x1C}, |
| 372 | /* Index 0xB0~0xB3 */ |
| 373 | {0x00, 0x00, 0x10}, {0x04, 0x00, 0x10}, {0x08, 0x00, 0x10}, {0x0C, |
| 374 | 0x00, |
| 375 | 0x10}, |
| 376 | /* Index 0xB4~0xB7 */ |
| 377 | {0x10, 0x00, 0x10}, {0x10, 0x00, 0x0C}, {0x10, 0x00, 0x08}, {0x10, |
| 378 | 0x00, |
| 379 | 0x04}, |
| 380 | /* Index 0xB8~0xBB */ |
| 381 | {0x10, 0x00, 0x00}, {0x10, 0x04, 0x00}, {0x10, 0x08, 0x00}, {0x10, |
| 382 | 0x0C, |
| 383 | 0x00}, |
| 384 | /* Index 0xBC~0xBF */ |
| 385 | {0x10, 0x10, 0x00}, {0x0C, 0x10, 0x00}, {0x08, 0x10, 0x00}, {0x04, |
| 386 | 0x10, |
| 387 | 0x00}, |
| 388 | /* Index 0xC0~0xC3 */ |
| 389 | {0x00, 0x10, 0x00}, {0x00, 0x10, 0x04}, {0x00, 0x10, 0x08}, {0x00, |
| 390 | 0x10, |
| 391 | 0x0C}, |
| 392 | /* Index 0xC4~0xC7 */ |
| 393 | {0x00, 0x10, 0x10}, {0x00, 0x0C, 0x10}, {0x00, 0x08, 0x10}, {0x00, |
| 394 | 0x04, |
| 395 | 0x10}, |
| 396 | /* Index 0xC8~0xCB */ |
| 397 | {0x08, 0x08, 0x10}, {0x0A, 0x08, 0x10}, {0x0C, 0x08, 0x10}, {0x0E, |
| 398 | 0x08, |
| 399 | 0x10}, |
| 400 | /* Index 0xCC~0xCF */ |
| 401 | {0x10, 0x08, 0x10}, {0x10, 0x08, 0x0E}, {0x10, 0x08, 0x0C}, {0x10, |
| 402 | 0x08, |
| 403 | 0x0A}, |
| 404 | /* Index 0xD0~0xD3 */ |
| 405 | {0x10, 0x08, 0x08}, {0x10, 0x0A, 0x08}, {0x10, 0x0C, 0x08}, {0x10, |
| 406 | 0x0E, |
| 407 | 0x08}, |
| 408 | /* Index 0xD4~0xD7 */ |
| 409 | {0x10, 0x10, 0x08}, {0x0E, 0x10, 0x08}, {0x0C, 0x10, 0x08}, {0x0A, |
| 410 | 0x10, |
| 411 | 0x08}, |
| 412 | /* Index 0xD8~0xDB */ |
| 413 | {0x08, 0x10, 0x08}, {0x08, 0x10, 0x0A}, {0x08, 0x10, 0x0C}, {0x08, |
| 414 | 0x10, |
| 415 | 0x0E}, |
| 416 | /* Index 0xDC~0xDF */ |
| 417 | {0x08, 0x10, 0x10}, {0x08, 0x0E, 0x10}, {0x08, 0x0C, 0x10}, {0x08, |
| 418 | 0x0A, |
| 419 | 0x10}, |
| 420 | /* Index 0xE0~0xE3 */ |
| 421 | {0x0B, 0x0B, 0x10}, {0x0C, 0x0B, 0x10}, {0x0D, 0x0B, 0x10}, {0x0F, |
| 422 | 0x0B, |
| 423 | 0x10}, |
| 424 | /* Index 0xE4~0xE7 */ |
| 425 | {0x10, 0x0B, 0x10}, {0x10, 0x0B, 0x0F}, {0x10, 0x0B, 0x0D}, {0x10, |
| 426 | 0x0B, |
| 427 | 0x0C}, |
| 428 | /* Index 0xE8~0xEB */ |
| 429 | {0x10, 0x0B, 0x0B}, {0x10, 0x0C, 0x0B}, {0x10, 0x0D, 0x0B}, {0x10, |
| 430 | 0x0F, |
| 431 | 0x0B}, |
| 432 | /* Index 0xEC~0xEF */ |
| 433 | {0x10, 0x10, 0x0B}, {0x0F, 0x10, 0x0B}, {0x0D, 0x10, 0x0B}, {0x0C, |
| 434 | 0x10, |
| 435 | 0x0B}, |
| 436 | /* Index 0xF0~0xF3 */ |
| 437 | {0x0B, 0x10, 0x0B}, {0x0B, 0x10, 0x0C}, {0x0B, 0x10, 0x0D}, {0x0B, |
| 438 | 0x10, |
| 439 | 0x0F}, |
| 440 | /* Index 0xF4~0xF7 */ |
| 441 | {0x0B, 0x10, 0x10}, {0x0B, 0x0F, 0x10}, {0x0B, 0x0D, 0x10}, {0x0B, |
| 442 | 0x0C, |
| 443 | 0x10}, |
| 444 | /* Index 0xF8~0xFB */ |
| 445 | {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, |
| 446 | 0x00, |
| 447 | 0x00}, |
| 448 | /* Index 0xFC~0xFF */ |
| 449 | {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, |
| 450 | 0x00, |
| 451 | 0x00} |
| 452 | }; |
| 453 | |
Florian Tobias Schandinat | 2a91839 | 2010-09-05 01:33:28 +0000 | [diff] [blame] | 454 | static struct via_device_mapping device_mapping[] = { |
Florian Tobias Schandinat | a2aa9f9 | 2010-09-19 04:40:15 +0000 | [diff] [blame] | 455 | {VIA_LDVP0, "LDVP0"}, |
| 456 | {VIA_LDVP1, "LDVP1"}, |
| 457 | {VIA_DVP0, "DVP0"}, |
Florian Tobias Schandinat | 2a91839 | 2010-09-05 01:33:28 +0000 | [diff] [blame] | 458 | {VIA_CRT, "CRT"}, |
| 459 | {VIA_DVP1, "DVP1"}, |
| 460 | {VIA_LVDS1, "LVDS1"}, |
| 461 | {VIA_LVDS2, "LVDS2"} |
| 462 | }; |
| 463 | |
Florian Tobias Schandinat | 2c536f8 | 2011-03-24 13:30:09 +0000 | [diff] [blame] | 464 | /* structure with function pointers to support clock control */ |
| 465 | static struct via_clock clock; |
| 466 | |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 467 | static void load_fix_bit_crtc_reg(void); |
Florian Tobias Schandinat | f4ab2f7a | 2010-08-09 01:34:27 +0000 | [diff] [blame] | 468 | static void __devinit init_gfx_chip_info(int chip_type); |
| 469 | static void __devinit init_tmds_chip_info(void); |
| 470 | static void __devinit init_lvds_chip_info(void); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 471 | static void device_screen_off(void); |
| 472 | static void device_screen_on(void); |
| 473 | static void set_display_channel(void); |
| 474 | static void device_off(void); |
| 475 | static void device_on(void); |
| 476 | static void enable_second_display_channel(void); |
Florian Tobias Schandinat | bc68488 | 2010-08-11 00:37:58 +0000 | [diff] [blame] | 477 | static void disable_second_display_channel(void); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 478 | |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 479 | void viafb_lock_crt(void) |
| 480 | { |
| 481 | viafb_write_reg_mask(CR11, VIACR, BIT7, BIT7); |
| 482 | } |
| 483 | |
| 484 | void viafb_unlock_crt(void) |
| 485 | { |
| 486 | viafb_write_reg_mask(CR11, VIACR, 0, BIT7); |
| 487 | viafb_write_reg_mask(CR47, VIACR, 0, BIT0); |
| 488 | } |
| 489 | |
Stephen Hemminger | 23e5abd | 2011-03-03 10:00:08 -0800 | [diff] [blame] | 490 | static void write_dac_reg(u8 index, u8 r, u8 g, u8 b) |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 491 | { |
| 492 | outb(index, LUT_INDEX_WRITE); |
| 493 | outb(r, LUT_DATA); |
| 494 | outb(g, LUT_DATA); |
| 495 | outb(b, LUT_DATA); |
| 496 | } |
| 497 | |
Florian Tobias Schandinat | 18d9dc0 | 2010-08-10 02:44:44 +0000 | [diff] [blame] | 498 | static u32 get_dvi_devices(int output_interface) |
| 499 | { |
| 500 | switch (output_interface) { |
| 501 | case INTERFACE_DVP0: |
Florian Tobias Schandinat | a2aa9f9 | 2010-09-19 04:40:15 +0000 | [diff] [blame] | 502 | return VIA_DVP0 | VIA_LDVP0; |
Florian Tobias Schandinat | 18d9dc0 | 2010-08-10 02:44:44 +0000 | [diff] [blame] | 503 | |
| 504 | case INTERFACE_DVP1: |
| 505 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) |
Florian Tobias Schandinat | a2aa9f9 | 2010-09-19 04:40:15 +0000 | [diff] [blame] | 506 | return VIA_LDVP1; |
Florian Tobias Schandinat | 18d9dc0 | 2010-08-10 02:44:44 +0000 | [diff] [blame] | 507 | else |
| 508 | return VIA_DVP1; |
| 509 | |
| 510 | case INTERFACE_DFP_HIGH: |
| 511 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) |
| 512 | return 0; |
| 513 | else |
Florian Tobias Schandinat | a2aa9f9 | 2010-09-19 04:40:15 +0000 | [diff] [blame] | 514 | return VIA_LVDS2 | VIA_DVP0; |
Florian Tobias Schandinat | 18d9dc0 | 2010-08-10 02:44:44 +0000 | [diff] [blame] | 515 | |
| 516 | case INTERFACE_DFP_LOW: |
| 517 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) |
| 518 | return 0; |
| 519 | else |
| 520 | return VIA_DVP1 | VIA_LVDS1; |
| 521 | |
| 522 | case INTERFACE_TMDS: |
| 523 | return VIA_LVDS1; |
| 524 | } |
| 525 | |
| 526 | return 0; |
| 527 | } |
| 528 | |
| 529 | static u32 get_lcd_devices(int output_interface) |
| 530 | { |
| 531 | switch (output_interface) { |
| 532 | case INTERFACE_DVP0: |
Florian Tobias Schandinat | a2aa9f9 | 2010-09-19 04:40:15 +0000 | [diff] [blame] | 533 | return VIA_DVP0; |
Florian Tobias Schandinat | 18d9dc0 | 2010-08-10 02:44:44 +0000 | [diff] [blame] | 534 | |
| 535 | case INTERFACE_DVP1: |
| 536 | return VIA_DVP1; |
| 537 | |
| 538 | case INTERFACE_DFP_HIGH: |
Florian Tobias Schandinat | a2aa9f9 | 2010-09-19 04:40:15 +0000 | [diff] [blame] | 539 | return VIA_LVDS2 | VIA_DVP0; |
Florian Tobias Schandinat | 18d9dc0 | 2010-08-10 02:44:44 +0000 | [diff] [blame] | 540 | |
| 541 | case INTERFACE_DFP_LOW: |
| 542 | return VIA_LVDS1 | VIA_DVP1; |
| 543 | |
| 544 | case INTERFACE_DFP: |
| 545 | return VIA_LVDS1 | VIA_LVDS2; |
| 546 | |
| 547 | case INTERFACE_LVDS0: |
| 548 | case INTERFACE_LVDS0LVDS1: |
| 549 | return VIA_LVDS1; |
| 550 | |
| 551 | case INTERFACE_LVDS1: |
| 552 | return VIA_LVDS2; |
| 553 | } |
| 554 | |
| 555 | return 0; |
| 556 | } |
| 557 | |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 558 | /*Set IGA path for each device*/ |
| 559 | void viafb_set_iga_path(void) |
| 560 | { |
Florian Tobias Schandinat | 0523656 | 2011-03-21 01:46:24 +0000 | [diff] [blame] | 561 | int crt_iga_path = 0; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 562 | |
| 563 | if (viafb_SAMM_ON == 1) { |
| 564 | if (viafb_CRT_ON) { |
| 565 | if (viafb_primary_dev == CRT_Device) |
Florian Tobias Schandinat | 0523656 | 2011-03-21 01:46:24 +0000 | [diff] [blame] | 566 | crt_iga_path = IGA1; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 567 | else |
Florian Tobias Schandinat | 0523656 | 2011-03-21 01:46:24 +0000 | [diff] [blame] | 568 | crt_iga_path = IGA2; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 569 | } |
| 570 | |
| 571 | if (viafb_DVI_ON) { |
| 572 | if (viafb_primary_dev == DVI_Device) |
| 573 | viaparinfo->tmds_setting_info->iga_path = IGA1; |
| 574 | else |
| 575 | viaparinfo->tmds_setting_info->iga_path = IGA2; |
| 576 | } |
| 577 | |
| 578 | if (viafb_LCD_ON) { |
| 579 | if (viafb_primary_dev == LCD_Device) { |
| 580 | if (viafb_dual_fb && |
| 581 | (viaparinfo->chip_info->gfx_chip_name == |
| 582 | UNICHROME_CLE266)) { |
| 583 | viaparinfo-> |
| 584 | lvds_setting_info->iga_path = IGA2; |
Florian Tobias Schandinat | 0523656 | 2011-03-21 01:46:24 +0000 | [diff] [blame] | 585 | crt_iga_path = IGA1; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 586 | viaparinfo-> |
| 587 | tmds_setting_info->iga_path = IGA1; |
| 588 | } else |
| 589 | viaparinfo-> |
| 590 | lvds_setting_info->iga_path = IGA1; |
| 591 | } else { |
| 592 | viaparinfo->lvds_setting_info->iga_path = IGA2; |
| 593 | } |
| 594 | } |
| 595 | if (viafb_LCD2_ON) { |
| 596 | if (LCD2_Device == viafb_primary_dev) |
| 597 | viaparinfo->lvds_setting_info2->iga_path = IGA1; |
| 598 | else |
| 599 | viaparinfo->lvds_setting_info2->iga_path = IGA2; |
| 600 | } |
| 601 | } else { |
| 602 | viafb_SAMM_ON = 0; |
| 603 | |
| 604 | if (viafb_CRT_ON && viafb_LCD_ON) { |
Florian Tobias Schandinat | 0523656 | 2011-03-21 01:46:24 +0000 | [diff] [blame] | 605 | crt_iga_path = IGA1; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 606 | viaparinfo->lvds_setting_info->iga_path = IGA2; |
| 607 | } else if (viafb_CRT_ON && viafb_DVI_ON) { |
Florian Tobias Schandinat | 0523656 | 2011-03-21 01:46:24 +0000 | [diff] [blame] | 608 | crt_iga_path = IGA1; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 609 | viaparinfo->tmds_setting_info->iga_path = IGA2; |
| 610 | } else if (viafb_LCD_ON && viafb_DVI_ON) { |
| 611 | viaparinfo->tmds_setting_info->iga_path = IGA1; |
| 612 | viaparinfo->lvds_setting_info->iga_path = IGA2; |
| 613 | } else if (viafb_LCD_ON && viafb_LCD2_ON) { |
| 614 | viaparinfo->lvds_setting_info->iga_path = IGA2; |
| 615 | viaparinfo->lvds_setting_info2->iga_path = IGA2; |
| 616 | } else if (viafb_CRT_ON) { |
Florian Tobias Schandinat | 0523656 | 2011-03-21 01:46:24 +0000 | [diff] [blame] | 617 | crt_iga_path = IGA1; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 618 | } else if (viafb_LCD_ON) { |
| 619 | viaparinfo->lvds_setting_info->iga_path = IGA2; |
| 620 | } else if (viafb_DVI_ON) { |
| 621 | viaparinfo->tmds_setting_info->iga_path = IGA1; |
| 622 | } |
| 623 | } |
Florian Tobias Schandinat | 18d9dc0 | 2010-08-10 02:44:44 +0000 | [diff] [blame] | 624 | |
| 625 | viaparinfo->shared->iga1_devices = 0; |
| 626 | viaparinfo->shared->iga2_devices = 0; |
| 627 | if (viafb_CRT_ON) { |
Florian Tobias Schandinat | 0523656 | 2011-03-21 01:46:24 +0000 | [diff] [blame] | 628 | if (crt_iga_path == IGA1) |
Florian Tobias Schandinat | 18d9dc0 | 2010-08-10 02:44:44 +0000 | [diff] [blame] | 629 | viaparinfo->shared->iga1_devices |= VIA_CRT; |
| 630 | else |
| 631 | viaparinfo->shared->iga2_devices |= VIA_CRT; |
| 632 | } |
| 633 | |
| 634 | if (viafb_DVI_ON) { |
| 635 | if (viaparinfo->tmds_setting_info->iga_path == IGA1) |
| 636 | viaparinfo->shared->iga1_devices |= get_dvi_devices( |
| 637 | viaparinfo->chip_info-> |
| 638 | tmds_chip_info.output_interface); |
| 639 | else |
| 640 | viaparinfo->shared->iga2_devices |= get_dvi_devices( |
| 641 | viaparinfo->chip_info-> |
| 642 | tmds_chip_info.output_interface); |
| 643 | } |
| 644 | |
| 645 | if (viafb_LCD_ON) { |
| 646 | if (viaparinfo->lvds_setting_info->iga_path == IGA1) |
| 647 | viaparinfo->shared->iga1_devices |= get_lcd_devices( |
| 648 | viaparinfo->chip_info-> |
| 649 | lvds_chip_info.output_interface); |
| 650 | else |
| 651 | viaparinfo->shared->iga2_devices |= get_lcd_devices( |
| 652 | viaparinfo->chip_info-> |
| 653 | lvds_chip_info.output_interface); |
| 654 | } |
| 655 | |
| 656 | if (viafb_LCD2_ON) { |
| 657 | if (viaparinfo->lvds_setting_info2->iga_path == IGA1) |
| 658 | viaparinfo->shared->iga1_devices |= get_lcd_devices( |
| 659 | viaparinfo->chip_info-> |
| 660 | lvds_chip_info2.output_interface); |
| 661 | else |
| 662 | viaparinfo->shared->iga2_devices |= get_lcd_devices( |
| 663 | viaparinfo->chip_info-> |
| 664 | lvds_chip_info2.output_interface); |
| 665 | } |
Florian Tobias Schandinat | 32fab7b | 2011-04-23 22:06:18 +0000 | [diff] [blame] | 666 | |
| 667 | /* looks like the OLPC has its display wired to DVP1 and LVDS2 */ |
| 668 | if (machine_is_olpc()) |
| 669 | viaparinfo->shared->iga2_devices = VIA_DVP1 | VIA_LVDS2; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 670 | } |
| 671 | |
Florian Tobias Schandinat | 415559f | 2010-03-10 15:21:40 -0800 | [diff] [blame] | 672 | static void set_color_register(u8 index, u8 red, u8 green, u8 blue) |
| 673 | { |
| 674 | outb(0xFF, 0x3C6); /* bit mask of palette */ |
| 675 | outb(index, 0x3C8); |
| 676 | outb(red, 0x3C9); |
| 677 | outb(green, 0x3C9); |
| 678 | outb(blue, 0x3C9); |
| 679 | } |
| 680 | |
| 681 | void viafb_set_primary_color_register(u8 index, u8 red, u8 green, u8 blue) |
| 682 | { |
| 683 | viafb_write_reg_mask(0x1A, VIASR, 0x00, 0x01); |
| 684 | set_color_register(index, red, green, blue); |
| 685 | } |
| 686 | |
| 687 | void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue) |
| 688 | { |
| 689 | viafb_write_reg_mask(0x1A, VIASR, 0x01, 0x01); |
| 690 | set_color_register(index, red, green, blue); |
| 691 | } |
| 692 | |
Florian Tobias Schandinat | a54be17 | 2010-07-28 23:06:04 +0000 | [diff] [blame] | 693 | static void set_source_common(u8 index, u8 offset, u8 iga) |
| 694 | { |
| 695 | u8 value, mask = 1 << offset; |
| 696 | |
| 697 | switch (iga) { |
| 698 | case IGA1: |
| 699 | value = 0x00; |
| 700 | break; |
| 701 | case IGA2: |
| 702 | value = mask; |
| 703 | break; |
| 704 | default: |
| 705 | printk(KERN_WARNING "viafb: Unsupported source: %d\n", iga); |
| 706 | return; |
| 707 | } |
| 708 | |
| 709 | via_write_reg_mask(VIACR, index, value, mask); |
| 710 | } |
| 711 | |
| 712 | static void set_crt_source(u8 iga) |
| 713 | { |
| 714 | u8 value; |
| 715 | |
| 716 | switch (iga) { |
| 717 | case IGA1: |
| 718 | value = 0x00; |
| 719 | break; |
| 720 | case IGA2: |
| 721 | value = 0x40; |
| 722 | break; |
| 723 | default: |
| 724 | printk(KERN_WARNING "viafb: Unsupported source: %d\n", iga); |
| 725 | return; |
| 726 | } |
| 727 | |
| 728 | via_write_reg_mask(VIASR, 0x16, value, 0x40); |
| 729 | } |
| 730 | |
Florian Tobias Schandinat | a2aa9f9 | 2010-09-19 04:40:15 +0000 | [diff] [blame] | 731 | static inline void set_ldvp0_source(u8 iga) |
Florian Tobias Schandinat | a54be17 | 2010-07-28 23:06:04 +0000 | [diff] [blame] | 732 | { |
| 733 | set_source_common(0x6C, 7, iga); |
| 734 | } |
| 735 | |
Florian Tobias Schandinat | a2aa9f9 | 2010-09-19 04:40:15 +0000 | [diff] [blame] | 736 | static inline void set_ldvp1_source(u8 iga) |
Florian Tobias Schandinat | a54be17 | 2010-07-28 23:06:04 +0000 | [diff] [blame] | 737 | { |
| 738 | set_source_common(0x93, 7, iga); |
| 739 | } |
| 740 | |
Florian Tobias Schandinat | a2aa9f9 | 2010-09-19 04:40:15 +0000 | [diff] [blame] | 741 | static inline void set_dvp0_source(u8 iga) |
Florian Tobias Schandinat | a54be17 | 2010-07-28 23:06:04 +0000 | [diff] [blame] | 742 | { |
| 743 | set_source_common(0x96, 4, iga); |
| 744 | } |
| 745 | |
| 746 | static inline void set_dvp1_source(u8 iga) |
| 747 | { |
| 748 | set_source_common(0x9B, 4, iga); |
| 749 | } |
| 750 | |
| 751 | static inline void set_lvds1_source(u8 iga) |
| 752 | { |
| 753 | set_source_common(0x99, 4, iga); |
| 754 | } |
| 755 | |
| 756 | static inline void set_lvds2_source(u8 iga) |
| 757 | { |
| 758 | set_source_common(0x97, 4, iga); |
| 759 | } |
| 760 | |
Florian Tobias Schandinat | bc68488 | 2010-08-11 00:37:58 +0000 | [diff] [blame] | 761 | void via_set_source(u32 devices, u8 iga) |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 762 | { |
Florian Tobias Schandinat | a2aa9f9 | 2010-09-19 04:40:15 +0000 | [diff] [blame] | 763 | if (devices & VIA_LDVP0) |
| 764 | set_ldvp0_source(iga); |
| 765 | if (devices & VIA_LDVP1) |
| 766 | set_ldvp1_source(iga); |
| 767 | if (devices & VIA_DVP0) |
| 768 | set_dvp0_source(iga); |
Florian Tobias Schandinat | bc68488 | 2010-08-11 00:37:58 +0000 | [diff] [blame] | 769 | if (devices & VIA_CRT) |
| 770 | set_crt_source(iga); |
| 771 | if (devices & VIA_DVP1) |
| 772 | set_dvp1_source(iga); |
| 773 | if (devices & VIA_LVDS1) |
| 774 | set_lvds1_source(iga); |
| 775 | if (devices & VIA_LVDS2) |
| 776 | set_lvds2_source(iga); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 777 | } |
| 778 | |
Florian Tobias Schandinat | 6f9422d | 2010-09-07 14:28:26 +0000 | [diff] [blame] | 779 | static void set_crt_state(u8 state) |
| 780 | { |
| 781 | u8 value; |
| 782 | |
| 783 | switch (state) { |
| 784 | case VIA_STATE_ON: |
| 785 | value = 0x00; |
| 786 | break; |
| 787 | case VIA_STATE_STANDBY: |
| 788 | value = 0x10; |
| 789 | break; |
| 790 | case VIA_STATE_SUSPEND: |
| 791 | value = 0x20; |
| 792 | break; |
| 793 | case VIA_STATE_OFF: |
| 794 | value = 0x30; |
| 795 | break; |
| 796 | default: |
| 797 | return; |
| 798 | } |
| 799 | |
| 800 | via_write_reg_mask(VIACR, 0x36, value, 0x30); |
| 801 | } |
| 802 | |
Florian Tobias Schandinat | a2aa9f9 | 2010-09-19 04:40:15 +0000 | [diff] [blame] | 803 | static void set_dvp0_state(u8 state) |
Florian Tobias Schandinat | 6f9422d | 2010-09-07 14:28:26 +0000 | [diff] [blame] | 804 | { |
| 805 | u8 value; |
| 806 | |
| 807 | switch (state) { |
| 808 | case VIA_STATE_ON: |
| 809 | value = 0xC0; |
| 810 | break; |
| 811 | case VIA_STATE_OFF: |
| 812 | value = 0x00; |
| 813 | break; |
| 814 | default: |
| 815 | return; |
| 816 | } |
| 817 | |
| 818 | via_write_reg_mask(VIASR, 0x1E, value, 0xC0); |
| 819 | } |
| 820 | |
| 821 | static void set_dvp1_state(u8 state) |
| 822 | { |
| 823 | u8 value; |
| 824 | |
| 825 | switch (state) { |
| 826 | case VIA_STATE_ON: |
| 827 | value = 0x30; |
| 828 | break; |
| 829 | case VIA_STATE_OFF: |
| 830 | value = 0x00; |
| 831 | break; |
| 832 | default: |
| 833 | return; |
| 834 | } |
| 835 | |
| 836 | via_write_reg_mask(VIASR, 0x1E, value, 0x30); |
| 837 | } |
| 838 | |
| 839 | static void set_lvds1_state(u8 state) |
| 840 | { |
| 841 | u8 value; |
| 842 | |
| 843 | switch (state) { |
| 844 | case VIA_STATE_ON: |
| 845 | value = 0x03; |
| 846 | break; |
| 847 | case VIA_STATE_OFF: |
| 848 | value = 0x00; |
| 849 | break; |
| 850 | default: |
| 851 | return; |
| 852 | } |
| 853 | |
| 854 | via_write_reg_mask(VIASR, 0x2A, value, 0x03); |
| 855 | } |
| 856 | |
| 857 | static void set_lvds2_state(u8 state) |
| 858 | { |
| 859 | u8 value; |
| 860 | |
| 861 | switch (state) { |
| 862 | case VIA_STATE_ON: |
| 863 | value = 0x0C; |
| 864 | break; |
| 865 | case VIA_STATE_OFF: |
| 866 | value = 0x00; |
| 867 | break; |
| 868 | default: |
| 869 | return; |
| 870 | } |
| 871 | |
| 872 | via_write_reg_mask(VIASR, 0x2A, value, 0x0C); |
| 873 | } |
| 874 | |
| 875 | void via_set_state(u32 devices, u8 state) |
| 876 | { |
| 877 | /* |
| 878 | TODO: Can we enable/disable these devices? How? |
Florian Tobias Schandinat | a2aa9f9 | 2010-09-19 04:40:15 +0000 | [diff] [blame] | 879 | if (devices & VIA_LDVP0) |
| 880 | if (devices & VIA_LDVP1) |
Florian Tobias Schandinat | 6f9422d | 2010-09-07 14:28:26 +0000 | [diff] [blame] | 881 | */ |
Florian Tobias Schandinat | a2aa9f9 | 2010-09-19 04:40:15 +0000 | [diff] [blame] | 882 | if (devices & VIA_DVP0) |
| 883 | set_dvp0_state(state); |
Florian Tobias Schandinat | 6f9422d | 2010-09-07 14:28:26 +0000 | [diff] [blame] | 884 | if (devices & VIA_CRT) |
| 885 | set_crt_state(state); |
| 886 | if (devices & VIA_DVP1) |
| 887 | set_dvp1_state(state); |
| 888 | if (devices & VIA_LVDS1) |
| 889 | set_lvds1_state(state); |
| 890 | if (devices & VIA_LVDS2) |
| 891 | set_lvds2_state(state); |
| 892 | } |
| 893 | |
Florian Tobias Schandinat | 7f0e153 | 2010-09-18 23:47:28 +0000 | [diff] [blame] | 894 | void via_set_sync_polarity(u32 devices, u8 polarity) |
| 895 | { |
| 896 | if (polarity & ~(VIA_HSYNC_NEGATIVE | VIA_VSYNC_NEGATIVE)) { |
| 897 | printk(KERN_WARNING "viafb: Unsupported polarity: %d\n", |
| 898 | polarity); |
| 899 | return; |
| 900 | } |
| 901 | |
| 902 | if (devices & VIA_CRT) |
| 903 | via_write_misc_reg_mask(polarity << 6, 0xC0); |
| 904 | if (devices & VIA_DVP1) |
| 905 | via_write_reg_mask(VIACR, 0x9B, polarity << 5, 0x60); |
| 906 | if (devices & VIA_LVDS1) |
| 907 | via_write_reg_mask(VIACR, 0x99, polarity << 5, 0x60); |
| 908 | if (devices & VIA_LVDS2) |
| 909 | via_write_reg_mask(VIACR, 0x97, polarity << 5, 0x60); |
| 910 | } |
| 911 | |
Florian Tobias Schandinat | 2a91839 | 2010-09-05 01:33:28 +0000 | [diff] [blame] | 912 | u32 via_parse_odev(char *input, char **end) |
| 913 | { |
| 914 | char *ptr = input; |
| 915 | u32 odev = 0; |
| 916 | bool next = true; |
| 917 | int i, len; |
| 918 | |
| 919 | while (next) { |
| 920 | next = false; |
| 921 | for (i = 0; i < ARRAY_SIZE(device_mapping); i++) { |
| 922 | len = strlen(device_mapping[i].name); |
| 923 | if (!strncmp(ptr, device_mapping[i].name, len)) { |
| 924 | odev |= device_mapping[i].device; |
| 925 | ptr += len; |
| 926 | if (*ptr == ',') { |
| 927 | ptr++; |
| 928 | next = true; |
| 929 | } |
| 930 | } |
| 931 | } |
| 932 | } |
| 933 | |
| 934 | *end = ptr; |
| 935 | return odev; |
| 936 | } |
| 937 | |
| 938 | void via_odev_to_seq(struct seq_file *m, u32 odev) |
| 939 | { |
| 940 | int i, count = 0; |
| 941 | |
| 942 | for (i = 0; i < ARRAY_SIZE(device_mapping); i++) { |
| 943 | if (odev & device_mapping[i].device) { |
| 944 | if (count > 0) |
| 945 | seq_putc(m, ','); |
| 946 | |
| 947 | seq_puts(m, device_mapping[i].name); |
| 948 | count++; |
| 949 | } |
| 950 | } |
| 951 | |
| 952 | seq_putc(m, '\n'); |
| 953 | } |
| 954 | |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 955 | static void load_fix_bit_crtc_reg(void) |
| 956 | { |
Florian Tobias Schandinat | 0f8132b | 2011-03-16 13:11:17 +0000 | [diff] [blame] | 957 | viafb_unlock_crt(); |
| 958 | |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 959 | /* always set to 1 */ |
| 960 | viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7); |
| 961 | /* line compare should set all bits = 1 (extend modes) */ |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 962 | viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4); |
| 963 | /* line compare should set all bits = 1 (extend modes) */ |
| 964 | viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2); |
| 965 | /*viafb_write_reg_mask(CR32, VIACR, 0x01, BIT0); */ |
Florian Tobias Schandinat | 0f8132b | 2011-03-16 13:11:17 +0000 | [diff] [blame] | 966 | |
| 967 | viafb_lock_crt(); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 968 | |
| 969 | /* If K8M800, enable Prefetch Mode. */ |
| 970 | if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) |
| 971 | || (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890)) |
| 972 | viafb_write_reg_mask(CR33, VIACR, 0x08, BIT3); |
| 973 | if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) |
| 974 | && (viaparinfo->chip_info->gfx_chip_revision == CLE266_REVISION_AX)) |
| 975 | viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1); |
| 976 | |
| 977 | } |
| 978 | |
| 979 | void viafb_load_reg(int timing_value, int viafb_load_reg_num, |
| 980 | struct io_register *reg, |
| 981 | int io_type) |
| 982 | { |
| 983 | int reg_mask; |
| 984 | int bit_num = 0; |
| 985 | int data; |
| 986 | int i, j; |
| 987 | int shift_next_reg; |
| 988 | int start_index, end_index, cr_index; |
| 989 | u16 get_bit; |
| 990 | |
| 991 | for (i = 0; i < viafb_load_reg_num; i++) { |
| 992 | reg_mask = 0; |
| 993 | data = 0; |
| 994 | start_index = reg[i].start_bit; |
| 995 | end_index = reg[i].end_bit; |
| 996 | cr_index = reg[i].io_addr; |
| 997 | |
| 998 | shift_next_reg = bit_num; |
| 999 | for (j = start_index; j <= end_index; j++) { |
| 1000 | /*if (bit_num==8) timing_value = timing_value >>8; */ |
| 1001 | reg_mask = reg_mask | (BIT0 << j); |
| 1002 | get_bit = (timing_value & (BIT0 << bit_num)); |
| 1003 | data = |
| 1004 | data | ((get_bit >> shift_next_reg) << start_index); |
| 1005 | bit_num++; |
| 1006 | } |
| 1007 | if (io_type == VIACR) |
| 1008 | viafb_write_reg_mask(cr_index, VIACR, data, reg_mask); |
| 1009 | else |
| 1010 | viafb_write_reg_mask(cr_index, VIASR, data, reg_mask); |
| 1011 | } |
| 1012 | |
| 1013 | } |
| 1014 | |
| 1015 | /* Write Registers */ |
| 1016 | void viafb_write_regx(struct io_reg RegTable[], int ItemNum) |
| 1017 | { |
| 1018 | int i; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1019 | |
| 1020 | /*DEBUG_MSG(KERN_INFO "Table Size : %x!!\n",ItemNum ); */ |
| 1021 | |
Florian Tobias Schandinat | 384c304 | 2010-04-17 19:44:54 +0000 | [diff] [blame] | 1022 | for (i = 0; i < ItemNum; i++) |
| 1023 | via_write_reg_mask(RegTable[i].port, RegTable[i].index, |
| 1024 | RegTable[i].value, RegTable[i].mask); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1025 | } |
| 1026 | |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1027 | void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga) |
| 1028 | { |
| 1029 | int reg_value; |
| 1030 | int viafb_load_reg_num; |
| 1031 | struct io_register *reg = NULL; |
| 1032 | |
| 1033 | switch (set_iga) { |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1034 | case IGA1: |
| 1035 | reg_value = IGA1_FETCH_COUNT_FORMULA(h_addr, bpp_byte); |
| 1036 | viafb_load_reg_num = fetch_count_reg. |
| 1037 | iga1_fetch_count_reg.reg_num; |
| 1038 | reg = fetch_count_reg.iga1_fetch_count_reg.reg; |
| 1039 | viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR); |
Florian Tobias Schandinat | 4bbac05 | 2010-03-10 15:21:36 -0800 | [diff] [blame] | 1040 | break; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1041 | case IGA2: |
| 1042 | reg_value = IGA2_FETCH_COUNT_FORMULA(h_addr, bpp_byte); |
| 1043 | viafb_load_reg_num = fetch_count_reg. |
| 1044 | iga2_fetch_count_reg.reg_num; |
| 1045 | reg = fetch_count_reg.iga2_fetch_count_reg.reg; |
| 1046 | viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR); |
| 1047 | break; |
| 1048 | } |
| 1049 | |
| 1050 | } |
| 1051 | |
| 1052 | void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active) |
| 1053 | { |
| 1054 | int reg_value; |
| 1055 | int viafb_load_reg_num; |
| 1056 | struct io_register *reg = NULL; |
| 1057 | int iga1_fifo_max_depth = 0, iga1_fifo_threshold = |
| 1058 | 0, iga1_fifo_high_threshold = 0, iga1_display_queue_expire_num = 0; |
| 1059 | int iga2_fifo_max_depth = 0, iga2_fifo_threshold = |
| 1060 | 0, iga2_fifo_high_threshold = 0, iga2_display_queue_expire_num = 0; |
| 1061 | |
| 1062 | if (set_iga == IGA1) { |
| 1063 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) { |
| 1064 | iga1_fifo_max_depth = K800_IGA1_FIFO_MAX_DEPTH; |
| 1065 | iga1_fifo_threshold = K800_IGA1_FIFO_THRESHOLD; |
| 1066 | iga1_fifo_high_threshold = |
| 1067 | K800_IGA1_FIFO_HIGH_THRESHOLD; |
| 1068 | /* If resolution > 1280x1024, expire length = 64, else |
| 1069 | expire length = 128 */ |
| 1070 | if ((hor_active > 1280) && (ver_active > 1024)) |
| 1071 | iga1_display_queue_expire_num = 16; |
| 1072 | else |
| 1073 | iga1_display_queue_expire_num = |
| 1074 | K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; |
| 1075 | |
| 1076 | } |
| 1077 | |
| 1078 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) { |
| 1079 | iga1_fifo_max_depth = P880_IGA1_FIFO_MAX_DEPTH; |
| 1080 | iga1_fifo_threshold = P880_IGA1_FIFO_THRESHOLD; |
| 1081 | iga1_fifo_high_threshold = |
| 1082 | P880_IGA1_FIFO_HIGH_THRESHOLD; |
| 1083 | iga1_display_queue_expire_num = |
| 1084 | P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; |
| 1085 | |
| 1086 | /* If resolution > 1280x1024, expire length = 64, else |
| 1087 | expire length = 128 */ |
| 1088 | if ((hor_active > 1280) && (ver_active > 1024)) |
| 1089 | iga1_display_queue_expire_num = 16; |
| 1090 | else |
| 1091 | iga1_display_queue_expire_num = |
| 1092 | P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; |
| 1093 | } |
| 1094 | |
| 1095 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) { |
| 1096 | iga1_fifo_max_depth = CN700_IGA1_FIFO_MAX_DEPTH; |
| 1097 | iga1_fifo_threshold = CN700_IGA1_FIFO_THRESHOLD; |
| 1098 | iga1_fifo_high_threshold = |
| 1099 | CN700_IGA1_FIFO_HIGH_THRESHOLD; |
| 1100 | |
| 1101 | /* If resolution > 1280x1024, expire length = 64, |
| 1102 | else expire length = 128 */ |
| 1103 | if ((hor_active > 1280) && (ver_active > 1024)) |
| 1104 | iga1_display_queue_expire_num = 16; |
| 1105 | else |
| 1106 | iga1_display_queue_expire_num = |
| 1107 | CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; |
| 1108 | } |
| 1109 | |
| 1110 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) { |
| 1111 | iga1_fifo_max_depth = CX700_IGA1_FIFO_MAX_DEPTH; |
| 1112 | iga1_fifo_threshold = CX700_IGA1_FIFO_THRESHOLD; |
| 1113 | iga1_fifo_high_threshold = |
| 1114 | CX700_IGA1_FIFO_HIGH_THRESHOLD; |
| 1115 | iga1_display_queue_expire_num = |
| 1116 | CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; |
| 1117 | } |
| 1118 | |
| 1119 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) { |
| 1120 | iga1_fifo_max_depth = K8M890_IGA1_FIFO_MAX_DEPTH; |
| 1121 | iga1_fifo_threshold = K8M890_IGA1_FIFO_THRESHOLD; |
| 1122 | iga1_fifo_high_threshold = |
| 1123 | K8M890_IGA1_FIFO_HIGH_THRESHOLD; |
| 1124 | iga1_display_queue_expire_num = |
| 1125 | K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; |
| 1126 | } |
| 1127 | |
| 1128 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) { |
| 1129 | iga1_fifo_max_depth = P4M890_IGA1_FIFO_MAX_DEPTH; |
| 1130 | iga1_fifo_threshold = P4M890_IGA1_FIFO_THRESHOLD; |
| 1131 | iga1_fifo_high_threshold = |
| 1132 | P4M890_IGA1_FIFO_HIGH_THRESHOLD; |
| 1133 | iga1_display_queue_expire_num = |
| 1134 | P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; |
| 1135 | } |
| 1136 | |
| 1137 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) { |
| 1138 | iga1_fifo_max_depth = P4M900_IGA1_FIFO_MAX_DEPTH; |
| 1139 | iga1_fifo_threshold = P4M900_IGA1_FIFO_THRESHOLD; |
| 1140 | iga1_fifo_high_threshold = |
| 1141 | P4M900_IGA1_FIFO_HIGH_THRESHOLD; |
| 1142 | iga1_display_queue_expire_num = |
| 1143 | P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; |
| 1144 | } |
| 1145 | |
| 1146 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) { |
| 1147 | iga1_fifo_max_depth = VX800_IGA1_FIFO_MAX_DEPTH; |
| 1148 | iga1_fifo_threshold = VX800_IGA1_FIFO_THRESHOLD; |
| 1149 | iga1_fifo_high_threshold = |
| 1150 | VX800_IGA1_FIFO_HIGH_THRESHOLD; |
| 1151 | iga1_display_queue_expire_num = |
| 1152 | VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; |
| 1153 | } |
| 1154 | |
Harald Welte | 0306ab1 | 2009-09-22 16:47:35 -0700 | [diff] [blame] | 1155 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) { |
| 1156 | iga1_fifo_max_depth = VX855_IGA1_FIFO_MAX_DEPTH; |
| 1157 | iga1_fifo_threshold = VX855_IGA1_FIFO_THRESHOLD; |
| 1158 | iga1_fifo_high_threshold = |
| 1159 | VX855_IGA1_FIFO_HIGH_THRESHOLD; |
| 1160 | iga1_display_queue_expire_num = |
| 1161 | VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; |
| 1162 | } |
| 1163 | |
Florian Tobias Schandinat | 51f4332 | 2010-10-24 04:02:14 +0000 | [diff] [blame] | 1164 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX900) { |
| 1165 | iga1_fifo_max_depth = VX900_IGA1_FIFO_MAX_DEPTH; |
| 1166 | iga1_fifo_threshold = VX900_IGA1_FIFO_THRESHOLD; |
| 1167 | iga1_fifo_high_threshold = |
| 1168 | VX900_IGA1_FIFO_HIGH_THRESHOLD; |
| 1169 | iga1_display_queue_expire_num = |
| 1170 | VX900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; |
| 1171 | } |
| 1172 | |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1173 | /* Set Display FIFO Depath Select */ |
| 1174 | reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth); |
| 1175 | viafb_load_reg_num = |
| 1176 | display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg_num; |
| 1177 | reg = display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg; |
| 1178 | viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR); |
| 1179 | |
| 1180 | /* Set Display FIFO Threshold Select */ |
| 1181 | reg_value = IGA1_FIFO_THRESHOLD_FORMULA(iga1_fifo_threshold); |
| 1182 | viafb_load_reg_num = |
| 1183 | fifo_threshold_select_reg. |
| 1184 | iga1_fifo_threshold_select_reg.reg_num; |
| 1185 | reg = |
| 1186 | fifo_threshold_select_reg. |
| 1187 | iga1_fifo_threshold_select_reg.reg; |
| 1188 | viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR); |
| 1189 | |
| 1190 | /* Set FIFO High Threshold Select */ |
| 1191 | reg_value = |
| 1192 | IGA1_FIFO_HIGH_THRESHOLD_FORMULA(iga1_fifo_high_threshold); |
| 1193 | viafb_load_reg_num = |
| 1194 | fifo_high_threshold_select_reg. |
| 1195 | iga1_fifo_high_threshold_select_reg.reg_num; |
| 1196 | reg = |
| 1197 | fifo_high_threshold_select_reg. |
| 1198 | iga1_fifo_high_threshold_select_reg.reg; |
| 1199 | viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR); |
| 1200 | |
| 1201 | /* Set Display Queue Expire Num */ |
| 1202 | reg_value = |
| 1203 | IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA |
| 1204 | (iga1_display_queue_expire_num); |
| 1205 | viafb_load_reg_num = |
| 1206 | display_queue_expire_num_reg. |
| 1207 | iga1_display_queue_expire_num_reg.reg_num; |
| 1208 | reg = |
| 1209 | display_queue_expire_num_reg. |
| 1210 | iga1_display_queue_expire_num_reg.reg; |
| 1211 | viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR); |
| 1212 | |
| 1213 | } else { |
| 1214 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) { |
| 1215 | iga2_fifo_max_depth = K800_IGA2_FIFO_MAX_DEPTH; |
| 1216 | iga2_fifo_threshold = K800_IGA2_FIFO_THRESHOLD; |
| 1217 | iga2_fifo_high_threshold = |
| 1218 | K800_IGA2_FIFO_HIGH_THRESHOLD; |
| 1219 | |
| 1220 | /* If resolution > 1280x1024, expire length = 64, |
| 1221 | else expire length = 128 */ |
| 1222 | if ((hor_active > 1280) && (ver_active > 1024)) |
| 1223 | iga2_display_queue_expire_num = 16; |
| 1224 | else |
| 1225 | iga2_display_queue_expire_num = |
| 1226 | K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM; |
| 1227 | } |
| 1228 | |
| 1229 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) { |
| 1230 | iga2_fifo_max_depth = P880_IGA2_FIFO_MAX_DEPTH; |
| 1231 | iga2_fifo_threshold = P880_IGA2_FIFO_THRESHOLD; |
| 1232 | iga2_fifo_high_threshold = |
| 1233 | P880_IGA2_FIFO_HIGH_THRESHOLD; |
| 1234 | |
| 1235 | /* If resolution > 1280x1024, expire length = 64, |
| 1236 | else expire length = 128 */ |
| 1237 | if ((hor_active > 1280) && (ver_active > 1024)) |
| 1238 | iga2_display_queue_expire_num = 16; |
| 1239 | else |
| 1240 | iga2_display_queue_expire_num = |
| 1241 | P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM; |
| 1242 | } |
| 1243 | |
| 1244 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) { |
| 1245 | iga2_fifo_max_depth = CN700_IGA2_FIFO_MAX_DEPTH; |
| 1246 | iga2_fifo_threshold = CN700_IGA2_FIFO_THRESHOLD; |
| 1247 | iga2_fifo_high_threshold = |
| 1248 | CN700_IGA2_FIFO_HIGH_THRESHOLD; |
| 1249 | |
| 1250 | /* If resolution > 1280x1024, expire length = 64, |
| 1251 | else expire length = 128 */ |
| 1252 | if ((hor_active > 1280) && (ver_active > 1024)) |
| 1253 | iga2_display_queue_expire_num = 16; |
| 1254 | else |
| 1255 | iga2_display_queue_expire_num = |
| 1256 | CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM; |
| 1257 | } |
| 1258 | |
| 1259 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) { |
| 1260 | iga2_fifo_max_depth = CX700_IGA2_FIFO_MAX_DEPTH; |
| 1261 | iga2_fifo_threshold = CX700_IGA2_FIFO_THRESHOLD; |
| 1262 | iga2_fifo_high_threshold = |
| 1263 | CX700_IGA2_FIFO_HIGH_THRESHOLD; |
| 1264 | iga2_display_queue_expire_num = |
| 1265 | CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM; |
| 1266 | } |
| 1267 | |
| 1268 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) { |
| 1269 | iga2_fifo_max_depth = K8M890_IGA2_FIFO_MAX_DEPTH; |
| 1270 | iga2_fifo_threshold = K8M890_IGA2_FIFO_THRESHOLD; |
| 1271 | iga2_fifo_high_threshold = |
| 1272 | K8M890_IGA2_FIFO_HIGH_THRESHOLD; |
| 1273 | iga2_display_queue_expire_num = |
| 1274 | K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM; |
| 1275 | } |
| 1276 | |
| 1277 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) { |
| 1278 | iga2_fifo_max_depth = P4M890_IGA2_FIFO_MAX_DEPTH; |
| 1279 | iga2_fifo_threshold = P4M890_IGA2_FIFO_THRESHOLD; |
| 1280 | iga2_fifo_high_threshold = |
| 1281 | P4M890_IGA2_FIFO_HIGH_THRESHOLD; |
| 1282 | iga2_display_queue_expire_num = |
| 1283 | P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM; |
| 1284 | } |
| 1285 | |
| 1286 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) { |
| 1287 | iga2_fifo_max_depth = P4M900_IGA2_FIFO_MAX_DEPTH; |
| 1288 | iga2_fifo_threshold = P4M900_IGA2_FIFO_THRESHOLD; |
| 1289 | iga2_fifo_high_threshold = |
| 1290 | P4M900_IGA2_FIFO_HIGH_THRESHOLD; |
| 1291 | iga2_display_queue_expire_num = |
| 1292 | P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM; |
| 1293 | } |
| 1294 | |
| 1295 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) { |
| 1296 | iga2_fifo_max_depth = VX800_IGA2_FIFO_MAX_DEPTH; |
| 1297 | iga2_fifo_threshold = VX800_IGA2_FIFO_THRESHOLD; |
| 1298 | iga2_fifo_high_threshold = |
| 1299 | VX800_IGA2_FIFO_HIGH_THRESHOLD; |
| 1300 | iga2_display_queue_expire_num = |
| 1301 | VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM; |
| 1302 | } |
| 1303 | |
Harald Welte | 0306ab1 | 2009-09-22 16:47:35 -0700 | [diff] [blame] | 1304 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) { |
| 1305 | iga2_fifo_max_depth = VX855_IGA2_FIFO_MAX_DEPTH; |
| 1306 | iga2_fifo_threshold = VX855_IGA2_FIFO_THRESHOLD; |
| 1307 | iga2_fifo_high_threshold = |
| 1308 | VX855_IGA2_FIFO_HIGH_THRESHOLD; |
| 1309 | iga2_display_queue_expire_num = |
| 1310 | VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM; |
| 1311 | } |
| 1312 | |
Florian Tobias Schandinat | 51f4332 | 2010-10-24 04:02:14 +0000 | [diff] [blame] | 1313 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX900) { |
| 1314 | iga2_fifo_max_depth = VX900_IGA2_FIFO_MAX_DEPTH; |
| 1315 | iga2_fifo_threshold = VX900_IGA2_FIFO_THRESHOLD; |
| 1316 | iga2_fifo_high_threshold = |
| 1317 | VX900_IGA2_FIFO_HIGH_THRESHOLD; |
| 1318 | iga2_display_queue_expire_num = |
| 1319 | VX900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM; |
| 1320 | } |
| 1321 | |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1322 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) { |
| 1323 | /* Set Display FIFO Depath Select */ |
| 1324 | reg_value = |
| 1325 | IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth) |
| 1326 | - 1; |
| 1327 | /* Patch LCD in IGA2 case */ |
| 1328 | viafb_load_reg_num = |
| 1329 | display_fifo_depth_reg. |
| 1330 | iga2_fifo_depth_select_reg.reg_num; |
| 1331 | reg = |
| 1332 | display_fifo_depth_reg. |
| 1333 | iga2_fifo_depth_select_reg.reg; |
| 1334 | viafb_load_reg(reg_value, |
| 1335 | viafb_load_reg_num, reg, VIACR); |
| 1336 | } else { |
| 1337 | |
| 1338 | /* Set Display FIFO Depath Select */ |
| 1339 | reg_value = |
| 1340 | IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth); |
| 1341 | viafb_load_reg_num = |
| 1342 | display_fifo_depth_reg. |
| 1343 | iga2_fifo_depth_select_reg.reg_num; |
| 1344 | reg = |
| 1345 | display_fifo_depth_reg. |
| 1346 | iga2_fifo_depth_select_reg.reg; |
| 1347 | viafb_load_reg(reg_value, |
| 1348 | viafb_load_reg_num, reg, VIACR); |
| 1349 | } |
| 1350 | |
| 1351 | /* Set Display FIFO Threshold Select */ |
| 1352 | reg_value = IGA2_FIFO_THRESHOLD_FORMULA(iga2_fifo_threshold); |
| 1353 | viafb_load_reg_num = |
| 1354 | fifo_threshold_select_reg. |
| 1355 | iga2_fifo_threshold_select_reg.reg_num; |
| 1356 | reg = |
| 1357 | fifo_threshold_select_reg. |
| 1358 | iga2_fifo_threshold_select_reg.reg; |
| 1359 | viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR); |
| 1360 | |
| 1361 | /* Set FIFO High Threshold Select */ |
| 1362 | reg_value = |
| 1363 | IGA2_FIFO_HIGH_THRESHOLD_FORMULA(iga2_fifo_high_threshold); |
| 1364 | viafb_load_reg_num = |
| 1365 | fifo_high_threshold_select_reg. |
| 1366 | iga2_fifo_high_threshold_select_reg.reg_num; |
| 1367 | reg = |
| 1368 | fifo_high_threshold_select_reg. |
| 1369 | iga2_fifo_high_threshold_select_reg.reg; |
| 1370 | viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR); |
| 1371 | |
| 1372 | /* Set Display Queue Expire Num */ |
| 1373 | reg_value = |
| 1374 | IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA |
| 1375 | (iga2_display_queue_expire_num); |
| 1376 | viafb_load_reg_num = |
| 1377 | display_queue_expire_num_reg. |
| 1378 | iga2_display_queue_expire_num_reg.reg_num; |
| 1379 | reg = |
| 1380 | display_queue_expire_num_reg. |
| 1381 | iga2_display_queue_expire_num_reg.reg; |
| 1382 | viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR); |
| 1383 | |
| 1384 | } |
| 1385 | |
| 1386 | } |
| 1387 | |
Florian Tobias Schandinat | 2c536f8 | 2011-03-24 13:30:09 +0000 | [diff] [blame] | 1388 | static struct via_pll_config get_pll_config(struct pll_limit *limits, int size, |
Florian Tobias Schandinat | e4fcaef | 2011-03-12 01:36:38 +0000 | [diff] [blame] | 1389 | int clk) |
| 1390 | { |
Florian Tobias Schandinat | 2c536f8 | 2011-03-24 13:30:09 +0000 | [diff] [blame] | 1391 | struct via_pll_config cur, up, down, best = {0, 1, 0}; |
Florian Tobias Schandinat | e4fcaef | 2011-03-12 01:36:38 +0000 | [diff] [blame] | 1392 | const u32 f0 = 14318180; /* X1 frequency */ |
Florian Tobias Schandinat | eb0536c | 2011-03-21 13:28:26 +0000 | [diff] [blame] | 1393 | int i, f; |
Florian Tobias Schandinat | e4fcaef | 2011-03-12 01:36:38 +0000 | [diff] [blame] | 1394 | |
Florian Tobias Schandinat | eb0536c | 2011-03-21 13:28:26 +0000 | [diff] [blame] | 1395 | for (i = 0; i < size; i++) { |
| 1396 | cur.rshift = limits[i].rshift; |
| 1397 | cur.divisor = limits[i].divisor; |
| 1398 | cur.multiplier = clk / ((f0 / cur.divisor)>>cur.rshift); |
| 1399 | f = abs(get_pll_output_frequency(f0, cur) - clk); |
| 1400 | up = down = cur; |
| 1401 | up.multiplier++; |
| 1402 | down.multiplier--; |
| 1403 | if (abs(get_pll_output_frequency(f0, up) - clk) < f) |
| 1404 | cur = up; |
| 1405 | else if (abs(get_pll_output_frequency(f0, down) - clk) < f) |
| 1406 | cur = down; |
| 1407 | |
| 1408 | if (cur.multiplier < limits[i].multiplier_min) |
| 1409 | cur.multiplier = limits[i].multiplier_min; |
| 1410 | else if (cur.multiplier > limits[i].multiplier_max) |
| 1411 | cur.multiplier = limits[i].multiplier_max; |
| 1412 | |
| 1413 | f = abs(get_pll_output_frequency(f0, cur) - clk); |
| 1414 | if (f < abs(get_pll_output_frequency(f0, best) - clk)) |
| 1415 | best = cur; |
Florian Tobias Schandinat | e4fcaef | 2011-03-12 01:36:38 +0000 | [diff] [blame] | 1416 | } |
| 1417 | |
| 1418 | return best; |
| 1419 | } |
| 1420 | |
Florian Tobias Schandinat | 2c536f8 | 2011-03-24 13:30:09 +0000 | [diff] [blame] | 1421 | static struct via_pll_config get_best_pll_config(int clk) |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1422 | { |
Florian Tobias Schandinat | 2c536f8 | 2011-03-24 13:30:09 +0000 | [diff] [blame] | 1423 | struct via_pll_config config; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1424 | |
Florian Tobias Schandinat | 97597a3 | 2011-03-10 22:39:22 +0000 | [diff] [blame] | 1425 | switch (viaparinfo->chip_info->gfx_chip_name) { |
| 1426 | case UNICHROME_CLE266: |
| 1427 | case UNICHROME_K400: |
Florian Tobias Schandinat | 0f77d4a | 2011-03-23 17:14:26 +0000 | [diff] [blame] | 1428 | config = get_pll_config(cle266_pll_limits, |
| 1429 | ARRAY_SIZE(cle266_pll_limits), clk); |
Florian Tobias Schandinat | 97597a3 | 2011-03-10 22:39:22 +0000 | [diff] [blame] | 1430 | break; |
| 1431 | case UNICHROME_K800: |
| 1432 | case UNICHROME_PM800: |
| 1433 | case UNICHROME_CN700: |
Florian Tobias Schandinat | 0f77d4a | 2011-03-23 17:14:26 +0000 | [diff] [blame] | 1434 | config = get_pll_config(k800_pll_limits, |
| 1435 | ARRAY_SIZE(k800_pll_limits), clk); |
Florian Tobias Schandinat | 97597a3 | 2011-03-10 22:39:22 +0000 | [diff] [blame] | 1436 | break; |
| 1437 | case UNICHROME_CX700: |
| 1438 | case UNICHROME_CN750: |
| 1439 | case UNICHROME_K8M890: |
| 1440 | case UNICHROME_P4M890: |
| 1441 | case UNICHROME_P4M900: |
| 1442 | case UNICHROME_VX800: |
Florian Tobias Schandinat | 0f77d4a | 2011-03-23 17:14:26 +0000 | [diff] [blame] | 1443 | config = get_pll_config(cx700_pll_limits, |
| 1444 | ARRAY_SIZE(cx700_pll_limits), clk); |
Florian Tobias Schandinat | 97597a3 | 2011-03-10 22:39:22 +0000 | [diff] [blame] | 1445 | break; |
| 1446 | case UNICHROME_VX855: |
| 1447 | case UNICHROME_VX900: |
Florian Tobias Schandinat | 0f77d4a | 2011-03-23 17:14:26 +0000 | [diff] [blame] | 1448 | config = get_pll_config(vx855_pll_limits, |
| 1449 | ARRAY_SIZE(vx855_pll_limits), clk); |
Florian Tobias Schandinat | 97597a3 | 2011-03-10 22:39:22 +0000 | [diff] [blame] | 1450 | break; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1451 | } |
| 1452 | |
Florian Tobias Schandinat | 0f77d4a | 2011-03-23 17:14:26 +0000 | [diff] [blame] | 1453 | return config; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1454 | } |
| 1455 | |
| 1456 | /* Set VCLK*/ |
Florian Tobias Schandinat | 1f84435 | 2010-07-11 00:57:34 +0000 | [diff] [blame] | 1457 | void viafb_set_vclock(u32 clk, int set_iga) |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1458 | { |
Florian Tobias Schandinat | 2c536f8 | 2011-03-24 13:30:09 +0000 | [diff] [blame] | 1459 | struct via_pll_config config = get_best_pll_config(clk); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1460 | |
Florian Tobias Schandinat | 2c536f8 | 2011-03-24 13:30:09 +0000 | [diff] [blame] | 1461 | if (set_iga == IGA1) |
| 1462 | clock.set_primary_pll(config); |
| 1463 | if (set_iga == IGA2) |
| 1464 | clock.set_secondary_pll(config); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1465 | |
| 1466 | /* Fire! */ |
Florian Tobias Schandinat | 162fc8c | 2010-04-17 19:44:55 +0000 | [diff] [blame] | 1467 | via_write_misc_reg_mask(0x0C, 0x0C); /* select external clock */ |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1468 | } |
| 1469 | |
Florian Tobias Schandinat | ebb29fb | 2011-08-07 01:51:41 +0000 | [diff] [blame] | 1470 | static struct display_timing var_to_timing(const struct fb_var_screeninfo *var) |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1471 | { |
Florian Tobias Schandinat | ebb29fb | 2011-08-07 01:51:41 +0000 | [diff] [blame] | 1472 | struct display_timing timing; |
Florian Tobias Schandinat | 726abbc | 2011-03-16 16:31:32 +0000 | [diff] [blame] | 1473 | |
Florian Tobias Schandinat | ebb29fb | 2011-08-07 01:51:41 +0000 | [diff] [blame] | 1474 | timing.hor_addr = var->xres; |
| 1475 | timing.hor_sync_start = timing.hor_addr + var->right_margin; |
| 1476 | timing.hor_sync_end = timing.hor_sync_start + var->hsync_len; |
| 1477 | timing.hor_total = timing.hor_sync_end + var->left_margin; |
| 1478 | timing.hor_blank_start = timing.hor_addr; |
| 1479 | timing.hor_blank_end = timing.hor_total; |
| 1480 | timing.ver_addr = var->yres; |
| 1481 | timing.ver_sync_start = timing.ver_addr + var->lower_margin; |
| 1482 | timing.ver_sync_end = timing.ver_sync_start + var->vsync_len; |
| 1483 | timing.ver_total = timing.ver_sync_end + var->upper_margin; |
| 1484 | timing.ver_blank_start = timing.ver_addr; |
| 1485 | timing.ver_blank_end = timing.ver_total; |
| 1486 | return timing; |
| 1487 | } |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1488 | |
Florian Tobias Schandinat | ebb29fb | 2011-08-07 01:51:41 +0000 | [diff] [blame] | 1489 | void viafb_fill_crtc_timing(const struct fb_var_screeninfo *var, int iga) |
| 1490 | { |
| 1491 | struct display_timing crt_reg = var_to_timing(var); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1492 | |
Florian Tobias Schandinat | ebb29fb | 2011-08-07 01:51:41 +0000 | [diff] [blame] | 1493 | if (iga == IGA1) |
Florian Tobias Schandinat | f18e3e0 | 2011-05-22 23:30:48 +0000 | [diff] [blame] | 1494 | via_set_primary_timing(&crt_reg); |
Florian Tobias Schandinat | ebb29fb | 2011-08-07 01:51:41 +0000 | [diff] [blame] | 1495 | else if (iga == IGA2) |
Florian Tobias Schandinat | f18e3e0 | 2011-05-22 23:30:48 +0000 | [diff] [blame] | 1496 | via_set_secondary_timing(&crt_reg); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1497 | |
Florian Tobias Schandinat | ebb29fb | 2011-08-07 01:51:41 +0000 | [diff] [blame] | 1498 | viafb_load_fetch_count_reg(var->xres, var->bits_per_pixel / 8, iga); |
| 1499 | if (viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266 |
| 1500 | && viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400) |
| 1501 | viafb_load_FIFO_reg(iga, var->xres, var->yres); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1502 | |
Florian Tobias Schandinat | ebb29fb | 2011-08-07 01:51:41 +0000 | [diff] [blame] | 1503 | viafb_set_vclock(PICOS2KHZ(var->pixclock) * 1000, iga); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1504 | } |
| 1505 | |
Florian Tobias Schandinat | f4ab2f7a | 2010-08-09 01:34:27 +0000 | [diff] [blame] | 1506 | void __devinit viafb_init_chip_info(int chip_type) |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1507 | { |
Florian Tobias Schandinat | 2c536f8 | 2011-03-24 13:30:09 +0000 | [diff] [blame] | 1508 | via_clock_init(&clock, chip_type); |
Jonathan Corbet | 24b4d82 | 2010-04-22 13:48:09 -0600 | [diff] [blame] | 1509 | init_gfx_chip_info(chip_type); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1510 | init_tmds_chip_info(); |
| 1511 | init_lvds_chip_info(); |
| 1512 | |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1513 | /*Set IGA path for each device */ |
| 1514 | viafb_set_iga_path(); |
| 1515 | |
| 1516 | viaparinfo->lvds_setting_info->display_method = viafb_lcd_dsp_method; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1517 | viaparinfo->lvds_setting_info->lcd_mode = viafb_lcd_mode; |
| 1518 | viaparinfo->lvds_setting_info2->display_method = |
| 1519 | viaparinfo->lvds_setting_info->display_method; |
| 1520 | viaparinfo->lvds_setting_info2->lcd_mode = |
| 1521 | viaparinfo->lvds_setting_info->lcd_mode; |
| 1522 | } |
| 1523 | |
Florian Tobias Schandinat | 726abbc | 2011-03-16 16:31:32 +0000 | [diff] [blame] | 1524 | void viafb_update_device_setting(int hres, int vres, int bpp, int flag) |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1525 | { |
| 1526 | if (flag == 0) { |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1527 | viaparinfo->tmds_setting_info->h_active = hres; |
| 1528 | viaparinfo->tmds_setting_info->v_active = vres; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1529 | |
| 1530 | viaparinfo->lvds_setting_info->h_active = hres; |
| 1531 | viaparinfo->lvds_setting_info->v_active = vres; |
| 1532 | viaparinfo->lvds_setting_info->bpp = bpp; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1533 | viaparinfo->lvds_setting_info2->h_active = hres; |
| 1534 | viaparinfo->lvds_setting_info2->v_active = vres; |
| 1535 | viaparinfo->lvds_setting_info2->bpp = bpp; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1536 | } else { |
| 1537 | |
| 1538 | if (viaparinfo->tmds_setting_info->iga_path == IGA2) { |
| 1539 | viaparinfo->tmds_setting_info->h_active = hres; |
| 1540 | viaparinfo->tmds_setting_info->v_active = vres; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1541 | } |
| 1542 | |
| 1543 | if (viaparinfo->lvds_setting_info->iga_path == IGA2) { |
| 1544 | viaparinfo->lvds_setting_info->h_active = hres; |
| 1545 | viaparinfo->lvds_setting_info->v_active = vres; |
| 1546 | viaparinfo->lvds_setting_info->bpp = bpp; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1547 | } |
| 1548 | if (IGA2 == viaparinfo->lvds_setting_info2->iga_path) { |
| 1549 | viaparinfo->lvds_setting_info2->h_active = hres; |
| 1550 | viaparinfo->lvds_setting_info2->v_active = vres; |
| 1551 | viaparinfo->lvds_setting_info2->bpp = bpp; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1552 | } |
| 1553 | } |
| 1554 | } |
| 1555 | |
Florian Tobias Schandinat | f4ab2f7a | 2010-08-09 01:34:27 +0000 | [diff] [blame] | 1556 | static void __devinit init_gfx_chip_info(int chip_type) |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1557 | { |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1558 | u8 tmp; |
| 1559 | |
Jonathan Corbet | 24b4d82 | 2010-04-22 13:48:09 -0600 | [diff] [blame] | 1560 | viaparinfo->chip_info->gfx_chip_name = chip_type; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1561 | |
| 1562 | /* Check revision of CLE266 Chip */ |
| 1563 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) { |
| 1564 | /* CR4F only define in CLE266.CX chip */ |
| 1565 | tmp = viafb_read_reg(VIACR, CR4F); |
| 1566 | viafb_write_reg(CR4F, VIACR, 0x55); |
| 1567 | if (viafb_read_reg(VIACR, CR4F) != 0x55) |
| 1568 | viaparinfo->chip_info->gfx_chip_revision = |
| 1569 | CLE266_REVISION_AX; |
| 1570 | else |
| 1571 | viaparinfo->chip_info->gfx_chip_revision = |
| 1572 | CLE266_REVISION_CX; |
| 1573 | /* restore orignal CR4F value */ |
| 1574 | viafb_write_reg(CR4F, VIACR, tmp); |
| 1575 | } |
| 1576 | |
| 1577 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) { |
| 1578 | tmp = viafb_read_reg(VIASR, SR43); |
| 1579 | DEBUG_MSG(KERN_INFO "SR43:%X\n", tmp); |
| 1580 | if (tmp & 0x02) { |
| 1581 | viaparinfo->chip_info->gfx_chip_revision = |
| 1582 | CX700_REVISION_700M2; |
| 1583 | } else if (tmp & 0x40) { |
| 1584 | viaparinfo->chip_info->gfx_chip_revision = |
| 1585 | CX700_REVISION_700M; |
| 1586 | } else { |
| 1587 | viaparinfo->chip_info->gfx_chip_revision = |
| 1588 | CX700_REVISION_700; |
| 1589 | } |
| 1590 | } |
Harald Welte | 107ea34 | 2009-05-20 01:36:03 +0800 | [diff] [blame] | 1591 | |
| 1592 | /* Determine which 2D engine we have */ |
| 1593 | switch (viaparinfo->chip_info->gfx_chip_name) { |
| 1594 | case UNICHROME_VX800: |
| 1595 | case UNICHROME_VX855: |
Florian Tobias Schandinat | 51f4332 | 2010-10-24 04:02:14 +0000 | [diff] [blame] | 1596 | case UNICHROME_VX900: |
Harald Welte | 107ea34 | 2009-05-20 01:36:03 +0800 | [diff] [blame] | 1597 | viaparinfo->chip_info->twod_engine = VIA_2D_ENG_M1; |
| 1598 | break; |
| 1599 | case UNICHROME_K8M890: |
| 1600 | case UNICHROME_P4M900: |
| 1601 | viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H5; |
| 1602 | break; |
| 1603 | default: |
| 1604 | viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H2; |
| 1605 | break; |
| 1606 | } |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1607 | } |
| 1608 | |
Florian Tobias Schandinat | f4ab2f7a | 2010-08-09 01:34:27 +0000 | [diff] [blame] | 1609 | static void __devinit init_tmds_chip_info(void) |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1610 | { |
| 1611 | viafb_tmds_trasmitter_identify(); |
| 1612 | |
| 1613 | if (INTERFACE_NONE == viaparinfo->chip_info->tmds_chip_info. |
| 1614 | output_interface) { |
| 1615 | switch (viaparinfo->chip_info->gfx_chip_name) { |
| 1616 | case UNICHROME_CX700: |
| 1617 | { |
| 1618 | /* we should check support by hardware layout.*/ |
| 1619 | if ((viafb_display_hardware_layout == |
| 1620 | HW_LAYOUT_DVI_ONLY) |
| 1621 | || (viafb_display_hardware_layout == |
| 1622 | HW_LAYOUT_LCD_DVI)) { |
| 1623 | viaparinfo->chip_info->tmds_chip_info. |
| 1624 | output_interface = INTERFACE_TMDS; |
| 1625 | } else { |
| 1626 | viaparinfo->chip_info->tmds_chip_info. |
| 1627 | output_interface = |
| 1628 | INTERFACE_NONE; |
| 1629 | } |
| 1630 | break; |
| 1631 | } |
| 1632 | case UNICHROME_K8M890: |
| 1633 | case UNICHROME_P4M900: |
| 1634 | case UNICHROME_P4M890: |
| 1635 | /* TMDS on PCIE, we set DFPLOW as default. */ |
| 1636 | viaparinfo->chip_info->tmds_chip_info.output_interface = |
| 1637 | INTERFACE_DFP_LOW; |
| 1638 | break; |
| 1639 | default: |
| 1640 | { |
| 1641 | /* set DVP1 default for DVI */ |
| 1642 | viaparinfo->chip_info->tmds_chip_info |
| 1643 | .output_interface = INTERFACE_DVP1; |
| 1644 | } |
| 1645 | } |
| 1646 | } |
| 1647 | |
| 1648 | DEBUG_MSG(KERN_INFO "TMDS Chip = %d\n", |
| 1649 | viaparinfo->chip_info->tmds_chip_info.tmds_chip_name); |
Florian Tobias Schandinat | c5f06f5 | 2010-03-10 15:21:30 -0800 | [diff] [blame] | 1650 | viafb_init_dvi_size(&viaparinfo->shared->chip_info.tmds_chip_info, |
| 1651 | &viaparinfo->shared->tmds_setting_info); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1652 | } |
| 1653 | |
Florian Tobias Schandinat | f4ab2f7a | 2010-08-09 01:34:27 +0000 | [diff] [blame] | 1654 | static void __devinit init_lvds_chip_info(void) |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1655 | { |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1656 | viafb_lvds_trasmitter_identify(); |
| 1657 | viafb_init_lcd_size(); |
| 1658 | viafb_init_lvds_output_interface(&viaparinfo->chip_info->lvds_chip_info, |
| 1659 | viaparinfo->lvds_setting_info); |
| 1660 | if (viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name) { |
| 1661 | viafb_init_lvds_output_interface(&viaparinfo->chip_info-> |
| 1662 | lvds_chip_info2, viaparinfo->lvds_setting_info2); |
| 1663 | } |
| 1664 | /*If CX700,two singel LCD, we need to reassign |
| 1665 | LCD interface to different LVDS port */ |
| 1666 | if ((UNICHROME_CX700 == viaparinfo->chip_info->gfx_chip_name) |
| 1667 | && (HW_LAYOUT_LCD1_LCD2 == viafb_display_hardware_layout)) { |
| 1668 | if ((INTEGRATED_LVDS == viaparinfo->chip_info->lvds_chip_info. |
| 1669 | lvds_chip_name) && (INTEGRATED_LVDS == |
| 1670 | viaparinfo->chip_info-> |
| 1671 | lvds_chip_info2.lvds_chip_name)) { |
| 1672 | viaparinfo->chip_info->lvds_chip_info.output_interface = |
| 1673 | INTERFACE_LVDS0; |
| 1674 | viaparinfo->chip_info->lvds_chip_info2. |
| 1675 | output_interface = |
| 1676 | INTERFACE_LVDS1; |
| 1677 | } |
| 1678 | } |
| 1679 | |
| 1680 | DEBUG_MSG(KERN_INFO "LVDS Chip = %d\n", |
| 1681 | viaparinfo->chip_info->lvds_chip_info.lvds_chip_name); |
| 1682 | DEBUG_MSG(KERN_INFO "LVDS1 output_interface = %d\n", |
| 1683 | viaparinfo->chip_info->lvds_chip_info.output_interface); |
| 1684 | DEBUG_MSG(KERN_INFO "LVDS2 output_interface = %d\n", |
| 1685 | viaparinfo->chip_info->lvds_chip_info.output_interface); |
| 1686 | } |
| 1687 | |
Florian Tobias Schandinat | f4ab2f7a | 2010-08-09 01:34:27 +0000 | [diff] [blame] | 1688 | void __devinit viafb_init_dac(int set_iga) |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1689 | { |
| 1690 | int i; |
| 1691 | u8 tmp; |
| 1692 | |
| 1693 | if (set_iga == IGA1) { |
| 1694 | /* access Primary Display's LUT */ |
| 1695 | viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0); |
| 1696 | /* turn off LCK */ |
| 1697 | viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6); |
| 1698 | for (i = 0; i < 256; i++) { |
| 1699 | write_dac_reg(i, palLUT_table[i].red, |
| 1700 | palLUT_table[i].green, |
| 1701 | palLUT_table[i].blue); |
| 1702 | } |
| 1703 | /* turn on LCK */ |
| 1704 | viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6); |
| 1705 | } else { |
| 1706 | tmp = viafb_read_reg(VIACR, CR6A); |
| 1707 | /* access Secondary Display's LUT */ |
| 1708 | viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6); |
| 1709 | viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0); |
| 1710 | for (i = 0; i < 256; i++) { |
| 1711 | write_dac_reg(i, palLUT_table[i].red, |
| 1712 | palLUT_table[i].green, |
| 1713 | palLUT_table[i].blue); |
| 1714 | } |
| 1715 | /* set IGA1 DAC for default */ |
| 1716 | viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0); |
| 1717 | viafb_write_reg(CR6A, VIACR, tmp); |
| 1718 | } |
| 1719 | } |
| 1720 | |
| 1721 | static void device_screen_off(void) |
| 1722 | { |
| 1723 | /* turn off CRT screen (IGA1) */ |
| 1724 | viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5); |
| 1725 | } |
| 1726 | |
| 1727 | static void device_screen_on(void) |
| 1728 | { |
| 1729 | /* turn on CRT screen (IGA1) */ |
| 1730 | viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5); |
| 1731 | } |
| 1732 | |
| 1733 | static void set_display_channel(void) |
| 1734 | { |
| 1735 | /*If viafb_LCD2_ON, on cx700, internal lvds's information |
| 1736 | is keeped on lvds_setting_info2 */ |
| 1737 | if (viafb_LCD2_ON && |
| 1738 | viaparinfo->lvds_setting_info2->device_lcd_dualedge) { |
| 1739 | /* For dual channel LCD: */ |
| 1740 | /* Set to Dual LVDS channel. */ |
| 1741 | viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5); |
| 1742 | } else if (viafb_LCD_ON && viafb_DVI_ON) { |
| 1743 | /* For LCD+DFP: */ |
| 1744 | /* Set to LVDS1 + TMDS channel. */ |
| 1745 | viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5); |
| 1746 | } else if (viafb_DVI_ON) { |
| 1747 | /* Set to single TMDS channel. */ |
| 1748 | viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5); |
| 1749 | } else if (viafb_LCD_ON) { |
| 1750 | if (viaparinfo->lvds_setting_info->device_lcd_dualedge) { |
| 1751 | /* For dual channel LCD: */ |
| 1752 | /* Set to Dual LVDS channel. */ |
| 1753 | viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5); |
| 1754 | } else { |
| 1755 | /* Set to LVDS0 + LVDS1 channel. */ |
| 1756 | viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5); |
| 1757 | } |
| 1758 | } |
| 1759 | } |
| 1760 | |
Florian Tobias Schandinat | 2e1abbd | 2010-09-19 01:20:19 +0000 | [diff] [blame] | 1761 | static u8 get_sync(struct fb_info *info) |
| 1762 | { |
| 1763 | u8 polarity = 0; |
| 1764 | |
| 1765 | if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT)) |
| 1766 | polarity |= VIA_HSYNC_NEGATIVE; |
| 1767 | if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT)) |
| 1768 | polarity |= VIA_VSYNC_NEGATIVE; |
| 1769 | return polarity; |
| 1770 | } |
| 1771 | |
Florian Tobias Schandinat | 4fbf4bf | 2011-08-07 11:13:39 +0000 | [diff] [blame] | 1772 | static void hw_init(void) |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1773 | { |
Florian Tobias Schandinat | 4fbf4bf | 2011-08-07 11:13:39 +0000 | [diff] [blame] | 1774 | int i; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1775 | |
| 1776 | inb(VIAStatus); |
| 1777 | outb(0x00, VIAAR); |
| 1778 | |
| 1779 | /* Write Common Setting for Video Mode */ |
Florian Tobias Schandinat | 95d517c | 2011-03-26 23:39:07 +0000 | [diff] [blame] | 1780 | viafb_write_regx(common_vga, ARRAY_SIZE(common_vga)); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1781 | switch (viaparinfo->chip_info->gfx_chip_name) { |
| 1782 | case UNICHROME_CLE266: |
| 1783 | viafb_write_regx(CLE266_ModeXregs, NUM_TOTAL_CLE266_ModeXregs); |
| 1784 | break; |
| 1785 | |
| 1786 | case UNICHROME_K400: |
| 1787 | viafb_write_regx(KM400_ModeXregs, NUM_TOTAL_KM400_ModeXregs); |
| 1788 | break; |
| 1789 | |
| 1790 | case UNICHROME_K800: |
| 1791 | case UNICHROME_PM800: |
| 1792 | viafb_write_regx(CN400_ModeXregs, NUM_TOTAL_CN400_ModeXregs); |
| 1793 | break; |
| 1794 | |
| 1795 | case UNICHROME_CN700: |
| 1796 | case UNICHROME_K8M890: |
| 1797 | case UNICHROME_P4M890: |
| 1798 | case UNICHROME_P4M900: |
| 1799 | viafb_write_regx(CN700_ModeXregs, NUM_TOTAL_CN700_ModeXregs); |
| 1800 | break; |
| 1801 | |
| 1802 | case UNICHROME_CX700: |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1803 | case UNICHROME_VX800: |
Florian Tobias Schandinat | 0e3ca33 | 2009-09-22 16:47:10 -0700 | [diff] [blame] | 1804 | viafb_write_regx(CX700_ModeXregs, NUM_TOTAL_CX700_ModeXregs); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1805 | break; |
Harald Welte | 0306ab1 | 2009-09-22 16:47:35 -0700 | [diff] [blame] | 1806 | |
| 1807 | case UNICHROME_VX855: |
Florian Tobias Schandinat | 51f4332 | 2010-10-24 04:02:14 +0000 | [diff] [blame] | 1808 | case UNICHROME_VX900: |
Harald Welte | 0306ab1 | 2009-09-22 16:47:35 -0700 | [diff] [blame] | 1809 | viafb_write_regx(VX855_ModeXregs, NUM_TOTAL_VX855_ModeXregs); |
| 1810 | break; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1811 | } |
| 1812 | |
Florian Tobias Schandinat | e292063 | 2012-02-22 18:53:08 +0000 | [diff] [blame] | 1813 | /* magic required on VX900 for correct modesetting on IGA1 */ |
| 1814 | via_write_reg_mask(VIACR, 0x45, 0x00, 0x01); |
| 1815 | |
Florian Tobias Schandinat | 4fbf4bf | 2011-08-07 11:13:39 +0000 | [diff] [blame] | 1816 | /* probably this should go to the scaling code one day */ |
Florian Tobias Schandinat | 050f0e0 | 2012-02-22 18:53:07 +0000 | [diff] [blame] | 1817 | via_write_reg_mask(VIACR, 0xFD, 0, 0x80); /* VX900 hw scale on IGA2 */ |
Florian Tobias Schandinat | bf5ea02 | 2011-01-05 10:36:05 +0000 | [diff] [blame] | 1818 | viafb_write_regx(scaling_parameters, ARRAY_SIZE(scaling_parameters)); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1819 | |
| 1820 | /* Fill VPIT Parameters */ |
| 1821 | /* Write Misc Register */ |
Florian Tobias Schandinat | 162fc8c | 2010-04-17 19:44:55 +0000 | [diff] [blame] | 1822 | outb(VPIT.Misc, VIA_MISC_REG_WRITE); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1823 | |
| 1824 | /* Write Sequencer */ |
Florian Tobias Schandinat | 384c304 | 2010-04-17 19:44:54 +0000 | [diff] [blame] | 1825 | for (i = 1; i <= StdSR; i++) |
| 1826 | via_write_reg(VIASR, i, VPIT.SR[i - 1]); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1827 | |
Florian Tobias Schandinat | 415559f | 2010-03-10 15:21:40 -0800 | [diff] [blame] | 1828 | viafb_write_reg_mask(0x15, VIASR, 0xA2, 0xA2); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1829 | |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1830 | /* Write Graphic Controller */ |
Florian Tobias Schandinat | 384c304 | 2010-04-17 19:44:54 +0000 | [diff] [blame] | 1831 | for (i = 0; i < StdGR; i++) |
| 1832 | via_write_reg(VIAGR, i, VPIT.GR[i]); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1833 | |
| 1834 | /* Write Attribute Controller */ |
| 1835 | for (i = 0; i < StdAR; i++) { |
| 1836 | inb(VIAStatus); |
| 1837 | outb(i, VIAAR); |
| 1838 | outb(VPIT.AR[i], VIAAR); |
| 1839 | } |
| 1840 | |
| 1841 | inb(VIAStatus); |
| 1842 | outb(0x20, VIAAR); |
| 1843 | |
Florian Tobias Schandinat | 4fbf4bf | 2011-08-07 11:13:39 +0000 | [diff] [blame] | 1844 | load_fix_bit_crtc_reg(); |
| 1845 | } |
| 1846 | |
Florian Tobias Schandinat | 5dd72f1 | 2011-08-07 13:34:35 +0000 | [diff] [blame] | 1847 | int viafb_setmode(int video_bpp, int video_bpp1) |
Florian Tobias Schandinat | 4fbf4bf | 2011-08-07 11:13:39 +0000 | [diff] [blame] | 1848 | { |
| 1849 | int j; |
| 1850 | int port; |
| 1851 | u32 devices = viaparinfo->shared->iga1_devices |
| 1852 | | viaparinfo->shared->iga2_devices; |
| 1853 | u8 value, index, mask; |
Florian Tobias Schandinat | 4fbf4bf | 2011-08-07 11:13:39 +0000 | [diff] [blame] | 1854 | struct fb_var_screeninfo var2; |
| 1855 | |
| 1856 | device_screen_off(); |
Florian Tobias Schandinat | 4fbf4bf | 2011-08-07 11:13:39 +0000 | [diff] [blame] | 1857 | device_off(); |
| 1858 | via_set_state(devices, VIA_STATE_OFF); |
| 1859 | |
| 1860 | hw_init(); |
| 1861 | |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1862 | /* Update Patch Register */ |
| 1863 | |
Florian Tobias Schandinat | dd73d68 | 2010-03-10 15:21:28 -0800 | [diff] [blame] | 1864 | if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266 |
Florian Tobias Schandinat | 5dd72f1 | 2011-08-07 13:34:35 +0000 | [diff] [blame] | 1865 | || viaparinfo->chip_info->gfx_chip_name == UNICHROME_K400) |
| 1866 | && viafbinfo->var.xres == 1024 && viafbinfo->var.yres == 768) { |
Florian Tobias Schandinat | dd73d68 | 2010-03-10 15:21:28 -0800 | [diff] [blame] | 1867 | for (j = 0; j < res_patch_table[0].table_length; j++) { |
| 1868 | index = res_patch_table[0].io_reg_table[j].index; |
| 1869 | port = res_patch_table[0].io_reg_table[j].port; |
| 1870 | value = res_patch_table[0].io_reg_table[j].value; |
| 1871 | mask = res_patch_table[0].io_reg_table[j].mask; |
| 1872 | viafb_write_reg_mask(index, port, value, mask); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1873 | } |
| 1874 | } |
| 1875 | |
Florian Tobias Schandinat | 2749413 | 2010-04-17 19:44:52 +0000 | [diff] [blame] | 1876 | via_set_primary_pitch(viafbinfo->fix.line_length); |
| 1877 | via_set_secondary_pitch(viafb_dual_fb ? viafbinfo1->fix.line_length |
Florian Tobias Schandinat | 2d6e885 | 2009-09-22 16:47:29 -0700 | [diff] [blame] | 1878 | : viafbinfo->fix.line_length); |
Florian Tobias Schandinat | 2749413 | 2010-04-17 19:44:52 +0000 | [diff] [blame] | 1879 | via_set_primary_color_depth(viaparinfo->depth); |
| 1880 | via_set_secondary_color_depth(viafb_dual_fb ? viaparinfo1->depth |
Florian Tobias Schandinat | daacccd | 2010-03-10 15:21:35 -0800 | [diff] [blame] | 1881 | : viaparinfo->depth); |
Florian Tobias Schandinat | bc68488 | 2010-08-11 00:37:58 +0000 | [diff] [blame] | 1882 | via_set_source(viaparinfo->shared->iga1_devices, IGA1); |
| 1883 | via_set_source(viaparinfo->shared->iga2_devices, IGA2); |
| 1884 | if (viaparinfo->shared->iga2_devices) |
| 1885 | enable_second_display_channel(); |
| 1886 | else |
| 1887 | disable_second_display_channel(); |
| 1888 | |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1889 | /* Update Refresh Rate Setting */ |
| 1890 | |
| 1891 | /* Clear On Screen */ |
| 1892 | |
Florian Tobias Schandinat | ebb29fb | 2011-08-07 01:51:41 +0000 | [diff] [blame] | 1893 | if (viafb_dual_fb) { |
| 1894 | var2 = viafbinfo1->var; |
| 1895 | } else if (viafb_SAMM_ON) { |
| 1896 | viafb_fill_var_timing_info(&var2, viafb_get_best_mode( |
Florian Tobias Schandinat | 5dd72f1 | 2011-08-07 13:34:35 +0000 | [diff] [blame] | 1897 | viafb_second_xres, viafb_second_yres, viafb_refresh1)); |
Florian Tobias Schandinat | ebb29fb | 2011-08-07 01:51:41 +0000 | [diff] [blame] | 1898 | var2.bits_per_pixel = viafbinfo->var.bits_per_pixel; |
| 1899 | } |
| 1900 | |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1901 | /* CRT set mode */ |
| 1902 | if (viafb_CRT_ON) { |
Florian Tobias Schandinat | ebb29fb | 2011-08-07 01:51:41 +0000 | [diff] [blame] | 1903 | if (viaparinfo->shared->iga2_devices & VIA_CRT |
| 1904 | && viafb_SAMM_ON) |
| 1905 | viafb_fill_crtc_timing(&var2, IGA2); |
| 1906 | else |
| 1907 | viafb_fill_crtc_timing(&viafbinfo->var, |
Florian Tobias Schandinat | 0523656 | 2011-03-21 01:46:24 +0000 | [diff] [blame] | 1908 | (viaparinfo->shared->iga1_devices & VIA_CRT) |
| 1909 | ? IGA1 : IGA2); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1910 | |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1911 | /* Patch if set_hres is not 8 alignment (1366) to viafb_setmode |
| 1912 | to 8 alignment (1368),there is several pixels (2 pixels) |
| 1913 | on right side of screen. */ |
Florian Tobias Schandinat | 5dd72f1 | 2011-08-07 13:34:35 +0000 | [diff] [blame] | 1914 | if (viafbinfo->var.xres % 8) { |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1915 | viafb_unlock_crt(); |
| 1916 | viafb_write_reg(CR02, VIACR, |
| 1917 | viafb_read_reg(VIACR, CR02) - 1); |
| 1918 | viafb_lock_crt(); |
| 1919 | } |
| 1920 | } |
| 1921 | |
| 1922 | if (viafb_DVI_ON) { |
Florian Tobias Schandinat | ebb29fb | 2011-08-07 01:51:41 +0000 | [diff] [blame] | 1923 | if (viaparinfo->shared->tmds_setting_info.iga_path == IGA2 |
| 1924 | && viafb_SAMM_ON) |
| 1925 | viafb_dvi_set_mode(&var2, IGA2); |
| 1926 | else |
| 1927 | viafb_dvi_set_mode(&viafbinfo->var, |
| 1928 | viaparinfo->tmds_setting_info->iga_path); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1929 | } |
| 1930 | |
| 1931 | if (viafb_LCD_ON) { |
| 1932 | if (viafb_SAMM_ON && |
| 1933 | (viaparinfo->lvds_setting_info->iga_path == IGA2)) { |
| 1934 | viaparinfo->lvds_setting_info->bpp = video_bpp1; |
Florian Tobias Schandinat | bfe7d5f | 2011-08-07 13:08:45 +0000 | [diff] [blame] | 1935 | viafb_lcd_set_mode(viaparinfo->lvds_setting_info, |
| 1936 | &viaparinfo->chip_info->lvds_chip_info); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1937 | } else { |
| 1938 | /* IGA1 doesn't have LCD scaling, so set it center. */ |
| 1939 | if (viaparinfo->lvds_setting_info->iga_path == IGA1) { |
| 1940 | viaparinfo->lvds_setting_info->display_method = |
| 1941 | LCD_CENTERING; |
| 1942 | } |
| 1943 | viaparinfo->lvds_setting_info->bpp = video_bpp; |
Florian Tobias Schandinat | bfe7d5f | 2011-08-07 13:08:45 +0000 | [diff] [blame] | 1944 | viafb_lcd_set_mode(viaparinfo->lvds_setting_info, |
| 1945 | &viaparinfo->chip_info->lvds_chip_info); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1946 | } |
| 1947 | } |
| 1948 | if (viafb_LCD2_ON) { |
| 1949 | if (viafb_SAMM_ON && |
| 1950 | (viaparinfo->lvds_setting_info2->iga_path == IGA2)) { |
| 1951 | viaparinfo->lvds_setting_info2->bpp = video_bpp1; |
Florian Tobias Schandinat | bfe7d5f | 2011-08-07 13:08:45 +0000 | [diff] [blame] | 1952 | viafb_lcd_set_mode(viaparinfo->lvds_setting_info2, |
| 1953 | &viaparinfo->chip_info->lvds_chip_info2); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1954 | } else { |
| 1955 | /* IGA1 doesn't have LCD scaling, so set it center. */ |
| 1956 | if (viaparinfo->lvds_setting_info2->iga_path == IGA1) { |
| 1957 | viaparinfo->lvds_setting_info2->display_method = |
| 1958 | LCD_CENTERING; |
| 1959 | } |
| 1960 | viaparinfo->lvds_setting_info2->bpp = video_bpp; |
Florian Tobias Schandinat | bfe7d5f | 2011-08-07 13:08:45 +0000 | [diff] [blame] | 1961 | viafb_lcd_set_mode(viaparinfo->lvds_setting_info2, |
| 1962 | &viaparinfo->chip_info->lvds_chip_info2); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1963 | } |
| 1964 | } |
| 1965 | |
| 1966 | if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) |
| 1967 | && (viafb_LCD_ON || viafb_DVI_ON)) |
| 1968 | set_display_channel(); |
| 1969 | |
| 1970 | /* If set mode normally, save resolution information for hot-plug . */ |
| 1971 | if (!viafb_hotplug) { |
Florian Tobias Schandinat | 5dd72f1 | 2011-08-07 13:34:35 +0000 | [diff] [blame] | 1972 | viafb_hotplug_Xres = viafbinfo->var.xres; |
| 1973 | viafb_hotplug_Yres = viafbinfo->var.yres; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1974 | viafb_hotplug_bpp = video_bpp; |
| 1975 | viafb_hotplug_refresh = viafb_refresh; |
| 1976 | |
| 1977 | if (viafb_DVI_ON) |
| 1978 | viafb_DeviceStatus = DVI_Device; |
| 1979 | else |
| 1980 | viafb_DeviceStatus = CRT_Device; |
| 1981 | } |
| 1982 | device_on(); |
Florian Tobias Schandinat | 2e1abbd | 2010-09-19 01:20:19 +0000 | [diff] [blame] | 1983 | if (!viafb_dual_fb) |
| 1984 | via_set_sync_polarity(devices, get_sync(viafbinfo)); |
| 1985 | else { |
| 1986 | via_set_sync_polarity(viaparinfo->shared->iga1_devices, |
| 1987 | get_sync(viafbinfo)); |
| 1988 | via_set_sync_polarity(viaparinfo->shared->iga2_devices, |
| 1989 | get_sync(viafbinfo1)); |
| 1990 | } |
| 1991 | |
Florian Tobias Schandinat | bea02e4 | 2011-03-26 02:29:18 +0000 | [diff] [blame] | 1992 | clock.set_engine_pll_state(VIA_STATE_ON); |
Florian Tobias Schandinat | b692a63 | 2011-03-24 14:25:51 +0000 | [diff] [blame] | 1993 | clock.set_primary_clock_source(VIA_CLKSRC_X1, true); |
| 1994 | clock.set_secondary_clock_source(VIA_CLKSRC_X1, true); |
| 1995 | |
Florian Tobias Schandinat | 2946294 | 2011-04-23 23:52:45 +0000 | [diff] [blame] | 1996 | #ifdef CONFIG_FB_VIA_X_COMPATIBILITY |
| 1997 | clock.set_primary_pll_state(VIA_STATE_ON); |
| 1998 | clock.set_primary_clock_state(VIA_STATE_ON); |
| 1999 | clock.set_secondary_pll_state(VIA_STATE_ON); |
| 2000 | clock.set_secondary_clock_state(VIA_STATE_ON); |
| 2001 | #else |
Florian Tobias Schandinat | b692a63 | 2011-03-24 14:25:51 +0000 | [diff] [blame] | 2002 | if (viaparinfo->shared->iga1_devices) { |
| 2003 | clock.set_primary_pll_state(VIA_STATE_ON); |
| 2004 | clock.set_primary_clock_state(VIA_STATE_ON); |
| 2005 | } else { |
| 2006 | clock.set_primary_pll_state(VIA_STATE_OFF); |
| 2007 | clock.set_primary_clock_state(VIA_STATE_OFF); |
| 2008 | } |
| 2009 | |
| 2010 | if (viaparinfo->shared->iga2_devices) { |
| 2011 | clock.set_secondary_pll_state(VIA_STATE_ON); |
| 2012 | clock.set_secondary_clock_state(VIA_STATE_ON); |
| 2013 | } else { |
| 2014 | clock.set_secondary_pll_state(VIA_STATE_OFF); |
| 2015 | clock.set_secondary_clock_state(VIA_STATE_OFF); |
| 2016 | } |
Florian Tobias Schandinat | 2946294 | 2011-04-23 23:52:45 +0000 | [diff] [blame] | 2017 | #endif /*CONFIG_FB_VIA_X_COMPATIBILITY*/ |
Florian Tobias Schandinat | b692a63 | 2011-03-24 14:25:51 +0000 | [diff] [blame] | 2018 | |
Florian Tobias Schandinat | 6f9422d | 2010-09-07 14:28:26 +0000 | [diff] [blame] | 2019 | via_set_state(devices, VIA_STATE_ON); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2020 | device_screen_on(); |
| 2021 | return 1; |
| 2022 | } |
| 2023 | |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2024 | int viafb_get_refresh(int hres, int vres, u32 long_refresh) |
| 2025 | { |
Florian Tobias Schandinat | f5b1c4b | 2011-03-09 22:13:32 +0000 | [diff] [blame] | 2026 | struct crt_mode_table *best; |
Florian Tobias Schandinat | f5b1c4b | 2011-03-09 22:13:32 +0000 | [diff] [blame] | 2027 | |
Florian Tobias Schandinat | 94715ba | 2011-08-06 23:04:43 +0000 | [diff] [blame] | 2028 | best = viafb_get_best_mode(hres, vres, long_refresh); |
| 2029 | if (!best) |
Florian Tobias Schandinat | f5b1c4b | 2011-03-09 22:13:32 +0000 | [diff] [blame] | 2030 | return 60; |
| 2031 | |
Florian Tobias Schandinat | b4ce6a2 | 2011-04-15 21:35:25 +0000 | [diff] [blame] | 2032 | if (abs(best->refresh_rate - long_refresh) > 3) { |
| 2033 | if (hres == 1200 && vres == 900) |
Florian Tobias Schandinat | c5a4e6d | 2011-04-23 22:24:52 +0000 | [diff] [blame] | 2034 | return 49; /* OLPC DCON only supports 50 Hz */ |
Florian Tobias Schandinat | b4ce6a2 | 2011-04-15 21:35:25 +0000 | [diff] [blame] | 2035 | else |
| 2036 | return 60; |
| 2037 | } |
Florian Tobias Schandinat | f5b1c4b | 2011-03-09 22:13:32 +0000 | [diff] [blame] | 2038 | |
| 2039 | return best->refresh_rate; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2040 | } |
| 2041 | |
| 2042 | static void device_off(void) |
| 2043 | { |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2044 | viafb_dvi_disable(); |
| 2045 | viafb_lcd_disable(); |
| 2046 | } |
| 2047 | |
| 2048 | static void device_on(void) |
| 2049 | { |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2050 | if (viafb_DVI_ON == 1) |
| 2051 | viafb_dvi_enable(); |
| 2052 | if (viafb_LCD_ON == 1) |
| 2053 | viafb_lcd_enable(); |
| 2054 | } |
| 2055 | |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2056 | static void enable_second_display_channel(void) |
| 2057 | { |
| 2058 | /* to enable second display channel. */ |
| 2059 | viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6); |
| 2060 | viafb_write_reg_mask(CR6A, VIACR, BIT7, BIT7); |
| 2061 | viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6); |
| 2062 | } |
| 2063 | |
Florian Tobias Schandinat | bc68488 | 2010-08-11 00:37:58 +0000 | [diff] [blame] | 2064 | static void disable_second_display_channel(void) |
| 2065 | { |
| 2066 | /* to disable second display channel. */ |
| 2067 | viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6); |
| 2068 | viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT7); |
| 2069 | viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6); |
| 2070 | } |
| 2071 | |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2072 | void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\ |
| 2073 | *p_gfx_dpa_setting) |
| 2074 | { |
| 2075 | switch (output_interface) { |
| 2076 | case INTERFACE_DVP0: |
| 2077 | { |
| 2078 | /* DVP0 Clock Polarity and Adjust: */ |
| 2079 | viafb_write_reg_mask(CR96, VIACR, |
| 2080 | p_gfx_dpa_setting->DVP0, 0x0F); |
| 2081 | |
| 2082 | /* DVP0 Clock and Data Pads Driving: */ |
| 2083 | viafb_write_reg_mask(SR1E, VIASR, |
| 2084 | p_gfx_dpa_setting->DVP0ClockDri_S, BIT2); |
| 2085 | viafb_write_reg_mask(SR2A, VIASR, |
| 2086 | p_gfx_dpa_setting->DVP0ClockDri_S1, |
| 2087 | BIT4); |
| 2088 | viafb_write_reg_mask(SR1B, VIASR, |
| 2089 | p_gfx_dpa_setting->DVP0DataDri_S, BIT1); |
| 2090 | viafb_write_reg_mask(SR2A, VIASR, |
| 2091 | p_gfx_dpa_setting->DVP0DataDri_S1, BIT5); |
| 2092 | break; |
| 2093 | } |
| 2094 | |
| 2095 | case INTERFACE_DVP1: |
| 2096 | { |
| 2097 | /* DVP1 Clock Polarity and Adjust: */ |
| 2098 | viafb_write_reg_mask(CR9B, VIACR, |
| 2099 | p_gfx_dpa_setting->DVP1, 0x0F); |
| 2100 | |
| 2101 | /* DVP1 Clock and Data Pads Driving: */ |
| 2102 | viafb_write_reg_mask(SR65, VIASR, |
| 2103 | p_gfx_dpa_setting->DVP1Driving, 0x0F); |
| 2104 | break; |
| 2105 | } |
| 2106 | |
| 2107 | case INTERFACE_DFP_HIGH: |
| 2108 | { |
| 2109 | viafb_write_reg_mask(CR97, VIACR, |
| 2110 | p_gfx_dpa_setting->DFPHigh, 0x0F); |
| 2111 | break; |
| 2112 | } |
| 2113 | |
| 2114 | case INTERFACE_DFP_LOW: |
| 2115 | { |
| 2116 | viafb_write_reg_mask(CR99, VIACR, |
| 2117 | p_gfx_dpa_setting->DFPLow, 0x0F); |
| 2118 | break; |
| 2119 | } |
| 2120 | |
| 2121 | case INTERFACE_DFP: |
| 2122 | { |
| 2123 | viafb_write_reg_mask(CR97, VIACR, |
| 2124 | p_gfx_dpa_setting->DFPHigh, 0x0F); |
| 2125 | viafb_write_reg_mask(CR99, VIACR, |
| 2126 | p_gfx_dpa_setting->DFPLow, 0x0F); |
| 2127 | break; |
| 2128 | } |
| 2129 | } |
| 2130 | } |
| 2131 | |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2132 | /*According var's xres, yres fill var's other timing information*/ |
Florian Tobias Schandinat | 94715ba | 2011-08-06 23:04:43 +0000 | [diff] [blame] | 2133 | void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, |
| 2134 | struct crt_mode_table *mode) |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2135 | { |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2136 | struct display_timing crt_reg; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2137 | |
Florian Tobias Schandinat | 94715ba | 2011-08-06 23:04:43 +0000 | [diff] [blame] | 2138 | crt_reg = mode->crtc; |
Florian Tobias Schandinat | 42edcb1 | 2011-08-06 23:35:25 +0000 | [diff] [blame] | 2139 | var->pixclock = 1000000000 / (crt_reg.hor_total * crt_reg.ver_total) |
| 2140 | * 1000 / mode->refresh_rate; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2141 | var->left_margin = |
| 2142 | crt_reg.hor_total - (crt_reg.hor_sync_start + crt_reg.hor_sync_end); |
| 2143 | var->right_margin = crt_reg.hor_sync_start - crt_reg.hor_addr; |
| 2144 | var->hsync_len = crt_reg.hor_sync_end; |
| 2145 | var->upper_margin = |
| 2146 | crt_reg.ver_total - (crt_reg.ver_sync_start + crt_reg.ver_sync_end); |
| 2147 | var->lower_margin = crt_reg.ver_sync_start - crt_reg.ver_addr; |
| 2148 | var->vsync_len = crt_reg.ver_sync_end; |
Florian Tobias Schandinat | 2e1abbd | 2010-09-19 01:20:19 +0000 | [diff] [blame] | 2149 | var->sync = 0; |
Florian Tobias Schandinat | 94715ba | 2011-08-06 23:04:43 +0000 | [diff] [blame] | 2150 | if (mode->h_sync_polarity == POSITIVE) |
Florian Tobias Schandinat | 2e1abbd | 2010-09-19 01:20:19 +0000 | [diff] [blame] | 2151 | var->sync |= FB_SYNC_HOR_HIGH_ACT; |
Florian Tobias Schandinat | 94715ba | 2011-08-06 23:04:43 +0000 | [diff] [blame] | 2152 | if (mode->v_sync_polarity == POSITIVE) |
Florian Tobias Schandinat | 2e1abbd | 2010-09-19 01:20:19 +0000 | [diff] [blame] | 2153 | var->sync |= FB_SYNC_VERT_HIGH_ACT; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2154 | } |