Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 1 | /* linux/arch/arm/mach-msm/gpio.c |
| 2 | * |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 3 | * Copyright (C) 2007 Google, Inc. |
Jeff Hugo | 5ba15fe | 2013-05-06 14:24:24 -0600 | [diff] [blame] | 4 | * Copyright (c) 2009-2013, The Linux Foundation. All rights reserved. |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 5 | * |
| 6 | * This software is licensed under the terms of the GNU General Public |
| 7 | * License version 2, as published by the Free Software Foundation, and |
| 8 | * may be copied, distributed, and modified under those terms. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | */ |
| 16 | |
| 17 | #include <linux/bitops.h> |
| 18 | #include <linux/gpio.h> |
| 19 | #include <linux/interrupt.h> |
| 20 | #include <linux/io.h> |
| 21 | #include <linux/irq.h> |
| 22 | #include <linux/module.h> |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 23 | #include <linux/platform_device.h> |
| 24 | #include <asm/mach/irq.h> |
| 25 | #include <mach/gpiomux.h> |
David Brown | 9def3ef | 2011-06-06 14:09:45 -0700 | [diff] [blame] | 26 | #include <mach/msm_iomap.h> |
Jeff Hugo | 5ba15fe | 2013-05-06 14:24:24 -0600 | [diff] [blame] | 27 | #include <mach/msm_smem.h> |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 28 | #include <mach/proc_comm.h> |
| 29 | |
David Brown | 9def3ef | 2011-06-06 14:09:45 -0700 | [diff] [blame] | 30 | |
| 31 | /* see 80-VA736-2 Rev C pp 695-751 |
| 32 | ** |
| 33 | ** These are actually the *shadow* gpio registers, since the |
| 34 | ** real ones (which allow full access) are only available to the |
| 35 | ** ARM9 side of the world. |
| 36 | ** |
| 37 | ** Since the _BASE need to be page-aligned when we're mapping them |
| 38 | ** to virtual addresses, adjust for the additional offset in these |
| 39 | ** macros. |
| 40 | */ |
| 41 | |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 42 | #if defined(CONFIG_ARCH_MSM7X30) |
David Brown | 9def3ef | 2011-06-06 14:09:45 -0700 | [diff] [blame] | 43 | #define MSM_GPIO1_REG(off) (MSM_GPIO1_BASE + (off)) |
| 44 | #define MSM_GPIO2_REG(off) (MSM_GPIO2_BASE + 0x400 + (off)) |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 45 | #else |
| 46 | #define MSM_GPIO1_REG(off) (MSM_GPIO1_BASE + 0x800 + (off)) |
| 47 | #define MSM_GPIO2_REG(off) (MSM_GPIO2_BASE + 0xC00 + (off)) |
| 48 | #endif |
David Brown | 9def3ef | 2011-06-06 14:09:45 -0700 | [diff] [blame] | 49 | |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 50 | #if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_MSM7X25) ||\ |
| 51 | defined(CONFIG_ARCH_MSM7X27) |
| 52 | |
David Brown | 9def3ef | 2011-06-06 14:09:45 -0700 | [diff] [blame] | 53 | /* output value */ |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 54 | #define MSM_GPIO_OUT_0 MSM_GPIO1_REG(0x00) /* gpio 15-0 */ |
| 55 | #define MSM_GPIO_OUT_1 MSM_GPIO2_REG(0x00) /* gpio 42-16 */ |
| 56 | #define MSM_GPIO_OUT_2 MSM_GPIO1_REG(0x04) /* gpio 67-43 */ |
| 57 | #define MSM_GPIO_OUT_3 MSM_GPIO1_REG(0x08) /* gpio 94-68 */ |
| 58 | #define MSM_GPIO_OUT_4 MSM_GPIO1_REG(0x0C) /* gpio 106-95 */ |
| 59 | #define MSM_GPIO_OUT_5 MSM_GPIO1_REG(0x50) /* gpio 107-121 */ |
David Brown | 9def3ef | 2011-06-06 14:09:45 -0700 | [diff] [blame] | 60 | |
| 61 | /* same pin map as above, output enable */ |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 62 | #define MSM_GPIO_OE_0 MSM_GPIO1_REG(0x10) |
| 63 | #define MSM_GPIO_OE_1 MSM_GPIO2_REG(0x08) |
| 64 | #define MSM_GPIO_OE_2 MSM_GPIO1_REG(0x14) |
| 65 | #define MSM_GPIO_OE_3 MSM_GPIO1_REG(0x18) |
| 66 | #define MSM_GPIO_OE_4 MSM_GPIO1_REG(0x1C) |
| 67 | #define MSM_GPIO_OE_5 MSM_GPIO1_REG(0x54) |
David Brown | 9def3ef | 2011-06-06 14:09:45 -0700 | [diff] [blame] | 68 | |
| 69 | /* same pin map as above, input read */ |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 70 | #define MSM_GPIO_IN_0 MSM_GPIO1_REG(0x34) |
| 71 | #define MSM_GPIO_IN_1 MSM_GPIO2_REG(0x20) |
| 72 | #define MSM_GPIO_IN_2 MSM_GPIO1_REG(0x38) |
| 73 | #define MSM_GPIO_IN_3 MSM_GPIO1_REG(0x3C) |
| 74 | #define MSM_GPIO_IN_4 MSM_GPIO1_REG(0x40) |
| 75 | #define MSM_GPIO_IN_5 MSM_GPIO1_REG(0x44) |
David Brown | 9def3ef | 2011-06-06 14:09:45 -0700 | [diff] [blame] | 76 | |
| 77 | /* same pin map as above, 1=edge 0=level interrup */ |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 78 | #define MSM_GPIO_INT_EDGE_0 MSM_GPIO1_REG(0x60) |
| 79 | #define MSM_GPIO_INT_EDGE_1 MSM_GPIO2_REG(0x50) |
| 80 | #define MSM_GPIO_INT_EDGE_2 MSM_GPIO1_REG(0x64) |
| 81 | #define MSM_GPIO_INT_EDGE_3 MSM_GPIO1_REG(0x68) |
| 82 | #define MSM_GPIO_INT_EDGE_4 MSM_GPIO1_REG(0x6C) |
| 83 | #define MSM_GPIO_INT_EDGE_5 MSM_GPIO1_REG(0xC0) |
David Brown | 9def3ef | 2011-06-06 14:09:45 -0700 | [diff] [blame] | 84 | |
| 85 | /* same pin map as above, 1=positive 0=negative */ |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 86 | #define MSM_GPIO_INT_POS_0 MSM_GPIO1_REG(0x70) |
| 87 | #define MSM_GPIO_INT_POS_1 MSM_GPIO2_REG(0x58) |
| 88 | #define MSM_GPIO_INT_POS_2 MSM_GPIO1_REG(0x74) |
| 89 | #define MSM_GPIO_INT_POS_3 MSM_GPIO1_REG(0x78) |
| 90 | #define MSM_GPIO_INT_POS_4 MSM_GPIO1_REG(0x7C) |
| 91 | #define MSM_GPIO_INT_POS_5 MSM_GPIO1_REG(0xBC) |
David Brown | 9def3ef | 2011-06-06 14:09:45 -0700 | [diff] [blame] | 92 | |
| 93 | /* same pin map as above, interrupt enable */ |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 94 | #define MSM_GPIO_INT_EN_0 MSM_GPIO1_REG(0x80) |
| 95 | #define MSM_GPIO_INT_EN_1 MSM_GPIO2_REG(0x60) |
| 96 | #define MSM_GPIO_INT_EN_2 MSM_GPIO1_REG(0x84) |
| 97 | #define MSM_GPIO_INT_EN_3 MSM_GPIO1_REG(0x88) |
| 98 | #define MSM_GPIO_INT_EN_4 MSM_GPIO1_REG(0x8C) |
| 99 | #define MSM_GPIO_INT_EN_5 MSM_GPIO1_REG(0xB8) |
David Brown | 9def3ef | 2011-06-06 14:09:45 -0700 | [diff] [blame] | 100 | |
| 101 | /* same pin map as above, write 1 to clear interrupt */ |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 102 | #define MSM_GPIO_INT_CLEAR_0 MSM_GPIO1_REG(0x90) |
| 103 | #define MSM_GPIO_INT_CLEAR_1 MSM_GPIO2_REG(0x68) |
| 104 | #define MSM_GPIO_INT_CLEAR_2 MSM_GPIO1_REG(0x94) |
| 105 | #define MSM_GPIO_INT_CLEAR_3 MSM_GPIO1_REG(0x98) |
| 106 | #define MSM_GPIO_INT_CLEAR_4 MSM_GPIO1_REG(0x9C) |
| 107 | #define MSM_GPIO_INT_CLEAR_5 MSM_GPIO1_REG(0xB4) |
David Brown | 9def3ef | 2011-06-06 14:09:45 -0700 | [diff] [blame] | 108 | |
| 109 | /* same pin map as above, 1=interrupt pending */ |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 110 | #define MSM_GPIO_INT_STATUS_0 MSM_GPIO1_REG(0xA0) |
| 111 | #define MSM_GPIO_INT_STATUS_1 MSM_GPIO2_REG(0x70) |
| 112 | #define MSM_GPIO_INT_STATUS_2 MSM_GPIO1_REG(0xA4) |
| 113 | #define MSM_GPIO_INT_STATUS_3 MSM_GPIO1_REG(0xA8) |
| 114 | #define MSM_GPIO_INT_STATUS_4 MSM_GPIO1_REG(0xAC) |
| 115 | #define MSM_GPIO_INT_STATUS_5 MSM_GPIO1_REG(0xB0) |
David Brown | 9def3ef | 2011-06-06 14:09:45 -0700 | [diff] [blame] | 116 | |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 117 | #endif |
| 118 | |
| 119 | #if defined(CONFIG_ARCH_MSM7X30) |
| 120 | |
David Brown | 9def3ef | 2011-06-06 14:09:45 -0700 | [diff] [blame] | 121 | /* output value */ |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 122 | #define MSM_GPIO_OUT_0 MSM_GPIO1_REG(0x00) /* gpio 15-0 */ |
| 123 | #define MSM_GPIO_OUT_1 MSM_GPIO2_REG(0x00) /* gpio 43-16 */ |
| 124 | #define MSM_GPIO_OUT_2 MSM_GPIO1_REG(0x04) /* gpio 67-44 */ |
| 125 | #define MSM_GPIO_OUT_3 MSM_GPIO1_REG(0x08) /* gpio 94-68 */ |
| 126 | #define MSM_GPIO_OUT_4 MSM_GPIO1_REG(0x0C) /* gpio 106-95 */ |
| 127 | #define MSM_GPIO_OUT_5 MSM_GPIO1_REG(0x50) /* gpio 133-107 */ |
| 128 | #define MSM_GPIO_OUT_6 MSM_GPIO1_REG(0xC4) /* gpio 150-134 */ |
| 129 | #define MSM_GPIO_OUT_7 MSM_GPIO1_REG(0x214) /* gpio 181-151 */ |
David Brown | 9def3ef | 2011-06-06 14:09:45 -0700 | [diff] [blame] | 130 | |
| 131 | /* same pin map as above, output enable */ |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 132 | #define MSM_GPIO_OE_0 MSM_GPIO1_REG(0x10) |
| 133 | #define MSM_GPIO_OE_1 MSM_GPIO2_REG(0x08) |
| 134 | #define MSM_GPIO_OE_2 MSM_GPIO1_REG(0x14) |
| 135 | #define MSM_GPIO_OE_3 MSM_GPIO1_REG(0x18) |
| 136 | #define MSM_GPIO_OE_4 MSM_GPIO1_REG(0x1C) |
| 137 | #define MSM_GPIO_OE_5 MSM_GPIO1_REG(0x54) |
| 138 | #define MSM_GPIO_OE_6 MSM_GPIO1_REG(0xC8) |
| 139 | #define MSM_GPIO_OE_7 MSM_GPIO1_REG(0x218) |
David Brown | 9def3ef | 2011-06-06 14:09:45 -0700 | [diff] [blame] | 140 | |
| 141 | /* same pin map as above, input read */ |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 142 | #define MSM_GPIO_IN_0 MSM_GPIO1_REG(0x34) |
| 143 | #define MSM_GPIO_IN_1 MSM_GPIO2_REG(0x20) |
| 144 | #define MSM_GPIO_IN_2 MSM_GPIO1_REG(0x38) |
| 145 | #define MSM_GPIO_IN_3 MSM_GPIO1_REG(0x3C) |
| 146 | #define MSM_GPIO_IN_4 MSM_GPIO1_REG(0x40) |
| 147 | #define MSM_GPIO_IN_5 MSM_GPIO1_REG(0x44) |
| 148 | #define MSM_GPIO_IN_6 MSM_GPIO1_REG(0xCC) |
| 149 | #define MSM_GPIO_IN_7 MSM_GPIO1_REG(0x21C) |
David Brown | 9def3ef | 2011-06-06 14:09:45 -0700 | [diff] [blame] | 150 | |
| 151 | /* same pin map as above, 1=edge 0=level interrup */ |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 152 | #define MSM_GPIO_INT_EDGE_0 MSM_GPIO1_REG(0x60) |
| 153 | #define MSM_GPIO_INT_EDGE_1 MSM_GPIO2_REG(0x50) |
| 154 | #define MSM_GPIO_INT_EDGE_2 MSM_GPIO1_REG(0x64) |
| 155 | #define MSM_GPIO_INT_EDGE_3 MSM_GPIO1_REG(0x68) |
| 156 | #define MSM_GPIO_INT_EDGE_4 MSM_GPIO1_REG(0x6C) |
| 157 | #define MSM_GPIO_INT_EDGE_5 MSM_GPIO1_REG(0xC0) |
| 158 | #define MSM_GPIO_INT_EDGE_6 MSM_GPIO1_REG(0xD0) |
| 159 | #define MSM_GPIO_INT_EDGE_7 MSM_GPIO1_REG(0x240) |
David Brown | 9def3ef | 2011-06-06 14:09:45 -0700 | [diff] [blame] | 160 | |
| 161 | /* same pin map as above, 1=positive 0=negative */ |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 162 | #define MSM_GPIO_INT_POS_0 MSM_GPIO1_REG(0x70) |
| 163 | #define MSM_GPIO_INT_POS_1 MSM_GPIO2_REG(0x58) |
| 164 | #define MSM_GPIO_INT_POS_2 MSM_GPIO1_REG(0x74) |
| 165 | #define MSM_GPIO_INT_POS_3 MSM_GPIO1_REG(0x78) |
| 166 | #define MSM_GPIO_INT_POS_4 MSM_GPIO1_REG(0x7C) |
| 167 | #define MSM_GPIO_INT_POS_5 MSM_GPIO1_REG(0xBC) |
| 168 | #define MSM_GPIO_INT_POS_6 MSM_GPIO1_REG(0xD4) |
| 169 | #define MSM_GPIO_INT_POS_7 MSM_GPIO1_REG(0x228) |
David Brown | 9def3ef | 2011-06-06 14:09:45 -0700 | [diff] [blame] | 170 | |
| 171 | /* same pin map as above, interrupt enable */ |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 172 | #define MSM_GPIO_INT_EN_0 MSM_GPIO1_REG(0x80) |
| 173 | #define MSM_GPIO_INT_EN_1 MSM_GPIO2_REG(0x60) |
| 174 | #define MSM_GPIO_INT_EN_2 MSM_GPIO1_REG(0x84) |
| 175 | #define MSM_GPIO_INT_EN_3 MSM_GPIO1_REG(0x88) |
| 176 | #define MSM_GPIO_INT_EN_4 MSM_GPIO1_REG(0x8C) |
| 177 | #define MSM_GPIO_INT_EN_5 MSM_GPIO1_REG(0xB8) |
| 178 | #define MSM_GPIO_INT_EN_6 MSM_GPIO1_REG(0xD8) |
| 179 | #define MSM_GPIO_INT_EN_7 MSM_GPIO1_REG(0x22C) |
David Brown | 9def3ef | 2011-06-06 14:09:45 -0700 | [diff] [blame] | 180 | |
| 181 | /* same pin map as above, write 1 to clear interrupt */ |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 182 | #define MSM_GPIO_INT_CLEAR_0 MSM_GPIO1_REG(0x90) |
| 183 | #define MSM_GPIO_INT_CLEAR_1 MSM_GPIO2_REG(0x68) |
| 184 | #define MSM_GPIO_INT_CLEAR_2 MSM_GPIO1_REG(0x94) |
| 185 | #define MSM_GPIO_INT_CLEAR_3 MSM_GPIO1_REG(0x98) |
| 186 | #define MSM_GPIO_INT_CLEAR_4 MSM_GPIO1_REG(0x9C) |
| 187 | #define MSM_GPIO_INT_CLEAR_5 MSM_GPIO1_REG(0xB4) |
| 188 | #define MSM_GPIO_INT_CLEAR_6 MSM_GPIO1_REG(0xDC) |
| 189 | #define MSM_GPIO_INT_CLEAR_7 MSM_GPIO1_REG(0x230) |
David Brown | 9def3ef | 2011-06-06 14:09:45 -0700 | [diff] [blame] | 190 | |
| 191 | /* same pin map as above, 1=interrupt pending */ |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 192 | #define MSM_GPIO_INT_STATUS_0 MSM_GPIO1_REG(0xA0) |
| 193 | #define MSM_GPIO_INT_STATUS_1 MSM_GPIO2_REG(0x70) |
| 194 | #define MSM_GPIO_INT_STATUS_2 MSM_GPIO1_REG(0xA4) |
| 195 | #define MSM_GPIO_INT_STATUS_3 MSM_GPIO1_REG(0xA8) |
| 196 | #define MSM_GPIO_INT_STATUS_4 MSM_GPIO1_REG(0xAC) |
| 197 | #define MSM_GPIO_INT_STATUS_5 MSM_GPIO1_REG(0xB0) |
| 198 | #define MSM_GPIO_INT_STATUS_6 MSM_GPIO1_REG(0xE0) |
| 199 | #define MSM_GPIO_INT_STATUS_7 MSM_GPIO1_REG(0x234) |
David Brown | 9def3ef | 2011-06-06 14:09:45 -0700 | [diff] [blame] | 200 | |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 201 | #endif |
David Brown | 9def3ef | 2011-06-06 14:09:45 -0700 | [diff] [blame] | 202 | |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 203 | enum { |
| 204 | GPIO_DEBUG_SLEEP = 1U << 0, |
| 205 | }; |
| 206 | static int msm_gpio_debug_mask; |
| 207 | module_param_named(debug_mask, msm_gpio_debug_mask, int, |
| 208 | S_IRUGO | S_IWUSR | S_IWGRP); |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 209 | |
| 210 | #define FIRST_GPIO_IRQ MSM_GPIO_TO_INT(0) |
| 211 | |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 212 | #define MSM_GPIO_BANK(bank, first, last) \ |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 213 | { \ |
| 214 | .regs = { \ |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 215 | .out = MSM_GPIO_OUT_##bank, \ |
| 216 | .in = MSM_GPIO_IN_##bank, \ |
| 217 | .int_status = MSM_GPIO_INT_STATUS_##bank, \ |
| 218 | .int_clear = MSM_GPIO_INT_CLEAR_##bank, \ |
| 219 | .int_en = MSM_GPIO_INT_EN_##bank, \ |
| 220 | .int_edge = MSM_GPIO_INT_EDGE_##bank, \ |
| 221 | .int_pos = MSM_GPIO_INT_POS_##bank, \ |
| 222 | .oe = MSM_GPIO_OE_##bank, \ |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 223 | }, \ |
| 224 | .chip = { \ |
| 225 | .base = (first), \ |
| 226 | .ngpio = (last) - (first) + 1, \ |
| 227 | .get = msm_gpio_get, \ |
| 228 | .set = msm_gpio_set, \ |
| 229 | .direction_input = msm_gpio_direction_input, \ |
| 230 | .direction_output = msm_gpio_direction_output, \ |
| 231 | .to_irq = msm_gpio_to_irq, \ |
Gregory Bean | 26cc666 | 2010-09-10 15:03:37 -0700 | [diff] [blame] | 232 | .request = msm_gpio_request, \ |
| 233 | .free = msm_gpio_free, \ |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 234 | } \ |
| 235 | } |
| 236 | |
| 237 | #define MSM_GPIO_BROKEN_INT_CLEAR 1 |
| 238 | |
| 239 | struct msm_gpio_regs { |
| 240 | void __iomem *out; |
| 241 | void __iomem *in; |
| 242 | void __iomem *int_status; |
| 243 | void __iomem *int_clear; |
| 244 | void __iomem *int_en; |
| 245 | void __iomem *int_edge; |
| 246 | void __iomem *int_pos; |
| 247 | void __iomem *oe; |
| 248 | }; |
| 249 | |
| 250 | struct msm_gpio_chip { |
| 251 | spinlock_t lock; |
| 252 | struct gpio_chip chip; |
| 253 | struct msm_gpio_regs regs; |
| 254 | #if MSM_GPIO_BROKEN_INT_CLEAR |
| 255 | unsigned int_status_copy; |
| 256 | #endif |
| 257 | unsigned int both_edge_detect; |
| 258 | unsigned int int_enable[2]; /* 0: awake, 1: sleep */ |
| 259 | }; |
| 260 | |
| 261 | static int msm_gpio_write(struct msm_gpio_chip *msm_chip, |
| 262 | unsigned offset, unsigned on) |
| 263 | { |
| 264 | unsigned mask = BIT(offset); |
| 265 | unsigned val; |
| 266 | |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 267 | val = __raw_readl(msm_chip->regs.out); |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 268 | if (on) |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 269 | __raw_writel(val | mask, msm_chip->regs.out); |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 270 | else |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 271 | __raw_writel(val & ~mask, msm_chip->regs.out); |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 272 | return 0; |
| 273 | } |
| 274 | |
| 275 | static void msm_gpio_update_both_edge_detect(struct msm_gpio_chip *msm_chip) |
| 276 | { |
| 277 | int loop_limit = 100; |
| 278 | unsigned pol, val, val2, intstat; |
| 279 | do { |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 280 | val = __raw_readl(msm_chip->regs.in); |
| 281 | pol = __raw_readl(msm_chip->regs.int_pos); |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 282 | pol = (pol & ~msm_chip->both_edge_detect) | |
| 283 | (~val & msm_chip->both_edge_detect); |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 284 | __raw_writel(pol, msm_chip->regs.int_pos); |
| 285 | intstat = __raw_readl(msm_chip->regs.int_status); |
| 286 | val2 = __raw_readl(msm_chip->regs.in); |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 287 | if (((val ^ val2) & msm_chip->both_edge_detect & ~intstat) == 0) |
| 288 | return; |
| 289 | } while (loop_limit-- > 0); |
| 290 | printk(KERN_ERR "msm_gpio_update_both_edge_detect, " |
| 291 | "failed to reach stable state %x != %x\n", val, val2); |
| 292 | } |
| 293 | |
| 294 | static int msm_gpio_clear_detect_status(struct msm_gpio_chip *msm_chip, |
| 295 | unsigned offset) |
| 296 | { |
| 297 | unsigned bit = BIT(offset); |
| 298 | |
| 299 | #if MSM_GPIO_BROKEN_INT_CLEAR |
| 300 | /* Save interrupts that already triggered before we loose them. */ |
| 301 | /* Any interrupt that triggers between the read of int_status */ |
| 302 | /* and the write to int_clear will still be lost though. */ |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 303 | msm_chip->int_status_copy |= __raw_readl(msm_chip->regs.int_status); |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 304 | msm_chip->int_status_copy &= ~bit; |
| 305 | #endif |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 306 | __raw_writel(bit, msm_chip->regs.int_clear); |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 307 | msm_gpio_update_both_edge_detect(msm_chip); |
| 308 | return 0; |
| 309 | } |
| 310 | |
| 311 | static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
| 312 | { |
| 313 | struct msm_gpio_chip *msm_chip; |
| 314 | unsigned long irq_flags; |
| 315 | |
| 316 | msm_chip = container_of(chip, struct msm_gpio_chip, chip); |
| 317 | spin_lock_irqsave(&msm_chip->lock, irq_flags); |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 318 | __raw_writel(__raw_readl(msm_chip->regs.oe) & ~BIT(offset), |
| 319 | msm_chip->regs.oe); |
| 320 | mb(); |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 321 | spin_unlock_irqrestore(&msm_chip->lock, irq_flags); |
| 322 | return 0; |
| 323 | } |
| 324 | |
| 325 | static int |
| 326 | msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) |
| 327 | { |
| 328 | struct msm_gpio_chip *msm_chip; |
| 329 | unsigned long irq_flags; |
| 330 | |
| 331 | msm_chip = container_of(chip, struct msm_gpio_chip, chip); |
| 332 | spin_lock_irqsave(&msm_chip->lock, irq_flags); |
| 333 | msm_gpio_write(msm_chip, offset, value); |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 334 | __raw_writel(__raw_readl(msm_chip->regs.oe) | BIT(offset), |
| 335 | msm_chip->regs.oe); |
| 336 | mb(); |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 337 | spin_unlock_irqrestore(&msm_chip->lock, irq_flags); |
| 338 | return 0; |
| 339 | } |
| 340 | |
| 341 | static int msm_gpio_get(struct gpio_chip *chip, unsigned offset) |
| 342 | { |
| 343 | struct msm_gpio_chip *msm_chip; |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 344 | int rc; |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 345 | |
| 346 | msm_chip = container_of(chip, struct msm_gpio_chip, chip); |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 347 | rc = (__raw_readl(msm_chip->regs.in) & (1U << offset)) ? 1 : 0; |
| 348 | mb(); |
| 349 | return rc; |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 350 | } |
| 351 | |
| 352 | static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
| 353 | { |
| 354 | struct msm_gpio_chip *msm_chip; |
| 355 | unsigned long irq_flags; |
| 356 | |
| 357 | msm_chip = container_of(chip, struct msm_gpio_chip, chip); |
| 358 | spin_lock_irqsave(&msm_chip->lock, irq_flags); |
| 359 | msm_gpio_write(msm_chip, offset, value); |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 360 | mb(); |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 361 | spin_unlock_irqrestore(&msm_chip->lock, irq_flags); |
| 362 | } |
| 363 | |
| 364 | static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
| 365 | { |
| 366 | return MSM_GPIO_TO_INT(chip->base + offset); |
| 367 | } |
| 368 | |
Gregory Bean | 26cc666 | 2010-09-10 15:03:37 -0700 | [diff] [blame] | 369 | #ifdef CONFIG_MSM_GPIOMUX |
| 370 | static int msm_gpio_request(struct gpio_chip *chip, unsigned offset) |
| 371 | { |
| 372 | return msm_gpiomux_get(chip->base + offset); |
| 373 | } |
| 374 | |
| 375 | static void msm_gpio_free(struct gpio_chip *chip, unsigned offset) |
| 376 | { |
| 377 | msm_gpiomux_put(chip->base + offset); |
| 378 | } |
| 379 | #else |
| 380 | #define msm_gpio_request NULL |
| 381 | #define msm_gpio_free NULL |
| 382 | #endif |
| 383 | |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 384 | struct msm_gpio_chip msm_gpio_chips[] = { |
| 385 | #if defined(CONFIG_ARCH_MSM7X00A) |
| 386 | MSM_GPIO_BANK(0, 0, 15), |
| 387 | MSM_GPIO_BANK(1, 16, 42), |
| 388 | MSM_GPIO_BANK(2, 43, 67), |
| 389 | MSM_GPIO_BANK(3, 68, 94), |
| 390 | MSM_GPIO_BANK(4, 95, 106), |
| 391 | MSM_GPIO_BANK(5, 107, 121), |
| 392 | #elif defined(CONFIG_ARCH_MSM7X25) || defined(CONFIG_ARCH_MSM7X27) |
| 393 | MSM_GPIO_BANK(0, 0, 15), |
| 394 | MSM_GPIO_BANK(1, 16, 42), |
| 395 | MSM_GPIO_BANK(2, 43, 67), |
| 396 | MSM_GPIO_BANK(3, 68, 94), |
| 397 | MSM_GPIO_BANK(4, 95, 106), |
| 398 | MSM_GPIO_BANK(5, 107, 132), |
| 399 | #elif defined(CONFIG_ARCH_MSM7X30) |
| 400 | MSM_GPIO_BANK(0, 0, 15), |
| 401 | MSM_GPIO_BANK(1, 16, 43), |
| 402 | MSM_GPIO_BANK(2, 44, 67), |
| 403 | MSM_GPIO_BANK(3, 68, 94), |
| 404 | MSM_GPIO_BANK(4, 95, 106), |
| 405 | MSM_GPIO_BANK(5, 107, 133), |
| 406 | MSM_GPIO_BANK(6, 134, 150), |
| 407 | MSM_GPIO_BANK(7, 151, 181), |
| 408 | #elif defined(CONFIG_ARCH_QSD8X50) |
| 409 | MSM_GPIO_BANK(0, 0, 15), |
| 410 | MSM_GPIO_BANK(1, 16, 42), |
| 411 | MSM_GPIO_BANK(2, 43, 67), |
| 412 | MSM_GPIO_BANK(3, 68, 94), |
| 413 | MSM_GPIO_BANK(4, 95, 103), |
| 414 | MSM_GPIO_BANK(5, 104, 121), |
| 415 | MSM_GPIO_BANK(6, 122, 152), |
| 416 | MSM_GPIO_BANK(7, 153, 164), |
| 417 | #endif |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 418 | }; |
| 419 | |
Lennert Buytenhek | 0f86ee0 | 2010-11-29 10:37:34 +0100 | [diff] [blame] | 420 | static void msm_gpio_irq_ack(struct irq_data *d) |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 421 | { |
| 422 | unsigned long irq_flags; |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 423 | struct msm_gpio_chip *msm_chip = irq_get_chip_data(d->irq); |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 424 | spin_lock_irqsave(&msm_chip->lock, irq_flags); |
| 425 | msm_gpio_clear_detect_status(msm_chip, |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 426 | d->irq - gpio_to_irq(msm_chip->chip.base)); |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 427 | spin_unlock_irqrestore(&msm_chip->lock, irq_flags); |
| 428 | } |
| 429 | |
Lennert Buytenhek | 0f86ee0 | 2010-11-29 10:37:34 +0100 | [diff] [blame] | 430 | static void msm_gpio_irq_mask(struct irq_data *d) |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 431 | { |
| 432 | unsigned long irq_flags; |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 433 | struct msm_gpio_chip *msm_chip = irq_get_chip_data(d->irq); |
Lennert Buytenhek | 0f86ee0 | 2010-11-29 10:37:34 +0100 | [diff] [blame] | 434 | unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base); |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 435 | |
| 436 | spin_lock_irqsave(&msm_chip->lock, irq_flags); |
| 437 | /* level triggered interrupts are also latched */ |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 438 | if (!(__raw_readl(msm_chip->regs.int_edge) & BIT(offset))) |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 439 | msm_gpio_clear_detect_status(msm_chip, offset); |
| 440 | msm_chip->int_enable[0] &= ~BIT(offset); |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 441 | __raw_writel(msm_chip->int_enable[0], msm_chip->regs.int_en); |
| 442 | mb(); |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 443 | spin_unlock_irqrestore(&msm_chip->lock, irq_flags); |
| 444 | } |
| 445 | |
Lennert Buytenhek | 0f86ee0 | 2010-11-29 10:37:34 +0100 | [diff] [blame] | 446 | static void msm_gpio_irq_unmask(struct irq_data *d) |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 447 | { |
| 448 | unsigned long irq_flags; |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 449 | struct msm_gpio_chip *msm_chip = irq_get_chip_data(d->irq); |
Lennert Buytenhek | 0f86ee0 | 2010-11-29 10:37:34 +0100 | [diff] [blame] | 450 | unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base); |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 451 | |
| 452 | spin_lock_irqsave(&msm_chip->lock, irq_flags); |
| 453 | /* level triggered interrupts are also latched */ |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 454 | if (!(__raw_readl(msm_chip->regs.int_edge) & BIT(offset))) |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 455 | msm_gpio_clear_detect_status(msm_chip, offset); |
| 456 | msm_chip->int_enable[0] |= BIT(offset); |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 457 | __raw_writel(msm_chip->int_enable[0], msm_chip->regs.int_en); |
| 458 | mb(); |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 459 | spin_unlock_irqrestore(&msm_chip->lock, irq_flags); |
| 460 | } |
| 461 | |
Lennert Buytenhek | 0f86ee0 | 2010-11-29 10:37:34 +0100 | [diff] [blame] | 462 | static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 463 | { |
| 464 | unsigned long irq_flags; |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 465 | struct msm_gpio_chip *msm_chip = irq_get_chip_data(d->irq); |
Lennert Buytenhek | 0f86ee0 | 2010-11-29 10:37:34 +0100 | [diff] [blame] | 466 | unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base); |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 467 | |
| 468 | spin_lock_irqsave(&msm_chip->lock, irq_flags); |
| 469 | |
| 470 | if (on) |
| 471 | msm_chip->int_enable[1] |= BIT(offset); |
| 472 | else |
| 473 | msm_chip->int_enable[1] &= ~BIT(offset); |
| 474 | |
| 475 | spin_unlock_irqrestore(&msm_chip->lock, irq_flags); |
| 476 | return 0; |
| 477 | } |
| 478 | |
Lennert Buytenhek | 0f86ee0 | 2010-11-29 10:37:34 +0100 | [diff] [blame] | 479 | static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type) |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 480 | { |
| 481 | unsigned long irq_flags; |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 482 | struct msm_gpio_chip *msm_chip = irq_get_chip_data(d->irq); |
Lennert Buytenhek | 0f86ee0 | 2010-11-29 10:37:34 +0100 | [diff] [blame] | 483 | unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base); |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 484 | unsigned val, mask = BIT(offset); |
| 485 | |
| 486 | spin_lock_irqsave(&msm_chip->lock, irq_flags); |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 487 | val = __raw_readl(msm_chip->regs.int_edge); |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 488 | if (flow_type & IRQ_TYPE_EDGE_BOTH) { |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 489 | __raw_writel(val | mask, msm_chip->regs.int_edge); |
Thomas Gleixner | 70c4fa2 | 2011-03-24 12:41:27 +0100 | [diff] [blame] | 490 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 491 | } else { |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 492 | __raw_writel(val & ~mask, msm_chip->regs.int_edge); |
Thomas Gleixner | 70c4fa2 | 2011-03-24 12:41:27 +0100 | [diff] [blame] | 493 | __irq_set_handler_locked(d->irq, handle_level_irq); |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 494 | } |
| 495 | if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { |
| 496 | msm_chip->both_edge_detect |= mask; |
| 497 | msm_gpio_update_both_edge_detect(msm_chip); |
| 498 | } else { |
| 499 | msm_chip->both_edge_detect &= ~mask; |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 500 | val = __raw_readl(msm_chip->regs.int_pos); |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 501 | if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_HIGH)) |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 502 | __raw_writel(val | mask, msm_chip->regs.int_pos); |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 503 | else |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 504 | __raw_writel(val & ~mask, msm_chip->regs.int_pos); |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 505 | } |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 506 | mb(); |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 507 | spin_unlock_irqrestore(&msm_chip->lock, irq_flags); |
| 508 | return 0; |
| 509 | } |
| 510 | |
| 511 | static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
| 512 | { |
| 513 | int i, j, mask; |
| 514 | unsigned val; |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 515 | struct irq_chip *chip = irq_desc_get_chip(desc); |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 516 | |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 517 | chained_irq_enter(chip, desc); |
| 518 | |
| 519 | for (i = 0; i < ARRAY_SIZE(msm_gpio_chips); i++) { |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 520 | struct msm_gpio_chip *msm_chip = &msm_gpio_chips[i]; |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 521 | val = __raw_readl(msm_chip->regs.int_status); |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 522 | val &= msm_chip->int_enable[0]; |
| 523 | while (val) { |
| 524 | mask = val & -val; |
| 525 | j = fls(mask) - 1; |
| 526 | /* printk("%s %08x %08x bit %d gpio %d irq %d\n", |
| 527 | __func__, v, m, j, msm_chip->chip.start + j, |
| 528 | FIRST_GPIO_IRQ + msm_chip->chip.start + j); */ |
| 529 | val &= ~mask; |
| 530 | generic_handle_irq(FIRST_GPIO_IRQ + |
| 531 | msm_chip->chip.base + j); |
| 532 | } |
| 533 | } |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 534 | |
| 535 | chained_irq_exit(chip, desc); |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 536 | } |
| 537 | |
| 538 | static struct irq_chip msm_gpio_irq_chip = { |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 539 | .name = "msmgpio", |
| 540 | .irq_ack = msm_gpio_irq_ack, |
| 541 | .irq_mask = msm_gpio_irq_mask, |
| 542 | .irq_unmask = msm_gpio_irq_unmask, |
| 543 | .irq_set_wake = msm_gpio_irq_set_wake, |
| 544 | .irq_set_type = msm_gpio_irq_set_type, |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 545 | }; |
| 546 | |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 547 | #define NUM_GPIO_SMEM_BANKS 6 |
| 548 | #define GPIO_SMEM_NUM_GROUPS 2 |
| 549 | #define GPIO_SMEM_MAX_PC_INTERRUPTS 8 |
| 550 | struct tramp_gpio_smem { |
| 551 | uint16_t num_fired[GPIO_SMEM_NUM_GROUPS]; |
| 552 | uint16_t fired[GPIO_SMEM_NUM_GROUPS][GPIO_SMEM_MAX_PC_INTERRUPTS]; |
| 553 | uint32_t enabled[NUM_GPIO_SMEM_BANKS]; |
| 554 | uint32_t detection[NUM_GPIO_SMEM_BANKS]; |
| 555 | uint32_t polarity[NUM_GPIO_SMEM_BANKS]; |
| 556 | }; |
| 557 | |
| 558 | static void msm_gpio_sleep_int(unsigned long arg) |
| 559 | { |
| 560 | int i, j; |
| 561 | struct tramp_gpio_smem *smem_gpio; |
| 562 | |
| 563 | BUILD_BUG_ON(NR_GPIO_IRQS > NUM_GPIO_SMEM_BANKS * 32); |
| 564 | |
| 565 | smem_gpio = smem_alloc(SMEM_GPIO_INT, sizeof(*smem_gpio)); |
| 566 | if (smem_gpio == NULL) |
| 567 | return; |
| 568 | |
| 569 | local_irq_disable(); |
| 570 | for (i = 0; i < GPIO_SMEM_NUM_GROUPS; i++) { |
| 571 | int count = smem_gpio->num_fired[i]; |
| 572 | for (j = 0; j < count; j++) { |
| 573 | /* TODO: Check mask */ |
| 574 | generic_handle_irq( |
| 575 | MSM_GPIO_TO_INT(smem_gpio->fired[i][j])); |
| 576 | } |
| 577 | } |
| 578 | local_irq_enable(); |
| 579 | } |
| 580 | |
| 581 | static DECLARE_TASKLET(msm_gpio_sleep_int_tasklet, msm_gpio_sleep_int, 0); |
| 582 | |
| 583 | void msm_gpio_enter_sleep(int from_idle) |
| 584 | { |
| 585 | int i; |
| 586 | struct tramp_gpio_smem *smem_gpio; |
| 587 | |
| 588 | smem_gpio = smem_alloc(SMEM_GPIO_INT, sizeof(*smem_gpio)); |
| 589 | |
| 590 | if (smem_gpio) { |
| 591 | for (i = 0; i < ARRAY_SIZE(smem_gpio->enabled); i++) { |
| 592 | smem_gpio->enabled[i] = 0; |
| 593 | smem_gpio->detection[i] = 0; |
| 594 | smem_gpio->polarity[i] = 0; |
| 595 | } |
| 596 | } |
| 597 | |
| 598 | for (i = 0; i < ARRAY_SIZE(msm_gpio_chips); i++) { |
| 599 | __raw_writel(msm_gpio_chips[i].int_enable[!from_idle], |
| 600 | msm_gpio_chips[i].regs.int_en); |
| 601 | if (smem_gpio) { |
| 602 | uint32_t tmp; |
| 603 | int start, index, shiftl, shiftr; |
| 604 | start = msm_gpio_chips[i].chip.base; |
| 605 | index = start / 32; |
| 606 | shiftl = start % 32; |
| 607 | shiftr = 32 - shiftl; |
| 608 | tmp = msm_gpio_chips[i].int_enable[!from_idle]; |
| 609 | smem_gpio->enabled[index] |= tmp << shiftl; |
| 610 | smem_gpio->enabled[index+1] |= tmp >> shiftr; |
| 611 | smem_gpio->detection[index] |= |
| 612 | __raw_readl(msm_gpio_chips[i].regs.int_edge) << |
| 613 | shiftl; |
| 614 | smem_gpio->detection[index+1] |= |
| 615 | __raw_readl(msm_gpio_chips[i].regs.int_edge) >> |
| 616 | shiftr; |
| 617 | smem_gpio->polarity[index] |= |
| 618 | __raw_readl(msm_gpio_chips[i].regs.int_pos) << |
| 619 | shiftl; |
| 620 | smem_gpio->polarity[index+1] |= |
| 621 | __raw_readl(msm_gpio_chips[i].regs.int_pos) >> |
| 622 | shiftr; |
| 623 | } |
| 624 | } |
| 625 | mb(); |
| 626 | |
| 627 | if (smem_gpio) { |
| 628 | if (msm_gpio_debug_mask & GPIO_DEBUG_SLEEP) |
| 629 | for (i = 0; i < ARRAY_SIZE(smem_gpio->enabled); i++) { |
| 630 | printk("msm_gpio_enter_sleep gpio %d-%d: enable" |
| 631 | " %08x, edge %08x, polarity %08x\n", |
| 632 | i * 32, i * 32 + 31, |
| 633 | smem_gpio->enabled[i], |
| 634 | smem_gpio->detection[i], |
| 635 | smem_gpio->polarity[i]); |
| 636 | } |
| 637 | for (i = 0; i < GPIO_SMEM_NUM_GROUPS; i++) |
| 638 | smem_gpio->num_fired[i] = 0; |
| 639 | } |
| 640 | } |
| 641 | |
| 642 | void msm_gpio_exit_sleep(void) |
| 643 | { |
| 644 | int i; |
| 645 | struct tramp_gpio_smem *smem_gpio; |
| 646 | |
| 647 | smem_gpio = smem_alloc(SMEM_GPIO_INT, sizeof(*smem_gpio)); |
| 648 | |
| 649 | for (i = 0; i < ARRAY_SIZE(msm_gpio_chips); i++) { |
| 650 | __raw_writel(msm_gpio_chips[i].int_enable[0], |
| 651 | msm_gpio_chips[i].regs.int_en); |
| 652 | } |
| 653 | mb(); |
| 654 | |
| 655 | if (smem_gpio && (smem_gpio->num_fired[0] || smem_gpio->num_fired[1])) { |
| 656 | if (msm_gpio_debug_mask & GPIO_DEBUG_SLEEP) |
| 657 | printk(KERN_INFO "gpio: fired %x %x\n", |
| 658 | smem_gpio->num_fired[0], smem_gpio->num_fired[1]); |
| 659 | tasklet_schedule(&msm_gpio_sleep_int_tasklet); |
| 660 | } |
| 661 | } |
| 662 | |
| 663 | |
| 664 | int gpio_tlmm_config(unsigned config, unsigned disable) |
| 665 | { |
| 666 | return msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, &disable); |
| 667 | } |
| 668 | EXPORT_SYMBOL(gpio_tlmm_config); |
| 669 | |
| 670 | int msm_gpios_request_enable(const struct msm_gpio *table, int size) |
| 671 | { |
| 672 | int rc = msm_gpios_request(table, size); |
| 673 | if (rc) |
| 674 | return rc; |
| 675 | rc = msm_gpios_enable(table, size); |
| 676 | if (rc) |
| 677 | msm_gpios_free(table, size); |
| 678 | return rc; |
| 679 | } |
| 680 | EXPORT_SYMBOL(msm_gpios_request_enable); |
| 681 | |
| 682 | void msm_gpios_disable_free(const struct msm_gpio *table, int size) |
| 683 | { |
| 684 | msm_gpios_disable(table, size); |
| 685 | msm_gpios_free(table, size); |
| 686 | } |
| 687 | EXPORT_SYMBOL(msm_gpios_disable_free); |
| 688 | |
| 689 | int msm_gpios_request(const struct msm_gpio *table, int size) |
| 690 | { |
| 691 | int rc; |
| 692 | int i; |
| 693 | const struct msm_gpio *g; |
| 694 | for (i = 0; i < size; i++) { |
| 695 | g = table + i; |
| 696 | rc = gpio_request(GPIO_PIN(g->gpio_cfg), g->label); |
| 697 | if (rc) { |
| 698 | pr_err("gpio_request(%d) <%s> failed: %d\n", |
| 699 | GPIO_PIN(g->gpio_cfg), g->label ?: "?", rc); |
| 700 | goto err; |
| 701 | } |
| 702 | } |
| 703 | return 0; |
| 704 | err: |
| 705 | msm_gpios_free(table, i); |
| 706 | return rc; |
| 707 | } |
| 708 | EXPORT_SYMBOL(msm_gpios_request); |
| 709 | |
| 710 | void msm_gpios_free(const struct msm_gpio *table, int size) |
| 711 | { |
| 712 | int i; |
| 713 | const struct msm_gpio *g; |
| 714 | for (i = size-1; i >= 0; i--) { |
| 715 | g = table + i; |
| 716 | gpio_free(GPIO_PIN(g->gpio_cfg)); |
| 717 | } |
| 718 | } |
| 719 | EXPORT_SYMBOL(msm_gpios_free); |
| 720 | |
| 721 | int msm_gpios_enable(const struct msm_gpio *table, int size) |
| 722 | { |
| 723 | int rc; |
| 724 | int i; |
| 725 | const struct msm_gpio *g; |
| 726 | for (i = 0; i < size; i++) { |
| 727 | g = table + i; |
| 728 | rc = gpio_tlmm_config(g->gpio_cfg, GPIO_CFG_ENABLE); |
| 729 | if (rc) { |
| 730 | pr_err("gpio_tlmm_config(0x%08x, GPIO_CFG_ENABLE)" |
| 731 | " <%s> failed: %d\n", |
| 732 | g->gpio_cfg, g->label ?: "?", rc); |
| 733 | pr_err("pin %d func %d dir %d pull %d drvstr %d\n", |
| 734 | GPIO_PIN(g->gpio_cfg), GPIO_FUNC(g->gpio_cfg), |
| 735 | GPIO_DIR(g->gpio_cfg), GPIO_PULL(g->gpio_cfg), |
| 736 | GPIO_DRVSTR(g->gpio_cfg)); |
| 737 | goto err; |
| 738 | } |
| 739 | } |
| 740 | return 0; |
| 741 | err: |
| 742 | msm_gpios_disable(table, i); |
| 743 | return rc; |
| 744 | } |
| 745 | EXPORT_SYMBOL(msm_gpios_enable); |
| 746 | |
| 747 | int msm_gpios_disable(const struct msm_gpio *table, int size) |
| 748 | { |
| 749 | int rc = 0; |
| 750 | int i; |
| 751 | const struct msm_gpio *g; |
| 752 | for (i = size-1; i >= 0; i--) { |
| 753 | int tmp; |
| 754 | g = table + i; |
| 755 | tmp = gpio_tlmm_config(g->gpio_cfg, GPIO_CFG_DISABLE); |
| 756 | if (tmp) { |
| 757 | pr_err("gpio_tlmm_config(0x%08x, GPIO_CFG_DISABLE)" |
| 758 | " <%s> failed: %d\n", |
| 759 | g->gpio_cfg, g->label ?: "?", rc); |
| 760 | pr_err("pin %d func %d dir %d pull %d drvstr %d\n", |
| 761 | GPIO_PIN(g->gpio_cfg), GPIO_FUNC(g->gpio_cfg), |
| 762 | GPIO_DIR(g->gpio_cfg), GPIO_PULL(g->gpio_cfg), |
| 763 | GPIO_DRVSTR(g->gpio_cfg)); |
| 764 | if (!rc) |
| 765 | rc = tmp; |
| 766 | } |
| 767 | } |
| 768 | |
| 769 | return rc; |
| 770 | } |
| 771 | EXPORT_SYMBOL(msm_gpios_disable); |
| 772 | |
| 773 | /* Locate the GPIO_OUT register for the given GPIO and return its address |
| 774 | * and the bit position of the gpio's bit within the register. |
| 775 | * |
| 776 | * This function is used by gpiomux-v1 in order to support output transitions. |
| 777 | */ |
| 778 | void msm_gpio_find_out(const unsigned gpio, void __iomem **out, |
| 779 | unsigned *offset) |
| 780 | { |
| 781 | struct msm_gpio_chip *msm_chip = msm_gpio_chips; |
| 782 | |
| 783 | while (gpio >= msm_chip->chip.base + msm_chip->chip.ngpio) |
| 784 | ++msm_chip; |
| 785 | |
| 786 | *out = msm_chip->regs.out; |
| 787 | *offset = gpio - msm_chip->chip.base; |
| 788 | } |
| 789 | |
| 790 | static int __devinit msm_gpio_probe(struct platform_device *dev) |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 791 | { |
| 792 | int i, j = 0; |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 793 | int grp_irq; |
David Brown | 10eb5f6 | 2011-05-12 01:28:01 -0700 | [diff] [blame] | 794 | |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 795 | for (i = FIRST_GPIO_IRQ; i < FIRST_GPIO_IRQ + NR_GPIO_IRQS; i++) { |
| 796 | if (i - FIRST_GPIO_IRQ >= |
| 797 | msm_gpio_chips[j].chip.base + |
| 798 | msm_gpio_chips[j].chip.ngpio) |
| 799 | j++; |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 800 | irq_set_chip_data(i, &msm_gpio_chips[j]); |
Thomas Gleixner | f38c02f | 2011-03-24 13:35:09 +0100 | [diff] [blame] | 801 | irq_set_chip_and_handler(i, &msm_gpio_irq_chip, |
| 802 | handle_edge_irq); |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 803 | set_irq_flags(i, IRQF_VALID); |
| 804 | } |
| 805 | |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 806 | for (i = 0; i < dev->num_resources; i++) { |
| 807 | grp_irq = platform_get_irq(dev, i); |
| 808 | if (grp_irq < 0) |
| 809 | return -ENXIO; |
| 810 | |
| 811 | irq_set_chained_handler(grp_irq, msm_gpio_irq_handler); |
| 812 | irq_set_irq_wake(grp_irq, (i + 1)); |
| 813 | } |
| 814 | |
| 815 | for (i = 0; i < ARRAY_SIZE(msm_gpio_chips); i++) { |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 816 | spin_lock_init(&msm_gpio_chips[i].lock); |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 817 | __raw_writel(0, msm_gpio_chips[i].regs.int_en); |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 818 | gpiochip_add(&msm_gpio_chips[i].chip); |
| 819 | } |
| 820 | |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 821 | mb(); |
Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 822 | return 0; |
| 823 | } |
| 824 | |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 825 | static struct platform_driver msm_gpio_driver = { |
| 826 | .probe = msm_gpio_probe, |
| 827 | .driver = { |
| 828 | .name = "msmgpio", |
| 829 | .owner = THIS_MODULE, |
| 830 | }, |
| 831 | }; |
| 832 | |
| 833 | static int __init msm_gpio_init(void) |
| 834 | { |
| 835 | return platform_driver_register(&msm_gpio_driver); |
| 836 | } |
| 837 | postcore_initcall(msm_gpio_init); |