Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 1 | /* |
Mike Frysinger | af5d7fc | 2009-11-15 18:18:41 -0500 | [diff] [blame] | 2 | * DO NOT EDIT THIS FILE |
| 3 | * This file is under version control at |
| 4 | * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/ |
| 5 | * and can be replaced with that version at any time |
| 6 | * DO NOT EDIT THIS FILE |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 7 | * |
Mike Frysinger | dc7101b | 2010-05-27 21:47:31 +0000 | [diff] [blame] | 8 | * Copyright 2004-2010 Analog Devices Inc. |
Mike Frysinger | af5d7fc | 2009-11-15 18:18:41 -0500 | [diff] [blame] | 9 | * Licensed under the ADI BSD license. |
| 10 | * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 11 | */ |
| 12 | |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 13 | /* This file should be up to date with: |
Yi Li | bd411b1 | 2009-08-05 10:02:14 +0000 | [diff] [blame] | 14 | * - Revision I, 07/23/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 15 | */ |
| 16 | |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 17 | #ifndef _MACH_ANOMALY_H_ |
| 18 | #define _MACH_ANOMALY_H_ |
Mike Frysinger | 287050f | 2007-07-24 15:23:20 +0800 | [diff] [blame] | 19 | |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 20 | /* We do not support 0.0 or 0.1 silicon - sorry */ |
| 21 | #if __SILICON_REVISION__ < 2 |
| 22 | # error will not work on BF548 silicon version 0.0, or 0.1 |
| 23 | #endif |
| 24 | |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 25 | /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 26 | #define ANOMALY_05000074 (1) |
| 27 | /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ |
| 28 | #define ANOMALY_05000119 (1) |
| 29 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ |
| 30 | #define ANOMALY_05000122 (1) |
Mike Frysinger | dc7101b | 2010-05-27 21:47:31 +0000 | [diff] [blame] | 31 | /* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */ |
Mike Frysinger | af5d7fc | 2009-11-15 18:18:41 -0500 | [diff] [blame] | 32 | #define ANOMALY_05000220 (1) |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 33 | /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 34 | #define ANOMALY_05000245 (1) |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 35 | /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ |
| 36 | #define ANOMALY_05000265 (1) |
| 37 | /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ |
| 38 | #define ANOMALY_05000272 (1) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 39 | /* False Hardware Error Exception when ISR Context Is Not Restored */ |
Mike Frysinger | 7cc1c4b | 2007-12-24 20:05:09 +0800 | [diff] [blame] | 40 | #define ANOMALY_05000281 (__SILICON_REVISION__ < 1) |
Mike Frysinger | bc8c84c | 2007-08-05 17:32:25 +0800 | [diff] [blame] | 41 | /* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ |
Mike Frysinger | 7cc1c4b | 2007-12-24 20:05:09 +0800 | [diff] [blame] | 42 | #define ANOMALY_05000304 (__SILICON_REVISION__ < 1) |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 43 | /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ |
| 44 | #define ANOMALY_05000310 (1) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 45 | /* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ |
Mike Frysinger | 7cc1c4b | 2007-12-24 20:05:09 +0800 | [diff] [blame] | 46 | #define ANOMALY_05000312 (__SILICON_REVISION__ < 1) |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 47 | /* TWI Slave Boot Mode Is Not Functional */ |
Mike Frysinger | 7cc1c4b | 2007-12-24 20:05:09 +0800 | [diff] [blame] | 48 | #define ANOMALY_05000324 (__SILICON_REVISION__ < 1) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 49 | /* FIFO Boot Mode Not Functional */ |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 50 | #define ANOMALY_05000325 (__SILICON_REVISION__ < 2) |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 51 | /* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */ |
Mike Frysinger | 7cc1c4b | 2007-12-24 20:05:09 +0800 | [diff] [blame] | 52 | #define ANOMALY_05000327 (__SILICON_REVISION__ < 1) |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 53 | /* Incorrect Access of OTP_STATUS During otp_write() Function */ |
Mike Frysinger | 7cc1c4b | 2007-12-24 20:05:09 +0800 | [diff] [blame] | 54 | #define ANOMALY_05000328 (__SILICON_REVISION__ < 1) |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 55 | /* Synchronous Burst Flash Boot Mode Is Not Functional */ |
Mike Frysinger | 7cc1c4b | 2007-12-24 20:05:09 +0800 | [diff] [blame] | 56 | #define ANOMALY_05000329 (__SILICON_REVISION__ < 1) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 57 | /* Host DMA Boot Modes Are Not Functional */ |
Mike Frysinger | 7cc1c4b | 2007-12-24 20:05:09 +0800 | [diff] [blame] | 58 | #define ANOMALY_05000330 (__SILICON_REVISION__ < 1) |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 59 | /* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */ |
Mike Frysinger | 7cc1c4b | 2007-12-24 20:05:09 +0800 | [diff] [blame] | 60 | #define ANOMALY_05000334 (__SILICON_REVISION__ < 1) |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 61 | /* Inadequate Rotary Debounce Logic Duration */ |
Mike Frysinger | 7cc1c4b | 2007-12-24 20:05:09 +0800 | [diff] [blame] | 62 | #define ANOMALY_05000335 (__SILICON_REVISION__ < 1) |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 63 | /* Phantom Interrupt Occurs After First Configuration of Host DMA Port */ |
Mike Frysinger | 7cc1c4b | 2007-12-24 20:05:09 +0800 | [diff] [blame] | 64 | #define ANOMALY_05000336 (__SILICON_REVISION__ < 1) |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 65 | /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ |
Mike Frysinger | 7cc1c4b | 2007-12-24 20:05:09 +0800 | [diff] [blame] | 66 | #define ANOMALY_05000337 (__SILICON_REVISION__ < 1) |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 67 | /* Slave-Mode SPI0 MISO Failure With CPHA = 0 */ |
Mike Frysinger | 7cc1c4b | 2007-12-24 20:05:09 +0800 | [diff] [blame] | 68 | #define ANOMALY_05000338 (__SILICON_REVISION__ < 1) |
Mike Frysinger | bc8c84c | 2007-08-05 17:32:25 +0800 | [diff] [blame] | 69 | /* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */ |
Mike Frysinger | 7cc1c4b | 2007-12-24 20:05:09 +0800 | [diff] [blame] | 70 | #define ANOMALY_05000340 (__SILICON_REVISION__ < 1) |
Mike Frysinger | bc8c84c | 2007-08-05 17:32:25 +0800 | [diff] [blame] | 71 | /* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */ |
Mike Frysinger | 7cc1c4b | 2007-12-24 20:05:09 +0800 | [diff] [blame] | 72 | #define ANOMALY_05000344 (__SILICON_REVISION__ < 1) |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 73 | /* USB Calibration Value Is Not Initialized */ |
Mike Frysinger | 7cc1c4b | 2007-12-24 20:05:09 +0800 | [diff] [blame] | 74 | #define ANOMALY_05000346 (__SILICON_REVISION__ < 1) |
Robin Getz | 202d7bd | 2008-10-09 11:59:46 +0800 | [diff] [blame] | 75 | /* USB Calibration Value to use */ |
| 76 | #define ANOMALY_05000346_value 0x5411 |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 77 | /* Preboot Routine Incorrectly Alters Reset Value of USB Register */ |
Mike Frysinger | 7cc1c4b | 2007-12-24 20:05:09 +0800 | [diff] [blame] | 78 | #define ANOMALY_05000347 (__SILICON_REVISION__ < 1) |
Mike Frysinger | bc8c84c | 2007-08-05 17:32:25 +0800 | [diff] [blame] | 79 | /* Data Lost when Core Reads SDH Data FIFO */ |
Mike Frysinger | 7cc1c4b | 2007-12-24 20:05:09 +0800 | [diff] [blame] | 80 | #define ANOMALY_05000349 (__SILICON_REVISION__ < 1) |
Mike Frysinger | bc8c84c | 2007-08-05 17:32:25 +0800 | [diff] [blame] | 81 | /* PLL Status Register Is Inaccurate */ |
Mike Frysinger | 7cc1c4b | 2007-12-24 20:05:09 +0800 | [diff] [blame] | 82 | #define ANOMALY_05000351 (__SILICON_REVISION__ < 1) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 83 | /* bfrom_SysControl() Firmware Function Performs Improper System Reset */ |
Mike Frysinger | de55aa3 | 2011-03-22 21:06:16 -0400 | [diff] [blame] | 84 | /* |
| 85 | * Note: anomaly sheet says this is fixed with bf54x-0.2+, but testing |
| 86 | * shows that the fix itself does not cover all cases. |
| 87 | */ |
| 88 | #define ANOMALY_05000353 (1) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 89 | /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ |
| 90 | #define ANOMALY_05000355 (__SILICON_REVISION__ < 1) |
| 91 | /* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */ |
| 92 | #define ANOMALY_05000356 (__SILICON_REVISION__ < 1) |
Mike Frysinger | 7cc1c4b | 2007-12-24 20:05:09 +0800 | [diff] [blame] | 93 | /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ |
| 94 | #define ANOMALY_05000357 (1) |
| 95 | /* External Memory Read Access Hangs Core With PLL Bypass */ |
| 96 | #define ANOMALY_05000360 (1) |
| 97 | /* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */ |
| 98 | #define ANOMALY_05000365 (1) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 99 | /* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */ |
| 100 | #define ANOMALY_05000367 (__SILICON_REVISION__ < 1) |
Mike Frysinger | 7cc1c4b | 2007-12-24 20:05:09 +0800 | [diff] [blame] | 101 | /* Addressing Conflict between Boot ROM and Asynchronous Memory */ |
| 102 | #define ANOMALY_05000369 (1) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 103 | /* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */ |
| 104 | #define ANOMALY_05000370 (__SILICON_REVISION__ < 1) |
Mike Frysinger | a70ce07 | 2008-05-31 15:47:17 +0800 | [diff] [blame] | 105 | /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 106 | #define ANOMALY_05000371 (__SILICON_REVISION__ < 2) |
| 107 | /* USB DP/DM Data Pins May Lose State When Entering Hibernate */ |
| 108 | #define ANOMALY_05000372 (__SILICON_REVISION__ < 1) |
Mike Frysinger | 7cc1c4b | 2007-12-24 20:05:09 +0800 | [diff] [blame] | 109 | /* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */ |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 110 | #define ANOMALY_05000378 (__SILICON_REVISION__ < 2) |
| 111 | /* 16-Bit NAND FLASH Boot Mode Is Not Functional */ |
| 112 | #define ANOMALY_05000379 (1) |
| 113 | /* 8-Bit NAND Flash Boot Mode Not Functional */ |
| 114 | #define ANOMALY_05000382 (__SILICON_REVISION__ < 1) |
| 115 | /* Some ATAPI Modes Are Not Functional */ |
| 116 | #define ANOMALY_05000383 (1) |
| 117 | /* Boot from OTP Memory Not Functional */ |
| 118 | #define ANOMALY_05000385 (__SILICON_REVISION__ < 1) |
| 119 | /* bfrom_SysControl() Firmware Routine Not Functional */ |
| 120 | #define ANOMALY_05000386 (__SILICON_REVISION__ < 1) |
| 121 | /* Programmable Preboot Settings Not Functional */ |
| 122 | #define ANOMALY_05000387 (__SILICON_REVISION__ < 1) |
| 123 | /* CRC32 Checksum Support Not Functional */ |
| 124 | #define ANOMALY_05000388 (__SILICON_REVISION__ < 1) |
| 125 | /* Reset Vector Must Not Be in SDRAM Memory Space */ |
| 126 | #define ANOMALY_05000389 (__SILICON_REVISION__ < 1) |
| 127 | /* Changed Meaning of BCODE Field in SYSCR Register */ |
| 128 | #define ANOMALY_05000390 (__SILICON_REVISION__ < 1) |
| 129 | /* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */ |
| 130 | #define ANOMALY_05000391 (__SILICON_REVISION__ < 1) |
| 131 | /* pTempCurrent Not Present in ADI_BOOT_DATA Structure */ |
| 132 | #define ANOMALY_05000392 (__SILICON_REVISION__ < 1) |
| 133 | /* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */ |
| 134 | #define ANOMALY_05000393 (__SILICON_REVISION__ < 1) |
| 135 | /* Log Buffer Not Functional */ |
| 136 | #define ANOMALY_05000394 (__SILICON_REVISION__ < 1) |
| 137 | /* Hook Routine Not Functional */ |
| 138 | #define ANOMALY_05000395 (__SILICON_REVISION__ < 1) |
| 139 | /* Header Indirect Bit Not Functional */ |
| 140 | #define ANOMALY_05000396 (__SILICON_REVISION__ < 1) |
| 141 | /* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */ |
| 142 | #define ANOMALY_05000397 (__SILICON_REVISION__ < 1) |
| 143 | /* Lockbox SESR Disallows Certain User Interrupts */ |
| 144 | #define ANOMALY_05000404 (__SILICON_REVISION__ < 2) |
| 145 | /* Lockbox SESR Firmware Does Not Save/Restore Full Context */ |
| 146 | #define ANOMALY_05000405 (1) |
| 147 | /* Lockbox SESR Argument Checking Does Not Check L2 Memory Protection Range */ |
| 148 | #define ANOMALY_05000406 (__SILICON_REVISION__ < 2) |
| 149 | /* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */ |
| 150 | #define ANOMALY_05000407 (__SILICON_REVISION__ < 2) |
| 151 | /* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */ |
| 152 | #define ANOMALY_05000408 (1) |
| 153 | /* Lockbox firmware leaves MDMA0 channel enabled */ |
| 154 | #define ANOMALY_05000409 (__SILICON_REVISION__ < 2) |
| 155 | /* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */ |
| 156 | #define ANOMALY_05000411 (__SILICON_REVISION__ < 2) |
| 157 | /* NAND Boot Mode Not Compatible With Some NAND Flash Devices */ |
| 158 | #define ANOMALY_05000413 (__SILICON_REVISION__ < 2) |
| 159 | /* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */ |
| 160 | #define ANOMALY_05000414 (__SILICON_REVISION__ < 2) |
| 161 | /* Speculative Fetches Can Cause Undesired External FIFO Operations */ |
| 162 | #define ANOMALY_05000416 (1) |
| 163 | /* Multichannel SPORT Channel Misalignment Under Specific Configuration */ |
| 164 | #define ANOMALY_05000425 (1) |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 165 | /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 166 | #define ANOMALY_05000426 (1) |
| 167 | /* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */ |
| 168 | #define ANOMALY_05000427 (__SILICON_REVISION__ < 2) |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 169 | /* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */ |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 170 | #define ANOMALY_05000429 (__SILICON_REVISION__ < 2) |
| 171 | /* Software System Reset Corrupts PLL_LOCKCNT Register */ |
| 172 | #define ANOMALY_05000430 (__SILICON_REVISION__ >= 2) |
Mike Frysinger | c18e99c | 2009-03-04 17:36:49 +0800 | [diff] [blame] | 173 | /* Incorrect Use of Stack in Lockbox Firmware During Authentication */ |
| 174 | #define ANOMALY_05000431 (__SILICON_REVISION__ < 3) |
Yi Li | bd411b1 | 2009-08-05 10:02:14 +0000 | [diff] [blame] | 175 | /* SW Breakpoints Ignored Upon Return From Lockbox Authentication */ |
| 176 | #define ANOMALY_05000434 (1) |
Mike Frysinger | c18e99c | 2009-03-04 17:36:49 +0800 | [diff] [blame] | 177 | /* OTP Write Accesses Not Supported */ |
| 178 | #define ANOMALY_05000442 (__SILICON_REVISION__ < 1) |
Mike Frysinger | 3529e041 | 2008-10-28 16:22:41 +0800 | [diff] [blame] | 179 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ |
| 180 | #define ANOMALY_05000443 (1) |
Mike Frysinger | c18e99c | 2009-03-04 17:36:49 +0800 | [diff] [blame] | 181 | /* CDMAPRIO and L2DMAPRIO Bits in the SYSCR Register Are Not Functional */ |
| 182 | #define ANOMALY_05000446 (1) |
| 183 | /* UART IrDA Receiver Fails on Extended Bit Pulses */ |
| 184 | #define ANOMALY_05000447 (1) |
| 185 | /* DDR Clock Duty Cycle Spec Violation (tCH, tCL) */ |
| 186 | #define ANOMALY_05000448 (__SILICON_REVISION__ == 1) |
| 187 | /* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */ |
| 188 | #define ANOMALY_05000449 (__SILICON_REVISION__ == 1) |
| 189 | /* USB DMA Mode 1 Short Packet Data Corruption */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 190 | #define ANOMALY_05000450 (1) |
Yi Li | bd411b1 | 2009-08-05 10:02:14 +0000 | [diff] [blame] | 191 | /* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */ |
| 192 | #define ANOMALY_05000452 (__SILICON_REVISION__ < 1) |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 193 | /* USB Receive Interrupt Is Not Generated in DMA Mode 1 */ |
Yi Li | bd411b1 | 2009-08-05 10:02:14 +0000 | [diff] [blame] | 194 | #define ANOMALY_05000456 (1) |
| 195 | /* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */ |
| 196 | #define ANOMALY_05000457 (1) |
| 197 | /* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */ |
| 198 | #define ANOMALY_05000460 (1) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 199 | /* False Hardware Error when RETI Points to Invalid Memory */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 200 | #define ANOMALY_05000461 (1) |
Yi Li | bd411b1 | 2009-08-05 10:02:14 +0000 | [diff] [blame] | 201 | /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ |
| 202 | #define ANOMALY_05000462 (1) |
| 203 | /* USB DMA RX Data Corruption */ |
| 204 | #define ANOMALY_05000463 (1) |
| 205 | /* USB TX DMA Hang */ |
| 206 | #define ANOMALY_05000464 (1) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 207 | /* USB Rx DMA hang */ |
| 208 | #define ANOMALY_05000465 (1) |
Yi Li | bd411b1 | 2009-08-05 10:02:14 +0000 | [diff] [blame] | 209 | /* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */ |
| 210 | #define ANOMALY_05000466 (1) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 211 | /* Possible RX data corruption when control & data EP FIFOs are accessed via the core */ |
| 212 | #define ANOMALY_05000467 (1) |
Mike Frysinger | af5d7fc | 2009-11-15 18:18:41 -0500 | [diff] [blame] | 213 | /* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ |
| 214 | #define ANOMALY_05000473 (1) |
| 215 | /* Access to DDR-SDRAM causes system hang under certain PLL/VR settings */ |
| 216 | #define ANOMALY_05000474 (1) |
Mike Frysinger | af5d7fc | 2009-11-15 18:18:41 -0500 | [diff] [blame] | 217 | /* TESTSET Instruction Cannot Be Interrupted */ |
| 218 | #define ANOMALY_05000477 (1) |
Mike Frysinger | dc7101b | 2010-05-27 21:47:31 +0000 | [diff] [blame] | 219 | /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ |
| 220 | #define ANOMALY_05000481 (1) |
| 221 | /* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */ |
| 222 | #define ANOMALY_05000483 (1) |
| 223 | /* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */ |
| 224 | #define ANOMALY_05000485 (__SILICON_REVISION__ >= 2) |
| 225 | /* IFLUSH sucks at life */ |
| 226 | #define ANOMALY_05000491 (1) |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 227 | |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 228 | /* Anomalies that don't exist on this proc */ |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 229 | #define ANOMALY_05000099 (0) |
| 230 | #define ANOMALY_05000120 (0) |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 231 | #define ANOMALY_05000125 (0) |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 232 | #define ANOMALY_05000149 (0) |
Bryan Wu | 2cbfe10 | 2007-08-05 15:31:16 +0800 | [diff] [blame] | 233 | #define ANOMALY_05000158 (0) |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 234 | #define ANOMALY_05000171 (0) |
| 235 | #define ANOMALY_05000179 (0) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 236 | #define ANOMALY_05000182 (0) |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 237 | #define ANOMALY_05000183 (0) |
Graf Yang | 976119b | 2009-07-01 07:05:40 +0000 | [diff] [blame] | 238 | #define ANOMALY_05000189 (0) |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 239 | #define ANOMALY_05000198 (0) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 240 | #define ANOMALY_05000202 (0) |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 241 | #define ANOMALY_05000215 (0) |
Mike Frysinger | dc7101b | 2010-05-27 21:47:31 +0000 | [diff] [blame] | 242 | #define ANOMALY_05000219 (0) |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 243 | #define ANOMALY_05000227 (0) |
Mike Frysinger | 0174dd5 | 2007-08-05 16:53:10 +0800 | [diff] [blame] | 244 | #define ANOMALY_05000230 (0) |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 245 | #define ANOMALY_05000231 (0) |
| 246 | #define ANOMALY_05000233 (0) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 247 | #define ANOMALY_05000234 (0) |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 248 | #define ANOMALY_05000242 (0) |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 249 | #define ANOMALY_05000244 (0) |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 250 | #define ANOMALY_05000248 (0) |
| 251 | #define ANOMALY_05000250 (0) |
| 252 | #define ANOMALY_05000254 (0) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 253 | #define ANOMALY_05000257 (0) |
Mike Frysinger | 60e9356 | 2007-07-25 11:56:01 +0800 | [diff] [blame] | 254 | #define ANOMALY_05000261 (0) |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 255 | #define ANOMALY_05000263 (0) |
| 256 | #define ANOMALY_05000266 (0) |
| 257 | #define ANOMALY_05000273 (0) |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 258 | #define ANOMALY_05000274 (0) |
Mike Frysinger | ee554be | 2009-03-03 16:52:55 +0800 | [diff] [blame] | 259 | #define ANOMALY_05000278 (0) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 260 | #define ANOMALY_05000283 (0) |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 261 | #define ANOMALY_05000287 (0) |
| 262 | #define ANOMALY_05000301 (0) |
Mike Frysinger | c18e99c | 2009-03-04 17:36:49 +0800 | [diff] [blame] | 263 | #define ANOMALY_05000305 (0) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 264 | #define ANOMALY_05000307 (0) |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 265 | #define ANOMALY_05000311 (0) |
Mike Frysinger | a200ad2 | 2009-06-13 06:37:14 -0400 | [diff] [blame] | 266 | #define ANOMALY_05000315 (0) |
Michael Hennerich | 2b39331 | 2007-10-10 16:58:49 +0800 | [diff] [blame] | 267 | #define ANOMALY_05000323 (0) |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 268 | #define ANOMALY_05000362 (1) |
Sonic Zhang | 4d55563 | 2008-04-25 03:28:10 +0800 | [diff] [blame] | 269 | #define ANOMALY_05000363 (0) |
Graf Yang | 976119b | 2009-07-01 07:05:40 +0000 | [diff] [blame] | 270 | #define ANOMALY_05000364 (0) |
Bryan Wu | 1c302b6 | 2009-02-04 16:49:45 +0800 | [diff] [blame] | 271 | #define ANOMALY_05000380 (0) |
Mike Frysinger | a413647 | 2009-05-08 07:40:25 +0000 | [diff] [blame] | 272 | #define ANOMALY_05000400 (0) |
Yi Li | bd411b1 | 2009-08-05 10:02:14 +0000 | [diff] [blame] | 273 | #define ANOMALY_05000402 (0) |
Mike Frysinger | 6651ece | 2009-01-07 23:14:38 +0800 | [diff] [blame] | 274 | #define ANOMALY_05000412 (0) |
| 275 | #define ANOMALY_05000432 (0) |
Mike Frysinger | 94b2821 | 2008-11-18 17:48:21 +0800 | [diff] [blame] | 276 | #define ANOMALY_05000435 (0) |
Mike Frysinger | dc7101b | 2010-05-27 21:47:31 +0000 | [diff] [blame] | 277 | #define ANOMALY_05000475 (0) |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 278 | |
| 279 | #endif |