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Kukjin Kim3109e552010-09-01 15:35:30 +09001/* linux/arch/arm/mach-s5p64x0/clock-s5p6450.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P6450 - Clock support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/list.h>
17#include <linux/errno.h>
18#include <linux/err.h>
19#include <linux/clk.h>
20#include <linux/sysdev.h>
21#include <linux/io.h>
22
23#include <mach/hardware.h>
24#include <mach/map.h>
25#include <mach/regs-clock.h>
26#include <mach/s5p64x0-clock.h>
27
28#include <plat/cpu-freq.h>
29#include <plat/clock.h>
30#include <plat/cpu.h>
31#include <plat/pll.h>
32#include <plat/s5p-clock.h>
33#include <plat/clock-clksrc.h>
34#include <plat/s5p6450.h>
35
36static struct clksrc_clk clk_mout_dpll = {
37 .clk = {
38 .name = "mout_dpll",
Kukjin Kim3109e552010-09-01 15:35:30 +090039 },
40 .sources = &clk_src_dpll,
41 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 5, .size = 1 },
42};
43
44static u32 epll_div[][5] = {
45 { 133000000, 27307, 55, 2, 2 },
46 { 100000000, 43691, 41, 2, 2 },
47 { 480000000, 0, 80, 2, 0 },
48};
49
50static int s5p6450_epll_set_rate(struct clk *clk, unsigned long rate)
51{
52 unsigned int epll_con, epll_con_k;
53 unsigned int i;
54
55 if (clk->rate == rate) /* Return if nothing changed */
56 return 0;
57
58 epll_con = __raw_readl(S5P64X0_EPLL_CON);
59 epll_con_k = __raw_readl(S5P64X0_EPLL_CON_K);
60
61 epll_con_k &= ~(PLL90XX_KDIV_MASK);
62 epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);
63
64 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
65 if (epll_div[i][0] == rate) {
66 epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
67 epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
68 (epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
69 (epll_div[i][4] << PLL90XX_SDIV_SHIFT);
70 break;
71 }
72 }
73
74 if (i == ARRAY_SIZE(epll_div)) {
75 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
76 return -EINVAL;
77 }
78
79 __raw_writel(epll_con, S5P64X0_EPLL_CON);
80 __raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);
81
Seungwhan Youn96166742010-10-14 10:39:33 +090082 printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
83 clk->rate, rate);
84
Kukjin Kim3109e552010-09-01 15:35:30 +090085 clk->rate = rate;
86
87 return 0;
88}
89
90static struct clk_ops s5p6450_epll_ops = {
Seungwhan Yound4b34c62010-10-14 10:39:08 +090091 .get_rate = s5p_epll_get_rate,
Kukjin Kim3109e552010-09-01 15:35:30 +090092 .set_rate = s5p6450_epll_set_rate,
93};
94
95static struct clksrc_clk clk_dout_epll = {
96 .clk = {
97 .name = "dout_epll",
Kukjin Kim3109e552010-09-01 15:35:30 +090098 .parent = &clk_mout_epll.clk,
99 },
100 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 24, .size = 4 },
101};
102
103static struct clksrc_clk clk_mout_hclk_sel = {
104 .clk = {
105 .name = "mout_hclk_sel",
Kukjin Kim3109e552010-09-01 15:35:30 +0900106 },
107 .sources = &clkset_hclk_low,
108 .reg_src = { .reg = S5P64X0_OTHERS, .shift = 15, .size = 1 },
109};
110
111static struct clk *clkset_hclk_list[] = {
112 &clk_mout_hclk_sel.clk,
113 &clk_armclk.clk,
114};
115
116static struct clksrc_sources clkset_hclk = {
117 .sources = clkset_hclk_list,
118 .nr_sources = ARRAY_SIZE(clkset_hclk_list),
119};
120
121static struct clksrc_clk clk_hclk = {
122 .clk = {
123 .name = "clk_hclk",
Kukjin Kim3109e552010-09-01 15:35:30 +0900124 },
125 .sources = &clkset_hclk,
126 .reg_src = { .reg = S5P64X0_OTHERS, .shift = 14, .size = 1 },
127 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
128};
129
130static struct clksrc_clk clk_pclk = {
131 .clk = {
132 .name = "clk_pclk",
Kukjin Kim3109e552010-09-01 15:35:30 +0900133 .parent = &clk_hclk.clk,
134 },
135 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
136};
137static struct clksrc_clk clk_dout_pwm_ratio0 = {
138 .clk = {
139 .name = "clk_dout_pwm_ratio0",
Kukjin Kim3109e552010-09-01 15:35:30 +0900140 .parent = &clk_mout_hclk_sel.clk,
141 },
142 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 16, .size = 4 },
143};
144
145static struct clksrc_clk clk_pclk_to_wdt_pwm = {
146 .clk = {
147 .name = "clk_pclk_to_wdt_pwm",
Kukjin Kim3109e552010-09-01 15:35:30 +0900148 .parent = &clk_dout_pwm_ratio0.clk,
149 },
150 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 20, .size = 4 },
151};
152
153static struct clksrc_clk clk_hclk_low = {
154 .clk = {
155 .name = "clk_hclk_low",
Kukjin Kim3109e552010-09-01 15:35:30 +0900156 },
157 .sources = &clkset_hclk_low,
158 .reg_src = { .reg = S5P64X0_OTHERS, .shift = 6, .size = 1 },
159 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 },
160};
161
162static struct clksrc_clk clk_pclk_low = {
163 .clk = {
164 .name = "clk_pclk_low",
Kukjin Kim3109e552010-09-01 15:35:30 +0900165 .parent = &clk_hclk_low.clk,
166 },
167 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
168};
169
170/*
171 * The following clocks will be disabled during clock initialization. It is
172 * recommended to keep the following clocks disabled until the driver requests
173 * for enabling the clock.
174 */
Kukjin Kim15266312011-01-04 18:14:00 +0900175static struct clk init_clocks_off[] = {
Kukjin Kim3109e552010-09-01 15:35:30 +0900176 {
177 .name = "usbhost",
Kukjin Kim3109e552010-09-01 15:35:30 +0900178 .parent = &clk_hclk_low.clk,
179 .enable = s5p64x0_hclk0_ctrl,
180 .ctrlbit = (1 << 3),
181 }, {
Boojin Kim3091e612011-09-02 09:44:39 +0900182 .name = "dma",
Boojin Kim2213d0c2011-08-18 19:24:55 +0900183 .devname = "dma-pl330",
Seungwhan Younb05d8532010-10-19 18:13:11 +0900184 .parent = &clk_hclk_low.clk,
185 .enable = s5p64x0_hclk0_ctrl,
186 .ctrlbit = (1 << 12),
187 }, {
Kukjin Kim3109e552010-09-01 15:35:30 +0900188 .name = "hsmmc",
Thomas Abrahamd8b22d22011-06-14 19:12:27 +0900189 .devname = "s3c-sdhci.0",
Kukjin Kim3109e552010-09-01 15:35:30 +0900190 .parent = &clk_hclk_low.clk,
191 .enable = s5p64x0_hclk0_ctrl,
192 .ctrlbit = (1 << 17),
193 }, {
194 .name = "hsmmc",
Thomas Abrahamd8b22d22011-06-14 19:12:27 +0900195 .devname = "s3c-sdhci.1",
Kukjin Kim3109e552010-09-01 15:35:30 +0900196 .parent = &clk_hclk_low.clk,
197 .enable = s5p64x0_hclk0_ctrl,
198 .ctrlbit = (1 << 18),
199 }, {
200 .name = "hsmmc",
Thomas Abrahamd8b22d22011-06-14 19:12:27 +0900201 .devname = "s3c-sdhci.2",
Kukjin Kim3109e552010-09-01 15:35:30 +0900202 .parent = &clk_hclk_low.clk,
203 .enable = s5p64x0_hclk0_ctrl,
204 .ctrlbit = (1 << 19),
205 }, {
206 .name = "usbotg",
Kukjin Kim3109e552010-09-01 15:35:30 +0900207 .parent = &clk_hclk_low.clk,
208 .enable = s5p64x0_hclk0_ctrl,
209 .ctrlbit = (1 << 20),
210 }, {
211 .name = "lcd",
Kukjin Kim3109e552010-09-01 15:35:30 +0900212 .parent = &clk_h,
213 .enable = s5p64x0_hclk1_ctrl,
214 .ctrlbit = (1 << 1),
215 }, {
216 .name = "watchdog",
Kukjin Kim3109e552010-09-01 15:35:30 +0900217 .parent = &clk_pclk_low.clk,
218 .enable = s5p64x0_pclk_ctrl,
219 .ctrlbit = (1 << 5),
220 }, {
Atul Dahiya232d1002010-12-02 13:36:12 +0900221 .name = "rtc",
Atul Dahiya232d1002010-12-02 13:36:12 +0900222 .parent = &clk_pclk_low.clk,
223 .enable = s5p64x0_pclk_ctrl,
224 .ctrlbit = (1 << 6),
225 }, {
Kukjin Kim3109e552010-09-01 15:35:30 +0900226 .name = "adc",
Kukjin Kim3109e552010-09-01 15:35:30 +0900227 .parent = &clk_pclk_low.clk,
228 .enable = s5p64x0_pclk_ctrl,
229 .ctrlbit = (1 << 12),
230 }, {
231 .name = "i2c",
Thomas Abrahamd8b22d22011-06-14 19:12:27 +0900232 .devname = "s3c2440-i2c.0",
Kukjin Kim3109e552010-09-01 15:35:30 +0900233 .parent = &clk_pclk_low.clk,
234 .enable = s5p64x0_pclk_ctrl,
235 .ctrlbit = (1 << 17),
236 }, {
237 .name = "spi",
Thomas Abrahamd8b22d22011-06-14 19:12:27 +0900238 .devname = "s3c64xx-spi.0",
Kukjin Kim3109e552010-09-01 15:35:30 +0900239 .parent = &clk_pclk_low.clk,
240 .enable = s5p64x0_pclk_ctrl,
241 .ctrlbit = (1 << 21),
242 }, {
243 .name = "spi",
Thomas Abrahamd8b22d22011-06-14 19:12:27 +0900244 .devname = "s3c64xx-spi.1",
Kukjin Kim3109e552010-09-01 15:35:30 +0900245 .parent = &clk_pclk_low.clk,
246 .enable = s5p64x0_pclk_ctrl,
247 .ctrlbit = (1 << 22),
248 }, {
249 .name = "iis",
Thomas Abrahamd8b22d22011-06-14 19:12:27 +0900250 .devname = "samsung-i2s.0",
Kukjin Kim3109e552010-09-01 15:35:30 +0900251 .parent = &clk_pclk_low.clk,
252 .enable = s5p64x0_pclk_ctrl,
253 .ctrlbit = (1 << 26),
254 }, {
Jassi Brar6cb26da2010-12-21 09:44:36 +0900255 .name = "iis",
Thomas Abrahamd8b22d22011-06-14 19:12:27 +0900256 .devname = "samsung-i2s.1",
Jassi Brar6cb26da2010-12-21 09:44:36 +0900257 .parent = &clk_pclk_low.clk,
258 .enable = s5p64x0_pclk_ctrl,
259 .ctrlbit = (1 << 15),
260 }, {
261 .name = "iis",
Thomas Abrahamd8b22d22011-06-14 19:12:27 +0900262 .devname = "samsung-i2s.2",
Jassi Brar6cb26da2010-12-21 09:44:36 +0900263 .parent = &clk_pclk_low.clk,
264 .enable = s5p64x0_pclk_ctrl,
265 .ctrlbit = (1 << 16),
266 }, {
Kukjin Kim3109e552010-09-01 15:35:30 +0900267 .name = "i2c",
Thomas Abrahamd8b22d22011-06-14 19:12:27 +0900268 .devname = "s3c2440-i2c.1",
Kukjin Kim3109e552010-09-01 15:35:30 +0900269 .parent = &clk_pclk_low.clk,
270 .enable = s5p64x0_pclk_ctrl,
271 .ctrlbit = (1 << 27),
272 }, {
273 .name = "dmc0",
Kukjin Kim3109e552010-09-01 15:35:30 +0900274 .parent = &clk_pclk.clk,
275 .enable = s5p64x0_pclk_ctrl,
276 .ctrlbit = (1 << 30),
277 }
278};
279
280/*
281 * The following clocks will be enabled during clock initialization.
282 */
283static struct clk init_clocks[] = {
284 {
285 .name = "intc",
Kukjin Kim3109e552010-09-01 15:35:30 +0900286 .parent = &clk_hclk.clk,
287 .enable = s5p64x0_hclk0_ctrl,
288 .ctrlbit = (1 << 1),
289 }, {
290 .name = "mem",
Kukjin Kim3109e552010-09-01 15:35:30 +0900291 .parent = &clk_hclk.clk,
292 .enable = s5p64x0_hclk0_ctrl,
293 .ctrlbit = (1 << 21),
294 }, {
Kukjin Kim3109e552010-09-01 15:35:30 +0900295 .name = "uart",
Thomas Abrahamd8b22d22011-06-14 19:12:27 +0900296 .devname = "s3c6400-uart.0",
Kukjin Kim3109e552010-09-01 15:35:30 +0900297 .parent = &clk_pclk_low.clk,
298 .enable = s5p64x0_pclk_ctrl,
299 .ctrlbit = (1 << 1),
300 }, {
301 .name = "uart",
Thomas Abrahamd8b22d22011-06-14 19:12:27 +0900302 .devname = "s3c6400-uart.1",
Kukjin Kim3109e552010-09-01 15:35:30 +0900303 .parent = &clk_pclk_low.clk,
304 .enable = s5p64x0_pclk_ctrl,
305 .ctrlbit = (1 << 2),
306 }, {
307 .name = "uart",
Thomas Abrahamd8b22d22011-06-14 19:12:27 +0900308 .devname = "s3c6400-uart.2",
Kukjin Kim3109e552010-09-01 15:35:30 +0900309 .parent = &clk_pclk_low.clk,
310 .enable = s5p64x0_pclk_ctrl,
311 .ctrlbit = (1 << 3),
312 }, {
313 .name = "uart",
Thomas Abrahamd8b22d22011-06-14 19:12:27 +0900314 .devname = "s3c6400-uart.3",
Kukjin Kim3109e552010-09-01 15:35:30 +0900315 .parent = &clk_pclk_low.clk,
316 .enable = s5p64x0_pclk_ctrl,
317 .ctrlbit = (1 << 4),
318 }, {
319 .name = "timers",
Kukjin Kim3109e552010-09-01 15:35:30 +0900320 .parent = &clk_pclk_to_wdt_pwm.clk,
321 .enable = s5p64x0_pclk_ctrl,
322 .ctrlbit = (1 << 7),
323 }, {
324 .name = "gpio",
Kukjin Kim3109e552010-09-01 15:35:30 +0900325 .parent = &clk_pclk_low.clk,
326 .enable = s5p64x0_pclk_ctrl,
327 .ctrlbit = (1 << 18),
328 },
329};
330
331static struct clk *clkset_uart_list[] = {
332 &clk_dout_epll.clk,
333 &clk_dout_mpll.clk,
334};
335
336static struct clksrc_sources clkset_uart = {
337 .sources = clkset_uart_list,
338 .nr_sources = ARRAY_SIZE(clkset_uart_list),
339};
340
341static struct clk *clkset_mali_list[] = {
342 &clk_mout_epll.clk,
343 &clk_mout_apll.clk,
344 &clk_mout_mpll.clk,
345};
346
347static struct clksrc_sources clkset_mali = {
348 .sources = clkset_mali_list,
349 .nr_sources = ARRAY_SIZE(clkset_mali_list),
350};
351
352static struct clk *clkset_group2_list[] = {
353 &clk_dout_epll.clk,
354 &clk_dout_mpll.clk,
355 &clk_ext_xtal_mux,
356};
357
358static struct clksrc_sources clkset_group2 = {
359 .sources = clkset_group2_list,
360 .nr_sources = ARRAY_SIZE(clkset_group2_list),
361};
362
363static struct clk *clkset_dispcon_list[] = {
364 &clk_dout_epll.clk,
365 &clk_dout_mpll.clk,
366 &clk_ext_xtal_mux,
367 &clk_mout_dpll.clk,
368};
369
370static struct clksrc_sources clkset_dispcon = {
371 .sources = clkset_dispcon_list,
372 .nr_sources = ARRAY_SIZE(clkset_dispcon_list),
373};
374
375static struct clk *clkset_hsmmc44_list[] = {
376 &clk_dout_epll.clk,
377 &clk_dout_mpll.clk,
378 &clk_ext_xtal_mux,
379 &s5p_clk_27m,
380 &clk_48m,
381};
382
383static struct clksrc_sources clkset_hsmmc44 = {
384 .sources = clkset_hsmmc44_list,
385 .nr_sources = ARRAY_SIZE(clkset_hsmmc44_list),
386};
387
388static struct clk *clkset_sclk_audio0_list[] = {
389 [0] = &clk_dout_epll.clk,
390 [1] = &clk_dout_mpll.clk,
391 [2] = &clk_ext_xtal_mux,
392 [3] = NULL,
393 [4] = NULL,
394};
395
396static struct clksrc_sources clkset_sclk_audio0 = {
397 .sources = clkset_sclk_audio0_list,
398 .nr_sources = ARRAY_SIZE(clkset_sclk_audio0_list),
399};
400
401static struct clksrc_clk clk_sclk_audio0 = {
402 .clk = {
403 .name = "audio-bus",
Kukjin Kim3109e552010-09-01 15:35:30 +0900404 .enable = s5p64x0_sclk_ctrl,
405 .ctrlbit = (1 << 8),
406 .parent = &clk_dout_epll.clk,
407 },
408 .sources = &clkset_sclk_audio0,
409 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 10, .size = 3 },
410 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 8, .size = 4 },
411};
412
413static struct clksrc_clk clksrcs[] = {
414 {
415 .clk = {
416 .name = "sclk_mmc",
Thomas Abrahamd8b22d22011-06-14 19:12:27 +0900417 .devname = "s3c-sdhci.0",
Kukjin Kim3109e552010-09-01 15:35:30 +0900418 .ctrlbit = (1 << 24),
419 .enable = s5p64x0_sclk_ctrl,
420 },
421 .sources = &clkset_group2,
422 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
423 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
424 }, {
425 .clk = {
426 .name = "sclk_mmc",
Thomas Abrahamd8b22d22011-06-14 19:12:27 +0900427 .devname = "s3c-sdhci.1",
Kukjin Kim3109e552010-09-01 15:35:30 +0900428 .ctrlbit = (1 << 25),
429 .enable = s5p64x0_sclk_ctrl,
430 },
431 .sources = &clkset_group2,
432 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
433 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
434 }, {
435 .clk = {
436 .name = "sclk_mmc",
Thomas Abrahamd8b22d22011-06-14 19:12:27 +0900437 .devname = "s3c-sdhci.2",
Kukjin Kim3109e552010-09-01 15:35:30 +0900438 .ctrlbit = (1 << 26),
439 .enable = s5p64x0_sclk_ctrl,
440 },
441 .sources = &clkset_group2,
442 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
443 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
444 }, {
445 .clk = {
Kukjin Kim3109e552010-09-01 15:35:30 +0900446 .name = "sclk_fimc",
Kukjin Kim3109e552010-09-01 15:35:30 +0900447 .ctrlbit = (1 << 10),
448 .enable = s5p64x0_sclk_ctrl,
449 },
450 .sources = &clkset_group2,
451 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 },
452 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 },
453 }, {
454 .clk = {
455 .name = "aclk_mali",
Kukjin Kim3109e552010-09-01 15:35:30 +0900456 .ctrlbit = (1 << 2),
457 .enable = s5p64x0_sclk1_ctrl,
458 },
459 .sources = &clkset_mali,
460 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 },
461 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 },
462 }, {
463 .clk = {
464 .name = "sclk_2d",
Kukjin Kim3109e552010-09-01 15:35:30 +0900465 .ctrlbit = (1 << 12),
466 .enable = s5p64x0_sclk_ctrl,
467 },
468 .sources = &clkset_mali,
469 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 30, .size = 2 },
470 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 20, .size = 4 },
471 }, {
472 .clk = {
473 .name = "sclk_usi",
Kukjin Kim3109e552010-09-01 15:35:30 +0900474 .ctrlbit = (1 << 7),
475 .enable = s5p64x0_sclk_ctrl,
476 },
477 .sources = &clkset_group2,
478 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 10, .size = 2 },
479 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 16, .size = 4 },
480 }, {
481 .clk = {
482 .name = "sclk_camif",
Kukjin Kim3109e552010-09-01 15:35:30 +0900483 .ctrlbit = (1 << 6),
484 .enable = s5p64x0_sclk_ctrl,
485 },
486 .sources = &clkset_group2,
487 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 28, .size = 2 },
488 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 20, .size = 4 },
489 }, {
490 .clk = {
491 .name = "sclk_dispcon",
Kukjin Kim3109e552010-09-01 15:35:30 +0900492 .ctrlbit = (1 << 1),
493 .enable = s5p64x0_sclk1_ctrl,
494 },
495 .sources = &clkset_dispcon,
496 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 4, .size = 2 },
497 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 },
498 }, {
499 .clk = {
500 .name = "sclk_hsmmc44",
Kukjin Kim3109e552010-09-01 15:35:30 +0900501 .ctrlbit = (1 << 30),
502 .enable = s5p64x0_sclk_ctrl,
503 },
504 .sources = &clkset_hsmmc44,
505 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 6, .size = 3 },
506 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 28, .size = 4 },
507 },
508};
509
Thomas Abraham0cfb26e2011-10-24 12:08:42 +0200510static struct clksrc_clk clk_sclk_uclk = {
511 .clk = {
512 .name = "uclk1",
513 .ctrlbit = (1 << 5),
514 .enable = s5p64x0_sclk_ctrl,
515 },
516 .sources = &clkset_uart,
517 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
518 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
519};
520
Padmavathi Vennac5967042011-11-02 20:04:08 +0900521static struct clksrc_clk clk_sclk_spi0 = {
522 .clk = {
523 .name = "sclk_spi",
524 .devname = "s3c64xx-spi.0",
525 .ctrlbit = (1 << 20),
526 .enable = s5p64x0_sclk_ctrl,
527 },
528 .sources = &clkset_group2,
529 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
530 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
531};
532
533static struct clksrc_clk clk_sclk_spi1 = {
534 .clk = {
535 .name = "sclk_spi",
536 .devname = "s3c64xx-spi.1",
537 .ctrlbit = (1 << 21),
538 .enable = s5p64x0_sclk_ctrl,
539 },
540 .sources = &clkset_group2,
541 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
542 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
543};
544
Thomas Abraham0cfb26e2011-10-24 12:08:42 +0200545static struct clksrc_clk *clksrc_cdev[] = {
546 &clk_sclk_uclk,
Padmavathi Vennac5967042011-11-02 20:04:08 +0900547 &clk_sclk_spi0,
548 &clk_sclk_spi1,
Thomas Abraham0cfb26e2011-10-24 12:08:42 +0200549};
550
551static struct clk_lookup s5p6450_clk_lookup[] = {
552 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
553 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
Padmavathi Vennac5967042011-11-02 20:04:08 +0900554 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
555 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
556 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
Thomas Abraham0cfb26e2011-10-24 12:08:42 +0200557};
558
Kukjin Kim3109e552010-09-01 15:35:30 +0900559/* Clock initialization code */
560static struct clksrc_clk *sysclks[] = {
561 &clk_mout_apll,
562 &clk_mout_epll,
563 &clk_dout_epll,
564 &clk_mout_mpll,
565 &clk_dout_mpll,
566 &clk_armclk,
567 &clk_mout_hclk_sel,
568 &clk_dout_pwm_ratio0,
569 &clk_pclk_to_wdt_pwm,
570 &clk_hclk,
571 &clk_pclk,
572 &clk_hclk_low,
573 &clk_pclk_low,
574 &clk_sclk_audio0,
575};
576
Boojin Kim3091e612011-09-02 09:44:39 +0900577static struct clk dummy_apb_pclk = {
578 .name = "apb_pclk",
579 .id = -1,
580};
581
Kukjin Kim3109e552010-09-01 15:35:30 +0900582void __init_or_cpufreq s5p6450_setup_clocks(void)
583{
584 struct clk *xtal_clk;
585
586 unsigned long xtal;
587 unsigned long fclk;
588 unsigned long hclk;
589 unsigned long hclk_low;
590 unsigned long pclk;
591 unsigned long pclk_low;
592
593 unsigned long apll;
594 unsigned long mpll;
595 unsigned long epll;
596 unsigned long dpll;
597 unsigned int ptr;
598
599 /* Set S5P6450 functions for clk_fout_epll */
600
Seungwhan Yound4b34c62010-10-14 10:39:08 +0900601 clk_fout_epll.enable = s5p_epll_enable;
Kukjin Kim3109e552010-09-01 15:35:30 +0900602 clk_fout_epll.ops = &s5p6450_epll_ops;
603
604 clk_48m.enable = s5p64x0_clk48m_ctrl;
605
606 xtal_clk = clk_get(NULL, "ext_xtal");
607 BUG_ON(IS_ERR(xtal_clk));
608
609 xtal = clk_get_rate(xtal_clk);
610 clk_put(xtal_clk);
611
612 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502);
613 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502);
614 epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON),
615 __raw_readl(S5P64X0_EPLL_CON_K));
616 dpll = s5p_get_pll46xx(xtal, __raw_readl(S5P6450_DPLL_CON),
617 __raw_readl(S5P6450_DPLL_CON_K), pll_4650c);
618
619 clk_fout_apll.rate = apll;
620 clk_fout_mpll.rate = mpll;
621 clk_fout_epll.rate = epll;
622 clk_fout_dpll.rate = dpll;
623
624 printk(KERN_INFO "S5P6450: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
625 " E=%ld.%ldMHz, D=%ld.%ldMHz\n",
626 print_mhz(apll), print_mhz(mpll), print_mhz(epll),
627 print_mhz(dpll));
628
629 fclk = clk_get_rate(&clk_armclk.clk);
630 hclk = clk_get_rate(&clk_hclk.clk);
631 pclk = clk_get_rate(&clk_pclk.clk);
632 hclk_low = clk_get_rate(&clk_hclk_low.clk);
633 pclk_low = clk_get_rate(&clk_pclk_low.clk);
634
635 printk(KERN_INFO "S5P6450: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
636 " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
637 print_mhz(hclk), print_mhz(hclk_low),
638 print_mhz(pclk), print_mhz(pclk_low));
639
640 clk_f.rate = fclk;
641 clk_h.rate = hclk;
642 clk_p.rate = pclk;
643
644 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
645 s3c_set_clksrc(&clksrcs[ptr], true);
646}
647
648void __init s5p6450_register_clocks(void)
649{
Kukjin Kim3109e552010-09-01 15:35:30 +0900650 int ptr;
651
652 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
653 s3c_register_clksrc(sysclks[ptr], 1);
654
655 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
656 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
Thomas Abraham0cfb26e2011-10-24 12:08:42 +0200657 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
658 s3c_register_clksrc(clksrc_cdev[ptr], 1);
Kukjin Kim3109e552010-09-01 15:35:30 +0900659
Kukjin Kim15266312011-01-04 18:14:00 +0900660 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
661 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
Thomas Abraham0cfb26e2011-10-24 12:08:42 +0200662 clkdev_add_table(s5p6450_clk_lookup, ARRAY_SIZE(s5p6450_clk_lookup));
Kukjin Kim3109e552010-09-01 15:35:30 +0900663
Boojin Kim3091e612011-09-02 09:44:39 +0900664 s3c24xx_register_clock(&dummy_apb_pclk);
665
Kukjin Kim3109e552010-09-01 15:35:30 +0900666 s3c_pwmclk_init();
667}