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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * lppaca.h
3 * Copyright (C) 2001 Mike Corrigan IBM Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
David Gibson8882a4d2005-11-09 13:38:01 +110019#ifndef _ASM_POWERPC_LPPACA_H
20#define _ASM_POWERPC_LPPACA_H
Arnd Bergmann88ced032005-12-16 22:43:46 +010021#ifdef __KERNEL__
Linus Torvalds1da177e2005-04-16 15:20:36 -070022
23//=============================================================================
24//
25// This control block contains the data that is shared between the
26// hypervisor (PLIC) and the OS.
27//
28//
29//----------------------------------------------------------------------------
30#include <asm/types.h>
31
David Gibson3356bb92006-01-13 10:26:42 +110032/* The Hypervisor barfs if the lppaca crosses a page boundary. A 1k
33 * alignment is sufficient to prevent this */
Bryan O'Sullivanc6b3fea2006-01-17 17:00:05 -080034struct lppaca {
Linus Torvalds1da177e2005-04-16 15:20:36 -070035//=============================================================================
36// CACHE_LINE_1 0x0000 - 0x007F Contains read-only data
37// NOTE: The xDynXyz fields are fields that will be dynamically changed by
38// PLIC when preparing to bring a processor online or when dispatching a
39// virtual processor!
40//=============================================================================
41 u32 desc; // Eye catcher 0xD397D781 x00-x03
42 u16 size; // Size of this struct x04-x05
43 u16 reserved1; // Reserved x06-x07
44 u16 reserved2:14; // Reserved x08-x09
45 u8 shared_proc:1; // Shared processor indicator ...
46 u8 secondary_thread:1; // Secondary thread indicator ...
47 volatile u8 dyn_proc_status:8; // Dynamic Status of this proc x0A-x0A
48 u8 secondary_thread_count; // Secondary thread count x0B-x0B
49 volatile u16 dyn_hv_phys_proc_index;// Dynamic HV Physical Proc Index0C-x0D
50 volatile u16 dyn_hv_log_proc_index;// Dynamic HV Logical Proc Indexx0E-x0F
51 u32 decr_val; // Value for Decr programming x10-x13
52 u32 pmc_val; // Value for PMC regs x14-x17
53 volatile u32 dyn_hw_node_id; // Dynamic Hardware Node id x18-x1B
54 volatile u32 dyn_hw_proc_id; // Dynamic Hardware Proc Id x1C-x1F
55 volatile u32 dyn_pir; // Dynamic ProcIdReg value x20-x23
56 u32 dsei_data; // DSEI data x24-x27
57 u64 sprg3; // SPRG3 value x28-x2F
58 u8 reserved3[80]; // Reserved x30-x7F
59
60//=============================================================================
61// CACHE_LINE_2 0x0080 - 0x00FF Contains local read-write data
62//=============================================================================
63 // This Dword contains a byte for each type of interrupt that can occur.
64 // The IPI is a count while the others are just a binary 1 or 0.
65 union {
66 u64 any_int;
67 struct {
68 u16 reserved; // Reserved - cleared by #mpasmbl
69 u8 xirr_int; // Indicates xXirrValue is valid or Immed IO
70 u8 ipi_cnt; // IPI Count
71 u8 decr_int; // DECR interrupt occurred
72 u8 pdc_int; // PDC interrupt occurred
73 u8 quantum_int; // Interrupt quantum reached
74 u8 old_plic_deferred_ext_int; // Old PLIC has a deferred XIRR pending
75 } fields;
76 } int_dword;
77
78 // Whenever any fields in this Dword are set then PLIC will defer the
79 // processing of external interrupts. Note that PLIC will store the
80 // XIRR directly into the xXirrValue field so that another XIRR will
81 // not be presented until this one clears. The layout of the low
82 // 4-bytes of this Dword is upto SLIC - PLIC just checks whether the
83 // entire Dword is zero or not. A non-zero value in the low order
84 // 2-bytes will result in SLIC being granted the highest thread
85 // priority upon return. A 0 will return to SLIC as medium priority.
86 u64 plic_defer_ints_area; // Entire Dword
87
88 // Used to pass the real SRR0/1 from PLIC to SLIC as well as to
89 // pass the target SRR0/1 from SLIC to PLIC on a SetAsrAndRfid.
90 u64 saved_srr0; // Saved SRR0 x10-x17
91 u64 saved_srr1; // Saved SRR1 x18-x1F
92
93 // Used to pass parms from the OS to PLIC for SetAsrAndRfid
94 u64 saved_gpr3; // Saved GPR3 x20-x27
95 u64 saved_gpr4; // Saved GPR4 x28-x2F
96 u64 saved_gpr5; // Saved GPR5 x30-x37
97
98 u8 reserved4; // Reserved x38-x38
99 u8 cpuctls_task_attrs; // Task attributes for cpuctls x39-x39
100 u8 fpregs_in_use; // FP regs in use x3A-x3A
101 u8 pmcregs_in_use; // PMC regs in use x3B-x3B
102 volatile u32 saved_decr; // Saved Decr Value x3C-x3F
103 volatile u64 emulated_time_base;// Emulated TB for this thread x40-x47
104 volatile u64 cur_plic_latency; // Unaccounted PLIC latency x48-x4F
105 u64 tot_plic_latency; // Accumulated PLIC latency x50-x57
106 u64 wait_state_cycles; // Wait cycles for this proc x58-x5F
107 u64 end_of_quantum; // TB at end of quantum x60-x67
108 u64 pdc_saved_sprg1; // Saved SPRG1 for PMC int x68-x6F
109 u64 pdc_saved_srr0; // Saved SRR0 for PMC int x70-x77
110 volatile u32 virtual_decr; // Virtual DECR for shared procsx78-x7B
111 u16 slb_count; // # of SLBs to maintain x7C-x7D
112 u8 idle; // Indicate OS is idle x7E
Olof Johansson233ccd02005-09-03 15:55:59 -0700113 u8 vmxregs_in_use; // VMX registers in use x7F
Linus Torvalds1da177e2005-04-16 15:20:36 -0700114
115
116//=============================================================================
117// CACHE_LINE_3 0x0100 - 0x007F: This line is shared with other processors
118//=============================================================================
119 // This is the yield_count. An "odd" value (low bit on) means that
120 // the processor is yielded (either because of an OS yield or a PLIC
121 // preempt). An even value implies that the processor is currently
122 // executing.
123 // NOTE: This value will ALWAYS be zero for dedicated processors and
124 // will NEVER be zero for shared processors (ie, initialized to a 1).
125 volatile u32 yield_count; // PLIC increments each dispatchx00-x03
126 u8 reserved6[124]; // Reserved x04-x7F
127
128//=============================================================================
129// CACHE_LINE_4-5 0x0100 - 0x01FF Contains PMC interrupt data
130//=============================================================================
131 u8 pmc_save_area[256]; // PMC interrupt Area x00-xFF
Bryan O'Sullivanc6b3fea2006-01-17 17:00:05 -0800132} __attribute__((__aligned__(0x400)));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700133
David Gibson3356bb92006-01-13 10:26:42 +1100134extern struct lppaca lppaca[];
135
Arnd Bergmann88ced032005-12-16 22:43:46 +0100136#endif /* __KERNEL__ */
David Gibson8882a4d2005-11-09 13:38:01 +1100137#endif /* _ASM_POWERPC_LPPACA_H */