Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1 | /* |
| 2 | * SPI bus driver for the Topcliff PCH used by Intel SoCs |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 3 | * |
Tomoya MORINAGA | 2b24628 | 2011-10-28 09:35:22 +0900 | [diff] [blame] | 4 | * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd. |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. |
| 18 | */ |
| 19 | |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 20 | #include <linux/delay.h> |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 21 | #include <linux/pci.h> |
| 22 | #include <linux/wait.h> |
| 23 | #include <linux/spi/spi.h> |
| 24 | #include <linux/interrupt.h> |
| 25 | #include <linux/sched.h> |
| 26 | #include <linux/spi/spidev.h> |
| 27 | #include <linux/module.h> |
| 28 | #include <linux/device.h> |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 29 | #include <linux/platform_device.h> |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 30 | |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 31 | #include <linux/dmaengine.h> |
| 32 | #include <linux/pch_dma.h> |
| 33 | |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 34 | /* Register offsets */ |
| 35 | #define PCH_SPCR 0x00 /* SPI control register */ |
| 36 | #define PCH_SPBRR 0x04 /* SPI baud rate register */ |
| 37 | #define PCH_SPSR 0x08 /* SPI status register */ |
| 38 | #define PCH_SPDWR 0x0C /* SPI write data register */ |
| 39 | #define PCH_SPDRR 0x10 /* SPI read data register */ |
| 40 | #define PCH_SSNXCR 0x18 /* SSN Expand Control Register */ |
| 41 | #define PCH_SRST 0x1C /* SPI reset register */ |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 42 | #define PCH_ADDRESS_SIZE 0x20 |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 43 | |
| 44 | #define PCH_SPSR_TFD 0x000007C0 |
| 45 | #define PCH_SPSR_RFD 0x0000F800 |
| 46 | |
| 47 | #define PCH_READABLE(x) (((x) & PCH_SPSR_RFD)>>11) |
| 48 | #define PCH_WRITABLE(x) (((x) & PCH_SPSR_TFD)>>6) |
| 49 | |
| 50 | #define PCH_RX_THOLD 7 |
| 51 | #define PCH_RX_THOLD_MAX 15 |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 52 | |
Tomoya MORINAGA | f3e03e2e | 2011-09-06 17:16:38 +0900 | [diff] [blame] | 53 | #define PCH_TX_THOLD 2 |
| 54 | |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 55 | #define PCH_MAX_BAUDRATE 5000000 |
| 56 | #define PCH_MAX_FIFO_DEPTH 16 |
| 57 | |
| 58 | #define STATUS_RUNNING 1 |
| 59 | #define STATUS_EXITING 2 |
| 60 | #define PCH_SLEEP_TIME 10 |
| 61 | |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 62 | #define SSN_LOW 0x02U |
Tomoya MORINAGA | 8b7aa96 | 2011-09-06 17:16:35 +0900 | [diff] [blame] | 63 | #define SSN_HIGH 0x03U |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 64 | #define SSN_NO_CONTROL 0x00U |
| 65 | #define PCH_MAX_CS 0xFF |
| 66 | #define PCI_DEVICE_ID_GE_SPI 0x8816 |
| 67 | |
| 68 | #define SPCR_SPE_BIT (1 << 0) |
| 69 | #define SPCR_MSTR_BIT (1 << 1) |
| 70 | #define SPCR_LSBF_BIT (1 << 4) |
| 71 | #define SPCR_CPHA_BIT (1 << 5) |
| 72 | #define SPCR_CPOL_BIT (1 << 6) |
| 73 | #define SPCR_TFIE_BIT (1 << 8) |
| 74 | #define SPCR_RFIE_BIT (1 << 9) |
| 75 | #define SPCR_FIE_BIT (1 << 10) |
| 76 | #define SPCR_ORIE_BIT (1 << 11) |
| 77 | #define SPCR_MDFIE_BIT (1 << 12) |
| 78 | #define SPCR_FICLR_BIT (1 << 24) |
| 79 | #define SPSR_TFI_BIT (1 << 0) |
| 80 | #define SPSR_RFI_BIT (1 << 1) |
| 81 | #define SPSR_FI_BIT (1 << 2) |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 82 | #define SPSR_ORF_BIT (1 << 3) |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 83 | #define SPBRR_SIZE_BIT (1 << 10) |
| 84 | |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 85 | #define PCH_ALL (SPCR_TFIE_BIT|SPCR_RFIE_BIT|SPCR_FIE_BIT|\ |
| 86 | SPCR_ORIE_BIT|SPCR_MDFIE_BIT) |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 87 | |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 88 | #define SPCR_RFIC_FIELD 20 |
| 89 | #define SPCR_TFIC_FIELD 16 |
| 90 | |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 91 | #define MASK_SPBRR_SPBR_BITS ((1 << 10) - 1) |
| 92 | #define MASK_RFIC_SPCR_BITS (0xf << SPCR_RFIC_FIELD) |
| 93 | #define MASK_TFIC_SPCR_BITS (0xf << SPCR_TFIC_FIELD) |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 94 | |
| 95 | #define PCH_CLOCK_HZ 50000000 |
| 96 | #define PCH_MAX_SPBR 1023 |
| 97 | |
Tomoya MORINAGA | 2b24628 | 2011-10-28 09:35:22 +0900 | [diff] [blame] | 98 | /* Definition for ML7213/ML7223/ML7831 by LAPIS Semiconductor */ |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 99 | #define PCI_VENDOR_ID_ROHM 0x10DB |
| 100 | #define PCI_DEVICE_ID_ML7213_SPI 0x802c |
Tomoya MORINAGA | 2e2de2e | 2011-06-17 09:34:25 +0900 | [diff] [blame] | 101 | #define PCI_DEVICE_ID_ML7223_SPI 0x800F |
Tomoya MORINAGA | 92b3a5c | 2011-10-28 09:35:21 +0900 | [diff] [blame] | 102 | #define PCI_DEVICE_ID_ML7831_SPI 0x8816 |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 103 | |
| 104 | /* |
| 105 | * Set the number of SPI instance max |
| 106 | * Intel EG20T PCH : 1ch |
Tomoya MORINAGA | 2b24628 | 2011-10-28 09:35:22 +0900 | [diff] [blame] | 107 | * LAPIS Semiconductor ML7213 IOH : 2ch |
| 108 | * LAPIS Semiconductor ML7223 IOH : 1ch |
| 109 | * LAPIS Semiconductor ML7831 IOH : 1ch |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 110 | */ |
| 111 | #define PCH_SPI_MAX_DEV 2 |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 112 | |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 113 | #define PCH_BUF_SIZE 4096 |
| 114 | #define PCH_DMA_TRANS_SIZE 12 |
| 115 | |
| 116 | static int use_dma = 1; |
| 117 | |
| 118 | struct pch_spi_dma_ctrl { |
| 119 | struct dma_async_tx_descriptor *desc_tx; |
| 120 | struct dma_async_tx_descriptor *desc_rx; |
| 121 | struct pch_dma_slave param_tx; |
| 122 | struct pch_dma_slave param_rx; |
| 123 | struct dma_chan *chan_tx; |
| 124 | struct dma_chan *chan_rx; |
| 125 | struct scatterlist *sg_tx_p; |
| 126 | struct scatterlist *sg_rx_p; |
| 127 | struct scatterlist sg_tx; |
| 128 | struct scatterlist sg_rx; |
| 129 | int nent; |
| 130 | void *tx_buf_virt; |
| 131 | void *rx_buf_virt; |
| 132 | dma_addr_t tx_buf_dma; |
| 133 | dma_addr_t rx_buf_dma; |
| 134 | }; |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 135 | /** |
| 136 | * struct pch_spi_data - Holds the SPI channel specific details |
| 137 | * @io_remap_addr: The remapped PCI base address |
| 138 | * @master: Pointer to the SPI master structure |
| 139 | * @work: Reference to work queue handler |
| 140 | * @wk: Workqueue for carrying out execution of the |
| 141 | * requests |
| 142 | * @wait: Wait queue for waking up upon receiving an |
| 143 | * interrupt. |
| 144 | * @transfer_complete: Status of SPI Transfer |
| 145 | * @bcurrent_msg_processing: Status flag for message processing |
| 146 | * @lock: Lock for protecting this structure |
| 147 | * @queue: SPI Message queue |
| 148 | * @status: Status of the SPI driver |
| 149 | * @bpw_len: Length of data to be transferred in bits per |
| 150 | * word |
| 151 | * @transfer_active: Flag showing active transfer |
| 152 | * @tx_index: Transmit data count; for bookkeeping during |
| 153 | * transfer |
| 154 | * @rx_index: Receive data count; for bookkeeping during |
| 155 | * transfer |
| 156 | * @tx_buff: Buffer for data to be transmitted |
| 157 | * @rx_index: Buffer for Received data |
| 158 | * @n_curnt_chip: The chip number that this SPI driver currently |
| 159 | * operates on |
| 160 | * @current_chip: Reference to the current chip that this SPI |
| 161 | * driver currently operates on |
| 162 | * @current_msg: The current message that this SPI driver is |
| 163 | * handling |
| 164 | * @cur_trans: The current transfer that this SPI driver is |
| 165 | * handling |
| 166 | * @board_dat: Reference to the SPI device data structure |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 167 | * @plat_dev: platform_device structure |
| 168 | * @ch: SPI channel number |
| 169 | * @irq_reg_sts: Status of IRQ registration |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 170 | */ |
| 171 | struct pch_spi_data { |
| 172 | void __iomem *io_remap_addr; |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 173 | unsigned long io_base_addr; |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 174 | struct spi_master *master; |
| 175 | struct work_struct work; |
| 176 | struct workqueue_struct *wk; |
| 177 | wait_queue_head_t wait; |
| 178 | u8 transfer_complete; |
| 179 | u8 bcurrent_msg_processing; |
| 180 | spinlock_t lock; |
| 181 | struct list_head queue; |
| 182 | u8 status; |
| 183 | u32 bpw_len; |
| 184 | u8 transfer_active; |
| 185 | u32 tx_index; |
| 186 | u32 rx_index; |
| 187 | u16 *pkt_tx_buff; |
| 188 | u16 *pkt_rx_buff; |
| 189 | u8 n_curnt_chip; |
| 190 | struct spi_device *current_chip; |
| 191 | struct spi_message *current_msg; |
| 192 | struct spi_transfer *cur_trans; |
| 193 | struct pch_spi_board_data *board_dat; |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 194 | struct platform_device *plat_dev; |
| 195 | int ch; |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 196 | struct pch_spi_dma_ctrl dma; |
| 197 | int use_dma; |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 198 | u8 irq_reg_sts; |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 199 | }; |
| 200 | |
| 201 | /** |
| 202 | * struct pch_spi_board_data - Holds the SPI device specific details |
| 203 | * @pdev: Pointer to the PCI device |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 204 | * @suspend_sts: Status of suspend |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 205 | * @num: The number of SPI device instance |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 206 | */ |
| 207 | struct pch_spi_board_data { |
| 208 | struct pci_dev *pdev; |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 209 | u8 suspend_sts; |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 210 | int num; |
| 211 | }; |
| 212 | |
| 213 | struct pch_pd_dev_save { |
| 214 | int num; |
| 215 | struct platform_device *pd_save[PCH_SPI_MAX_DEV]; |
| 216 | struct pch_spi_board_data *board_dat; |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 217 | }; |
| 218 | |
| 219 | static struct pci_device_id pch_spi_pcidev_id[] = { |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 220 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_GE_SPI), 1, }, |
| 221 | { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_SPI), 2, }, |
Tomoya MORINAGA | 2e2de2e | 2011-06-17 09:34:25 +0900 | [diff] [blame] | 222 | { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_SPI), 1, }, |
Tomoya MORINAGA | 92b3a5c | 2011-10-28 09:35:21 +0900 | [diff] [blame] | 223 | { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_SPI), 1, }, |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 224 | { } |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 225 | }; |
| 226 | |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 227 | /** |
| 228 | * pch_spi_writereg() - Performs register writes |
| 229 | * @master: Pointer to struct spi_master. |
| 230 | * @idx: Register offset. |
| 231 | * @val: Value to be written to register. |
| 232 | */ |
| 233 | static inline void pch_spi_writereg(struct spi_master *master, int idx, u32 val) |
| 234 | { |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 235 | struct pch_spi_data *data = spi_master_get_devdata(master); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 236 | iowrite32(val, (data->io_remap_addr + idx)); |
| 237 | } |
| 238 | |
| 239 | /** |
| 240 | * pch_spi_readreg() - Performs register reads |
| 241 | * @master: Pointer to struct spi_master. |
| 242 | * @idx: Register offset. |
| 243 | */ |
| 244 | static inline u32 pch_spi_readreg(struct spi_master *master, int idx) |
| 245 | { |
| 246 | struct pch_spi_data *data = spi_master_get_devdata(master); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 247 | return ioread32(data->io_remap_addr + idx); |
| 248 | } |
| 249 | |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 250 | static inline void pch_spi_setclr_reg(struct spi_master *master, int idx, |
| 251 | u32 set, u32 clr) |
| 252 | { |
| 253 | u32 tmp = pch_spi_readreg(master, idx); |
| 254 | tmp = (tmp & ~clr) | set; |
| 255 | pch_spi_writereg(master, idx, tmp); |
| 256 | } |
| 257 | |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 258 | static void pch_spi_set_master_mode(struct spi_master *master) |
| 259 | { |
| 260 | pch_spi_setclr_reg(master, PCH_SPCR, SPCR_MSTR_BIT, 0); |
| 261 | } |
| 262 | |
| 263 | /** |
| 264 | * pch_spi_clear_fifo() - Clears the Transmit and Receive FIFOs |
| 265 | * @master: Pointer to struct spi_master. |
| 266 | */ |
| 267 | static void pch_spi_clear_fifo(struct spi_master *master) |
| 268 | { |
| 269 | pch_spi_setclr_reg(master, PCH_SPCR, SPCR_FICLR_BIT, 0); |
| 270 | pch_spi_setclr_reg(master, PCH_SPCR, 0, SPCR_FICLR_BIT); |
| 271 | } |
| 272 | |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 273 | static void pch_spi_handler_sub(struct pch_spi_data *data, u32 reg_spsr_val, |
| 274 | void __iomem *io_remap_addr) |
| 275 | { |
| 276 | u32 n_read, tx_index, rx_index, bpw_len; |
| 277 | u16 *pkt_rx_buffer, *pkt_tx_buff; |
| 278 | int read_cnt; |
| 279 | u32 reg_spcr_val; |
| 280 | void __iomem *spsr; |
| 281 | void __iomem *spdrr; |
| 282 | void __iomem *spdwr; |
| 283 | |
| 284 | spsr = io_remap_addr + PCH_SPSR; |
| 285 | iowrite32(reg_spsr_val, spsr); |
| 286 | |
| 287 | if (data->transfer_active) { |
| 288 | rx_index = data->rx_index; |
| 289 | tx_index = data->tx_index; |
| 290 | bpw_len = data->bpw_len; |
| 291 | pkt_rx_buffer = data->pkt_rx_buff; |
| 292 | pkt_tx_buff = data->pkt_tx_buff; |
| 293 | |
| 294 | spdrr = io_remap_addr + PCH_SPDRR; |
| 295 | spdwr = io_remap_addr + PCH_SPDWR; |
| 296 | |
| 297 | n_read = PCH_READABLE(reg_spsr_val); |
| 298 | |
| 299 | for (read_cnt = 0; (read_cnt < n_read); read_cnt++) { |
| 300 | pkt_rx_buffer[rx_index++] = ioread32(spdrr); |
| 301 | if (tx_index < bpw_len) |
| 302 | iowrite32(pkt_tx_buff[tx_index++], spdwr); |
| 303 | } |
| 304 | |
| 305 | /* disable RFI if not needed */ |
| 306 | if ((bpw_len - rx_index) <= PCH_MAX_FIFO_DEPTH) { |
| 307 | reg_spcr_val = ioread32(io_remap_addr + PCH_SPCR); |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 308 | reg_spcr_val &= ~SPCR_RFIE_BIT; /* disable RFI */ |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 309 | |
| 310 | /* reset rx threshold */ |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 311 | reg_spcr_val &= ~MASK_RFIC_SPCR_BITS; |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 312 | reg_spcr_val |= (PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD); |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 313 | |
| 314 | iowrite32(reg_spcr_val, (io_remap_addr + PCH_SPCR)); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 315 | } |
| 316 | |
| 317 | /* update counts */ |
| 318 | data->tx_index = tx_index; |
| 319 | data->rx_index = rx_index; |
| 320 | |
| 321 | } |
| 322 | |
| 323 | /* if transfer complete interrupt */ |
| 324 | if (reg_spsr_val & SPSR_FI_BIT) { |
Tomoya MORINAGA | 373b0eb | 2011-09-06 17:16:36 +0900 | [diff] [blame] | 325 | if ((tx_index == bpw_len) && (rx_index == tx_index)) { |
| 326 | /* disable interrupts */ |
| 327 | pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL); |
| 328 | |
| 329 | /* transfer is completed; |
| 330 | inform pch_spi_process_messages */ |
| 331 | data->transfer_complete = true; |
| 332 | data->transfer_active = false; |
| 333 | wake_up(&data->wait); |
| 334 | } else { |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 335 | dev_err(&data->master->dev, |
| 336 | "%s : Transfer is not completed", __func__); |
Tomoya MORINAGA | 373b0eb | 2011-09-06 17:16:36 +0900 | [diff] [blame] | 337 | } |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 338 | } |
| 339 | } |
| 340 | |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 341 | /** |
| 342 | * pch_spi_handler() - Interrupt handler |
| 343 | * @irq: The interrupt number. |
| 344 | * @dev_id: Pointer to struct pch_spi_board_data. |
| 345 | */ |
| 346 | static irqreturn_t pch_spi_handler(int irq, void *dev_id) |
| 347 | { |
| 348 | u32 reg_spsr_val; |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 349 | void __iomem *spsr; |
| 350 | void __iomem *io_remap_addr; |
| 351 | irqreturn_t ret = IRQ_NONE; |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 352 | struct pch_spi_data *data = dev_id; |
| 353 | struct pch_spi_board_data *board_dat = data->board_dat; |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 354 | |
| 355 | if (board_dat->suspend_sts) { |
| 356 | dev_dbg(&board_dat->pdev->dev, |
| 357 | "%s returning due to suspend\n", __func__); |
| 358 | return IRQ_NONE; |
| 359 | } |
| 360 | |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 361 | io_remap_addr = data->io_remap_addr; |
| 362 | spsr = io_remap_addr + PCH_SPSR; |
| 363 | |
| 364 | reg_spsr_val = ioread32(spsr); |
| 365 | |
Tomoya MORINAGA | 25e803f | 2011-09-06 17:16:37 +0900 | [diff] [blame] | 366 | if (reg_spsr_val & SPSR_ORF_BIT) { |
| 367 | dev_err(&board_dat->pdev->dev, "%s Over run error\n", __func__); |
| 368 | if (data->current_msg->complete != 0) { |
| 369 | data->transfer_complete = true; |
| 370 | data->current_msg->status = -EIO; |
| 371 | data->current_msg->complete(data->current_msg->context); |
| 372 | data->bcurrent_msg_processing = false; |
| 373 | data->current_msg = NULL; |
| 374 | data->cur_trans = NULL; |
| 375 | } |
| 376 | } |
| 377 | |
| 378 | if (data->use_dma) |
| 379 | return IRQ_NONE; |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 380 | |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 381 | /* Check if the interrupt is for SPI device */ |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 382 | if (reg_spsr_val & (SPSR_FI_BIT | SPSR_RFI_BIT)) { |
| 383 | pch_spi_handler_sub(data, reg_spsr_val, io_remap_addr); |
| 384 | ret = IRQ_HANDLED; |
| 385 | } |
| 386 | |
| 387 | dev_dbg(&board_dat->pdev->dev, "%s EXIT return value=%d\n", |
| 388 | __func__, ret); |
| 389 | |
| 390 | return ret; |
| 391 | } |
| 392 | |
| 393 | /** |
| 394 | * pch_spi_set_baud_rate() - Sets SPBR field in SPBRR |
| 395 | * @master: Pointer to struct spi_master. |
| 396 | * @speed_hz: Baud rate. |
| 397 | */ |
| 398 | static void pch_spi_set_baud_rate(struct spi_master *master, u32 speed_hz) |
| 399 | { |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 400 | u32 n_spbr = PCH_CLOCK_HZ / (speed_hz * 2); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 401 | |
| 402 | /* if baud rate is less than we can support limit it */ |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 403 | if (n_spbr > PCH_MAX_SPBR) |
| 404 | n_spbr = PCH_MAX_SPBR; |
| 405 | |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 406 | pch_spi_setclr_reg(master, PCH_SPBRR, n_spbr, MASK_SPBRR_SPBR_BITS); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 407 | } |
| 408 | |
| 409 | /** |
| 410 | * pch_spi_set_bits_per_word() - Sets SIZE field in SPBRR |
| 411 | * @master: Pointer to struct spi_master. |
| 412 | * @bits_per_word: Bits per word for SPI transfer. |
| 413 | */ |
| 414 | static void pch_spi_set_bits_per_word(struct spi_master *master, |
| 415 | u8 bits_per_word) |
| 416 | { |
| 417 | if (bits_per_word == 8) |
| 418 | pch_spi_setclr_reg(master, PCH_SPBRR, 0, SPBRR_SIZE_BIT); |
| 419 | else |
| 420 | pch_spi_setclr_reg(master, PCH_SPBRR, SPBRR_SIZE_BIT, 0); |
| 421 | } |
| 422 | |
| 423 | /** |
| 424 | * pch_spi_setup_transfer() - Configures the PCH SPI hardware for transfer |
| 425 | * @spi: Pointer to struct spi_device. |
| 426 | */ |
| 427 | static void pch_spi_setup_transfer(struct spi_device *spi) |
| 428 | { |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 429 | u32 flags = 0; |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 430 | |
| 431 | dev_dbg(&spi->dev, "%s SPBRR content =%x setting baud rate=%d\n", |
| 432 | __func__, pch_spi_readreg(spi->master, PCH_SPBRR), |
| 433 | spi->max_speed_hz); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 434 | pch_spi_set_baud_rate(spi->master, spi->max_speed_hz); |
| 435 | |
| 436 | /* set bits per word */ |
| 437 | pch_spi_set_bits_per_word(spi->master, spi->bits_per_word); |
| 438 | |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 439 | if (!(spi->mode & SPI_LSB_FIRST)) |
| 440 | flags |= SPCR_LSBF_BIT; |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 441 | if (spi->mode & SPI_CPOL) |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 442 | flags |= SPCR_CPOL_BIT; |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 443 | if (spi->mode & SPI_CPHA) |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 444 | flags |= SPCR_CPHA_BIT; |
| 445 | pch_spi_setclr_reg(spi->master, PCH_SPCR, flags, |
| 446 | (SPCR_LSBF_BIT | SPCR_CPOL_BIT | SPCR_CPHA_BIT)); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 447 | |
| 448 | /* Clear the FIFO by toggling FICLR to 1 and back to 0 */ |
| 449 | pch_spi_clear_fifo(spi->master); |
| 450 | } |
| 451 | |
| 452 | /** |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 453 | * pch_spi_reset() - Clears SPI registers |
| 454 | * @master: Pointer to struct spi_master. |
| 455 | */ |
| 456 | static void pch_spi_reset(struct spi_master *master) |
| 457 | { |
| 458 | /* write 1 to reset SPI */ |
| 459 | pch_spi_writereg(master, PCH_SRST, 0x1); |
| 460 | |
| 461 | /* clear reset */ |
| 462 | pch_spi_writereg(master, PCH_SRST, 0x0); |
| 463 | } |
| 464 | |
| 465 | static int pch_spi_setup(struct spi_device *pspi) |
| 466 | { |
| 467 | /* check bits per word */ |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 468 | if (pspi->bits_per_word == 0) { |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 469 | pspi->bits_per_word = 8; |
| 470 | dev_dbg(&pspi->dev, "%s 8 bits per word\n", __func__); |
| 471 | } |
| 472 | |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 473 | if ((pspi->bits_per_word != 8) && (pspi->bits_per_word != 16)) { |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 474 | dev_err(&pspi->dev, "%s Invalid bits per word\n", __func__); |
| 475 | return -EINVAL; |
| 476 | } |
| 477 | |
| 478 | /* Check baud rate setting */ |
| 479 | /* if baud rate of chip is greater than |
| 480 | max we can support,return error */ |
| 481 | if ((pspi->max_speed_hz) > PCH_MAX_BAUDRATE) |
| 482 | pspi->max_speed_hz = PCH_MAX_BAUDRATE; |
| 483 | |
| 484 | dev_dbg(&pspi->dev, "%s MODE = %x\n", __func__, |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 485 | (pspi->mode) & (SPI_CPOL | SPI_CPHA)); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 486 | |
| 487 | return 0; |
| 488 | } |
| 489 | |
| 490 | static int pch_spi_transfer(struct spi_device *pspi, struct spi_message *pmsg) |
| 491 | { |
| 492 | |
| 493 | struct spi_transfer *transfer; |
| 494 | struct pch_spi_data *data = spi_master_get_devdata(pspi->master); |
| 495 | int retval; |
| 496 | unsigned long flags; |
| 497 | |
| 498 | /* validate spi message and baud rate */ |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 499 | if (unlikely(list_empty(&pmsg->transfers) == 1)) { |
| 500 | dev_err(&pspi->dev, "%s list empty\n", __func__); |
| 501 | retval = -EINVAL; |
| 502 | goto err_out; |
| 503 | } |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 504 | |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 505 | if (unlikely(pspi->max_speed_hz == 0)) { |
| 506 | dev_err(&pspi->dev, "%s pch_spi_tranfer maxspeed=%d\n", |
| 507 | __func__, pspi->max_speed_hz); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 508 | retval = -EINVAL; |
| 509 | goto err_out; |
| 510 | } |
| 511 | |
| 512 | dev_dbg(&pspi->dev, "%s Transfer List not empty. " |
| 513 | "Transfer Speed is set.\n", __func__); |
| 514 | |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 515 | spin_lock_irqsave(&data->lock, flags); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 516 | /* validate Tx/Rx buffers and Transfer length */ |
| 517 | list_for_each_entry(transfer, &pmsg->transfers, transfer_list) { |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 518 | if (!transfer->tx_buf && !transfer->rx_buf) { |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 519 | dev_err(&pspi->dev, |
| 520 | "%s Tx and Rx buffer NULL\n", __func__); |
| 521 | retval = -EINVAL; |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 522 | goto err_return_spinlock; |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 523 | } |
| 524 | |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 525 | if (!transfer->len) { |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 526 | dev_err(&pspi->dev, "%s Transfer length invalid\n", |
| 527 | __func__); |
| 528 | retval = -EINVAL; |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 529 | goto err_return_spinlock; |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 530 | } |
| 531 | |
| 532 | dev_dbg(&pspi->dev, "%s Tx/Rx buffer valid. Transfer length" |
| 533 | " valid\n", __func__); |
| 534 | |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 535 | /* if baud rate has been specified validate the same */ |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 536 | if (transfer->speed_hz > PCH_MAX_BAUDRATE) |
| 537 | transfer->speed_hz = PCH_MAX_BAUDRATE; |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 538 | |
| 539 | /* if bits per word has been specified validate the same */ |
| 540 | if (transfer->bits_per_word) { |
| 541 | if ((transfer->bits_per_word != 8) |
| 542 | && (transfer->bits_per_word != 16)) { |
| 543 | retval = -EINVAL; |
| 544 | dev_err(&pspi->dev, |
| 545 | "%s Invalid bits per word\n", __func__); |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 546 | goto err_return_spinlock; |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 547 | } |
| 548 | } |
| 549 | } |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 550 | spin_unlock_irqrestore(&data->lock, flags); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 551 | |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 552 | /* We won't process any messages if we have been asked to terminate */ |
| 553 | if (data->status == STATUS_EXITING) { |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 554 | dev_err(&pspi->dev, "%s status = STATUS_EXITING.\n", __func__); |
| 555 | retval = -ESHUTDOWN; |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 556 | goto err_out; |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 557 | } |
| 558 | |
| 559 | /* If suspended ,return -EINVAL */ |
| 560 | if (data->board_dat->suspend_sts) { |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 561 | dev_err(&pspi->dev, "%s suspend; returning EINVAL\n", __func__); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 562 | retval = -EINVAL; |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 563 | goto err_out; |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 564 | } |
| 565 | |
| 566 | /* set status of message */ |
| 567 | pmsg->actual_length = 0; |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 568 | dev_dbg(&pspi->dev, "%s - pmsg->status =%d\n", __func__, pmsg->status); |
| 569 | |
| 570 | pmsg->status = -EINPROGRESS; |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 571 | spin_lock_irqsave(&data->lock, flags); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 572 | /* add message to queue */ |
| 573 | list_add_tail(&pmsg->queue, &data->queue); |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 574 | spin_unlock_irqrestore(&data->lock, flags); |
| 575 | |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 576 | dev_dbg(&pspi->dev, "%s - Invoked list_add_tail\n", __func__); |
| 577 | |
| 578 | /* schedule work queue to run */ |
| 579 | queue_work(data->wk, &data->work); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 580 | dev_dbg(&pspi->dev, "%s - Invoked queue work\n", __func__); |
| 581 | |
| 582 | retval = 0; |
| 583 | |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 584 | err_out: |
| 585 | dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval); |
| 586 | return retval; |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 587 | err_return_spinlock: |
| 588 | dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval); |
| 589 | spin_unlock_irqrestore(&data->lock, flags); |
| 590 | return retval; |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 591 | } |
| 592 | |
| 593 | static inline void pch_spi_select_chip(struct pch_spi_data *data, |
| 594 | struct spi_device *pspi) |
| 595 | { |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 596 | if (data->current_chip != NULL) { |
| 597 | if (pspi->chip_select != data->n_curnt_chip) { |
| 598 | dev_dbg(&pspi->dev, "%s : different slave\n", __func__); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 599 | data->current_chip = NULL; |
| 600 | } |
| 601 | } |
| 602 | |
| 603 | data->current_chip = pspi; |
| 604 | |
| 605 | data->n_curnt_chip = data->current_chip->chip_select; |
| 606 | |
| 607 | dev_dbg(&pspi->dev, "%s :Invoking pch_spi_setup_transfer\n", __func__); |
| 608 | pch_spi_setup_transfer(pspi); |
| 609 | } |
| 610 | |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 611 | static void pch_spi_set_tx(struct pch_spi_data *data, int *bpw) |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 612 | { |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 613 | int size; |
| 614 | u32 n_writes; |
| 615 | int j; |
| 616 | struct spi_message *pmsg; |
| 617 | const u8 *tx_buf; |
| 618 | const u16 *tx_sbuf; |
| 619 | |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 620 | /* set baud rate if needed */ |
| 621 | if (data->cur_trans->speed_hz) { |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 622 | dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__); |
| 623 | pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 624 | } |
| 625 | |
| 626 | /* set bits per word if needed */ |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 627 | if (data->cur_trans->bits_per_word && |
| 628 | (data->current_msg->spi->bits_per_word != data->cur_trans->bits_per_word)) { |
| 629 | dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 630 | pch_spi_set_bits_per_word(data->master, |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 631 | data->cur_trans->bits_per_word); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 632 | *bpw = data->cur_trans->bits_per_word; |
| 633 | } else { |
| 634 | *bpw = data->current_msg->spi->bits_per_word; |
| 635 | } |
| 636 | |
| 637 | /* reset Tx/Rx index */ |
| 638 | data->tx_index = 0; |
| 639 | data->rx_index = 0; |
| 640 | |
| 641 | data->bpw_len = data->cur_trans->len / (*bpw / 8); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 642 | |
| 643 | /* find alloc size */ |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 644 | size = data->cur_trans->len * sizeof(*data->pkt_tx_buff); |
| 645 | |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 646 | /* allocate memory for pkt_tx_buff & pkt_rx_buffer */ |
| 647 | data->pkt_tx_buff = kzalloc(size, GFP_KERNEL); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 648 | if (data->pkt_tx_buff != NULL) { |
| 649 | data->pkt_rx_buff = kzalloc(size, GFP_KERNEL); |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 650 | if (!data->pkt_rx_buff) |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 651 | kfree(data->pkt_tx_buff); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 652 | } |
| 653 | |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 654 | if (!data->pkt_rx_buff) { |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 655 | /* flush queue and set status of all transfers to -ENOMEM */ |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 656 | dev_err(&data->master->dev, "%s :kzalloc failed\n", __func__); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 657 | list_for_each_entry(pmsg, data->queue.next, queue) { |
| 658 | pmsg->status = -ENOMEM; |
| 659 | |
| 660 | if (pmsg->complete != 0) |
| 661 | pmsg->complete(pmsg->context); |
| 662 | |
| 663 | /* delete from queue */ |
| 664 | list_del_init(&pmsg->queue); |
| 665 | } |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 666 | return; |
| 667 | } |
| 668 | |
| 669 | /* copy Tx Data */ |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 670 | if (data->cur_trans->tx_buf != NULL) { |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 671 | if (*bpw == 8) { |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 672 | tx_buf = data->cur_trans->tx_buf; |
| 673 | for (j = 0; j < data->bpw_len; j++) |
| 674 | data->pkt_tx_buff[j] = *tx_buf++; |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 675 | } else { |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 676 | tx_sbuf = data->cur_trans->tx_buf; |
| 677 | for (j = 0; j < data->bpw_len; j++) |
| 678 | data->pkt_tx_buff[j] = *tx_sbuf++; |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 679 | } |
| 680 | } |
| 681 | |
| 682 | /* if len greater than PCH_MAX_FIFO_DEPTH, write 16,else len bytes */ |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 683 | n_writes = data->bpw_len; |
| 684 | if (n_writes > PCH_MAX_FIFO_DEPTH) |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 685 | n_writes = PCH_MAX_FIFO_DEPTH; |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 686 | |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 687 | dev_dbg(&data->master->dev, "\n%s:Pulling down SSN low - writing " |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 688 | "0x2 to SSNXCR\n", __func__); |
| 689 | pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW); |
| 690 | |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 691 | for (j = 0; j < n_writes; j++) |
| 692 | pch_spi_writereg(data->master, PCH_SPDWR, data->pkt_tx_buff[j]); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 693 | |
| 694 | /* update tx_index */ |
| 695 | data->tx_index = j; |
| 696 | |
| 697 | /* reset transfer complete flag */ |
| 698 | data->transfer_complete = false; |
| 699 | data->transfer_active = true; |
| 700 | } |
| 701 | |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 702 | static void pch_spi_nomore_transfer(struct pch_spi_data *data) |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 703 | { |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 704 | struct spi_message *pmsg; |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 705 | dev_dbg(&data->master->dev, "%s called\n", __func__); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 706 | /* Invoke complete callback |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 707 | * [To the spi core..indicating end of transfer] */ |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 708 | data->current_msg->status = 0; |
| 709 | |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 710 | if (data->current_msg->complete != 0) { |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 711 | dev_dbg(&data->master->dev, |
| 712 | "%s:Invoking callback of SPI core\n", __func__); |
| 713 | data->current_msg->complete(data->current_msg->context); |
| 714 | } |
| 715 | |
| 716 | /* update status in global variable */ |
| 717 | data->bcurrent_msg_processing = false; |
| 718 | |
| 719 | dev_dbg(&data->master->dev, |
| 720 | "%s:data->bcurrent_msg_processing = false\n", __func__); |
| 721 | |
| 722 | data->current_msg = NULL; |
| 723 | data->cur_trans = NULL; |
| 724 | |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 725 | /* check if we have items in list and not suspending |
| 726 | * return 1 if list empty */ |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 727 | if ((list_empty(&data->queue) == 0) && |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 728 | (!data->board_dat->suspend_sts) && |
| 729 | (data->status != STATUS_EXITING)) { |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 730 | /* We have some more work to do (either there is more tranint |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 731 | * bpw;sfer requests in the current message or there are |
| 732 | *more messages) |
| 733 | */ |
| 734 | dev_dbg(&data->master->dev, "%s:Invoke queue_work\n", __func__); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 735 | queue_work(data->wk, &data->work); |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 736 | } else if (data->board_dat->suspend_sts || |
| 737 | data->status == STATUS_EXITING) { |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 738 | dev_dbg(&data->master->dev, |
| 739 | "%s suspend/remove initiated, flushing queue\n", |
| 740 | __func__); |
| 741 | list_for_each_entry(pmsg, data->queue.next, queue) { |
| 742 | pmsg->status = -EIO; |
| 743 | |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 744 | if (pmsg->complete) |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 745 | pmsg->complete(pmsg->context); |
| 746 | |
| 747 | /* delete from queue */ |
| 748 | list_del_init(&pmsg->queue); |
| 749 | } |
| 750 | } |
| 751 | } |
| 752 | |
| 753 | static void pch_spi_set_ir(struct pch_spi_data *data) |
| 754 | { |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 755 | /* enable interrupts, set threshold, enable SPI */ |
| 756 | if ((data->bpw_len) > PCH_MAX_FIFO_DEPTH) |
Justin P. Mattock | 77e58ef | 2010-12-31 09:50:31 -0800 | [diff] [blame] | 757 | /* set receive threshold to PCH_RX_THOLD */ |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 758 | pch_spi_setclr_reg(data->master, PCH_SPCR, |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 759 | PCH_RX_THOLD << SPCR_RFIC_FIELD | |
| 760 | SPCR_FIE_BIT | SPCR_RFIE_BIT | |
| 761 | SPCR_ORIE_BIT | SPCR_SPE_BIT, |
| 762 | MASK_RFIC_SPCR_BITS | PCH_ALL); |
| 763 | else |
Justin P. Mattock | 77e58ef | 2010-12-31 09:50:31 -0800 | [diff] [blame] | 764 | /* set receive threshold to maximum */ |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 765 | pch_spi_setclr_reg(data->master, PCH_SPCR, |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 766 | PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD | |
| 767 | SPCR_FIE_BIT | SPCR_ORIE_BIT | |
| 768 | SPCR_SPE_BIT, |
| 769 | MASK_RFIC_SPCR_BITS | PCH_ALL); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 770 | |
| 771 | /* Wait until the transfer completes; go to sleep after |
| 772 | initiating the transfer. */ |
| 773 | dev_dbg(&data->master->dev, |
| 774 | "%s:waiting for transfer to get over\n", __func__); |
| 775 | |
| 776 | wait_event_interruptible(data->wait, data->transfer_complete); |
| 777 | |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 778 | /* clear all interrupts */ |
| 779 | pch_spi_writereg(data->master, PCH_SPSR, |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 780 | pch_spi_readreg(data->master, PCH_SPSR)); |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 781 | /* Disable interrupts and SPI transfer */ |
| 782 | pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL | SPCR_SPE_BIT); |
| 783 | /* clear FIFO */ |
| 784 | pch_spi_clear_fifo(data->master); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 785 | } |
| 786 | |
| 787 | static void pch_spi_copy_rx_data(struct pch_spi_data *data, int bpw) |
| 788 | { |
| 789 | int j; |
| 790 | u8 *rx_buf; |
| 791 | u16 *rx_sbuf; |
| 792 | |
| 793 | /* copy Rx Data */ |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 794 | if (!data->cur_trans->rx_buf) |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 795 | return; |
| 796 | |
| 797 | if (bpw == 8) { |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 798 | rx_buf = data->cur_trans->rx_buf; |
| 799 | for (j = 0; j < data->bpw_len; j++) |
| 800 | *rx_buf++ = data->pkt_rx_buff[j] & 0xFF; |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 801 | } else { |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 802 | rx_sbuf = data->cur_trans->rx_buf; |
| 803 | for (j = 0; j < data->bpw_len; j++) |
| 804 | *rx_sbuf++ = data->pkt_rx_buff[j]; |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 805 | } |
| 806 | } |
| 807 | |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 808 | static void pch_spi_copy_rx_data_for_dma(struct pch_spi_data *data, int bpw) |
| 809 | { |
| 810 | int j; |
| 811 | u8 *rx_buf; |
| 812 | u16 *rx_sbuf; |
| 813 | const u8 *rx_dma_buf; |
| 814 | const u16 *rx_dma_sbuf; |
| 815 | |
| 816 | /* copy Rx Data */ |
| 817 | if (!data->cur_trans->rx_buf) |
| 818 | return; |
| 819 | |
| 820 | if (bpw == 8) { |
| 821 | rx_buf = data->cur_trans->rx_buf; |
| 822 | rx_dma_buf = data->dma.rx_buf_virt; |
| 823 | for (j = 0; j < data->bpw_len; j++) |
| 824 | *rx_buf++ = *rx_dma_buf++ & 0xFF; |
| 825 | } else { |
| 826 | rx_sbuf = data->cur_trans->rx_buf; |
| 827 | rx_dma_sbuf = data->dma.rx_buf_virt; |
| 828 | for (j = 0; j < data->bpw_len; j++) |
| 829 | *rx_sbuf++ = *rx_dma_sbuf++; |
| 830 | } |
| 831 | } |
| 832 | |
Tomoya MORINAGA | 25e803f | 2011-09-06 17:16:37 +0900 | [diff] [blame] | 833 | static int pch_spi_start_transfer(struct pch_spi_data *data) |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 834 | { |
| 835 | struct pch_spi_dma_ctrl *dma; |
| 836 | unsigned long flags; |
Tomoya MORINAGA | 25e803f | 2011-09-06 17:16:37 +0900 | [diff] [blame] | 837 | int rtn; |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 838 | |
| 839 | dma = &data->dma; |
| 840 | |
| 841 | spin_lock_irqsave(&data->lock, flags); |
| 842 | |
| 843 | /* disable interrupts, SPI set enable */ |
| 844 | pch_spi_setclr_reg(data->master, PCH_SPCR, SPCR_SPE_BIT, PCH_ALL); |
| 845 | |
| 846 | spin_unlock_irqrestore(&data->lock, flags); |
| 847 | |
| 848 | /* Wait until the transfer completes; go to sleep after |
| 849 | initiating the transfer. */ |
| 850 | dev_dbg(&data->master->dev, |
| 851 | "%s:waiting for transfer to get over\n", __func__); |
Tomoya MORINAGA | 25e803f | 2011-09-06 17:16:37 +0900 | [diff] [blame] | 852 | rtn = wait_event_interruptible_timeout(data->wait, |
| 853 | data->transfer_complete, |
| 854 | msecs_to_jiffies(2 * HZ)); |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 855 | |
| 856 | dma_sync_sg_for_cpu(&data->master->dev, dma->sg_rx_p, dma->nent, |
| 857 | DMA_FROM_DEVICE); |
Tomoya MORINAGA | 27504be | 2011-09-06 17:16:34 +0900 | [diff] [blame] | 858 | |
| 859 | dma_sync_sg_for_cpu(&data->master->dev, dma->sg_tx_p, dma->nent, |
| 860 | DMA_FROM_DEVICE); |
| 861 | memset(data->dma.tx_buf_virt, 0, PAGE_SIZE); |
| 862 | |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 863 | async_tx_ack(dma->desc_rx); |
| 864 | async_tx_ack(dma->desc_tx); |
| 865 | kfree(dma->sg_tx_p); |
| 866 | kfree(dma->sg_rx_p); |
| 867 | |
| 868 | spin_lock_irqsave(&data->lock, flags); |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 869 | |
| 870 | /* clear fifo threshold, disable interrupts, disable SPI transfer */ |
| 871 | pch_spi_setclr_reg(data->master, PCH_SPCR, 0, |
| 872 | MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS | PCH_ALL | |
| 873 | SPCR_SPE_BIT); |
| 874 | /* clear all interrupts */ |
| 875 | pch_spi_writereg(data->master, PCH_SPSR, |
| 876 | pch_spi_readreg(data->master, PCH_SPSR)); |
| 877 | /* clear FIFO */ |
| 878 | pch_spi_clear_fifo(data->master); |
| 879 | |
| 880 | spin_unlock_irqrestore(&data->lock, flags); |
Tomoya MORINAGA | 25e803f | 2011-09-06 17:16:37 +0900 | [diff] [blame] | 881 | |
| 882 | return rtn; |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 883 | } |
| 884 | |
| 885 | static void pch_dma_rx_complete(void *arg) |
| 886 | { |
| 887 | struct pch_spi_data *data = arg; |
| 888 | |
| 889 | /* transfer is completed;inform pch_spi_process_messages_dma */ |
| 890 | data->transfer_complete = true; |
| 891 | wake_up_interruptible(&data->wait); |
| 892 | } |
| 893 | |
| 894 | static bool pch_spi_filter(struct dma_chan *chan, void *slave) |
| 895 | { |
| 896 | struct pch_dma_slave *param = slave; |
| 897 | |
| 898 | if ((chan->chan_id == param->chan_id) && |
| 899 | (param->dma_dev == chan->device->dev)) { |
| 900 | chan->private = param; |
| 901 | return true; |
| 902 | } else { |
| 903 | return false; |
| 904 | } |
| 905 | } |
| 906 | |
| 907 | static void pch_spi_request_dma(struct pch_spi_data *data, int bpw) |
| 908 | { |
| 909 | dma_cap_mask_t mask; |
| 910 | struct dma_chan *chan; |
| 911 | struct pci_dev *dma_dev; |
| 912 | struct pch_dma_slave *param; |
| 913 | struct pch_spi_dma_ctrl *dma; |
| 914 | unsigned int width; |
| 915 | |
| 916 | if (bpw == 8) |
| 917 | width = PCH_DMA_WIDTH_1_BYTE; |
| 918 | else |
| 919 | width = PCH_DMA_WIDTH_2_BYTES; |
| 920 | |
| 921 | dma = &data->dma; |
| 922 | dma_cap_zero(mask); |
| 923 | dma_cap_set(DMA_SLAVE, mask); |
| 924 | |
| 925 | /* Get DMA's dev information */ |
| 926 | dma_dev = pci_get_bus_and_slot(2, PCI_DEVFN(12, 0)); |
| 927 | |
| 928 | /* Set Tx DMA */ |
| 929 | param = &dma->param_tx; |
| 930 | param->dma_dev = &dma_dev->dev; |
| 931 | param->chan_id = data->master->bus_num * 2; /* Tx = 0, 2 */ |
| 932 | param->tx_reg = data->io_base_addr + PCH_SPDWR; |
| 933 | param->width = width; |
| 934 | chan = dma_request_channel(mask, pch_spi_filter, param); |
| 935 | if (!chan) { |
| 936 | dev_err(&data->master->dev, |
| 937 | "ERROR: dma_request_channel FAILS(Tx)\n"); |
| 938 | data->use_dma = 0; |
| 939 | return; |
| 940 | } |
| 941 | dma->chan_tx = chan; |
| 942 | |
| 943 | /* Set Rx DMA */ |
| 944 | param = &dma->param_rx; |
| 945 | param->dma_dev = &dma_dev->dev; |
| 946 | param->chan_id = data->master->bus_num * 2 + 1; /* Rx = Tx + 1 */ |
| 947 | param->rx_reg = data->io_base_addr + PCH_SPDRR; |
| 948 | param->width = width; |
| 949 | chan = dma_request_channel(mask, pch_spi_filter, param); |
| 950 | if (!chan) { |
| 951 | dev_err(&data->master->dev, |
| 952 | "ERROR: dma_request_channel FAILS(Rx)\n"); |
| 953 | dma_release_channel(dma->chan_tx); |
| 954 | dma->chan_tx = NULL; |
| 955 | data->use_dma = 0; |
| 956 | return; |
| 957 | } |
| 958 | dma->chan_rx = chan; |
| 959 | } |
| 960 | |
| 961 | static void pch_spi_release_dma(struct pch_spi_data *data) |
| 962 | { |
| 963 | struct pch_spi_dma_ctrl *dma; |
| 964 | |
| 965 | dma = &data->dma; |
| 966 | if (dma->chan_tx) { |
| 967 | dma_release_channel(dma->chan_tx); |
| 968 | dma->chan_tx = NULL; |
| 969 | } |
| 970 | if (dma->chan_rx) { |
| 971 | dma_release_channel(dma->chan_rx); |
| 972 | dma->chan_rx = NULL; |
| 973 | } |
| 974 | return; |
| 975 | } |
| 976 | |
| 977 | static void pch_spi_handle_dma(struct pch_spi_data *data, int *bpw) |
| 978 | { |
| 979 | const u8 *tx_buf; |
| 980 | const u16 *tx_sbuf; |
| 981 | u8 *tx_dma_buf; |
| 982 | u16 *tx_dma_sbuf; |
| 983 | struct scatterlist *sg; |
| 984 | struct dma_async_tx_descriptor *desc_tx; |
| 985 | struct dma_async_tx_descriptor *desc_rx; |
| 986 | int num; |
| 987 | int i; |
| 988 | int size; |
| 989 | int rem; |
| 990 | unsigned long flags; |
| 991 | struct pch_spi_dma_ctrl *dma; |
| 992 | |
| 993 | dma = &data->dma; |
| 994 | |
| 995 | /* set baud rate if needed */ |
| 996 | if (data->cur_trans->speed_hz) { |
| 997 | dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__); |
| 998 | spin_lock_irqsave(&data->lock, flags); |
| 999 | pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz); |
| 1000 | spin_unlock_irqrestore(&data->lock, flags); |
| 1001 | } |
| 1002 | |
| 1003 | /* set bits per word if needed */ |
| 1004 | if (data->cur_trans->bits_per_word && |
| 1005 | (data->current_msg->spi->bits_per_word != |
| 1006 | data->cur_trans->bits_per_word)) { |
| 1007 | dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__); |
| 1008 | spin_lock_irqsave(&data->lock, flags); |
| 1009 | pch_spi_set_bits_per_word(data->master, |
| 1010 | data->cur_trans->bits_per_word); |
| 1011 | spin_unlock_irqrestore(&data->lock, flags); |
| 1012 | *bpw = data->cur_trans->bits_per_word; |
| 1013 | } else { |
| 1014 | *bpw = data->current_msg->spi->bits_per_word; |
| 1015 | } |
| 1016 | data->bpw_len = data->cur_trans->len / (*bpw / 8); |
| 1017 | |
| 1018 | /* copy Tx Data */ |
| 1019 | if (data->cur_trans->tx_buf != NULL) { |
| 1020 | if (*bpw == 8) { |
| 1021 | tx_buf = data->cur_trans->tx_buf; |
| 1022 | tx_dma_buf = dma->tx_buf_virt; |
| 1023 | for (i = 0; i < data->bpw_len; i++) |
| 1024 | *tx_dma_buf++ = *tx_buf++; |
| 1025 | } else { |
| 1026 | tx_sbuf = data->cur_trans->tx_buf; |
| 1027 | tx_dma_sbuf = dma->tx_buf_virt; |
| 1028 | for (i = 0; i < data->bpw_len; i++) |
| 1029 | *tx_dma_sbuf++ = *tx_sbuf++; |
| 1030 | } |
| 1031 | } |
| 1032 | if (data->bpw_len > PCH_DMA_TRANS_SIZE) { |
| 1033 | num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1; |
| 1034 | size = PCH_DMA_TRANS_SIZE; |
| 1035 | rem = data->bpw_len % PCH_DMA_TRANS_SIZE; |
| 1036 | } else { |
| 1037 | num = 1; |
| 1038 | size = data->bpw_len; |
| 1039 | rem = data->bpw_len; |
| 1040 | } |
| 1041 | dev_dbg(&data->master->dev, "%s num=%d size=%d rem=%d\n", |
| 1042 | __func__, num, size, rem); |
| 1043 | spin_lock_irqsave(&data->lock, flags); |
| 1044 | |
| 1045 | /* set receive fifo threshold and transmit fifo threshold */ |
| 1046 | pch_spi_setclr_reg(data->master, PCH_SPCR, |
| 1047 | ((size - 1) << SPCR_RFIC_FIELD) | |
Tomoya MORINAGA | f3e03e2e | 2011-09-06 17:16:38 +0900 | [diff] [blame] | 1048 | (PCH_TX_THOLD << SPCR_TFIC_FIELD), |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 1049 | MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS); |
| 1050 | |
| 1051 | spin_unlock_irqrestore(&data->lock, flags); |
| 1052 | |
| 1053 | /* RX */ |
| 1054 | dma->sg_rx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC); |
| 1055 | sg_init_table(dma->sg_rx_p, num); /* Initialize SG table */ |
| 1056 | /* offset, length setting */ |
| 1057 | sg = dma->sg_rx_p; |
| 1058 | for (i = 0; i < num; i++, sg++) { |
Tomoya MORINAGA | f3e03e2e | 2011-09-06 17:16:38 +0900 | [diff] [blame] | 1059 | if (i == (num - 2)) { |
| 1060 | sg->offset = size * i; |
| 1061 | sg->offset = sg->offset * (*bpw / 8); |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 1062 | sg_set_page(sg, virt_to_page(dma->rx_buf_virt), rem, |
| 1063 | sg->offset); |
| 1064 | sg_dma_len(sg) = rem; |
Tomoya MORINAGA | f3e03e2e | 2011-09-06 17:16:38 +0900 | [diff] [blame] | 1065 | } else if (i == (num - 1)) { |
| 1066 | sg->offset = size * (i - 1) + rem; |
| 1067 | sg->offset = sg->offset * (*bpw / 8); |
| 1068 | sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size, |
| 1069 | sg->offset); |
| 1070 | sg_dma_len(sg) = size; |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 1071 | } else { |
Tomoya MORINAGA | f3e03e2e | 2011-09-06 17:16:38 +0900 | [diff] [blame] | 1072 | sg->offset = size * i; |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 1073 | sg->offset = sg->offset * (*bpw / 8); |
| 1074 | sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size, |
| 1075 | sg->offset); |
| 1076 | sg_dma_len(sg) = size; |
| 1077 | } |
| 1078 | sg_dma_address(sg) = dma->rx_buf_dma + sg->offset; |
| 1079 | } |
| 1080 | sg = dma->sg_rx_p; |
| 1081 | desc_rx = dma->chan_rx->device->device_prep_slave_sg(dma->chan_rx, sg, |
Vinod Koul | a485df4 | 2011-10-14 10:47:38 +0530 | [diff] [blame] | 1082 | num, DMA_DEV_TO_MEM, |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 1083 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
| 1084 | if (!desc_rx) { |
| 1085 | dev_err(&data->master->dev, "%s:device_prep_slave_sg Failed\n", |
| 1086 | __func__); |
| 1087 | return; |
| 1088 | } |
| 1089 | dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_FROM_DEVICE); |
| 1090 | desc_rx->callback = pch_dma_rx_complete; |
| 1091 | desc_rx->callback_param = data; |
| 1092 | dma->nent = num; |
| 1093 | dma->desc_rx = desc_rx; |
| 1094 | |
| 1095 | /* TX */ |
Tomoya MORINAGA | f3e03e2e | 2011-09-06 17:16:38 +0900 | [diff] [blame] | 1096 | if (data->bpw_len > PCH_DMA_TRANS_SIZE) { |
| 1097 | num = data->bpw_len / PCH_DMA_TRANS_SIZE; |
| 1098 | size = PCH_DMA_TRANS_SIZE; |
| 1099 | rem = 16; |
| 1100 | } else { |
| 1101 | num = 1; |
| 1102 | size = data->bpw_len; |
| 1103 | rem = data->bpw_len; |
| 1104 | } |
| 1105 | |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 1106 | dma->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC); |
| 1107 | sg_init_table(dma->sg_tx_p, num); /* Initialize SG table */ |
| 1108 | /* offset, length setting */ |
| 1109 | sg = dma->sg_tx_p; |
| 1110 | for (i = 0; i < num; i++, sg++) { |
| 1111 | if (i == 0) { |
| 1112 | sg->offset = 0; |
| 1113 | sg_set_page(sg, virt_to_page(dma->tx_buf_virt), rem, |
| 1114 | sg->offset); |
| 1115 | sg_dma_len(sg) = rem; |
| 1116 | } else { |
| 1117 | sg->offset = rem + size * (i - 1); |
| 1118 | sg->offset = sg->offset * (*bpw / 8); |
| 1119 | sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size, |
| 1120 | sg->offset); |
| 1121 | sg_dma_len(sg) = size; |
| 1122 | } |
| 1123 | sg_dma_address(sg) = dma->tx_buf_dma + sg->offset; |
| 1124 | } |
| 1125 | sg = dma->sg_tx_p; |
| 1126 | desc_tx = dma->chan_tx->device->device_prep_slave_sg(dma->chan_tx, |
Vinod Koul | a485df4 | 2011-10-14 10:47:38 +0530 | [diff] [blame] | 1127 | sg, num, DMA_MEM_TO_DEV, |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 1128 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
| 1129 | if (!desc_tx) { |
| 1130 | dev_err(&data->master->dev, "%s:device_prep_slave_sg Failed\n", |
| 1131 | __func__); |
| 1132 | return; |
| 1133 | } |
| 1134 | dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_TO_DEVICE); |
| 1135 | desc_tx->callback = NULL; |
| 1136 | desc_tx->callback_param = data; |
| 1137 | dma->nent = num; |
| 1138 | dma->desc_tx = desc_tx; |
| 1139 | |
| 1140 | dev_dbg(&data->master->dev, "\n%s:Pulling down SSN low - writing " |
| 1141 | "0x2 to SSNXCR\n", __func__); |
| 1142 | |
| 1143 | spin_lock_irqsave(&data->lock, flags); |
| 1144 | pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW); |
| 1145 | desc_rx->tx_submit(desc_rx); |
| 1146 | desc_tx->tx_submit(desc_tx); |
| 1147 | spin_unlock_irqrestore(&data->lock, flags); |
| 1148 | |
| 1149 | /* reset transfer complete flag */ |
| 1150 | data->transfer_complete = false; |
| 1151 | } |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1152 | |
| 1153 | static void pch_spi_process_messages(struct work_struct *pwork) |
| 1154 | { |
| 1155 | struct spi_message *pmsg; |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 1156 | struct pch_spi_data *data; |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1157 | int bpw; |
| 1158 | |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 1159 | data = container_of(pwork, struct pch_spi_data, work); |
Grant Likely | 8e41b52 | 2010-10-13 23:03:15 -0600 | [diff] [blame] | 1160 | dev_dbg(&data->master->dev, "%s data initialized\n", __func__); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1161 | |
| 1162 | spin_lock(&data->lock); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1163 | /* check if suspend has been initiated;if yes flush queue */ |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 1164 | if (data->board_dat->suspend_sts || (data->status == STATUS_EXITING)) { |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 1165 | dev_dbg(&data->master->dev, "%s suspend/remove initiated," |
| 1166 | "flushing queue\n", __func__); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1167 | list_for_each_entry(pmsg, data->queue.next, queue) { |
| 1168 | pmsg->status = -EIO; |
| 1169 | |
| 1170 | if (pmsg->complete != 0) { |
| 1171 | spin_unlock(&data->lock); |
| 1172 | pmsg->complete(pmsg->context); |
| 1173 | spin_lock(&data->lock); |
| 1174 | } |
| 1175 | |
| 1176 | /* delete from queue */ |
| 1177 | list_del_init(&pmsg->queue); |
| 1178 | } |
| 1179 | |
| 1180 | spin_unlock(&data->lock); |
| 1181 | return; |
| 1182 | } |
| 1183 | |
| 1184 | data->bcurrent_msg_processing = true; |
| 1185 | dev_dbg(&data->master->dev, |
| 1186 | "%s Set data->bcurrent_msg_processing= true\n", __func__); |
| 1187 | |
| 1188 | /* Get the message from the queue and delete it from there. */ |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 1189 | data->current_msg = list_entry(data->queue.next, struct spi_message, |
| 1190 | queue); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1191 | |
| 1192 | list_del_init(&data->current_msg->queue); |
| 1193 | |
| 1194 | data->current_msg->status = 0; |
| 1195 | |
| 1196 | pch_spi_select_chip(data, data->current_msg->spi); |
| 1197 | |
| 1198 | spin_unlock(&data->lock); |
| 1199 | |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 1200 | if (data->use_dma) |
| 1201 | pch_spi_request_dma(data, |
| 1202 | data->current_msg->spi->bits_per_word); |
Tomoya MORINAGA | 8b7aa96 | 2011-09-06 17:16:35 +0900 | [diff] [blame] | 1203 | pch_spi_writereg(data->master, PCH_SSNXCR, SSN_NO_CONTROL); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1204 | do { |
| 1205 | /* If we are already processing a message get the next |
| 1206 | transfer structure from the message otherwise retrieve |
| 1207 | the 1st transfer request from the message. */ |
| 1208 | spin_lock(&data->lock); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1209 | if (data->cur_trans == NULL) { |
| 1210 | data->cur_trans = |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 1211 | list_entry(data->current_msg->transfers.next, |
| 1212 | struct spi_transfer, transfer_list); |
| 1213 | dev_dbg(&data->master->dev, "%s " |
| 1214 | ":Getting 1st transfer message\n", __func__); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1215 | } else { |
| 1216 | data->cur_trans = |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 1217 | list_entry(data->cur_trans->transfer_list.next, |
| 1218 | struct spi_transfer, transfer_list); |
| 1219 | dev_dbg(&data->master->dev, "%s " |
| 1220 | ":Getting next transfer message\n", __func__); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1221 | } |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1222 | spin_unlock(&data->lock); |
| 1223 | |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 1224 | if (data->use_dma) { |
| 1225 | pch_spi_handle_dma(data, &bpw); |
Tomoya MORINAGA | 25e803f | 2011-09-06 17:16:37 +0900 | [diff] [blame] | 1226 | if (!pch_spi_start_transfer(data)) |
| 1227 | goto out; |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 1228 | pch_spi_copy_rx_data_for_dma(data, bpw); |
| 1229 | } else { |
| 1230 | pch_spi_set_tx(data, &bpw); |
| 1231 | pch_spi_set_ir(data); |
| 1232 | pch_spi_copy_rx_data(data, bpw); |
| 1233 | kfree(data->pkt_rx_buff); |
| 1234 | data->pkt_rx_buff = NULL; |
| 1235 | kfree(data->pkt_tx_buff); |
| 1236 | data->pkt_tx_buff = NULL; |
| 1237 | } |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1238 | /* increment message count */ |
| 1239 | data->current_msg->actual_length += data->cur_trans->len; |
| 1240 | |
| 1241 | dev_dbg(&data->master->dev, |
| 1242 | "%s:data->current_msg->actual_length=%d\n", |
| 1243 | __func__, data->current_msg->actual_length); |
| 1244 | |
| 1245 | /* check for delay */ |
| 1246 | if (data->cur_trans->delay_usecs) { |
| 1247 | dev_dbg(&data->master->dev, "%s:" |
| 1248 | "delay in usec=%d\n", __func__, |
| 1249 | data->cur_trans->delay_usecs); |
| 1250 | udelay(data->cur_trans->delay_usecs); |
| 1251 | } |
| 1252 | |
| 1253 | spin_lock(&data->lock); |
| 1254 | |
| 1255 | /* No more transfer in this message. */ |
| 1256 | if ((data->cur_trans->transfer_list.next) == |
| 1257 | &(data->current_msg->transfers)) { |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 1258 | pch_spi_nomore_transfer(data); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1259 | } |
| 1260 | |
| 1261 | spin_unlock(&data->lock); |
| 1262 | |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 1263 | } while (data->cur_trans != NULL); |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 1264 | |
Tomoya MORINAGA | 25e803f | 2011-09-06 17:16:37 +0900 | [diff] [blame] | 1265 | out: |
Tomoya MORINAGA | 8b7aa96 | 2011-09-06 17:16:35 +0900 | [diff] [blame] | 1266 | pch_spi_writereg(data->master, PCH_SSNXCR, SSN_HIGH); |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 1267 | if (data->use_dma) |
| 1268 | pch_spi_release_dma(data); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1269 | } |
| 1270 | |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 1271 | static void pch_spi_free_resources(struct pch_spi_board_data *board_dat, |
| 1272 | struct pch_spi_data *data) |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1273 | { |
| 1274 | dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__); |
| 1275 | |
| 1276 | /* free workqueue */ |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 1277 | if (data->wk != NULL) { |
| 1278 | destroy_workqueue(data->wk); |
| 1279 | data->wk = NULL; |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1280 | dev_dbg(&board_dat->pdev->dev, |
| 1281 | "%s destroy_workqueue invoked successfully\n", |
| 1282 | __func__); |
| 1283 | } |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1284 | } |
| 1285 | |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 1286 | static int pch_spi_get_resources(struct pch_spi_board_data *board_dat, |
| 1287 | struct pch_spi_data *data) |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1288 | { |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 1289 | int retval = 0; |
| 1290 | |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1291 | dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__); |
| 1292 | |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1293 | /* create workqueue */ |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 1294 | data->wk = create_singlethread_workqueue(KBUILD_MODNAME); |
| 1295 | if (!data->wk) { |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1296 | dev_err(&board_dat->pdev->dev, |
| 1297 | "%s create_singlet hread_workqueue failed\n", __func__); |
| 1298 | retval = -EBUSY; |
| 1299 | goto err_return; |
| 1300 | } |
| 1301 | |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1302 | /* reset PCH SPI h/w */ |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 1303 | pch_spi_reset(data->master); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1304 | dev_dbg(&board_dat->pdev->dev, |
| 1305 | "%s pch_spi_reset invoked successfully\n", __func__); |
| 1306 | |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 1307 | dev_dbg(&board_dat->pdev->dev, "%s data->irq_reg_sts=true\n", __func__); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1308 | |
| 1309 | err_return: |
| 1310 | if (retval != 0) { |
| 1311 | dev_err(&board_dat->pdev->dev, |
| 1312 | "%s FAIL:invoking pch_spi_free_resources\n", __func__); |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 1313 | pch_spi_free_resources(board_dat, data); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1314 | } |
| 1315 | |
| 1316 | dev_dbg(&board_dat->pdev->dev, "%s Return=%d\n", __func__, retval); |
| 1317 | |
| 1318 | return retval; |
| 1319 | } |
| 1320 | |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 1321 | static void pch_free_dma_buf(struct pch_spi_board_data *board_dat, |
| 1322 | struct pch_spi_data *data) |
| 1323 | { |
| 1324 | struct pch_spi_dma_ctrl *dma; |
| 1325 | |
| 1326 | dma = &data->dma; |
| 1327 | if (dma->tx_buf_dma) |
| 1328 | dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE, |
| 1329 | dma->tx_buf_virt, dma->tx_buf_dma); |
| 1330 | if (dma->rx_buf_dma) |
| 1331 | dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE, |
| 1332 | dma->rx_buf_virt, dma->rx_buf_dma); |
| 1333 | return; |
| 1334 | } |
| 1335 | |
| 1336 | static void pch_alloc_dma_buf(struct pch_spi_board_data *board_dat, |
| 1337 | struct pch_spi_data *data) |
| 1338 | { |
| 1339 | struct pch_spi_dma_ctrl *dma; |
| 1340 | |
| 1341 | dma = &data->dma; |
| 1342 | /* Get Consistent memory for Tx DMA */ |
| 1343 | dma->tx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev, |
| 1344 | PCH_BUF_SIZE, &dma->tx_buf_dma, GFP_KERNEL); |
| 1345 | /* Get Consistent memory for Rx DMA */ |
| 1346 | dma->rx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev, |
| 1347 | PCH_BUF_SIZE, &dma->rx_buf_dma, GFP_KERNEL); |
| 1348 | } |
| 1349 | |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 1350 | static int __devinit pch_spi_pd_probe(struct platform_device *plat_dev) |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1351 | { |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 1352 | int ret; |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1353 | struct spi_master *master; |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 1354 | struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev); |
| 1355 | struct pch_spi_data *data; |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1356 | |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 1357 | dev_dbg(&plat_dev->dev, "%s:debug\n", __func__); |
| 1358 | |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 1359 | master = spi_alloc_master(&board_dat->pdev->dev, |
| 1360 | sizeof(struct pch_spi_data)); |
| 1361 | if (!master) { |
| 1362 | dev_err(&plat_dev->dev, "spi_alloc_master[%d] failed.\n", |
| 1363 | plat_dev->id); |
| 1364 | return -ENOMEM; |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1365 | } |
| 1366 | |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 1367 | data = spi_master_get_devdata(master); |
| 1368 | data->master = master; |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1369 | |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 1370 | platform_set_drvdata(plat_dev, data); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1371 | |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 1372 | /* baseaddress + address offset) */ |
| 1373 | data->io_base_addr = pci_resource_start(board_dat->pdev, 1) + |
| 1374 | PCH_ADDRESS_SIZE * plat_dev->id; |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 1375 | data->io_remap_addr = pci_iomap(board_dat->pdev, 1, 0) + |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 1376 | PCH_ADDRESS_SIZE * plat_dev->id; |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 1377 | if (!data->io_remap_addr) { |
| 1378 | dev_err(&plat_dev->dev, "%s pci_iomap failed\n", __func__); |
| 1379 | ret = -ENOMEM; |
| 1380 | goto err_pci_iomap; |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1381 | } |
| 1382 | |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 1383 | dev_dbg(&plat_dev->dev, "[ch%d] remap_addr=%p\n", |
| 1384 | plat_dev->id, data->io_remap_addr); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1385 | |
| 1386 | /* initialize members of SPI master */ |
| 1387 | master->bus_num = -1; |
| 1388 | master->num_chipselect = PCH_MAX_CS; |
| 1389 | master->setup = pch_spi_setup; |
| 1390 | master->transfer = pch_spi_transfer; |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1391 | |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 1392 | data->board_dat = board_dat; |
| 1393 | data->plat_dev = plat_dev; |
| 1394 | data->n_curnt_chip = 255; |
| 1395 | data->status = STATUS_RUNNING; |
| 1396 | data->ch = plat_dev->id; |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 1397 | data->use_dma = use_dma; |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1398 | |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 1399 | INIT_LIST_HEAD(&data->queue); |
| 1400 | spin_lock_init(&data->lock); |
| 1401 | INIT_WORK(&data->work, pch_spi_process_messages); |
| 1402 | init_waitqueue_head(&data->wait); |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 1403 | |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 1404 | ret = pch_spi_get_resources(board_dat, data); |
| 1405 | if (ret) { |
| 1406 | dev_err(&plat_dev->dev, "%s fail(retval=%d)\n", __func__, ret); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1407 | goto err_spi_get_resources; |
| 1408 | } |
| 1409 | |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 1410 | ret = request_irq(board_dat->pdev->irq, pch_spi_handler, |
| 1411 | IRQF_SHARED, KBUILD_MODNAME, data); |
| 1412 | if (ret) { |
| 1413 | dev_err(&plat_dev->dev, |
| 1414 | "%s request_irq failed\n", __func__); |
| 1415 | goto err_request_irq; |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1416 | } |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 1417 | data->irq_reg_sts = true; |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1418 | |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 1419 | pch_spi_set_master_mode(master); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1420 | |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 1421 | ret = spi_register_master(master); |
| 1422 | if (ret != 0) { |
| 1423 | dev_err(&plat_dev->dev, |
| 1424 | "%s spi_register_master FAILED\n", __func__); |
| 1425 | goto err_spi_register_master; |
| 1426 | } |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1427 | |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 1428 | if (use_dma) { |
| 1429 | dev_info(&plat_dev->dev, "Use DMA for data transfers\n"); |
| 1430 | pch_alloc_dma_buf(board_dat, data); |
| 1431 | } |
| 1432 | |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1433 | return 0; |
| 1434 | |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 1435 | err_spi_register_master: |
| 1436 | free_irq(board_dat->pdev->irq, board_dat); |
| 1437 | err_request_irq: |
| 1438 | pch_spi_free_resources(board_dat, data); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1439 | err_spi_get_resources: |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 1440 | pci_iounmap(board_dat->pdev, data->io_remap_addr); |
| 1441 | err_pci_iomap: |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1442 | spi_master_put(master); |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 1443 | |
| 1444 | return ret; |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1445 | } |
| 1446 | |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 1447 | static int __devexit pch_spi_pd_remove(struct platform_device *plat_dev) |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1448 | { |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 1449 | struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev); |
| 1450 | struct pch_spi_data *data = platform_get_drvdata(plat_dev); |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 1451 | int count; |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 1452 | unsigned long flags; |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1453 | |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 1454 | dev_dbg(&plat_dev->dev, "%s:[ch%d] irq=%d\n", |
| 1455 | __func__, plat_dev->id, board_dat->pdev->irq); |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 1456 | |
| 1457 | if (use_dma) |
| 1458 | pch_free_dma_buf(board_dat, data); |
| 1459 | |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 1460 | /* check for any pending messages; no action is taken if the queue |
| 1461 | * is still full; but at least we tried. Unload anyway */ |
| 1462 | count = 500; |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 1463 | spin_lock_irqsave(&data->lock, flags); |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 1464 | data->status = STATUS_EXITING; |
| 1465 | while ((list_empty(&data->queue) == 0) && --count) { |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 1466 | dev_dbg(&board_dat->pdev->dev, "%s :queue not empty\n", |
| 1467 | __func__); |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 1468 | spin_unlock_irqrestore(&data->lock, flags); |
Grant Likely | 65308c4 | 2010-09-29 17:31:34 +0900 | [diff] [blame] | 1469 | msleep(PCH_SLEEP_TIME); |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 1470 | spin_lock_irqsave(&data->lock, flags); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1471 | } |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 1472 | spin_unlock_irqrestore(&data->lock, flags); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1473 | |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 1474 | pch_spi_free_resources(board_dat, data); |
| 1475 | /* disable interrupts & free IRQ */ |
| 1476 | if (data->irq_reg_sts) { |
| 1477 | /* disable interrupts */ |
| 1478 | pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL); |
| 1479 | data->irq_reg_sts = false; |
| 1480 | free_irq(board_dat->pdev->irq, data); |
| 1481 | } |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1482 | |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 1483 | pci_iounmap(board_dat->pdev, data->io_remap_addr); |
| 1484 | spi_unregister_master(data->master); |
| 1485 | spi_master_put(data->master); |
| 1486 | platform_set_drvdata(plat_dev, NULL); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1487 | |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 1488 | return 0; |
| 1489 | } |
| 1490 | #ifdef CONFIG_PM |
| 1491 | static int pch_spi_pd_suspend(struct platform_device *pd_dev, |
| 1492 | pm_message_t state) |
| 1493 | { |
| 1494 | u8 count; |
| 1495 | struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev); |
| 1496 | struct pch_spi_data *data = platform_get_drvdata(pd_dev); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1497 | |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 1498 | dev_dbg(&pd_dev->dev, "%s ENTRY\n", __func__); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1499 | |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 1500 | if (!board_dat) { |
| 1501 | dev_err(&pd_dev->dev, |
| 1502 | "%s pci_get_drvdata returned NULL\n", __func__); |
| 1503 | return -EFAULT; |
| 1504 | } |
| 1505 | |
| 1506 | /* check if the current message is processed: |
| 1507 | Only after thats done the transfer will be suspended */ |
| 1508 | count = 255; |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 1509 | while ((--count) > 0) { |
| 1510 | if (!(data->bcurrent_msg_processing)) |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 1511 | break; |
| 1512 | msleep(PCH_SLEEP_TIME); |
| 1513 | } |
| 1514 | |
| 1515 | /* Free IRQ */ |
| 1516 | if (data->irq_reg_sts) { |
| 1517 | /* disable all interrupts */ |
| 1518 | pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL); |
| 1519 | pch_spi_reset(data->master); |
| 1520 | free_irq(board_dat->pdev->irq, data); |
| 1521 | |
| 1522 | data->irq_reg_sts = false; |
| 1523 | dev_dbg(&pd_dev->dev, |
| 1524 | "%s free_irq invoked successfully.\n", __func__); |
| 1525 | } |
| 1526 | |
| 1527 | return 0; |
| 1528 | } |
| 1529 | |
| 1530 | static int pch_spi_pd_resume(struct platform_device *pd_dev) |
| 1531 | { |
| 1532 | struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev); |
| 1533 | struct pch_spi_data *data = platform_get_drvdata(pd_dev); |
| 1534 | int retval; |
| 1535 | |
| 1536 | if (!board_dat) { |
| 1537 | dev_err(&pd_dev->dev, |
| 1538 | "%s pci_get_drvdata returned NULL\n", __func__); |
| 1539 | return -EFAULT; |
| 1540 | } |
| 1541 | |
| 1542 | if (!data->irq_reg_sts) { |
| 1543 | /* register IRQ */ |
| 1544 | retval = request_irq(board_dat->pdev->irq, pch_spi_handler, |
| 1545 | IRQF_SHARED, KBUILD_MODNAME, data); |
| 1546 | if (retval < 0) { |
| 1547 | dev_err(&pd_dev->dev, |
| 1548 | "%s request_irq failed\n", __func__); |
| 1549 | return retval; |
| 1550 | } |
| 1551 | |
| 1552 | /* reset PCH SPI h/w */ |
| 1553 | pch_spi_reset(data->master); |
| 1554 | pch_spi_set_master_mode(data->master); |
| 1555 | data->irq_reg_sts = true; |
| 1556 | } |
| 1557 | return 0; |
| 1558 | } |
| 1559 | #else |
| 1560 | #define pch_spi_pd_suspend NULL |
| 1561 | #define pch_spi_pd_resume NULL |
| 1562 | #endif |
| 1563 | |
| 1564 | static struct platform_driver pch_spi_pd_driver = { |
| 1565 | .driver = { |
| 1566 | .name = "pch-spi", |
| 1567 | .owner = THIS_MODULE, |
| 1568 | }, |
| 1569 | .probe = pch_spi_pd_probe, |
| 1570 | .remove = __devexit_p(pch_spi_pd_remove), |
| 1571 | .suspend = pch_spi_pd_suspend, |
| 1572 | .resume = pch_spi_pd_resume |
| 1573 | }; |
| 1574 | |
| 1575 | static int __devinit pch_spi_probe(struct pci_dev *pdev, |
| 1576 | const struct pci_device_id *id) |
| 1577 | { |
| 1578 | struct pch_spi_board_data *board_dat; |
| 1579 | struct platform_device *pd_dev = NULL; |
| 1580 | int retval; |
| 1581 | int i; |
| 1582 | struct pch_pd_dev_save *pd_dev_save; |
| 1583 | |
| 1584 | pd_dev_save = kzalloc(sizeof(struct pch_pd_dev_save), GFP_KERNEL); |
| 1585 | if (!pd_dev_save) { |
| 1586 | dev_err(&pdev->dev, "%s Can't allocate pd_dev_sav\n", __func__); |
| 1587 | return -ENOMEM; |
| 1588 | } |
| 1589 | |
| 1590 | board_dat = kzalloc(sizeof(struct pch_spi_board_data), GFP_KERNEL); |
| 1591 | if (!board_dat) { |
| 1592 | dev_err(&pdev->dev, "%s Can't allocate board_dat\n", __func__); |
| 1593 | retval = -ENOMEM; |
| 1594 | goto err_no_mem; |
| 1595 | } |
| 1596 | |
| 1597 | retval = pci_request_regions(pdev, KBUILD_MODNAME); |
| 1598 | if (retval) { |
| 1599 | dev_err(&pdev->dev, "%s request_region failed\n", __func__); |
| 1600 | goto pci_request_regions; |
| 1601 | } |
| 1602 | |
| 1603 | board_dat->pdev = pdev; |
| 1604 | board_dat->num = id->driver_data; |
| 1605 | pd_dev_save->num = id->driver_data; |
| 1606 | pd_dev_save->board_dat = board_dat; |
| 1607 | |
| 1608 | retval = pci_enable_device(pdev); |
| 1609 | if (retval) { |
| 1610 | dev_err(&pdev->dev, "%s pci_enable_device failed\n", __func__); |
| 1611 | goto pci_enable_device; |
| 1612 | } |
| 1613 | |
| 1614 | for (i = 0; i < board_dat->num; i++) { |
| 1615 | pd_dev = platform_device_alloc("pch-spi", i); |
| 1616 | if (!pd_dev) { |
| 1617 | dev_err(&pdev->dev, "platform_device_alloc failed\n"); |
| 1618 | goto err_platform_device; |
| 1619 | } |
| 1620 | pd_dev_save->pd_save[i] = pd_dev; |
| 1621 | pd_dev->dev.parent = &pdev->dev; |
| 1622 | |
| 1623 | retval = platform_device_add_data(pd_dev, board_dat, |
| 1624 | sizeof(*board_dat)); |
| 1625 | if (retval) { |
| 1626 | dev_err(&pdev->dev, |
| 1627 | "platform_device_add_data failed\n"); |
| 1628 | platform_device_put(pd_dev); |
| 1629 | goto err_platform_device; |
| 1630 | } |
| 1631 | |
| 1632 | retval = platform_device_add(pd_dev); |
| 1633 | if (retval) { |
| 1634 | dev_err(&pdev->dev, "platform_device_add failed\n"); |
| 1635 | platform_device_put(pd_dev); |
| 1636 | goto err_platform_device; |
| 1637 | } |
| 1638 | } |
| 1639 | |
| 1640 | pci_set_drvdata(pdev, pd_dev_save); |
| 1641 | |
| 1642 | return 0; |
| 1643 | |
| 1644 | err_platform_device: |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1645 | pci_disable_device(pdev); |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 1646 | pci_enable_device: |
| 1647 | pci_release_regions(pdev); |
| 1648 | pci_request_regions: |
| 1649 | kfree(board_dat); |
| 1650 | err_no_mem: |
| 1651 | kfree(pd_dev_save); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1652 | |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 1653 | return retval; |
| 1654 | } |
| 1655 | |
| 1656 | static void __devexit pch_spi_remove(struct pci_dev *pdev) |
| 1657 | { |
| 1658 | int i; |
| 1659 | struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev); |
| 1660 | |
| 1661 | dev_dbg(&pdev->dev, "%s ENTRY:pdev=%p\n", __func__, pdev); |
| 1662 | |
| 1663 | for (i = 0; i < pd_dev_save->num; i++) |
| 1664 | platform_device_unregister(pd_dev_save->pd_save[i]); |
| 1665 | |
| 1666 | pci_disable_device(pdev); |
| 1667 | pci_release_regions(pdev); |
| 1668 | kfree(pd_dev_save->board_dat); |
| 1669 | kfree(pd_dev_save); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1670 | } |
| 1671 | |
| 1672 | #ifdef CONFIG_PM |
| 1673 | static int pch_spi_suspend(struct pci_dev *pdev, pm_message_t state) |
| 1674 | { |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1675 | int retval; |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 1676 | struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1677 | |
| 1678 | dev_dbg(&pdev->dev, "%s ENTRY\n", __func__); |
| 1679 | |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 1680 | pd_dev_save->board_dat->suspend_sts = true; |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1681 | |
| 1682 | /* save config space */ |
| 1683 | retval = pci_save_state(pdev); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1684 | if (retval == 0) { |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1685 | pci_enable_wake(pdev, PCI_D3hot, 0); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1686 | pci_disable_device(pdev); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1687 | pci_set_power_state(pdev, PCI_D3hot); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1688 | } else { |
| 1689 | dev_err(&pdev->dev, "%s pci_save_state failed\n", __func__); |
| 1690 | } |
| 1691 | |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1692 | return retval; |
| 1693 | } |
| 1694 | |
| 1695 | static int pch_spi_resume(struct pci_dev *pdev) |
| 1696 | { |
| 1697 | int retval; |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 1698 | struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1699 | dev_dbg(&pdev->dev, "%s ENTRY\n", __func__); |
| 1700 | |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1701 | pci_set_power_state(pdev, PCI_D0); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1702 | pci_restore_state(pdev); |
| 1703 | |
| 1704 | retval = pci_enable_device(pdev); |
| 1705 | if (retval < 0) { |
| 1706 | dev_err(&pdev->dev, |
| 1707 | "%s pci_enable_device failed\n", __func__); |
| 1708 | } else { |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1709 | pci_enable_wake(pdev, PCI_D3hot, 0); |
| 1710 | |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 1711 | /* set suspend status to false */ |
| 1712 | pd_dev_save->board_dat->suspend_sts = false; |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1713 | } |
| 1714 | |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1715 | return retval; |
| 1716 | } |
| 1717 | #else |
| 1718 | #define pch_spi_suspend NULL |
| 1719 | #define pch_spi_resume NULL |
| 1720 | |
| 1721 | #endif |
| 1722 | |
Danny Kukawka | c88db23 | 2012-02-02 14:20:30 +0100 | [diff] [blame^] | 1723 | static struct pci_driver pch_spi_pcidev_driver = { |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1724 | .name = "pch_spi", |
| 1725 | .id_table = pch_spi_pcidev_id, |
| 1726 | .probe = pch_spi_probe, |
| 1727 | .remove = pch_spi_remove, |
| 1728 | .suspend = pch_spi_suspend, |
| 1729 | .resume = pch_spi_resume, |
| 1730 | }; |
| 1731 | |
| 1732 | static int __init pch_spi_init(void) |
| 1733 | { |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 1734 | int ret; |
| 1735 | ret = platform_driver_register(&pch_spi_pd_driver); |
| 1736 | if (ret) |
| 1737 | return ret; |
| 1738 | |
Danny Kukawka | c88db23 | 2012-02-02 14:20:30 +0100 | [diff] [blame^] | 1739 | ret = pci_register_driver(&pch_spi_pcidev_driver); |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 1740 | if (ret) |
| 1741 | return ret; |
| 1742 | |
| 1743 | return 0; |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1744 | } |
| 1745 | module_init(pch_spi_init); |
| 1746 | |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1747 | static void __exit pch_spi_exit(void) |
| 1748 | { |
Danny Kukawka | c88db23 | 2012-02-02 14:20:30 +0100 | [diff] [blame^] | 1749 | pci_unregister_driver(&pch_spi_pcidev_driver); |
Tomoya MORINAGA | f016aeb | 2011-06-07 14:50:10 +0900 | [diff] [blame] | 1750 | platform_driver_unregister(&pch_spi_pd_driver); |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1751 | } |
| 1752 | module_exit(pch_spi_exit); |
| 1753 | |
Tomoya MORINAGA | c37f3c2 | 2011-06-07 14:50:11 +0900 | [diff] [blame] | 1754 | module_param(use_dma, int, 0644); |
| 1755 | MODULE_PARM_DESC(use_dma, |
| 1756 | "to use DMA for data transfers pass 1 else 0; default 1"); |
| 1757 | |
Masayuki Ohtake | e8b17b5 | 2010-10-08 12:44:49 -0600 | [diff] [blame] | 1758 | MODULE_LICENSE("GPL"); |
Tomoya MORINAGA | 2b24628 | 2011-10-28 09:35:22 +0900 | [diff] [blame] | 1759 | MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semiconductor ML7xxx IOH SPI Driver"); |